KR20230071236A - Switched capacitor based disigal ldo regulator and operating method thereof - Google Patents

Abstract

An LDO regulator that converts a power supply voltage into an output voltage according to an embodiment of the present invention transfers the power supply voltage to an output terminal according to a level of a gate voltage to provide the output voltage, and at least one of a pass transistor and a plurality of flying capacitors. After charging the input voltage or discharging it to the ground, a gate controller based on a switched capacitor controls the gate voltage through charge distribution with the gate of the pass transistor, and generates a sampling clock signal with a frequency corresponding to the level of the output voltage. a clock generator that compares the output voltage and the reference voltage and outputs a logic value corresponding to the comparison result as a comparison signal, an analog-to-digital converter (ADC), and a plurality of digital converters based on the sampling clock signal and the comparison signal. It includes a decoder and a driver that control the charging or discharging of the flying capacitors.

Description

Switched capacitor based LDO regulator and its operating method

The present invention relates to a semiconductor device, and more particularly, to a switched capacitor based LDO regulator having a fast transient response and an operating method thereof.

In general, integrated circuits are designed to operate over a specific range of supply voltages. However, in an actual circuit operating environment, there are various variables such as a voltage higher than the power supply voltage set at the time of design being supplied or noise being introduced into the power supply voltage due to external factors. To solve this problem, a voltage regulator that supplies a constant power supply voltage to the integrated circuit is used. Low-dropout (hereinafter referred to as LDO) regulators, which are representative linear regulators, are mainly used when the difference between input voltage and output voltage is not large because energy is lost as much as the voltage drop.

The LDO regulator consists of an analog error amplifier, a pass transistor, and a feedback network. The error amplifier detects an error between the output voltage Vout and the reference voltage V _REF and controls the pass transistor to reduce the error between the two voltages according to a negative feedback structure. Error amplifier-based analog LDO regulators have a relatively high operating voltage range and are difficult to apply to circuits operating at high frequencies due to their limited operating bandwidth. In addition, as the current capacity increases, the size of the pass transistor to be controlled by the error amplifier increases, and accordingly, there is a problem of deterioration in stability due to an operating bandwidth or negative feedback. To solve this problem, research on digital LDO regulators implemented with comparators and shift registers is active.

Digital LDO regulators regulate the output voltage through complex digital logic circuitry, which limits the clock frequency due to the inherent delay of the digital logic circuitry. Even with adaptive sampling clocks in digital LDOs, transient response rates are limited. Accordingly, there is an urgent need for a digital LDO regulator capable of reducing delay caused by a digital logic circuit in order to increase transient response speed.

(1) Korean Patent Publication No. 10-2015-0073650 (2015.07.01) (2) Korean Patent Publication No. 10-2016-0052920 (2016.05.13)

An object of the present invention is to provide a digital LDO regulator capable of providing a high transient response speed by reducing delay due to intervention of logic circuits and an operating method thereof.

An LDO regulator that converts a power supply voltage into an output voltage according to an embodiment of the present invention transfers the power supply voltage to an output terminal according to a level of a gate voltage to provide the output voltage, and at least one of a pass transistor and a plurality of flying capacitors. After charging the input voltage or discharging it to the ground, a gate controller based on a switched capacitor controls the gate voltage through charge distribution with the gate of the pass transistor, and generates a sampling clock signal with a frequency corresponding to the level of the output voltage. a clock generator that compares the output voltage and the reference voltage and outputs a logic value corresponding to the comparison result as a comparison signal, an analog-to-digital converter (ADC), and a plurality of digital converters based on the sampling clock signal and the comparison signal. It includes a decoder and a driver that control the charging or discharging of the flying capacitors.

According to an embodiment of the present invention, a method of operating an LDO regulator including a pass transistor for providing an output voltage by transferring a power supply voltage to an output terminal according to a level of a gate voltage corresponds to a voltage difference between the output voltage and a reference voltage. Generating a sampling clock signal having a frequency, generating a comparison signal corresponding to a level difference between the output signal and the reference voltage based on the sampling clock signal, and among a plurality of flying capacitors according to the comparison signal. and adjusting the gate voltage through charge distribution with the gate of the pass transistor after charging at least one of the pass transistors with an input voltage or discharging them to a ground.

According to the above-described embodiment of the present invention, a digital LDO regulator capable of providing a fast recovery speed and robustness against process inconsistency can be implemented by adjusting the gate voltage of the pass transistor through a switched capacitor.

1 is a block diagram showing the structure of an LDO regulator based on a switched capacitor according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of the clock generator of FIG. 1 by way of example.
FIG. 3 is a waveform diagram exemplarily showing sampling clock signals output from the clock generator of FIG. 2 .
4 is a circuit diagram showing an exemplary configuration of the ADC of FIG. 1 .
5 is a waveform diagram exemplarily showing comparison signals (CMP _L , CMP _M , CMP _H ) output from the ADC of FIG. 4 .
6 is a circuit diagram showing an example of a gate controller based on a switched capacitor (SC).
7A and 7B are circuit diagrams illustrating a switching operation of a gate controller based on a switched capacitor (SC) when the output voltage (Vout) is lower than the first reference voltage (V _{REF_L} ).
8A and 8B are circuit diagrams illustrating a switching operation of a gate controller based on a switched capacitor SC when the output voltage Vout is higher than the first reference voltage V _{REF_L} and lower than the second reference voltage V _{REF_M} .
9A and 9B are circuit diagrams illustrating a switching operation of a gate controller based on a switched capacitor SC when the output voltage Vout is higher than the second reference voltage V _{REF_M} and lower than the third reference voltage V _{REF_H} .
10A and 10B are circuit diagrams illustrating a switching operation of a gate controller based on a switched capacitor SC when the output voltage Vout is higher than the third reference voltage V _{REF_H} .
11 is a flowchart briefly showing a method for controlling a switched capacitor (SC) of an LDO regulator according to the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible, even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

1 is a block diagram showing the structure of an LDO regulator based on a switched capacitor according to an embodiment of the present invention. Referring to FIG. 1, the LDO regulator 100 includes a clock generator 110, an ADC 120, a decoder and driver 130, a switched capacitor (SC) based gate controller 140, and a pass transistor (PT, 150). includes

The clock generator 110 compares the output voltage Vout and the reference voltage V _{REF_M} to generate sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 . The sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 are clock signals whose frequency varies according to a level difference between the output voltage Vout and the reference voltage V _{REF_M} . That is, when the level difference between the output voltage Vout and the reference voltage V _{REF_M} is large, high-frequency sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 are generated to pass transistor 150 ) can increase the rate of change of the gate voltage (V _G ). On the other hand, when the level difference between the output voltage Vout and the reference voltage V _{REF_M} is small, relatively low frequency sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ) are generated to pass transistors. The change rate of the gate voltage (V _G ) of (150) can be reduced. An exemplary configuration of the clock generator 110 will be described with reference to FIG. 2 described later.

The ADC 120 compares the levels of the output voltage Vout and the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} to provide comparison signals (CMP) for adjusting the capacitance of the flying capacitor of the SC-based gate controller 140 . _L , CMP _M , CMP _H ). The ADC 120 converts the first comparison signal CMP _L to logic '0' when the output voltage Vout is lower than the first reference voltage V _{REF_L} , and turns it into logic '0' when the output voltage Vout is greater than or equal to the first reference voltage V _{REF_L} . 1 The comparison signal CMP _L may be output as logic '1'. Further, the ADC 120 converts the second comparison signal CMP _M to logic '0' when the output voltage Vout is lower than the second reference voltage V _{REF_M} , and when the output voltage Vout is greater than or equal to the second reference voltage V _{REF_M} . The second comparison signal CMP _M will be output as logic '1'. The ADC 120 converts the third comparison signal CMP _H to logic '0' when the output voltage Vout is lower than the third reference voltage V _{REF_H} , and to logic '0' when the output voltage Vout is higher than the third reference voltage V _{REF_H} . 3 The comparison signal (CMP _M ) will be output as logic '1'. Levels of the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} have a relationship of 'V _{REF_L} < V _{REF_M} < V _{REF_H} '.

The decoder and driver 130 is a switched capacitor (SC) based gate based on sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ) and comparison signals (CMP _L , CMP _M , CMP _H ). Controls the controller 140. In detail, the decoder and driver 130 charges or discharges the flying capacitor of the gate controller 140 based on the switched capacitor (SC) with reference to the comparison signals CMP _L , CMP _M , and CMP _H . Also, the decoder and driver 130 may adjust the level of the gate voltage V _G through charge sharing between the charged or discharged flying capacitor and the gate of the pass transistor 150 . The switching speed of the flying capacitor may be controlled by the sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 having frequencies corresponding to the level of the output voltage Vout.

In addition, when four switched capacitor (SC)-based gate controllers 140 are connected in parallel to the gates of the pass transistors 150, the sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ) are respectively may be provided to the gate controller 140 based on a switched capacitor (SC) of Therefore, since the gate voltage (V _G ) of the pass transistor 150 can be independently adjusted by the different sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ), the transient response speed is improved. It is expected.

The gate controller 140 based on a switched capacitor (hereinafter referred to as SC) includes switches controlled by the decoder and driver 130 and flying capacitors (K _P C _{fly_up} , C _{fly_up} , K _P C _{fly_dw} , C _{fly_dw} ). . Through switching of the flying capacitors (K _P C _{fly_up} , C _{fly_up} , K _P C _{fly_dw} , C _{fly_dw} ) by the decoder and driver 130 , the gate voltage (V _G ) of the pass transistor 150 is grounded (GND, Vss ) or the input voltage (Vin) is discharged or charged. According to the present invention, when the output voltage Vout rises above the third reference voltage V _{REF_H} of the highest level, the gate of the pass transistor 150 is flown with the highest capacitance in order to quickly lower the output voltage Vout. We will use the capacitor (K _P C _{fly_dw} ) to charge it. On the other hand, when the output voltage Vout is lower than the first reference voltage V _{REF_L} of the lowest level, the gate of the pass transistor 150 is set to the largest capacity flying capacitor (K) in order to quickly increase the output voltage Vout. _P C _{fly_up} ) will be used to discharge.

The pass transistor 150 controls the output voltage Vout by providing the power supply voltage V _DD to an output terminal according to the gate voltage V _G adjusted by the SC-based gate controller 140 . A gate capacitor (C _G ) of parasitic capacitance that accumulates charges charged or discharged by the SC-based gate controller 140 exists at the gate of the pass transistor 150 . A coupling capacitor C _C may be provided between the gate of the pass transistor 150 and a drain provided as an output terminal. In the event that the output voltage Vout is rapidly reduced by the coupling capacitor C _C , the gate voltage of the pass transistor 150 may be adjusted by the coupling effect. Therefore, the coupling capacitor (C _C ) provides stability by providing a feedback loop for the rapid change of the output voltage (Vout).

According to the above LDO regulator 100 according to the embodiment of the present invention, the gate voltage (V _G ) of the pass transistor 150 can be controlled by the switching of the switched capacitor. Therefore, delay caused by logic circuits such as a charge pump or a bidirectional shift register occurring in general digital LDO regulators can be reduced. In addition, since the flying capacitor constituting the SC-based gate controller 140 is formed using a metal layer, it is less affected by PVT fluctuations. Therefore, when the LDO regulator 100 of the present invention is provided as a chip, it may have advantages in terms of reliability, stability, and yield.

FIG. 2 is a block diagram showing the configuration of the clock generator of FIG. 1 by way of example. Referring to FIG. 2 , the clock generator 110 may include voltage controlled oscillators 112 and 114 and D-flip-flops 116 and 118 . The clock generator 110 generates sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ) of frequencies adjusted according to the level of the output voltage Vout.

The first voltage controlled oscillator 112 generates a clock signal CLKo having a frequency corresponding to the level of the output voltage Vout. The second voltage controlled oscillator 114 generates a clock signal CLKr having a frequency corresponding to the level of the second reference voltage V _{REF_M} . It will be well understood that the voltage controlled oscillators 112 and 114 are clock generation circuits that generate an oscillation signal with a frequency that increases or decreases depending on the level of the input voltage.

The first D flip-flop 116 receives a clock signal CLKo through a data input terminal D and receives a clock signal CLKr through a rising edge triggered clock input terminal. In this case, the first D flip-flop 116 provides a function of a frequency subtractor for the clock signals CLKr and CLKo. Therefore, the first sampling clock signal (CLK SAM1) is transmitted to the positive output terminal (Q) of the first D flip-flop 116, and the inverted first sampling clock signal (/CLK _SAM1 ) is transmitted to the negative output terminal (/Q) of the first D flip-flop ₁₁₆ . ) is output.

The second D flip-flop 118 receives a clock signal CLKo through a data input terminal D and receives a clock signal CLKr through a falling edge triggered clock input terminal. In this case, the second D flip-flop 118 operates as a frequency subtractor for the clock signals CLKr and CLKo. The second sampling clock signal (CLK SAM2 ) is transmitted to the positive output terminal (Q) of the second D flip-flop 118, and the inverted second sampling clock signal (/CLK _SAM2 ) is transmitted to the negative output terminal (/Q ₎ . output However, although the frequency of the second sampling clock signal CLK _SAM2 is the same as that of the first sampling clock signal CLK _SAM1 , since the edge trigger time point is different, a clock signal having a different phase is provided. The inverted second sampling clock signal (/CLK _SAM2 ) may also have the same frequency as the inverted first sampling clock signal (/CLK _SAM1 ), but is provided with a different phase.

FIG. 3 is a waveform diagram exemplarily showing sampling clock signals output from the clock generator of FIG. 2 . Referring to FIG. 3 , the sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 have a frequency corresponding to a frequency difference between the clock signal CLKo and the clock signal CLKr.

The clock signal CLKo output from the first voltage controlled oscillator 112 has a frequency fo corresponding to the output voltage Vout. Also, the clock signal CLKr output from the second voltage controlled oscillator 114 has a frequency fr corresponding to the second reference voltage V _{REF_M} . And the sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ) generated from the D flip-flops 116 and 118 operating as frequency subtractors will have a frequency of 'fo-fr'. .

If the level of the output voltage Vout is equal to the level of the second reference voltage V _{REF_M} , theoretically, the sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 have a frequency '0'' and will be provided in a flat state. On the other hand, when the level of the output voltage Vout is higher than the level of the second reference voltage V _{REF_M} , the frequencies of the sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 also increase. Accordingly, a frequency domain feedback effect of the output voltage Vout may be provided by the sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 .

Each of the plurality of different sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ) is for switching of four SC-based gate controllers 140 connected in parallel to the gates of the pass transistors 150. Used as a control clock. Therefore, the four SC-based gate controllers 140 independently control the gate voltage (V _G ) of the pass transistor 150 by the different sampling clock signals (CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ). Since can be adjusted, it is possible to improve the transient response speed.

FIG. 4 is a circuit diagram showing an exemplary configuration of an analog-to-digital converter (ADC) of FIG. 1 . Referring to FIG. 4 , the ADC 120 may include synchronous comparators 122 , 124 , and 126 that generate comparison signals CMP _L , CMP _M , and CMP _H . Here, it is assumed that the levels of the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} have a relationship of 'V _{REF_L} < V _{REF_M} < V _{REF_H} '.

The first synchronous comparator 122 compares the output voltage Vout and the first reference voltage V _{REF_L} in synchronization with the first sampling clock signal CLK _SAM1 . The first synchronous comparator 122 sets the first comparison signal CMP _L to logic '0' when the output voltage Vout is lower than the first reference voltage V _{REF_L} , and the output voltage Vout is set to the first reference voltage V REF_L. When the voltage V _{REF_L} is greater than or equal to, the first comparison signal CMP _L may be output as logic '1'. The output of the first comparison signal CMP _L may be generated in synchronization with the first sampling clock signal CLK _SAM1 . However, it will be well understood that the first synchronous comparator 122 can be driven using any one of the other sampling clock signals (/CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ).

The second synchronous comparator 124 compares the output voltage Vout and the second reference voltage V _{REF_M} in synchronization with the first sampling clock signal CLK _SAM1 . The second synchronous comparator 124 converts the second comparison signal CMP _M to logic '0' when the output voltage Vout is lower than the second reference voltage V _{REF_M} , and the output voltage Vout becomes the second reference voltage. When the voltage V _{REF_M} is greater than or equal to, the second comparison signal CMP _M may be output as logic '1'. The output of the second comparison signal CMP _M may be generated in synchronization with the first sampling clock signal CLK _SAM1 .

The third synchronous comparator 126 compares the output voltage Vout and the third reference voltage V _{REF_H} in synchronization with the first sampling clock signal CLK _SAM1 . The third synchronous comparator 126 sets the third comparison signal CMP _H to logic '0' when the output voltage Vout is lower than the third reference voltage V _{REF_H} , and the output voltage Vout is the third reference voltage. When the voltage V _{REF_H} is greater than or equal to, the third comparison signal CMP _H may be output as logic '1'. The output of the third comparison signal CMP _H may be generated in synchronization with the first sampling clock signal CLK _SAM1 .

In the above, the configuration of the ADC 120 configured using three synchronous comparators has been briefly described. At this time, the comparison signals CMP _L , CMP _M , and CMP _H output in synchronization with the first sampling clock signal CLK _SAM1 have a 3-bit form. However, since the comparison result of the ADC 120 has four logical states, it will be well understood that the comparison signals CMP _L , CMP _M , and CMP _H may be provided as 2-bit data. In addition, the ADC 120 may be configured using four or more synchronous comparators.

FIG. 5 is a waveform diagram showing comparison signals (CMP _L , CMP _M , and CMP _H ) output from the ADC of FIG. 4 by way of example. Referring to FIG. 5, the ADC (120, see FIG. 4) compares the level of the output voltage (Vout) and the reference voltages (V _{REF_H} , V _{REF_M} , and V _{REF_L} ) to provide comparison signals for adjusting the capacitance of the flying capacitor. Creates [CMP _H , CMP _M , CMP _L ].

Prior to time T1, the output voltage Vout is detected to be higher than the second reference voltage V _{REF_M} and lower than the third reference voltage V _{REF_H} . Then, the comparison signals [CMP _H , CMP _M , CMP _L ] will be output as [011]. At the time T1, the output voltage Vout is detected to be higher than the third reference voltage V _{REF_H} . Then, the comparison signals [CMP _H , CMP _M , CMP _L ] are output as [111].

At time T3, it is detected that the output voltage Vout is lower than the third reference voltage V _{REF_H} and higher than the second reference voltage V _{REF_M} . Then, the comparison signals [CMP _H , CMP _M , CMP _L ] are output as [011]. On the other hand, at time T4, the output voltage Vout becomes lower than the first reference voltage V _{REF_L} . As a result, the output voltage Vout is detected to be lower than all of the first to third reference voltages V _{REF_H} , V _{REF_M} , and V _{REF_L} . Then, the comparison signals [CMP _H , CMP _M , CMP _L ] are output as [000].

The decoder and driver 130 controls the charging or discharging of the flying capacitors of the gate controller 140 based on the switched capacitor (SC) with reference to the bit values of the comparison signals [CMP _H , CMP _M , and CMP _L ].

6 is a circuit diagram showing an example of a gate controller based on a switched capacitor (SC). Referring to FIG. 6 , a switched capacitor (SC) based gate controller 142 that is one of four switched capacitor (SC) based gate controllers 140 is shown.

Charging of the first and second flying capacitors (K _P C _{fly_up} ) and the second flying capacitor (C _{fly_up} ) for discharging the gate of the pass transistor 150 and the first and second flying capacitors (K _P C _{fly_up} and C _{fly_up} ) and switches SW1, SW2, SW3, and SW4 for controlling discharge. The first flying capacitor (K _P C _{fly_up} ) has a capacity 'K _P ' times larger than that of the second flying capacitor (C _{fly_up} ). 'K _P ' is a rational number greater than 1. When the output voltage Vout needs to be increased, the decoder and driver 130 controls the switches SW1 , SW2 , SW3 , and SW4 to transfer the charge charged in the gate capacitance C _G to the first flying capacitor K _P C _{fly_up} ) or the second flying capacitor (C _{fly_up} ) and discharge. Then, the gate voltage (V _G ) is lowered in proportion to the discharged capacitance, and the amount of charge moving through the pass transistor 150 increases, so the output voltage (Vout) rises.

Charging the third and fourth flying capacitors K _P C _{fly_dw} and C _{fly_dw} and the third and fourth flying capacitors K _P C _{fly_dw} and C _{fly_dw} for charging the gate of the pass transistor 150 and switches SW5, SW6, SW7, and SW8 for controlling discharge. Here, 'K _P ' may have a value greater than 1. The third flying capacitor (K _P C _{fly_dw} ) has a capacitance 'K _P ' times greater than that of the fourth flying capacitor (C _{fly_dw} ). When the output voltage Vout needs to be lowered, the decoder and driver 130 controls the switches SW5, SW6, SW7, and SW8 to increase the input voltage Vin to the first flying capacitor K _P C _{fly_up} or the second The flying capacitor (C _{fly_up} ) is charged and distributed to the gate of the pass transistor 150 . Then, as charges are charged in the gate capacitance (C _G ), the gate voltage (V _G ) rises. As the gate voltage (V _G ) rises, the channel of the pass transistor 150 decreases and the output voltage (Vout) decreases. The response speed at this time is determined by the capacitance of the first flying capacitor (K _P C _{fly_up} ) or the second flying capacitor (C _{fly_up} ).

7A and 7B are circuit diagrams illustrating a switching operation of a gate controller based on a switched capacitor (SC) when the output voltage (Vout) is lower than the first reference voltage (V _{REF_L} ). FIG. 7A shows a switch state during a charging operation of the first flying capacitor K _P C _{fly_up} , and FIG. 7B shows a switch state during a discharging operation of the first flying capacitor K _P C _{fly_up} . Here, the levels of the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} have a relationship of 'V _{REF_L} < V _{REF_M} < V _{REF_H} '.

Referring to FIG. 7A , when the output voltage Vout is lower than the first reference voltage V _{REF_L} , it is necessary to increase the output voltage Vout at a high speed. To this end, the first switch SW1 is turned on, and the remaining switches SW2 to SW8 remain turned off. Then, the charges charged in the gate capacitor C _G corresponding to the parasitic capacitance are distributed to the first flying capacitor K _P C _{fly_up} . Due to the charge distribution, the gate voltage (V _G ) is lowered to the 'V _G -K _P ΔV _G ' level. The channel of the pass transistor PT is increased by the lowered gate voltage (V _G -K _P ΔV _G ). Then, the output voltage Vout rises to the level of 'Vout+K _P ΔVout'.

Referring to FIG. 7B , charges charged in the first flying capacitor K _P C _{fly_up} are discharged by voltage distribution. To discharge the first flying capacitor K _P C _{fly_up} , the second switch SW2 is turned on, and the remaining switches SW1 and SW3 to SW8 are turned off. Then, the charges charged in the first flying capacitor K _P C _{fly_up} are discharged to the ground. The gate voltage (V _G -K _P ΔV _G ) of the pass transistor PT is maintained by blocking the first switch SW1 . Also, the output voltage Vout will maintain the elevated level 'Vout+K _P ΔVout'.

8A and 8B are circuit diagrams illustrating a switching operation of the SC-based gate controller when the output voltage Vout is higher than the first reference voltage V _{REF_L} and lower than the second reference voltage V _{REF_M} . FIG. 8A shows a switch state during a charging operation of the second flying capacitor C _{fly_up} , and FIG. 8B shows a switch state during a discharging operation of the second flying capacitor C _{fly_up} . Here, the levels of the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} have a relationship of 'V _{REF_L} < V _{REF_M} < V _{REF_H} '.

Referring to FIG. 8A , when the output voltage Vout is higher than the first reference voltage V _{REF_L} and lower than the second reference voltage V _{REF_M} , it is necessary to increase the output voltage Vout. To this end, the third switch SW3 is turned on, and the remaining switches SW1 to SW2 and SW4 to SW8 are turned off. Then, the charges charged in the gate capacitor C _G are distributed to the second flying capacitor C _{fly_up} . Due to the charge distribution, the gate voltage (V _G ) is lowered to 'V _G -ΔV _G '. The channel of the pass transistor PT is increased by the lowered gate voltage (V _G -K _P ΔV _G ). Then, the output voltage Vout rises to the level of 'Vout+ΔVout'.

Referring to FIG. 8B , charges charged in the second flying capacitor C _{fly_up} are discharged by voltage distribution. To discharge the second flying capacitor C _{fly_up} , the fourth switch SW4 is turned on, and the remaining switches SW1 to SW3 and SW5 to SW8 are turned off. Then, the charges charged in the second flying capacitor C _{fly_up} are discharged to the ground. The gate voltage (V _G -ΔV _G ) of the pass transistor PT, which is raised by the third switch SW3 being cut off, is maintained. Also, the output voltage Vout will maintain the elevated level 'Vout+ΔVout'.

9A and 9B are circuit diagrams showing a switching operation of a gate controller based on a switched capacitor (SC) when the output voltage (Vout) is higher than the second reference voltage (V _{REF_M} ) and lower than the third reference voltage (V _{REF_H} ). FIG. 9A shows a switch state during a charging operation of the third flying capacitor C _{fly_dw} by the input voltage Vin, and FIG. 9B shows a charge distribution operation between the third flying capacitor C _{fly_dw} and the gate capacitor C _G . show each Here, the levels of the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} have a relationship of 'V _{REF_L} < V _{REF_M} < V _{REF_H} '.

Referring to FIG. 9A, when the output voltage Vout is greater than or equal to the second reference voltage V _{REF_M} and lower than the third reference voltage V _{REF_H} , the output voltage Vout is set to the level of the second reference voltage V _{REF_M} . need to lower For this purpose, the switches SW5 and SW8 are turned on, and the remaining switches SW1 to SW4 and SW6 to SW7 are turned off. Then, the third flying capacitor C _{fly_dw} is charged by the input voltage Vin.

Referring to FIG. 9B , in order to increase the gate voltage (V _G ) of the pass transistor (PT), the charge charged in the third flying capacitor (C _{fly_dw} ) is distributed to the gate capacitor (C _G ). To this end, the fifth switch SW5 connecting the input voltage Vin is blocked, and the sixth switch SW6 is turned on. Then, the charge charged in the third flying capacitor C _{fly_dw} is distributed to the gate capacitor C _G , and the gate voltage V _G rises to the 'V _G +ΔV _G ' level. In addition, the output voltage Vout will drop to the 'Vout-ΔVout' level due to the increased gate voltage (V _G +ΔV _G ).

10A and 10B are circuit diagrams illustrating a switching operation of a gate controller based on a switched capacitor (SC) when the output voltage (Vout) is greater than or equal to the third reference voltage (V _{REF_H} ). FIG. 10A shows a charging operation of the fourth flying capacitor K _{PC fly_dw} by the input voltage Vin, and FIG. 10B shows a charge distribution operation between the fourth flying capacitor K _{PC fly_dw} and the gate capacitor C _G . shows the status of the switch. Here, the levels of the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} have a relationship of 'V _{REF_L} < V _{REF_M} < V _{REF_H} '.

Referring to FIG. 10A , when the output voltage Vout is greater than or equal to the third reference voltage V _{REF_H} , it is necessary to rapidly lower the output voltage Vout to the second reference voltage V _{REF_M} level. For this purpose, the switches SW5 and SW7 are turned on, and the remaining switches SW1 to SW4, SW6 and SW8 are turned off. Then, the fourth flying capacitor K _P C _{fly_dw} is charged by the input voltage Vin.

Referring to FIG. 10B , in order to increase the gate voltage (V _G ) of the pass transistor (PT), the charge charged in the fourth flying capacitor (K _P C _{fly_dw} ) is distributed to the gate capacitor (C _G ). To this end, the fifth switch SW5 connecting the input voltage Vin is blocked, and the sixth switch SW6 is turned on. Then, the charge charged in the fourth flying capacitor (K _P C _{fly_dw} ) is distributed to the gate capacitor (C _G ), and the gate voltage (V _G ) rises to the 'V _G +K _P ΔV _G ' level. In addition, the output voltage Vout will drop to the 'Vout-K _P ΔVout' level due to the increased gate voltage (V _G +K _P ΔV _G ).

In the above, the switching method of the SC-based gate controller 142 according to the level of the output voltage Vout has been described as an example. In the SC-based gate controller 142, various arrangements or arrangements of the switches and flying capacitors may exist. Accordingly, the control method of the SC-based gate controller 142 of the present invention may be variously changed for controlling the output voltage Vout.

11 is a flowchart briefly showing a method of controlling the switched capacitor (SC) of the LDO regulator of the present invention. 1 and 11, the LDO regulator 100 of the present invention can control the gate voltage (V _G ) of the pass transistor 150 according to the level of the output voltage (Vout) in a switched capacitor (SC) method. there is.

In step S110, the clock generator 110 compares the output voltage Vout and the reference voltage V _{REF_M} to generate a plurality of sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , and /CLK _SAM2 . The clock generator 110 uses the voltage controlled oscillators 112 and 114 and the D-flip-flops 116 and 118 to generate sampling clock signals CLK _SAM1 having a frequency corresponding to the level of the output voltage Vout. /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ).

In step S120, the decoder and driver 130 uses the comparison signals CMP _L , CMP _M , and CMP _H generated by the ADC 120 and the sampling clock signals CLK _SAM1 , /CLK _SAM1 , CLK _SAM2 , /CLK _SAM2 ) is received. The comparison signals CMP _L , CMP _M , and CMP _H are signals that define a relative level relationship of the output voltage Vout with respect to the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} by the ADC 120 .

In step S130, the decoder and driver 130 performs an operation branch according to the level of the output voltage Vout and the first reference voltage V _{REF_L} . If the output voltage Vout is lower than the first reference voltage V _{REF_L} (YES direction), the process moves to step S140. On the other hand, when the output voltage Vout is not lower than the first reference voltage V _{REF_L} (direction NO), the process moves to step S150.

In step S140, the decoder and driver 130 transfers the charges charged in the gate capacitor C _G of the pass transistor 150 to the first flying capacitor K _P C _{fly_up} in order to increase the output voltage Vout at high speed. distribute The electric charge distributed to the first flying capacitor K _P C _{fly_up} is then discharged to the ground. Due to charge distribution by the first flying capacitor K _P C _{fly_up} , the gate voltage V _G is lowered to the 'V _G -K _P ΔV _G ' level. The channel of the pass transistor PT is expanded by the lowered gate voltage (V _G -K _P ΔV _G ). Then, the output voltage Vout rises to the level of 'Vout+K _P ΔVout'.

In step S150, the decoder and driver 130 checks whether the output voltage Vout corresponds to a case where the first reference voltage V _{REF_L} is higher than the second reference voltage V _{REF_M} . If the output voltage Vout is higher than the first reference voltage V _{REF_L} and lower than the second reference voltage V _{REF_M} (YES direction), the process moves to step S160. On the other hand, when the output voltage Vout is higher than the second reference voltage V _{REF_M} (direction NO), the process moves to step S170.

In step S160, the decoder and driver 130 distributes the charges charged in the gate capacitor C _G to the second flying capacitor C _{fly_up} in order to increase the output voltage Vout at a relatively low speed. Then, the electric charge distributed to the second flying capacitor C _{fly_up} is discharged to the ground side. By charge distribution using the second flying capacitor (C _{fly_up} ), the gate voltage (V _G ) is lowered to 'V _G -ΔV _G '. At the lowered gate voltage (V _G -K _P ΔV _G ), the output voltage (Vout) rises to a level of 'Vout+ΔVout'.

In step S170, the decoder and driver 130 checks whether the output voltage Vout is higher than the second reference voltage V _{REF_M} and lower than the third reference voltage V _{REF_H} . If the output voltage Vout is higher than the second reference voltage V _{REF_M} and lower than the third reference voltage V _{REF_H} (YES direction), the process moves to step S180. On the other hand, when the output voltage Vout is higher than the third reference voltage V _{REF_H} (direction NO), the procedure moves to step S190.

In step S180, the decoder and driver 130 charges the third flying capacitor C _{fly_dw} using the input voltage Vin to lower the level of the output voltage Vout, and then the third flying capacitor C _{fly_dw} ) is distributed to the gate capacitor (C _G ). By charging the gate capacitor (C _G ), the gate voltage (V _G ) rises to the 'V _G +ΔV _G ' level. In addition, the output voltage Vout will drop to the 'Vout-ΔVout' level due to the increased gate voltage (V _G +ΔV _G ).

In step S190, the decoder and driver 130 charges the fourth flying capacitor K _P C _{fly_dw} by using the input voltage Vin to lower the level of the output voltage Vout. Also, the decoder and driver 130 distributes the charges charged in the fourth flying capacitor K _P C _{fly_dw} to the gate capacitor C _G . Then, the gate voltage (V _G ) rises to the 'V _G +K _P ΔV _G ' level. In addition, the output voltage Vout will drop to the 'Vout-K _P ΔVout' level due to the increased gate voltage (V _G +K _P ΔV _G ).

In the above, the operating method of the LDO regulator according to an embodiment of the present invention has been briefly described. Although the reference voltages V _{REF_L} , V _{REF_M} , and V _{REF_H} described herein are defined as three levels, it will be well understood that the reference voltages of the present invention may be defined as four or more levels.

The foregoing are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should be defined by not only the claims to be described later, but also those equivalent to the claims of the present invention.

100: LDO regulator
110: clock generator
120: ADC
130: decoder and driver
140: switched capacitor (SC) based gate controller
150: pass transistor

Claims (15)

For an LDO regulator that converts a supply voltage to an output voltage:
a pass transistor for providing the output voltage by transferring the power supply voltage to an output terminal according to a level of a gate voltage;
a switched capacitor-based gate controller for controlling the gate voltage through charge distribution with the gate of the pass transistor after charging at least one of the plurality of flying capacitors with an input voltage or discharging to a ground;
a clock generator generating a sampling clock signal having a frequency corresponding to the level of the output voltage;
an analog-to-digital converter (ADC) comparing the output voltage and the reference voltage and outputting a logic value corresponding to the comparison result as a comparison signal; and
An LDO regulator including a decoder and a driver for controlling charging or discharging of a plurality of flying capacitors based on the sampling clock signal and the comparison signal. According to claim 1,
The clock generator:
a first voltage controlled oscillator generating a first oscillation signal having a frequency corresponding to the output voltage;
a second voltage controlled oscillator generating a second oscillation signal having a frequency corresponding to the reference voltage; and
and a frequency subtractor configured to generate a plurality of sampling clock signals having a difference frequency between the first oscillation signal and the second oscillation signal and having different phases. According to claim 1,
The reference voltage includes a first reference voltage, a second reference voltage higher than the first reference voltage, and a third reference voltage higher than the second reference voltage;
The analog-to-digital converter (ADC) compares each of the first reference voltage, the second reference voltage, and the third reference voltage with the output voltage in synchronization with the sampling clock signal, and outputs the comparison signal of a plurality of bits. an LDO regulator. According to claim 3,
The gate controller includes a first flying capacitor and a second flying capacitor having different capacitances for charging the gate of the pass transistor, a third flying capacitor having different capacitance for discharging the gate of the pass transistor, and a second flying capacitor having different capacitances for discharging the gate of the pass transistor. LDO regulator with 4 flying capacitors. According to claim 4,
wherein the decoder and driver select one of the first to fourth flying capacitors according to a relative difference between the output voltage and the reference voltage to charge or discharge the gate of the pass transistor. According to claim 5,
The decoder and driver are:
Discharging the gate of the pass transistor using the first flying capacitor when the output voltage is lower than the first reference voltage;
When the output voltage is higher than the first reference voltage and lower than the second reference voltage, the LDO regulator discharges the gate of the pass transistor using the second flying capacitor having a smaller capacity than the first flying capacitor. According to claim 5,
The decoder and driver are:
When the output voltage is higher than the second reference voltage and lower than the third reference voltage, charging the gate of the pass transistor using the third flying capacitor;
When the output voltage is equal to or greater than the third reference voltage, the LDO regulator charges the gate of the pass transistor using the fourth flying capacitor having a larger capacitance than the third flying capacitor. According to claim 1,
The pass transistor includes a PMOS transistor, and a coupling capacitor is connected between a gate and a drain of the PMOS transistor. In the operating method of the LDO regulator including a pass transistor for providing an output voltage by transferring a power supply voltage to an output terminal according to the level of the gate voltage:
generating a sampling clock signal having a frequency corresponding to a voltage difference between the output voltage and a reference voltage;
generating a comparison signal corresponding to a level difference between the output signal and the reference voltage based on the sampling clock signal; and
and adjusting the gate voltage through charge distribution with the gate of the pass transistor after charging at least one of the plurality of flying capacitors with an input voltage or discharging to a ground according to the comparison signal. According to claim 9,
The reference voltage includes a first reference voltage, a second reference voltage higher than the first reference voltage, and a third reference voltage higher than the second reference voltage;
The comparison signal has a multi-bit logical value defining a magnitude relationship between the output voltage and the first reference voltage, the second reference voltage, and the third reference voltage. According to claim 10,
The plurality of flying capacitors may include a first flying capacitor and a second flying capacitor having different capacitances for charging the gate of the pass transistor, and a third flying capacitor having different capacitance for discharging the gate of the pass transistor. and a fourth flying capacitor. According to claim 11,
In the step of adjusting the gate voltage,
Discharging the gate of the pass transistor using the first flying capacitor when the output voltage is lower than the first reference voltage;
Discharging the gate of the pass transistor by using the second flying capacitor having a smaller capacity than the first flying capacitor when the output voltage is higher than the first reference voltage and lower than the second reference voltage. According to claim 11,
In the step of adjusting the gate voltage,
When the output voltage is higher than the second reference voltage and lower than the third reference voltage, charging the gate of the pass transistor using the third flying capacitor;
When the output voltage is equal to or greater than the third reference voltage, charging the gate of the pass transistor using the fourth flying capacitor having a larger capacitance than the third flying capacitor. According to claim 9,
In the step of generating the comparison signal, the comparison signal is generated in synchronization with the sampling clock signal. According to claim 9,
The sampling clock signal includes a plurality of sampling clock signals having different phases, and each of a plurality of switched capacitor-based gate drivers respectively controlling the gate voltage of the pass transistor is based on each of the plurality of sampling clock signals. Controlled operation method.

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