KR102028655B1 - Digital low-dropout regulator reducing quiescent current - Google Patents

Abstract

According to the present invention, a digital low-dropout (LDO) regulator comprises: a pass transistor array to adjust an input voltage to output an output voltage; control logic to generate a control bit for controlling the pass transistor array based on the difference between a reference voltage and the output voltage, wherein whether to operate the same is determined based on a first clock generated from a clock received from the outside; and self-clock burst logic to sense a voltage variation of the output voltage without using the clock received from the outside and use the voltage variation to generate a second clock having a higher frequency than the first clock to allow the control logic to recover the output voltage in response to the voltage variation if the voltage variation occurs. The control logic generates the control bit based on the second clock if the voltage variation occurs.

Description

DIGITAL LOW-DROPOUT REGULATOR REDUCING QUIESCENT CURRENT}

The present invention relates to a regulator, and more particularly to a digital LDO regulator that reduces the standby current in the sleep mode.

Voltage regulators are used to provide stable power to electronic devices such as display devices. Voltage regulators are classified into linear regulators and switching regulators.

DC-DC converters are a type of switching regulator. DC-DC converters have a high conversion efficiency. However, the output voltage of the DC-DC converter contains more noise than the output voltage of the linear regulator.

Low-dropout (LDO) regulators are a type of linear regulator. LDO regulators have low conversion efficiency, but have fast response speeds. In addition, the output voltage of the LDO regulator contains less noise compared to the output voltage of the DC-DC converter. Thus, an LDO regulator can be used to compensate for the shortcomings of the DC-DC converter. In particular, LDO regulators can be used to power noise sensitive devices or devices that need to be driven at high performance.

Recently, low-power devices such as wearable devices, biografts, and biosignal sensors powered by energy harvesters have been widely used for digital LDO regulators without external output capacitors for high efficiency and low cost. However, since there is no external output capacitor, the instantaneous response characteristic of the load side is inferior. To improve this instantaneous response, digital LDO regulators usually use a high frequency clock to detect variations in the output voltage. Therefore, the digital LDO regulator has a problem of consuming a large standby current.

Republic of Korea Patent No. 10-1768064

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described technical problem, and an object of the present invention is to provide a digital LDO regulator that generates a clock used in burst mode by itself and reduces standby current in sleep mode.

A digital low drop-out (LDO) regulator according to the present invention generates a pass transistor array that regulates an input voltage to output an output voltage, and generates control bits for controlling the pass transistor array based on a difference between a reference voltage and the output voltage. And a control logic for determining whether to operate based on a first clock generated from an externally received clock, and detecting a voltage variation of the output voltage without using the externally received clock. Wherein the control logic includes its own clock burst logic to generate a second clock having a higher frequency than the first clock using the voltage variation such that the control logic recovers the output voltage in response to the voltage variation, wherein the control logic includes The control bit is generated based on the second clock when the voltage change occurs. It can be done.

In example embodiments, the control unit may further include a multiplexer configured to output the first clock or the second clock based on a selection signal, and the control logic may operate based on a clock output from the multiplexer.

In example embodiments, the self clock burst logic may include a voltage variation detector configured to detect the voltage variation, wherein the voltage variation detector outputs the second clock from a time point at which the voltage change occurs to a time point at which the output voltage is restored. The selection signal can be generated to be.

In example embodiments, the self clock burst logic may include a burst clock generator that generates the second clock, the burst clock generator sequentially delaying the selection signal according to a specific time interval corresponding to the frequency of the second clock. Generate the delayed signals, and the second clock may be generated by a logical operation of the delayed signals.

In example embodiments, the burst clock generator may include a plurality of inverters, and a frequency of the second clock may be adjusted according to delay characteristics of the inverters.

In an embodiment, the number of clocks of the second clock may be adjusted according to the number of inverters.

The digital low drop-out (LDO) regulator according to the present invention compares a reference voltage and the output voltage to select an operation mode and generates a normal clock based on an external clock received from the outside according to the selected operation mode. Detects a voltage variation of the output voltage without using the external clock, and generates a burst clock having a higher frequency than the external clock by using the voltage variation when the voltage variation occurs. A self clock burst logic that generates a selection signal based on the multiplexer, which outputs the burst clock when the voltage variation occurs based on the selection signal, and outputs the normal clock otherwise; and from the multiplexer Operating according to an output control clock, the reference voltage and the output May be based on the difference of the pressure comprise a control logic for generating a control bit for controlling the pass transistor array.

In example embodiments, the control logic may include direction control logic to generate an accumulator input signal and an accumulator direction signal based on a difference between the reference voltage and the output voltage, and the control based on the accumulator input signal and the accumulator direction signal. And an accumulator for generating a bit, wherein the accumulator input signal determines the magnitude of adjusting the output voltage, and the accumulator direction signal may determine the increase or decrease of the output voltage.

In example embodiments, the clock controller generates a switching signal for determining an internal voltage used in the direction control logic, and generates a normal clock, and a difference between the reference voltage and the output voltage and the accumulator. It may include a trigger for generating an internal clock for determining whether to operate the clock generator based on the direction signal.

In an embodiment, when the difference between the reference voltage and the output voltage is greater than a preset offset voltage, the trigger outputs the internal clock equal to the external clock, and the difference between the reference voltage and the output voltage is the offset voltage. If smaller, the trigger may not output the internal clock or output the internal clock having a low level.

In example embodiments, when the difference between the reference voltage and the output voltage is greater than a preset offset voltage, the trigger operates in a normal mode, and when the difference between the reference voltage and the output voltage is less than the offset voltage, the trigger. May operate in a sleep mode.

In an embodiment, the self-clock burst logic may include an undershoot detector for detecting a drop in the output voltage or an overshoot detector for detecting a rise in the output voltage.

In example embodiments, the undershoot detector or the overshoot detector may generate the selection signal such that the multiplexer outputs the burst clock from the time when the voltage change occurs to the time when the output voltage is restored.

In example embodiments, the self clock burst logic may include a burst clock generator configured to generate the burst clock according to a preset frequency, wherein the burst clock generator may generate the selection signal according to a specific time interval corresponding to the frequency of the burst clock. Generating delayed signals delayed sequentially, the burst clock may be generated by a logical operation of the delayed signals.

In example embodiments, the burst clock generator may include a plurality of inverters, and the frequency of the burst clock may be adjusted according to delay characteristics of the inverters.

In an embodiment, the clock number of the burst clock may be adjusted according to the number of inverters.

According to an exemplary embodiment of the present disclosure, a digital LDO regulator may be provided that generates a clock used in a burst mode by itself and reduces a standby current in a sleep mode.

1 is a block diagram illustrating a typical single-clock digital LDO regulator.
FIG. 2 is a timing diagram illustrating quiescent current of the single-clock digital LDO regulator of FIG. 1.
3 is a block diagram illustrating a typical dual-clock digital LDO regulator.
4 is a timing diagram illustrating the quiescent current of the dual-clock digital LDO regulator of FIG. 3.
5 is a block diagram illustrating a digital LDO regulator according to an embodiment of the present invention.
FIG. 6 is a timing diagram illustrating a standby current of the digital LDO regulator of FIG. 5.
FIG. 7 is a detailed block diagram illustrating the digital LDO regulator of FIG. 5.
FIG. 8 is a circuit diagram illustrating an embodiment of the trigger of FIG. 7.
9 is a timing diagram illustrating an operation of the trigger of FIG. 7.
FIG. 10 is a circuit diagram illustrating an embodiment of its own clock burst logic of FIG. 7.
11A is a timing diagram illustrating an operation of the undershoot detector of FIG. 10.
11B is a timing diagram illustrating operation of the burst clock generator of FIG. 10.
12 is a circuit diagram illustrating another embodiment of its own clock burst logic of FIG. 7.
13A is a timing diagram illustrating operation of the overshoot detector of FIG. 12.
FIG. 13B is a timing diagram illustrating operation of the burst clock generator of FIG. 12.
14 is a diagram illustrating a relationship between a frequency and a standby current of a clock used in a burst mode for a digital LDO regulator according to an exemplary embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided. Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are indicated in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The terms are only for the purpose of distinguishing one component from another component, for example, without departing from the scope of the rights according to the inventive concept, the first component may be called a second component, Similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Expressions describing relationships between components, such as "between" and "immediately between" or "directly neighboring", should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "having" are intended to designate that the stated feature, number, step, operation, component, part, or combination thereof is present, but one or more other features or numbers, It is to be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a typical single-clock digital LDO regulator. FIG. 2 is a timing diagram illustrating quiescent current of the single-clock digital LDO regulator of FIG. 1. Referring to FIG. 1, the single-clock digital LDO regulator 10 may include a control logic 11 and a pass transistor array 12. Referring to FIG. 2, the single-clock digital LDO regulator 10 can always operate using the same high frequency clock CLKH.

The single-clock digital LDO regulator 10 may supply a constant output voltage Vout to a load (not shown) corresponding to the input voltage Vin. The single-clock digital LDO regulator 10 may detect a voltage variation of the output voltage Vout and keep the output voltage Vout constant. For example, the control logic 11 may generate the control bit CB by comparing the reference voltage VREF and the output voltage Vout. The pass transistor array 12 may include a plurality of pass transistors. The pass transistors may be turned on or turned off based on the control bit CB. The output voltage Vout may be adjusted depending on whether the pass transistors are turned on or off.

Meanwhile, the single-clock digital LDO regulator 10 may operate based on one external clock. For example, the single-clock digital LDO regulator 10 uses a high frequency clock CLKH to respond to sudden variations in output voltage Vout. That is, the single-clock digital LDO regulator 10 operates using one high frequency clock CLKH regardless of the operation mode (there is no practically separate operation mode).

In FIG. 2, the control current Ictrl which is an operating current of the control logic 11 is Ic, and the standby current I_Q of the single-clock digital LDO regulator 10 has the same value as the control current Ictrl. Accordingly, the single-clock digital LDO regulator 10 consumes a large amount of standby current even when there is no voltage variation of the output voltage Vout.

3 is a block diagram illustrating a typical dual-clock digital LDO regulator. 4 is a timing diagram illustrating the quiescent current of the dual-clock digital LDO regulator of FIG. 3. Referring to FIG. 3, the dual-clock digital LDO regulator 20 may include a control logic 21, a pass transistor array 22, a multiplexer 23, and a burst logic 24. Referring to FIG. 4, the dual-clock digital LDO regulator 20 may operate by receiving a low frequency clock CLKL and a high frequency clock CLKH from the outside. The dual-clock digital LDO regulator 20 may selectively use a low frequency clock (CLKL) and a high frequency clock (CLKH) according to an operation mode to reduce quiescent current than the single-clock digital LDO regulator 10 of FIG. 1. .

The dual-clock digital LDO regulator 20 may supply a constant output voltage Vout to a load (not shown) corresponding to the input voltage Vin. The dual-clock digital LDO regulator 20 may detect voltage variation of the output voltage Vout and maintain the output voltage Vout constant. For example, the control logic 21 may generate the control bit CB by comparing the reference voltage VREF and the output voltage Vout. The pass transistor array 22 may include a plurality of pass transistors. The pass transistors may be turned on or off based on the control bit CB. The output voltage Vout may be adjusted depending on whether the pass transistors are turned on or off.

On the other hand, the dual-clock digital LDO regulator 20 can operate based on two external clocks. For example, the dual-clock digital LDO regulator 20 can receive a low frequency clock CLKL and a high frequency clock CLKH. The dual-clock digital LDO regulator 20 may operate by selecting one of a low frequency clock CLKL and a high frequency clock CLKH according to an operation mode.

The burst logic 24 may monitor the output voltage Vout and generate the selection signal S based on the state of the output voltage Vout. In the sleep mode Sleep without a change in the output voltage Vout, the burst logic 24 may output a signal (eg, logic 0) to select the low frequency clock CLKL. In the burst mode Burst in which the change of the output voltage Vout is sensed, the burst logic 24 may output a signal (eg, logic 1) for selecting the high frequency clock CLKH. The multiplexer 23 may output the control clock CLK_ctrl based on the selection signal S. FIG. The control logic 21 may generate the control bit CB based on the control clock CLK_ctrl. Therefore, the output voltage Vout can be adjusted based on the control bit CB, and the output voltage Vout can maintain a constant value.

The control logic 21 of the dual-clock digital LDO regulator 20 can operate using a low frequency clock (CLKL) in normal mode and a high frequency clock (CLKH) only in burst mode (Burst). have. Therefore, in FIG. 4, the control current Ictrl becomes Ic2 in the burst mode Burst and decreases to Ic1 in the normal mode Normal. Ic2 may be the same value as Ic of FIG. 2. Therefore, the control current Ictrl of the dual-clock digital LDO regulator 20 may be reduced than the control current Ictrl of the single-clock digital LDO regulator 10 of FIG. 1.

However, the standby current I_Q of the dual-clock digital LDO regulator 20 may be expressed as the sum of the control current Ictrl and the burst current Iburst according to the operation of the burst logic 24. The burst logic 24 also uses the high frequency CLKH in the normal mode to detect voltage variation of the output voltage Vout. Thus, the dual-clock digital LDO regulator 20 uses less quiescent current than the single-clock digital LDO regulator 10 of FIG. 1, but still requires a reduction in burst current Iburst.

5 is a block diagram illustrating a digital LDO regulator according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating a standby current of the digital LDO regulator of FIG. 5. 5 and 6, the digital LDO regulator 100 generates a high frequency clock by itself in burst mode and does not use an external clock in its clock burst logic 150, thereby sleeping. It is possible to reduce the burst current Iburst used in the time self clock burst logic 150. Accordingly, the digital LDO regulator 100 may reduce the standby current than the dual-clock digital LDO regulator 20 of FIG. 3.

In FIG. 5, the digital LDO regulator 100 may include a control logic 110, a pass transistor array 120, a multiplexer 130, a clock controller 140, and its own clock burst logic 150. For example, the digital LDO regulator 100 may supply a constant output voltage Vout to the load RL in response to the input voltage Vin. The digital LDO regulator 100 may detect a voltage variation of the output voltage Vout and keep the output voltage Vout constant. The control logic 110 may generate the control bit CB by comparing the reference voltage VREF and the output voltage Vout. The pass transistor array 120 may include a plurality of pass transistors. The pass transistors may be turned on or off based on the control bit CB. The output voltage Vout may be adjusted depending on whether the pass transistors are turned on or off.

The clock controller 140 may control the sleep mode and the normal mode by comparing the reference voltage VREF and the output voltage Vout. For example, the clock controller 140 may block the clock in the sleep mode and generate the normal clock CLKa in the normal mode.

The self clock burst logic 150 may control the burst mode Burst based on the output voltage Vout. For example, when voltage variation of the output voltage Vout occurs during the sleep mode and the normal mode, the digital LDO regulator 100 may operate in the burst mode Burst. . Only in burst mode Burst, its own clock burst logic 150 can generate a burst clock CLKb by itself. In addition, the self clock burst logic 150 may control the multiplexer 130 to generate the selection signal S to operate in the burst mode Burst. The self clock burst logic 150 may analogously detect voltage variation of the output voltage Vout regardless of an external clock. Accordingly, the burst current Iburst that is used by the self clock burst logic 150 during the sleep mode Sleep may be reduced than the burst current Iburst that the burst logic 24 of FIG. 3 uses during the normal mode Normal. have.

The multiplexer 130 may output the control clock CLK_ctrl according to the selection signal S. FIG. For example, the selection signal S may be generated to output the normal clock CLKa in the normal mode and the sleep mode Sleep (eg, logic 0). The selection signal S may be generated to output the burst clock CLKb in the burst mode Burst (eg, logic 1). The control logic 110 may operate based on the control clock CLK_ctrl.

In conclusion, the digital LDO regulator 100 may detect voltage variation of the output voltage Vout without using an external clock through its clock burst logic 150. That is, the self clock burst logic 150 may sense voltage variation of the output voltage Vout in an analog manner through an active circuit that does not use a clock during sleep mode and normal mode. have. Therefore, in FIG. 6, the burst current Iburst becomes Ib3 in the burst mode Burst, and can be reduced to Ib1 in the sleep mode and normal mode. Ib3 may be the same value as Ib of FIG. 4. As a result, the burst current Iburst of the digital LDO regulator 100 may be lower than the burst current Iburst of the dual-clock digital LDO regulator 20 of FIG. 3, and the digital LDO regulator 100 may be reduced to the dual current of FIG. 3. It is possible to reduce the quiescent current than the clock digital LDO regulator 20.

In addition, the control logic 110 is blocked in the sleep mode (Sleep) operation. Therefore, the standby current of the clock control unit 140 and the control logic 110 in the sleep mode (Sleep) is Ic1. In the normal mode, the standby current of the clock controller 140 and the control logic 110 is Ic2. In the burst mode Burst, the standby current of the clock control unit 140 and the control logic 110 is Ic3. Ic2 of FIG. 6 may be the same value as Ic1 of FIG. 4. Ic3 of FIG. 6 may be the same value as Ic2 of FIG. 4. That is, the standby current of the clock controller 140 and the control logic 110 in the sleep mode may be reduced than the standby current in the normal mode of the control logic 21 of FIG. 3.

FIG. 7 is a detailed block diagram illustrating the digital LDO regulator of FIG. 5. Referring to FIG. 7, the digital LDO regulator 100 may include a control logic 110, a pass transistor array 120, a multiplexer 130, a clock controller 140, and its own clock burst logic 150. The control logic 110 may include a direction control logic 111 and an accumulator (ACC) 112, and the clock controller 140 may include a trigger 141 and a clock generator 142.

The digital LDO regulator 100 may operate in one of a normal mode, a sleep mode, and a burst mode. For example, the clock controller 140 may block the clock in the sleep mode and generate the normal clock CLKa in the normal mode. In addition, the own clock burst logic 150 may control the multiplexer 130 to generate a select signal S to distinguish between the sleep mode / normal mode and the burst mode Burst. The self clock burst logic 150 may generate a burst clock CLKb in burst mode Burst.

In the sleep mode Sleep, the trigger 141 may block the internal clock CLKi. Therefore, the control logic 110 does not consume the standby current in the sleep mode. In addition, the self clock burst logic 150 does not generate the burst clock CLKb in the sleep mode and the normal mode.

In normal mode, the trigger 141 may generate an internal clock CLKi having the same frequency as the external low frequency clock CLKL. The clock generator 142 may generate the normal clock CLKa and the switching signal SW based on the internal clock CLKi. The normal clock CLKa is a clock for operating the accumulator 112. The switching signal SW is a signal for generating an internal reference voltage in the direction control logic 111.

In the normal mode, the direction control logic 111 may generate a signal for controlling the accumulator 112 based on a difference between the reference voltage VREF and the output voltage Vout. For example, the direction control logic 111 may generate an accumulator input signal INacc for selecting a specific bit in the accumulator 112. The direction control logic 111 may generate an accumulator direction signal Dacc for determining a direction of adding or subtracting a specific bit selected by the accumulator 112. The magnitude at which the output voltage Vout changes can be determined according to the particular bit selected. The accumulator 112 may generate a control bit CB based on the accumulator input signal INacc and the accumulator direction signal Dacc. The pass transistor array 120 may increase or decrease the output voltage Vout based on the control bit CB.

Meanwhile, when a momentary change in the output voltage Vout is detected during the sleep mode Sleep, the digital LDO regulator 100 may operate in the burst mode Burst. For example, the self clock burst logic 150 may sense voltage variation of the output voltage Vout in an analog manner. The self clock burst logic 150 may generate the selection signal S such that the multiplexer 130 outputs the normal clock CLKa in the normal mode and the sleep mode Sleep (eg, logic 0). ). The self clock burst logic 150 may generate the selection signal S such that the multiplexer 130 outputs the burst clock CLKb in burst mode Burst (eg, logic 1).

In the burst mode Burst, the self clock burst logic 150 may generate a high frequency burst clock CLKb based on a change in the output voltage Vout. For example, the burst clock CLKb may have a higher frequency than the low frequency clock CLKL. The burst clock CLKb may be generated to have a predetermined specific period. In addition, its clock burst logic 150 may generate a portion INacc [5: 8] of the accumulator input signal. The accumulator 112 may generate a control bit CB corresponding to the burst mode Burst based on some accumulator input signals INacc [5: 8], the burst clock CLKb, and the selection signal S. FIG. . The accumulator 112 may use some accumulator input signal INacc [5: 8] during the burst mode Burst according to the selection signal S. Accordingly, the digital LDO regulator 100 may quickly recover the output voltage Vout based on the control bit CB corresponding to the burst mode Burst.

In one embodiment, the clock number of the burst clock CLKb may be preset. After the burst clock CLKb having the set number of clocks is generated, the digital LDO regulator 100 may be switched to the normal mode. That is, the digital LDO regulator 100 partially recovers the voltage variation of the output voltage Vout through the burst mode and restores the output voltage Vout to the normal state through the normal mode. You can. After the output voltage Vout is restored to the normal state, the digital LDO regulator 100 may be switched to the sleep mode Sleep.

FIG. 8 is a circuit diagram illustrating an embodiment of the trigger of FIG. 7. 9 is a timing diagram illustrating an operation of the trigger of FIG. 7. 8 and 9, the trigger 141 selects a normal mode or a sleep mode based on a difference between the reference voltage VREF and the output voltage Vout, and internally according to an operation mode. The clock CLKi may be generated. For example, the trigger 141 may generate an internal clock CLKi that deactivates the clock generator 142 in the sleep mode. That is, the internal clock CLKi may not be output or have a low level in the sleep mode Sleep. Meanwhile, the trigger 141 may output the same internal clock CLKi as the low frequency clock CLKL in the normal mode.

Trigger 141 may include a bidirectional offset comparator 1411. The bidirectional offset comparator 1411 may include p-type transistors MP1 to MP4, n-type transistors MN1 to MN7, capacitors Coffset, and logic gates G1 and G2. In an embodiment, the logic gates G1 and G2 may be NOR gates.

The output of the bidirectional offset comparator 1411 (ie, the voltage at node N6) and the accumulator direction signal Dacc may be input to logic gate G3. The output of the low frequency clock CLKL and the logic gate G3 may be input to the logic gate G4. The logic gate G4 may output the internal clock CLKi. As an example, the logic gate G3 may output an inverted value after the XOR operation. Logic gate G4 may be an AND gate.

When the output voltage Vout is greater than the reference voltage VREF, the accumulator direction signal Dacc may have a high level. When the output voltage Vout is smaller than the reference voltage VREF, the accumulator direction signal Dacc may have a low level.

When the accumulator direction signal Dacc is at a high level, when the difference between the reference voltage VREF and the output voltage Vout is greater than the offset voltage Offset, the voltage at the node N6 is at a high level. At this time, the output of the logic gate G3 is at a high level, so the internal clock CLKi has the same value as the low frequency clock CLKL.

When the accumulator direction signal Dacc is at the high level, when the difference between the reference voltage VREF and the output voltage Vout is smaller than the offset voltage Offset, the voltage at the node N6 is at a low level. At this time, the output of the logic gate G3 is at a low level, and thus the internal clock CLKi is at a low level regardless of the low frequency clock CLKL.

When the accumulator direction signal Dacc is at the low level, when the difference between the reference voltage VREF and the output voltage Vout is smaller than the offset voltage Offset, the voltage at the node N6 is at a high level. At this time, the output of the logic gate G3 is at a low level, and thus the internal clock CLKi is at a low level regardless of the low frequency clock CLKL.

When the accumulator direction signal Dacc is at the low level, when the difference between the reference voltage VREF and the output voltage Vout is greater than the offset voltage Offset, the voltage at the node N6 is at the low level. At this time, the output of the logic gate G3 is at a high level, so the internal clock CLKi has the same value as the low frequency clock CLKL.

Therefore, when the accumulator direction signal Dacc and the voltage of the node N6 have the same logic value, the trigger 141 may output the internal clock CLKi corresponding to the normal mode Normal. When the accumulator direction signal Dacc and the voltage of the node N6 have different logic values, the trigger 141 may output the internal clock CLKi corresponding to the sleep mode Sleep. As a result, the digital LDO regulator 100 may be set to a normal mode or a sleep mode based on the internal clock CLKi.

FIG. 10 is a circuit diagram illustrating an embodiment of its own clock burst logic of FIG. 7. Referring to FIG. 10, the self clock burst logic 150 may include an undershoot detector 151 and a burst clock generator 152. 11A is a timing diagram illustrating an operation of the undershoot detector of FIG. 10. 11B is a timing diagram illustrating operation of the burst clock generator of FIG. 10.

In FIG. 10, the undershoot detector 151 includes p-type transistors PMb1 and PMb2, n-type transistor NMb1, capacitors Cb1 and Cb2, variable resistor Rb1, resistor Rb2, and inverter INVx. ) And an active beta multiplier (1511). The active beta multiplier 1511 may include p-type transistors PMa1 and PMa2, n-type transistors NMa1 and NMa2, capacitors Ca1 and Ca2, and resistors Ra1 to Ra3.

10 and 11A, the self clock burst logic 150 may detect an undershoot of the output voltage Vout analogously without an external clock. For example, when the output voltage Vout drops at the first time point t1, the voltages of the nodes Na1, the nodes Nb1, the nodes Na4, and the nodes Nb4 drop. On the other hand, the voltages of the nodes Na2 and Na3 increase due to the influence of the resistors Ra1 and Ra2. When the voltage at the node Na2 increases, the p-type transistor PMb1 is turned off. When the voltage at the node Na3 increases, the n-type transistor NMb1 is turned on. When the n-type transistor NMb1 is turned on, the voltage of the node Nb2 is at a low level, and the voltage of the node Nb3 is at a high level by the inverter INVx. In other words, the selection signal S is changed to the high level.

When the output voltage Vout rises and recovers later, the voltages of the nodes Na1, Nb1, Na4 and Nb4 rise and the voltages of the nodes Na2 and Na3 are reversed. Descends. Therefore, after the output voltage Vout rises, the selection signal S is changed to the low level at the second time point t2. In addition, the p-type transistor PMb2 may be turned on by the preset enable signal EN. When the p-type transistor PMb2 is turned on, the voltage of the node Nb2 is forcibly changed to the high level, and the selection signal S may be lowered to the low level. That is, the selection signal S may be set to descend to a low level after a predetermined time through the enable signal EN.

10 and 11B, the self clock burst logic 150 may generate some accumulator input signals INacc [5: 8] and a burst clock CLKb based on the selection signal S. Referring to FIG. For example, its clock burst logic 150 may include a burst clock generator 152. The burst clock generator 152 may include p-type transistors BPM1 to BPM8, n-type transistors BNM11 to BNM18, BNM21 to BNM28, and inverters INV1 to INV8.

At the first time point t1, the voltage of the node Na2 is at a high level, so all of the p-type transistors BPM1 to BPM8 are turned off. Since the voltage at the node Na3 is at a high level, all of the n-type transistors BNM21 to BNM28 are turned on. Since the selection signal S is at a high level, the n-type transistor BNM11 is turned on. When the n-type transistor BNM11 is turned on, the voltage of the node Nc1 becomes low level. When the voltage of the node Nc1 becomes low level, the delay signal Q1 becomes high level after a specific time is delayed by the inverter INV1. The delay signals Q2 to Q8 may sequentially become high levels after the first time point t1 in the same manner as the delay signal Q1.

The burst clock generator 152 may include logic gates Ga1 to Ga4. For example, the logic gate Ga1 may receive the selection signal S and the delay signal Q2 and output the accumulator input signal INacc [5]. The logic gate Ga2 may receive the delay signal Q2 and the delay signal Q4 and output the accumulator input signal INacc [6]. The logic gate Ga3 may receive the delay signal Q4 and the delay signal Q6 and output the accumulator input signal INacc [7]. The logic gate Ga4 may receive the delay signal Q6 and the delay signal Q8 and output the accumulator input signal INacc [8]. As an example, the logic gates Ga1 to Ga4 may be XOR gates. The accumulator input signals INacc [5: 8] may be delivered to the accumulator 112 as a coarse bit signal for quickly recovering the output voltage Vout in burst mode Burst.

In addition, the burst clock generator 152 may include logic gates Gb1 to Gb7. For example, the logic gates Gb1 to Gb7 may generate a burst clock CLKb by performing a logic operation on the delay signals Q1 to Q8. The logic gate Gb1 may receive delay signals Q1 and Q2. The logic gate Gb2 may receive the delay signals Q3 and Q4. The logic gate Gb4 may receive the delay signals Q5 and Q6. The logic gate Gb5 may receive the delay signals Q7 and Q8. The logic gate Gb3 may receive an output of the logic gates Gb1 and Gb2. The logic gate Gb6 may receive an output of the logic gates Gb4 and Gb5. The logic gate Gb7 may receive outputs of the logic gates Gb3 and Gb6. In an embodiment, the logic gates Gb1, Gb2, Gb4, and Gb5 may be XOR gates, the logic gates Gb3 and Gb6 may be NOR gates, and the logic gate Gb7 may be NAND gates.

The burst clock CLKb may be generated to have a higher frequency than the low frequency clock CLKL received from the outside. The frequency of the burst clock CLKb may be adjusted according to the delay characteristics of the inverters INV1 to INV8. In FIG. 10, eight inverters INV1 to INV8 are illustrated as an example, but the number of inverters is not limited thereto. The number of clocks of the burst clock CLKb may be adjusted by adjusting the number of inverters included in the burst clock generator 152. Meanwhile, after the output voltage Vout rises, the selection signal S and the delay signals Q1 to Q8 may fall to the low level at the second time point t2.

As described above, the burst clock generator 152 may detect an undershoot of the output voltage Vout without using an external clock. In addition, the burst clock generator 152 may generate a selection signal S, some accumulator input signals INacc [5: 8], and a burst clock CLKb in response to the sensed output voltage Vout. Thus, rather than the burst logic 24 of FIG. 3 using an external clock, the burst clock generator 152 can reduce quiescent current.

12 is a circuit diagram illustrating another embodiment of its own clock burst logic of FIG. 7. Referring to FIG. 12, the self clock burst logic 150 may include an overshoot detector 151 and a burst clock generator 152. 13A is a timing diagram illustrating operation of the overshoot detector of FIG. 12. FIG. 13B is a timing diagram illustrating operation of the burst clock generator of FIG. 12.

In FIG. 12, the overshoot detector 151 includes a p-type transistor PMb1, n-type transistors NMb1 and NMb2, capacitors Cb1 and Cb2, a resistor Rb1, a variable resistor Rb2, and an inverter INVx. ) And an active beta multiplier 1511. The active beta multiplier 1511 may include p-type transistors PMa1 and PMa2, n-type transistors NMa1 and NMa2, capacitors Ca1 and Ca2, and resistors Ra1 to Ra3.

12 and 13A, the own clock burst logic 150 may analogously detect an overshoot of the output voltage Vout without an external clock. For example, when the output voltage Vout rises at the first time point t1, the voltages of the node Na1, the node Nb1, the node Na4, and the node Nb4 increase. On the other hand, the voltages of the nodes Na2 and Na3 are reduced by the influence of the resistors Ra1 and Ra2. When the voltage at the node Na2 falls, the p-type transistor PMb1 is turned on. When the voltage at the node Na3 falls, the n-type transistor NMb1 is turned off. When the p-type transistor PMb1 is turned on, the voltage of the node Nb2 becomes a high level. In other words, the selection signal S is changed to the high level.

Afterwards, when the output voltage Vout falls and recovers, on the contrary, the voltages of the nodes Na1, Nb1, Na4 and Nb4 fall, and the voltages of the nodes Na2 and Na3 are reduced. Rises. Therefore, when the output voltage Vout falls at the second time point t2, the selection signal S is changed to the low level. In addition, the n-type transistor NMb2 may be turned on by the preset reset signal RST. When the n-type transistor NMb2 is turned on, the node Nb2 is forcibly changed to the low level, and the selection signal S may be lowered to the low level. That is, the selection signal S may be set to descend to a low level after a predetermined time through the reset signal RST.

12 and 13B, the self clock burst logic 150 may generate some accumulator input signals INacc [5: 8] and a burst clock CLKb based on the selection signal S. Referring to FIG. For example, its clock burst logic 150 may include a burst clock generator 152. The burst clock generator 152 may include p-type transistors BPM11 to BPM18 and BPM21 to BPM28, n-type transistors BNM1 to BNM8, and inverters INV1 to INV7.

At the first time point t1, the voltage of the node Na2 is at a low level, so all of the p-type transistors BPM11 to BPM18 are turned on. Since the voltage at the node Na3 is at a low level, all of the n-type transistors BNM1 to BNM8 are turned off. Since the selection signal S is at the high level, the voltage at the node Nb3 is at the low level by the inverter INVx, and the p-type transistor BPM21 is turned on. When the p-type transistor BPM21 is turned on, the delay signal Q1 becomes a high level. The delay signal Q1 becomes a high level after a specific time delay is delayed by the inverter INVx than the selection signal S. The delay signals Q2 to Q8 may sequentially become high levels after the first time point t1 in the same manner as the delay signal Q1.

The burst clock generator 152 may include logic gates Ga1 to Ga4. For example, the logic gate Ga1 may receive the selection signal S and the delay signal Q2 and output the accumulator input signal INacc [5]. The logic gate Ga2 may receive the delay signal Q2 and the delay signal Q4 and output the accumulator input signal INacc [6]. The logic gate Ga3 may receive the delay signal Q4 and the delay signal Q6 and output the accumulator input signal INacc [7]. The logic gate Ga4 may receive the delay signal Q6 and the delay signal Q8 and output the accumulator input signal INacc [8]. As an example, the logic gates Ga1 to Ga4 may be XOR gates. The accumulator input signals INacc [5: 8] may be delivered to the accumulator 112 as a coarse bit signal for quickly recovering the output voltage Vout in burst mode Burst.

In addition, the burst clock generator 152 may include logic gates Gb1 to Gb7. For example, the logic gates Gb1 to Gb7 may generate a burst clock CLKb by performing a logic operation on the delay signals Q1 to Q8. The logic gate Gb1 may receive delay signals Q1 and Q2. The logic gate Gb2 may receive the delay signals Q3 and Q4. The logic gate Gb4 may receive the delay signals Q5 and Q6. The logic gate Gb5 may receive the delay signals Q7 and Q8. The logic gate Gb3 may receive an output of the logic gates Gb1 and Gb2. The logic gate Gb6 may receive an output of the logic gates Gb4 and Gb5. The logic gate Gb7 may receive outputs of the logic gates Gb3 and Gb6. In an embodiment, the logic gates Gb1, Gb2, Gb4, and Gb5 may be XOR gates, the logic gates Gb3 and Gb6 may be NOR gates, and the logic gate Gb7 may be NAND gates.

The burst clock CLKb may be generated to have a higher frequency than the low frequency clock CLKL received from the outside. The frequency of the burst clock CLKb may be adjusted according to the delay characteristics of the inverters INVx and INV1 to INV7. In FIG. 12, eight inverters INVx and INV1 to INV7 are illustrated as examples, but the number of inverters is not limited thereto. The number of clocks of the burst clock CLKb may be adjusted by adjusting the number of inverters included in the burst clock generator 152. Meanwhile, when the output voltage Vout rises at the second time point t2, the selection signal S and the delay signals Q1 to Q8 may fall to a low level.

As described above, the burst clock generator 152 may detect an overshoot of the output voltage Vout without using an external clock. In addition, the burst clock generator 152 may generate a selection signal S, some accumulator input signals INacc [5: 8], and a burst clock CLKb in response to the sensed output voltage Vout. Thus, rather than the burst logic 24 of FIG. 3 using an external clock, the burst clock generator 152 can reduce quiescent current.

14 is a diagram illustrating a relationship between a frequency and a standby current of a clock used in a burst mode for a digital LDO regulator according to an exemplary embodiment of the present invention. Referring to FIG. 14, a single clock scheme shows the quiescent current of the single-clock digital LDO regulator 10 of FIG. 1. The synchronous dual-clock scheme shows the quiescent current of the dual-clock digital LDO regulator 20 of FIG. The self-clocking scheme shows the quiescent current of the digital LDO regulator 100 according to the invention of FIG. 5. In the graph of FIG. 14, the vertical axis represents standby current and the horizontal axis represents the frequency of the clock used in the burst mode.

The single-clock digital LDO regulator 10 of FIG. 1 uses one external clock in the control logic regardless of variations in the output voltage. Thus, regardless of the mode of operation (there is practically no distinction between modes of operation), the control logic always operates using an external clock. The quiescent current of the single-clock digital LDO regulator 10 of FIG. 1 increases in proportion to the frequency of the external clock.

The dual-clock digital LDO regulator 20 of FIG. 3 receives and uses a low frequency clock and a high frequency clock from the outside. The dual-clock digital LDO regulator 20 of FIG. 3 uses a low frequency clock in the control logic in sleep mode. However, in order to detect variations in the output voltage, burst logic 24 still uses a high frequency clock. Thus, the quiescent current of the dual-clock digital LDO regulator 20 of FIG. 3 is less than the quiescent current of the single-clock digital LDO regulator 10 of FIG. 1 but still increases with the clock frequency of the burst mode.

The digital LDO regulator 100 according to the present invention can be used in the normal mode by receiving only a low frequency clock from the outside. The digital LDO regulator 100 may sense a change in the output voltage analogously through an active circuit including transistors without using an external clock to detect a change in the output voltage in the sleep mode. The digital LDO regulator 100 may generate a burst clock itself based on the variation of the sensed output voltage in burst mode. Accordingly, the digital LDO regulator 100 has a constant quiescent current in the normal mode or the sleep mode regardless of the frequency of the burst clock.

The table of FIG. 14 measures the quiescent current of each regulator using the same external clock (low frequency clock and high frequency clock). It can be seen that the standby current of the digital LDO regulator 100 according to the present invention is reduced by 98.6% than the standby current of the single-clock digital LDO regulator 10 of FIG. 1. It can be seen that the standby current of the digital LDO regulator 100 according to the present invention is reduced by 87% than the standby current of the dual-clock digital LDO regulator 20 of FIG. 3.

As described above, the embodiments are disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

10: Single-Clock Digital LDO Regulator
11, 21, 110: control logic
12, 22, 120: pass transistor array
20: Dual-Clock Digital LDO Regulator
23, 130: multiplexer
24: Burst Logic
100: digital LDO regulator
111: direction control logic
112: accumulator
140: clock control unit
141: trigger
142: clock generator
150: self clock burst logic
151: undershoot (overshoot) detector
152: Burst Clock Generator

Claims (16)

A pass transistor array configured to output an output voltage by adjusting an input voltage;
Control logic for generating a control bit for controlling the pass transistor array based on a difference between a reference voltage and the output voltage, and determining whether to operate based on a first clock generated from an externally received clock; And
Detects the voltage variation of the output voltage without using the externally received clock, and if the voltage variation occurs the frequency is higher than the first clock so that the control logic recovers the output voltage in response to the voltage variation. Self clock burst logic that generates a high second clock using the voltage variation,
And the control logic generates the control bit based on the second clock when the voltage variation occurs. The method of claim 1,
Further comprising a multiplexer for outputting the first clock or the second clock based on the selection signal,
And the control logic operates based on a clock output from the multiplexer. The method of claim 2,
The self clock burst logic includes a voltage variation detector for detecting the voltage variation,
And the voltage change detector generates the selection signal to output the second clock from a time point at which the voltage change occurs to a time point at which the output voltage is restored. The method of claim 3,
The self clock burst logic includes a burst clock generator that generates the second clock,
The burst clock generator generates delay signals that sequentially delay the selection signal according to a specific time interval corresponding to the frequency of the second clock,
The second clock is generated by a logic operation of the delay signals. The method of claim 4, wherein
The burst clock generator comprises a plurality of inverters,
The frequency of the second clock is adjusted according to the delay characteristics of the inverters. The method of claim 5,
The number of clocks of the second clock is adjusted according to the number of inverters. A pass transistor array configured to output an output voltage by adjusting an input voltage;
A clock controller which selects an operation mode by comparing a reference voltage and the output voltage and generates a normal clock based on an external clock received from the outside according to the selected operation mode;
Detects the voltage variation of the output voltage without using the external clock, and generates a burst clock having a higher frequency than the external clock using the voltage variation when the voltage variation occurs, and based on whether the voltage variation occurs Its own clock burst logic to generate a select signal;
A multiplexer for outputting the burst clock when the voltage variation occurs based on the selection signal and outputting the normal clock in other cases; And
A digital low drop-out (LDO) regulator including control logic that operates in accordance with a control clock output from the multiplexer and generates control bits for controlling the pass transistor array based on a difference between the reference voltage and the output voltage. . The method of claim 7, wherein
The control logic,
Direction control logic to generate an accumulator input signal and an accumulator direction signal based on the difference between the reference voltage and the output voltage; And
An accumulator for generating the control bits based on the accumulator input signal and the accumulator direction signal,
The accumulator input signal determines a magnitude that adjusts the output voltage,
The accumulator direction signal determines the increase or decrease of the output voltage. The method of claim 8,
The clock control unit,
A clock generator for generating a switching signal for determining an internal voltage used in said direction control logic and for generating said normal clock; And
And a trigger for generating an internal clock that determines whether the clock generator is operating based on a difference between the reference voltage and the output voltage and the accumulator direction signal. The method of claim 9,
If the difference between the reference voltage and the output voltage is greater than a preset offset voltage, the trigger outputs the internal clock equal to the external clock,
And when the difference between the reference voltage and the output voltage is less than the offset voltage, the trigger does not output the internal clock or outputs the internal clock having a low level. The method of claim 9,
When the difference between the reference voltage and the output voltage is greater than the preset offset voltage, the trigger operates in the normal mode,
And the trigger operates in a sleep mode when the difference between the reference voltage and the output voltage is less than the offset voltage. The method of claim 7, wherein
The self clock burst logic includes an undershoot detector for detecting a drop in the output voltage or an overshoot detector for detecting a rise in the output voltage. The method of claim 12,
The undershoot detector or the overshoot detector generates the select signal such that the multiplexer outputs the burst clock from a time point at which the voltage change occurs to a time point at which the output voltage recovers. The method of claim 13,
The self clock burst logic includes a burst clock generator that generates the burst clock according to a predetermined frequency,
The burst clock generator generates delay signals that sequentially delay the selection signal according to a specific time interval corresponding to the frequency of the burst clock,
The burst clock is generated by a logic operation of the delay signals. The method of claim 14,
The burst clock generator comprises a plurality of inverters,
The frequency of the burst clock is adjusted according to the delay characteristics of the inverters. The method of claim 15,
The number of clocks of the burst clock is adjusted according to the number of inverters.

Images