KR20230016746A - Formation method of silicide layer using the Excimer laser for the semiconductor devices - Google Patents

Abstract

Provided is an annealing method using an excimer laser and a semiconductor device using the same to provide a silicide layer that does not require a deposition and removal process of a laser absorption layer and can reduce gate, source, and drain junction resistance. The present research was supported by the overseas source technology commercialization technology development project research fund. (Task number: S3010291). The method includes the steps of: forming monosilicide through primary excimer laser annealing; and forming a polycrystalline silicide layer through secondary excimer laser annealing.

Description

Formation method of silicide layer using the Excimer laser for the semiconductor devices}

The present invention relates to a method for forming an ultra-low junction silicide layer using excimer laser annealing.

Recent semiconductor devices are facing a technical challenge of achieving high integration and miniaturization at the same time. As a way to solve this problem, interest in a technology for forming an ultra-shallow junction in the case of manufacturing a CMOS (Complementary Metal-Oxide Semiconductor) transistor is increasing.

However, as the junction depth required for ultra-low junctions becomes thinner, the gate resistance and junction resistance of junctions formed by conventional heating methods increase. In order to overcome this, the degree of attention to the annealing process using a laser is increasing even in the heat treatment process of a semiconductor device having a line width of 50 nm or less.

In existing semiconductor devices and transistors having a gate length of 100 μm or more, an ultra-low junction source/drain extension doped layer is formed on each inner side of the source and drain regions, After impurity ion implantation, the source/drain region and wiring resistance of the transistor device are reduced, and a group 8 metal element is deposited to perform a lamp-based rapid thermal process, thereby extending the source/drain doping layer and source /A method of activating the doping material and silicide in the drain region is used.

However, the above method suffers from economic problems in that the process steps are complicated and a number of expensive processes are involved. In addition, a commonly used laser annealing process can be advantageously applied to a manufacturing method of a transistor having a silicon gate, but when a metal gate is included on top of the silicon gate, the laser light absorption rate of the metal gate is high, so the metal gate melts first. There is a problem in that a phenomenon in which the shape is deformed occurs.

As a way to solve this problem, a one-time method of depositing a metallic or carbonaceous laser absorption layer on the entire surface of the substrate and removing it after laser annealing has been disclosed. There is a phenomenon that components remain, and there is a problem that it is difficult to apply the laser absorption layer of carbonaceous material other than a method of etching and removing it.

This research was supported by the overseas source technology commercialization technology development project research fund. (Task number: S3010291)

(0001) Republic of Korea Patent No. 10-0365414 (2001. 04. 30.) (0002) Republic of Korea Patent Publication No. 10-2017-0056748 (2015. 11. 13.)

In order to solve the above problems, the conventional 180 nm level junction thickness is further reduced and controlled to 100 nm level. It is an object to provide a formation method.

One aspect of the present invention for achieving the above object relates to a method of forming an ultra-low junction silicide layer on a substrate using an excimer laser.

In the above aspect, the forming method,

Depositing a gate insulating layer and amorphous silicon on a silicon wafer substrate;

Etching the amorphous silicon;

forming a first spacer on a side surface of the gate region;

implanting ions into the wafer substrate to form a source region;

implanting ions into the wafer substrate to form a drain region;

removing the primary spacer;

depositing a metal layer over the gate, source and drain regions;

forming a secondary spacer on a side surface of the gate region;

forming monosilicide through primary excimer laser annealing;

forming a polycrystalline silicide layer through secondary excimer laser annealing;

It may contain.

In the above aspect, the amorphous silicon deposition may be performed at 300 to 380°C.

In the above aspect, the secondary spacer may be made of any one or two or more selected from the group consisting of tungsten nitride, silicon nitride, polytetrafluoroethylene (PTFE), polyethyl ether ketone (PEEK), and nylon. there is.

In the above aspect, the metal layer may be made of any one selected from Ni, Pd, Pt, and Co.

In the above aspect, the monosilicide may include NiSi.

In the above aspect, the silicide layer of the polycrystalline structure may include NiSi ₂ .

In the above aspect, the excimer laser may use a wavelength in a deep ultra violet (DUV) region.

In the above aspect, the wavelength of the DUV region may be 180 to 320 nm.

In the above aspect, the pulse energy density of the excimer laser is 500 to 1200 mJ/cm ² , and the duration of each pulse may be 5 to 50 ns.

In the above aspect, the excimer laser may have a linear beam spot.

In the above aspect, the length of the long edge of the linear beam spot may be 5 to 30 mm, and the length of the short edge may be 0.1 to 1.0 mm.

In the above aspect, the annealing process may be performed at 350 to 450°C.

Another aspect of the present invention relates to a semiconductor device including an ultra-low junction silicide layer manufactured according to the method for forming the ultra-low junction silicide layer.

The method of forming a silicide layer using excimer laser annealing according to the present invention provides an ultra-low junction silicide layer that does not require deposition and removal of a laser absorption layer and can reduce gate, source, and drain junction resistance.

1 to 6 are schematic diagrams illustrating a process of forming an ultra-low junction silicide layer on a semiconductor using excimer laser annealing according to an embodiment of the present invention.
7 is a graph showing the depth of molten silicon according to the wavelength, scanning time, and energy density of an excimer laser.
8 is a graph showing the time for which molten silicon is maintained according to the wavelength, scanning time, and energy density of an excimer laser.
9 is a graph showing the energy density of an excimer laser measured while scanning an excimer laser onto a wafer.
10 is a graph showing an X-Ray Diffraction (XRD) spectrum of a bonding layer appearing during rapid heating and cooling.
11 is a graph showing an X-Ray Diffraction (XRD) spectrum of a bonding layer appearing during excimer laser annealing.
12 is a graph showing absorbance of silicon and a representative laser wavelength region together.

Hereinafter, a method of forming a silicide layer using excimer laser annealing according to the present invention will be described in detail. The drawings introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art. Therefore, the present invention may be embodied in other forms without being limited to the drawings presented below, and the drawings presented below may be exaggerated to clarify the spirit of the present invention. At this time, unless there is another definition in the technical terms and scientific terms used, they have meanings commonly understood by those of ordinary skill in the art to which this invention belongs, and the gist of the present invention in the following description and accompanying drawings Descriptions of well-known functions and configurations that may be unnecessarily obscure are omitted.

A method for forming a silicide layer using excimer laser annealing according to an embodiment of the present invention,

depositing a gate insulating layer and amorphous silicon on top of a silicon wafer substrate;

Etching the amorphous silicon;

forming a first spacer on a side surface of the gate region;

implanting ions into the semiconductor substrate to form a source region;

forming a drain region by implanting ions into the semiconductor substrate;

removing the primary spacer;

depositing a metal layer over the gate, source and drain regions;

forming a secondary spacer on a side surface of the gate region;

forming monosilicide through primary excimer laser annealing;

forming a polycrystalline silicide layer through secondary excimer laser annealing;

It may contain.

The gate insulating layer may be performed before the deposition of the amorphous silicon. The gate insulating layer may be polysilicon or silicate.

The amorphous silicon may be deposited by any one method selected from plasma enhanced chemical vapor deposition, sputtering, thermal vacuum, and electron beam, but is not necessarily limited thereto.

The amorphous silicon deposition may be performed at 250 to 400 °C. At this time, it may be preferably carried out at 280 to 380 ℃. Depositing at such a temperature is preferable because the deposition yield can be increased.

The primary spacers may be used to control ranges of the source and drain regions during ion implantation, and may be removed by anisotropic etching afterward.

The excimer laser may use a wavelength in a deep ultra violet (DUV) region. Specifically, an excimer laser having a wavelength range of 180 to 320 nm may be used. Excimer lasers satisfying the above wavelength range may be, for example, XeCl (308 nm), KrF (248 nm), and ArF (193 nm) lasers. At this time, it is preferable to use a KrF or XeCl laser because it can further lower the junction resistance of the semiconductor.

Pulse energy density of the excimer laser may be 500 to 1200 mJ/cm ² . When the pulse energy is too low, junctions are not formed well, resulting in high junction resistance. When the pulse energy is too high, junction resistance may increase, which is undesirable.

A pulse duration of the excimer laser may be 5 to 50 ns. As the pulse duration of the excimer laser increases, the melting time of the laser-scanned surface increases. If the excimer laser pulse continues for more than 50 ns, excessive melting may occur, which may damage materials other than the annealing target material. If the duration is less than 5 ns, it is not preferable because annealing is not sufficiently performed.

The excimer laser may have a linear beam spot. A linear beam spot has a high throughput, but has a disadvantage in that the beams overlap. However, in the present invention, the above disadvantages can be overcome by using a target material that does not easily deteriorate in performance due to a tempering phenomenon, which is a disadvantage that may occur due to overlapping beams.

In the above aspect, the length of the long edge of the linear beam spot may be 5 to 30 mm, and the length of the short edge may be 0.1 to 1.0 mm. The semiconductor yield can be increased by maintaining the beam spot size within this range.

In the above aspect, the annealing process may be performed at 350 to 550°C. By performing annealing in this temperature range, a silicide layer is formed in a section having the lowest resistivity, and a high-performance device using the silicide layer can be implemented.

The amorphous silicon may be transformed into crystalline polysilicon through the excimer laser annealing twice.

In the method of forming the ultra-low junction silicide layer, a detailed description of the material used therein and its role will be described later along with the following examples.

In addition, the present invention provides a semiconductor device including silicide manufactured according to the above forming method. A semiconductor including silicide according to the present invention is characterized by having low junction resistance.

A more detailed description of the junction resistance of the semiconductor device will be described later along with the following examples.

Hereinafter, a method of forming a silicide layer using excimer laser annealing according to the present invention will be described in more detail through examples. However, the following examples are only one reference for explaining the present invention in detail, but the present invention is not limited thereto, and may be implemented in various forms.

Also, unless defined otherwise, all technical and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description herein is merely to effectively describe specific embodiments and is not intended to limit the present invention. In addition, the unit of additives not specifically described in the specification may be % by weight.

1 to 6 are cross-sectional views illustrating a method of forming a silicide layer using excimer laser annealing according to an embodiment of the present invention, which will be described below.

Referring to FIG. 1, a device isolation film 5 defining a field region and an active region is formed on a silicon wafer substrate 4, and an N-well and a P-well are formed by a known method (N-well and P-well not shown). Next, the gate insulating layer 11 and the first spacer 6a are sequentially formed on the silicon wafer substrate 4, and then amorphous silicon 10 is deposited. Thereafter, impurities for generating source and drain regions are implanted.

In this case, the silicon wafer may be a single crystal wafer or a polycrystalline wafer, but is not necessarily limited thereto. The primary spacer may be made of one or two or more materials selected from the group consisting of silicon nitride, polytetrafluoroethylene (PTFE), polyethyl ether ketone (PEEK), and nylon. At this time, it is preferable to use Si ₃ N ₄ because it is easy to remove later.

Referring to FIG. 2 , it can be seen that a source region 21 and a drain region 31 are formed by impurity implantation. Next, the first spacer and a portion of the gate insulating layer 11 under the first spacer are selectively etched away and deposited to form a metal layer.

The metal layer may be made of any one element selected from Ni, Pd, Pt, and Co. Specifically, the element may be any one selected from group 8 elements, but in the present invention, an element such as Co may be included in addition to the group 8 elements described above.

In this case, the metal layer may be deposited to a thickness of 250 to 750 Å.

Referring to FIG. 3 , it can be seen that deposition is performed to form a gate region metal layer 13 , a source region metal layer 23 , and a drain region metal layer 33 . Next, secondary spacers 6b are formed on the side of the amorphous silicon 10 so that the metal layers 23/33 of the source/drain regions can be selectively annealed.

Referring to FIG. 4 , it can be seen that the range in which annealing of the metal layers 23/33 in the source/drain regions is possible is limited by forming the secondary spacers 6b. Thereafter, primary excimer laser annealing is performed.

The secondary spacer may be made of one or two or more materials selected from the group consisting of tungsten nitride, silicon nitride, polytetrafluoroethylene (PTFE), polyethyl ether ketone (PEEK), and nylon. In this case, the secondary spacer may be formed to a thickness of 500 to 1000 Å. By satisfying these conditions, it is possible to provide a secondary spacer excellent in thermal stability and electrical stability.

Referring to FIG. 5 , it can be seen that a gate region single crystal silicide layer 12a, a source region single crystal silicide layer 22a, and a drain region single crystal silicide layer 32a are formed after the first excimer laser annealing. Secondary excimer laser annealing is performed to convert the single crystal into a polycrystal.

The monosilicide may include NiSi. In this case, the monosilicide may refer to a compound composed of a transition metal and silicon atomic ratio of 1:1.

The silicide layer of the polycrystalline structure may include NiSi ₂ .

Referring to FIG. 6 , the gate insulating layer 11 , the gate region polycrystalline silicide layer 12 , and the crystalline polysilicon layer 14 form the gate 1 through secondary excimer laser annealing, and the source region 21 , the source region polycrystalline silicide layer 22 and the source region metal layer 23 form the source 2, and the drain region 31, the drain region polycrystalline silicide layer 32 and the drain region metal layer 33 form the drain region 3 ) can be formed.

Then, a semiconductor device having an ultra-low junction silicide layer is completed by performing a known subsequent process, for example, an interlayer insulating film formation, a contact formation, and a wiring process.

By performing the excimer laser annealing as described above, a semiconductor device having an ultra-low junction silicide layer can be provided at a low cost because there is no process of separately depositing and removing the laser absorption layer, unlike the previously known method of using a laser absorption layer. there is.

[Example 1-1]

After the gate, source, and drain regions were respectively formed on the silicon wafer in the same manner as described above, a Ni layer was deposited to a thickness of 500 Å. Then, tungsten nitride was deposited to a thickness of 800 Å to form secondary spacers.

Next, a KrF laser (248 nm) was adjusted to an energy density of 500 mJ/cm ² and primary annealing was performed for 30 ns. At this time, the laser was scanned as a linear beam spot with a long edge of 15 mm and a short edge of 0.5 mm.

Finally, a second annealing was performed under the same conditions as the first annealing to complete an ultra-low junction transistor.

[Examples 1-2 to 1-6]

All processes were performed in the same manner as in Example 1-1 except that the energy density of the KrF laser was changed as shown in Table 1 below.

[Comparative Example 1-1]

All processes were performed in the same manner as in Example 1-1 except that laser annealing was not performed.

[Comparative Examples 1-2 to 1-4]

All processes were performed in the same manner as in Example 1-1 except that the energy density of the KrF laser was changed as shown in Table 1 below.

[Example 2-1]

Gate, source, and drain regions were respectively formed on the silicon wafer as described above, and then a Ni layer was deposited to a thickness of 500 Å. Thereafter, tungsten nitride was deposited to a thickness of 800 Å to form secondary spacers.

Next, primary annealing was performed for 30 ns by adjusting the XeCl laser (308 nm) to an energy density of 500 mJ/cm ² . At this time, the laser was scanned as a linear beam spot with a long edge of 15 mm and a short edge of 0.5 mm.

Finally, a second annealing was performed under the same conditions as the first annealing to complete an ultra-low junction transistor.

[Examples 2-2 to 2-5]

All processes were performed in the same manner as in Example 2-1 except that the energy density of the XeCl laser was changed as shown in Table 1 below.

[Comparative Example 2-1]

All processes were performed in the same manner as in Example 2-1 except that laser annealing was not performed.

[Comparative Example 2-2]

All processes were performed in the same manner as in Example 2-1 except that the energy density of the XeCl laser was changed as shown in Table 1 below.

[Characteristic evaluation method]

A. Measurement of junction resistance

Bonding resistances according to energy densities of the excimer lasers used in the manufacture of the above Examples and Comparative Examples were measured and shown in Tables 1 and 2.

Comparative Example 1-1 Comparative Example 1-2 Comparative Example 1-3 Example 1-1 Example 1-2 Examples 1-3 Example 1-4 Example 1-5 Example 1-6 Comparative Example 1-4 KrF laser energy density
(mJ/cm ² ) 0 350 400 500 600 700 800 1000 1200 1300 junction resistance
(R _s , Ω) 18 23 61 44 21 20 19 23 35 56 Formation of silicide layer × × × ○ ○ ○ ○ ○ ○ ○

Table 1 shows the results of experiments using a KrF laser having a wavelength of 248 nm. Referring to this, bonding from Comparative Example 1-1 to Comparative Example 1-3 (400 mJ/cm ² ) in which laser annealing was not performed resistance tends to increase. However, this tendency disappears when the energy density of the laser exceeds 400mJ/cm ² , and in Example 1-1 (500mJ/cm ² ), the junction resistance starts to decrease remarkably, and in Example 1-2 (600mJ / cm ² ), it can be seen that low junction resistance is maintained.

At this time, in Examples 1-2 to 1-5, the low junction resistance is maintained, and in Comparative Example 1-5, which is a case where the energy density of the laser exceeds 1200mJ/cm ² , the junction resistance increases significantly again. so it was not desirable.

Comparative Example 2-1 Example 2-1 Example 2-2 Example 2-3 Example 2-4 Example 2-5 Comparative Example 2-2 XeCl laser energy density
(mJ/cm ² ) 0 500 600 800 1000 1200 1500 junction resistance
(R _s , Ω) 18 59 30 22 23 35 62 Formation of silicide layer × ○ ○ ○ ○ ○ ○

Table 2 shows the results of experiments using a XeCl laser with a wavelength of 308 nm. Referring to this, the junction resistance of Example 2-1 is relatively high at 59 Ω, but Examples 2-2 to 2-4 have a relatively high junction resistance of 31 , 22 and 23 Ω. In addition, Example 2-5 slightly rose to 35Ω, but it was not a problem level when applying the device, and the junction resistance of Comparative Example 2-2, which is a case where the energy density of the laser exceeds 1200mJ/cm ² , was 62Ω. A large rise was not desirable.

Summarizing the above results, when the energy density of the laser is less than 400mJ/cm ² and exceeds 1200mJ/cm ² , the junction resistance tends to increase significantly, and the junction resistance decreases and the reduced junction resistance is maintained. It can be seen that is greater than 400 and less than 1200 mJ/cm ² .

However, Comparative Example 1-1 and Comparative Example 2-1 in which laser annealing was not performed have lower junction resistance than all other Comparative Examples and Examples, but do not have a silicide layer, so when applied as a transistor device, their performance is very poor, which is not preferable. .

Referring to FIG. 7 of the present invention as a basis for predicting the above results, it is possible to grasp the relationship between the type of laser, the scanning time of the laser, the total amount of energy of the laser, and the maximum melting depth.

In addition, referring to FIG. 8 , the relationship between the type of laser, the scanning time of the laser, the total amount of energy of the laser, and the melting time can be grasped.

B. Analysis of the crystal structure of the silicide layer

The surface of the device subjected to RTA (rapid heat treatment process) and the surface of the device formed through KrF laser annealing according to the present invention were analyzed by X-ray diffraction, and the results are shown in FIGS. 10 and 11, respectively. showed up

As can be seen from FIG. 10 , crystalline states such as NiSi (monosilicide) and Ni ₃ Si ₂ were found below RTA 500° C. Such a crystal structure generally has a higher resistance value than the NiSi ₂ crystal structure provided in the embodiment of the present invention, which is not preferable.

On the other hand, as can be seen from FIG. 11, it can be confirmed that the NiSi ₂ crystal structure is formed only when the energy density of the laser is increased to 500 mJ/cm ² on the surface of the device subjected to KrF laser annealing.

Although the present invention has been described through specific details and limited examples as described above, this is only provided to help a more general understanding of the present invention, the present invention is not limited to the above examples, and the present invention belongs Various modifications and variations from these descriptions are possible to those skilled in the art.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and it will be said that not only the claims to be described later, but also all modifications equivalent or equivalent to these claims belong to the scope of the present invention. .

Claims (13)

forming a gate region by depositing a gate insulating layer and amorphous silicon on the silicon wafer substrate;
Etching the amorphous silicon;
forming a first spacer on a side surface of the gate region;
implanting ions into the silicon wafer substrate to form a source region;
forming a drain region by implanting ions into the silicon wafer substrate;
removing the primary spacer;
depositing a metal layer over the gate, source and drain regions;
forming a secondary spacer on a side surface of the gate region;
forming monosilicide through primary excimer laser annealing;
forming a silicide layer through secondary excimer laser annealing;
A method of forming an ultra-low junction silicide layer comprising: According to claim 1,
The method of forming the ultra-low junction silicide layer, wherein the amorphous silicon deposition is performed at 300 to 380 ° C. According to claim 1,
The secondary spacer is formed of one or two or more selected from the group consisting of tungsten nitride, silicon nitride, polytetrafluoroethylene (PTFE), polyethyl ether ketone (PEEK), and nylon. According to claim 1,
The method of forming the ultra-low junction silicide layer, characterized in that the metal layer is made of any one selected from Ni, Pd, Pt and Co. According to claim 1,
The method of forming an ultra-low junction silicide layer, characterized in that the monosilicide includes NiSi. According to claim 1,
The method of forming an ultra-low junction silicide layer, wherein the silicide layer includes NiSi ₂ . According to claim 1,
The method of forming an ultra-low junction silicide layer, characterized in that the excimer laser uses a wavelength in the DUV (Deep Ultra Violet) region. According to claim 7,
The method of forming an ultra-low junction silicide layer, characterized in that the wavelength of the DUV region is 180 to 320 nm. According to claim 7,
The pulse energy density of the excimer laser is 500 to 1200 mJ/cm ² , and the duration of each pulse is 5 to 50 ns. According to claim 7,
The method of forming an ultra-low junction silicide layer, characterized in that the excimer laser has a linear beam spot. According to claim 10,
The linear beam spot is a rectangular shape having a long edge of 5 to 30 mm and a short edge of 0.1 to 1.0 mm. According to claim 1,
The annealing process is performed at 350 to 550 ° C. A semiconductor device comprising an ultra-low junction silicide layer formed according to any one of claims 1 to 12.

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