KR20010061783A - Method for fabricating mos transistor - Google Patents

Abstract

PURPOSE: A method for manufacturing a metal-oxide-semiconductor(MOS) transistor is provided to prevent a gate oxide integrity(GOI) characteristic from being degraded by interfacial roughness, by minimizing variation of composition of poly-SiGe. CONSTITUTION: A gate oxide layer(2) is formed on a semiconductor substrate(1). A doped crystalline SiGe layer(5) and an amorphous silicon layer are formed on the gate oxide layer. An amorphous transition metal layer is formed on the amorphous silicon layer. A heat treatment process is performed to make the transition metal layer react with silicon so that a crystalline transition metal silicide layer(6) is formed on the crystalline SiGe layer. A hard mask(8) is formed on the transition metal silicide layer. The hard mask, the transition metal silicide layer, the crystalline SiGe layer and the gate oxide layer are patterned to form a gate electrode.

Description

Manufacturing method of MOS transistor {METHOD FOR FABRICATING MOS TRANSISTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS transistor of a semiconductor device. More specifically, the present invention relates to a MOS transistor having a poly-SiGe gate capable of improving the interface roughness between a poly-SiGe layer and a transition metal silicide layer and preventing a gate depletion effect. A method of manufacturing a transistor.

As the gate electrode material of the MOS transistor, a polysilicon film is most commonly used. The polysilicon film has high melting point, ease of forming a thin film, ease of forming a line pattern, stability to an oxidizing atmosphere, and smooth surface formation. This is because it has very excellent physical properties as a gate electrode.

However, since only the polysilicon film is directly applied to the gate electrode of the MOS transistor, since the resistance value is very high, it is applied to the gate by reducing the resistance value by containing dopants such as P, As, and B.

In applying a polysilicon gate to a CMOS transistor, the first n ⁺ polysilicon gate doped with n-type impurities was used as an NMOS transistor and a PMOS transistor. However, in such a CMOS transistor, a buried channel is formed in the PMOS transistor region so that the short channel effect is relatively increased. Accordingly, there is a problem that the threshold voltage of the device is reduced, and leakage current and drain induced barrier lowering (DIBL) are increased.

In order to solve the above problem, a CMOS transistor having a dual gate forming a p ⁺ polysilicon gate in a PMOS transistor region and an n ⁺ polysilicon gate in an NMOS transistor region has been proposed.

The CMOS transistor having such a dual gate can form a surface channel in the PMOS transistor region, but there is a problem in that a gate depletion effect and boron penetration occur in the PMOS transistor region.

The gate depletion effect is that the dopant present in the polysilicon gate diffuses into the upper gate layer in the subsequent heat treatment process, thereby increasing the resistance of the polysilicon film, thereby increasing the threshold voltage, and sufficient activation of the dopant in the gate electrode during the activation heat process. It does not mean that the electrical thickness of the gate insulating film increases.

The boron penetration phenomenon refers to a phenomenon in which boron present in the P ⁺ polysilicon film penetrates into the channel region through the gate insulating film to change the threshold voltage of the device and deteriorate GOI (gate oxide intergrity) characteristics.

Recently, active researches on next-generation gate electrode materials capable of forming surface channels in the PMOS transistor region and the MOS transistor region while solving the disadvantages of the polysilicon gate electrode have been conducted. Representative gate electrode materials include metal gates and poly-SiGe gates.

Metal gates include tungsten, tantalum, molybdenum, tungsten nitride, and titanium nitride, which can realize low resistance values and intermediate bandgap gates, and do not use dopants, resulting in no gate depletion effect and boron penetration. Although it has an excellent advantage, there was a problem that can not proceed the LDD oxidation process that must be performed essentially when forming the gate electrode.

Meanwhile, the poly-SiGe gate is a dual gate that can form a surface channel region in both the NMOS transistor and the PMOS transistor region, and at the same time, the low resistance value, gate depletion effect, and boron penetration phenomenon are reduced compared to conventional polysilicon. Has an advantage. In addition, poly-SiGe gates containing high concentrations of Ge are contained by containing high concentrations of Ge such that the Fermi energy level is located near the middle bandgap of silicon using the intrinsic properties of the Ge fraction, that is, the work function varies depending on the composition. It is possible to form a single gate electrode having a threshold voltage of symmetry.

However, as the high integration of the device proceeds rapidly, the gate width and gate resistance of the gate are greatly reduced. Therefore, there is a need for a new material and a laminated structure that can satisfy the above conditions, that is, a small gate line width and resistance value. Therefore, it is common to use a laminated structure of transition metal-silicide / posi-SiGe having low resistance even when manufacturing a MOS transistor having a poly-SiGe gate electrode.

1A to 1H illustrate a method of manufacturing a MOS transistor having a conventional poly-SiGe gate. Thermally growing a gate oxide film 2 on the semiconductor substrate 1 as shown in FIG. 1A, and then undoped the poly-SiGe layer 3 using chemical vapor deposition as shown in FIG. The polysilicon film 4 is continuously deposited in-situ.

As shown in FIG. 1C, the doped poly-SiGe layer 5 is formed by ion implanting n-type or p-type impurities into the poly-SiGe layer 3, and then as shown in FIG. 1D. A transition metal layer 7 for forming silicide is formed.

As shown in FIG. 1E, a rapid heat treatment (RTP) is performed to induce silicidation between the transition metal layer 7 and the polysilicon film 4 to form crystalline transition metal silicide 6.

As shown in FIG. 1F, an oxide film or a nitride film is deposited as a hard mask 8 for patterning the gate electrode, and then a photolithography process is performed as shown in FIG. 1G to transfer the hard mask 8 and the lower part thereof. The metal silicide layer 6, the doped poly-SiGe layer 5, and the gate oxide film 2 are etched to form a gate electrode.

As shown in FIG. 1H, a gate reoxidation process, which is an LDD oxidation process, is used to recover substrate damage generated in an etching process for forming a gate electrode and to prevent substrate damage during subsequent source / drain region formation. Is performed to thermally form the screen oxide film 9 on the substrate surface.

As shown in FIG. 1I, a self-aligned contact (SAC) is performed to form a source / drain region 14 to form a MOS transistor.

In the conventional method of manufacturing a MOS transistor, Budvik is induced in the gate oxide film present at the edge of the gate electrode during the reoxidation process, thereby minimizing the occurrence of overlap capacitance between the gate and the drain of the MOS transistor. By forming an oxide film on the sidewalls, the effect of removing fine residues remaining on the gate electrode after the etching process was simultaneously obtained.

However, when inducing a silicidation reaction between the transition metal and the doped polysilicon film by the rapid heat treatment process to form the transition metal silicide, the silicidation reaction is unevenly along the grain boundary of the polysilicon film. Generated, the roughness of the interface between the transition metal silicide layer 6 and the poly-SiGe layer 5 becomes poor.

After forming such a gate electrode, a subsequent thermal process such as a subsequent reoxidation process, an RTP process for forming a source / drain, and a flow process of a BPSG film for planarization is performed to produce a MOS transistor. At the interface between the silicide layer 6 and the poly-SiGe layer 5, the reaction between the transition metal and the silicon atom is further intensified, so that the composition of the poly-SiGe layer 5 is locally changed, and thus its work function is changed. There is a problem that the reproducibility of the device characteristics is lowered.

In addition, the roughness of the interface becomes even worse, and the transition metal passes through the poly-SiGe layer to the gate oxide film, thereby degrading the GOI characteristics and the dopant present in the poly-SiGe layer. The dopant is reduced by out-diffusion to the silicide layer, which causes an increase in the gate resistance value, that is, a gate depletion effect, thereby degrading the characteristics of the MOS transistor.

The present invention is to solve the problems of the prior art as described above, to minimize the change in the composition of the poly-SiGe to prevent the degradation of GOI characteristics due to the interfacial roughness of the MOS having a poly-SiGe gate using an amorphous silicon film It is an object of the present invention to provide a method for manufacturing a transistor.

1A to 1I illustrate a manufacturing process diagram of a MOS transistor having a poly-SiGe gate according to an embodiment of the present invention;

2A to 1I illustrate a manufacturing process diagram of a MOS transistor having a poly-SiGe gate according to another embodiment of the present invention;

4A to 4I are diagrams illustrating a manufacturing process of a MOS transistor having a poly-SiGe gate according to another embodiment of the present invention;

4A to 4I are diagrams illustrating a manufacturing process of a MOS transistor having a poly-SiGe gate according to another embodiment of the present invention;

(Explanation of symbols for the main parts of the drawing)

1 semiconductor substrate 2 gate oxide film

3: crystalline poly-SiGe layer 4: polysilicon film

5: doped crystalline poly-SiGe layer 6: crystalline transition metal silicide layer

7: amorphous transition metal layer 8: hard mask

9: screen mask 10: amorphous silicon layer

11: amorphous SiGe layer 12: doped amorphous SiGe layer

13 amorphous transition metal silicide layer 14 source / drain region

In order to achieve the above object of the present invention, the present invention comprises the steps of forming a gate oxide film on a semiconductor substrate; Forming a crystalline SiGe layer and an amorphous silicide layer on the gate oxide film; Forming an amorphous transition metal layer on the amorphous silicon layer; Performing a heat treatment process to react the transition metal with silicon to form a crystalline transition metal silicide layer on the crystalline SiGe; Forming a hard mask on the transition metal silicide layer; It provides a method of manufacturing a MOS transistor comprising a step of forming a gate electrode by patterning a hard mask and a transition metal silicide layer, a crystalline SiGe layer and a gate oxide film thereunder.

The crystalline SiGe layer and the amorphous silicon layer are each one of SiH ₄ or Si ₂ H ₆ gas and GeH ₄ gas as a source gas using one of HVCVD, LPCVD, or APCVD methods in a temperature range of 500 to 600 ° C. It is characterized in that the deposition to a thickness of 500-1500Å.

The method of forming the doped crystalline SiGe layer is to form a crystalline SiGe layer and then ion implanted n-type or p-type dopant with a dose of 2.0-5.0x10 ¹⁵ / cm 2 to form a doped crystalline SiGe layer or Or the doped crystalline SiGe layer is deposited by an in-situ method by adding a source gas containing a dopant.

The amorphous transition metal layer is deposited to a thickness of 300 to 800 kPa by physical vapor deposition, and the transition metal is characterized by using one of tungsten, cobalt, nickel, titanium.

The heat treatment is characterized in that the RTP process is carried out for 10-30 seconds at a temperature of 750-900 ° C. under a nitrogen atmosphere or the furnace annealing is carried out at a temperature of 650-850 ° C. for 30-60 minutes under a nitrogen atmosphere.

The hard mask is characterized in that to form one of the oxide film or nitride film to a thickness of 900 to 1200Å.

Forming the gate electrode, and then performing a reoxidation process to form a screen oxide film on the sidewall of the gate and the substrate to a thickness of 30 to 100 kPa at a temperature of 650 to 850 캜; The method may further include forming a source / drain region in the substrate through a self-aligned contact method.

The present invention also provides a process for forming a gate oxide film on a semiconductor substrate; Forming a doped amorphous SiGe layer and an amorphous silicon layer on the gate oxide film; Forming an amorphous transition metal layer on the amorphous silicon layer; Performing a heat treatment process to react the transition metal with silicon to form a crystalline transition metal silicide layer on the crystalline SiGe; Forming a hard mask on the transition metal silicide layer; It provides a method of manufacturing a MOS transistor comprising a step of forming a gate electrode by patterning a hard mask and a transition metal silicide layer, a crystalline SiGe layer and a gate oxide film thereunder.

The present invention also provides a process for forming a gate oxide film on a semiconductor substrate; Forming a doped SiGe layer on the gate oxide film; Forming an amorphous transition metal silicide layer; Performing a heat treatment process to form a crystalline transition metal silicide layer on the crystalline SiGe; Forming a hard mask on the transition metal silicide layer; It provides a method of manufacturing a MOS transistor comprising a step of forming a gate electrode by patterning a hard mask and a transition metal silicide layer, a crystalline SiGe layer and a gate oxide film thereunder.

The SiGe layer is deposited in an amorphous state or a crystalline state in a temperature range of 500 to 550 ° C. or less by using one of SiH ₄ or Si ₂ H ₆ gas and GeH ₄ gas as a source gas using one of HVCVD, LPCVD, or APCVD methods. Characterized in that.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2I illustrate a method of manufacturing a MOS transistor having a poly-SiGe gate according to a first embodiment of the present invention. In the method of manufacturing a MOS transistor having a poly-SiGe gate according to the first embodiment, an amorphous silicon layer is formed on a crystalline poly-SiGe layer, and then a silicidation process is performed to form a crystalline transition metal-silicide layer. Way.

A gate oxide film 2 is grown on a silicon substrate, which is a semiconductor substrate 1, as shown in FIG. 2A, and then high vacuum CVD, low pressure CVD, or atmospheric pressure as shown in FIG. 2B. (atmospheric pressure) SiH ₄ or Si ₂ H ₆ and GeH ₄ gas as a source gas by CVD method, the poly-SiGe layer 3 and the amorphous silicon layer 10 in a continuous in-situ method of 500 to 1500 각각 respectively. To be deposited.

In this case, the SiGe layer 3 is deposited in a crystalline state, and the silicon layer 10 is deposited in an in-situ method in a temperature range of 500 to 600 ° C. so as to be amorphous. This is because the minimum temperature value that can be deposited in the crystalline state or the maximum temperature value that can be deposited in the amorphous state is lower than that of the silicon layer 10 so that the SiGe layer 3 has a lower temperature. When the deposition temperature is set between the temperature values, the laminated thin film of the SiGe layer 10 in the crystalline state and the silicon layer 10 in the amorphous state can be formed in situ.

As illustrated in FIG. 2C, n-type impurities such as P or As ions or p-type impurities such as B ions are ion-implanted into the poly-SiGe layer 3 to form a doped poly-SiGe layer 5.

At this time, the impurity ion implantation process has a dose of 2.0-5.0x10 ¹⁵ / cm 2, and the ion implantation energy is set such that the ion implanted dopant is present only in the poly-SiGe layer 3.

Instead of depositing the undoped poly-SiGe layer (3) as described above, followed by an ion implantation process to form the doped poly-SiGe layer (5), the dopant element is contained when the poly-SiGe layer is deposited. The source gas may be further injected to form an in-situ doped poly-SiGe layer 5.

As shown in FIG. 2D, an amorphous transition metal layer 7 is formed on the amorphous silicon layer 10 to have a thickness of 300 to 800 μm using physical vapor deposition. Here, as the transition metal, tungsten silicide (WSi ₂ ), titanium silicide (TiSi ₂ ), in a subsequent silicidation process using tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), etc. Transition metal-silicide layers such as cobalt silicide (CoSi ₂ ) and nickel silicide (NiTi) are formed.

As shown in FIG. 2E, a low-resistance crystalline transition metal-silicide layer is induced by inducing silicidation reaction between the transition metal and amorphous silicon by performing the RTP process under a nitrogen atmosphere for 10-30 seconds at a temperature range of 750-900 ° C. (6) is formed. At the same time, the dopant implanted into the poly-SiGe layer 5 is activated.

In order to form the transition metal silicide layer, instead of the RTP process, a furnace anneal may be formed under a nitrogen atmosphere for 30 to 60 minutes in a temperature range of 650 to 850 ° C.

As shown in FIG. 2F, an oxide film or a nitride film is deposited to a thickness of 900 to 1200 로서 as a hard mask 8 for the gate electrode patterning, and a photolithography process is performed to show the hard mask 8 and the hard mask 8. The bottom transition metal-silicide layer 6, the doped poly-SiGe layer 5 and the gate oxide film 2 are etched to form a gate electrode.

As shown in FIG. 2H, the LDD oxidation process, that is, the reoxidation process, is carried out at a temperature of 650-850 ° C. to deposit the screen mask 9 on the sidewalls of the silicon substrate 1 and the gate electrode at a thickness of 30 to 100 μs. As shown in FIG. 2I, a MOS transistor is fabricated by forming a source / drain region 14 by performing a self-aligned contact process.

3A to 3I illustrate a method of manufacturing a MOS transistor having a poly-SiGe gate according to a second embodiment of the present invention. In the method of manufacturing a MOS transistor having a poly-SiGe gate according to the second embodiment, an amorphous silicon layer is formed on an SiGe layer in an amorphous state, and then a silicidation process is performed to form a crystalline transition metal-silicide on a crystalline SiGe layer. It is a method of forming a layer.

A gate oxide film 2 is grown on a silicon substrate, which is a semiconductor substrate 1, as shown in FIG. 3A, and then high vacuum CVD, low pressure CVD, or atmospheric pressure as shown in FIG. 3B. (atmospheric pressure) SiH ₄ or Si ₂ H ₆ and GeH ₄ gas as a source gas by the CVD method, the thickness of 500 to 1500 kPa in the in-situ method of the amorphous SiGe layer 11 and the amorphous silicon layer 10, respectively, continuously To be deposited.

At this time, when the thin film is deposited, the SiGe layer 3 and the silicon layer 10 are deposited by an in-situ method at a temperature of 500 to 550 ° C. or less so as to be in an amorphous state. Therefore, when the amorphous SiGe layer 11 and the silicon layer 10 are crystallized by a subsequent heat treatment process, a crystalline SiGe layer and a silicon layer having relatively large grains are formed. Accordingly, the gate depletion effect due to out-diffusion of the dopant in the doped poly-SiGe layer can be minimized by reducing the grain boundary area in the thin film.

As shown in FIG. 3C, n-type impurities such as P or As ions or p-type impurities such as B ions are implanted into the amorphous SiGe layer 11 to form a doped SiGe layer 12.

At this time, the impurity ion implantation process has a dose of 2.0-5.0 × ^{10 15} / cm 2, and the ion implantation energy is set such that the ion implanted dopant is present only in the SiGe layer 12.

Instead of depositing the undoped SiGe layer 11 and then performing an ion implantation process to form the doped SiGe layer 12, a source gas containing a dopant element is deposited when the amorphous SiGe layer is deposited. Further implantation may be performed to form an in-situ doped SiGe layer 12.

As shown in FIG. 3D, an amorphous transition metal layer 7 is formed on the amorphous silicon layer 10 to have a thickness of 300 to 800 μm using physical vapor deposition. Here, as the transition metal, tungsten silicide (WSi ₂ ), titanium silicide (TiSi ₂ ), in a subsequent silicidation process using tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), etc. Transition metal-silicide layers such as cobalt silicide (CoSi ₂ ) and nickel silicide (NiTi) are formed.

As shown in FIG. 3E, a low-resistance crystalline transition metal-silicide layer is formed by inducing a silicidation reaction between the transition metal and the amorphous silicon by performing the RTP process at a temperature range of 750-900 ° C. for 10-30 seconds under a nitrogen atmosphere. (6) is formed. In addition, the amorphous SiGe layer is crystallized with the poly-SiGe layer 5, and the dopant implanted therein is activated.

In order to form the transition metal silicide layer, instead of the RTP process, a furnace anneal may be formed under a nitrogen atmosphere for 30 to 60 minutes in a temperature range of 650 to 850 ° C.

As shown in FIG. 3F, an oxide film or a nitride film is deposited to have a thickness of 900 to 1200 로서 as a hard mask 8 for the gate electrode patterning, and a photolithography process is performed as shown in FIG. 3G. The bottom transition metal-silicide layer 6, the doped poly-SiGe layer 5 and the gate oxide film 2 are etched to form a gate electrode.

As shown in FIG. 3H, the LDD oxidation process is performed at a temperature of 650-850 ° C. to deposit a screen mask 9 on the sidewalls of the silicon substrate 1 and the gate electrode at a thickness of 30 to 100 microseconds, and as shown in FIG. 3I. As described above, a MOS transistor is manufactured by forming a source / drain region 14 by performing a self-aligned contact process.

4A to 4I illustrate a method of manufacturing a MOS transistor having a poly-SiGe gate according to a third embodiment of the present invention. In the method of manufacturing a MOS transistor having a poly-SiGe gate according to the third embodiment, an amorphous transition metal silicide layer is formed on an amorphous SiGe layer, and then subjected to a heat treatment process to form a crystalline transition metal silicide on the crystalline SiGe layer. It is a method of forming a layer.

A gate oxide film 2 is grown on a silicon substrate, which is a semiconductor substrate 1, as shown in FIG. 4A, and then high vacuum CVD, low pressure CVD, or atmospheric pressure as shown in FIG. 4B. (atmospheric pressure) An amorphous SiGe layer 11 is deposited to a thickness of 500 to 1500 kPa using SiH ₄ or Si ₂ H ₆ and GeH ₄ gas as a source gas by a CVD method.

At this time, when the thin film is deposited, the SiGe layer 3 is deposited at a temperature of 500 to 550 ° C. or less so as to be in an amorphous state. Here, the SiGe layer may be deposited at a deposition temperature of 500-550 ° C. or higher to form a poly-SiGe layer having a crystal structure.

As shown in FIG. 4C, n-type impurities such as P or As ions or p-type impurities such as B ions are ion-implanted into the poly-SiGe layer 3 to form a doped SiGe layer 12.

At this time, the impurity ion implantation process has a dose of 2.0-5.0x10 ¹⁵ / cm 2, and the ion implantation energy is set such that the ion implanted dopant is present only in the SiGe layer 11.

As described above, instead of forming the doped SiGe layer 12 by depositing the undoped SiGe layer 11 and then performing an ion implantation process, an additional source gas containing a dopant element is injected when the SiGe layer is deposited. To form an in-situ doped SiGe layer 12.

As shown in FIG. 4D, an amorphous transition metal silicide layer 13 is formed on the amorphous SiGe layer 12 to a thickness of 500 to 1500 kV by physical vapor deposition using a compound target having a desired composition. Here, tungsten silicide (WSi ₂ ), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ), nickel silicide (NiTi) and the like are used as the transition metal silicide layer.

As shown in FIG. 4E, the crystalline transition metal silicide layer 6 is formed by crystallizing the amorphous transition metal silicide layer by performing the RTP process under a nitrogen atmosphere at a temperature range of 750-900 ° C. for 10-30 seconds. . In addition, the amorphous doped SiGe layer 12 becomes a poly-SiGe layer 5 having a crystalline structure, and the dopant implanted therein is activated.

In the third embodiment of the present invention, only the crystallization of the amorphous transition metal silicide layer to the crystalline transition metal silicide layer in the RTP process induces the silicidation between the transition metal and the silicon layer to form a crystalline transition metal silicide. In comparison with this case, a better interface between the transition metal silicide layer and the poly-SiGe layer can be obtained.

Instead of the RTP process, the furnace annealing can be carried out under a nitrogen atmosphere for 30-60 minutes at a temperature of 650-860 ° C.

As shown in FIG. 4F, an oxide film or a nitride film is deposited to a thickness of 900 to 1200 로서 as a hard mask 8 for gate electrode patterning, and a photolithography process is performed to show the hard mask 8 as shown in FIG. 4G. And the lower transition metal-silicide layer 6, the doped poly-SiGe layer 5, and the gate oxide film 2 are etched to form a gate electrode.

As shown in FIG. 4H, an LDD oxidation process is performed at a temperature of 650-850 ° C. to deposit a screen mask 9 on the sidewalls of the silicon substrate 1 and the gate electrode to a thickness of 30 to 100 microseconds, as shown in FIG. 4I. As described above, a MOS transistor is manufactured by forming a source / drain region 14 by performing a self-aligned contact process.

According to the manufacturing method of the MOS transistor having a poly-SiGe gate of the present invention as described above, as follows.

Firstly, instead of using a conventional crystalline silicon layer, an amorphous silicon layer is formed and then a silicidation with the transition metal layer is formed to form a transition metal silicide layer, thereby forming an interface roughness between the poly-SiGe layer and the transition metal silicide layer. It can be improved, and there is an advantage that can prevent GOI properties deterioration by preventing a change in the composition of the poly-SiGe layer formed under the transition metal silicide layer.

Secondly, after forming the amorphous silicon layer, subsequent silicidation with the transition metal layer is performed by subsequent heat treatment to form a crystalline transition metal silicide layer, thereby reducing the area of the grain boundary than the conventional crystalline transition metal silicide layer. By preventing the diffusion of the dopant doped into the transition metal silicide layer doped in the poly-SiGe layer, there is an advantage that can prevent the gate depletion effect.

Third, as described above, there is an advantage in that a highly integrated MOS transistor having excellent and stable gate characteristics can be manufactured by improving the interface roughness between the poly-SiGe layer and the transition metal silicide layer and preventing the gate depletion effect.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (39)

Forming a gate oxide film on the semiconductor substrate; Forming a crystalline SiGe layer and an amorphous silicide layer on the gate oxide film; Forming an amorphous transition metal layer on the amorphous silicon layer; Performing a heat treatment process to react the transition metal with silicon to form a crystalline transition metal silicide layer on the crystalline SiGe; Forming a hard mask on the transition metal silicide layer; And forming a gate electrode by patterning a hard mask and a transition metal silicide layer below, a crystalline SiGe layer, and a gate oxide film. The method of claim 1, wherein the crystalline SiGe layer and the amorphous silicon layer are successively formed in-situ using one of HVCVD, LPCVD, and APCVD methods. The method of claim 2, wherein the crystalline SiGe layer and the amorphous silicon layer of the SiH ₄ or Si ₂ H ₆ gas and GeH ₄ gas source gas 500 to 600 ℃ each in a thickness range of 500-1500Å A method for producing a MOS transistor, characterized in that for depositing. The method of claim 1, wherein the method of forming the doped crystalline SiGe layer to form a crystalline SiGe layer and then ion-implanted an n-type or p-type dopant to form a doped crystalline SiGe layer, characterized in that Method for manufacturing a transistor. The method of claim 4, wherein the dopant is ion-implanted into a crystalline SiGe layer with a dose of 2.0-5.0 × ^{10 15} / cm 2. The method of claim 1, wherein the doped crystalline SiGe layer is deposited in-situ by adding a source gas containing a dopant. The method of claim 1, wherein the amorphous transition metal layer is deposited to a thickness of 300 to 800 Å by physical vapor deposition. The method of claim 7, wherein tungsten, cobalt, nickel, or titanium is used as the transition metal for the transition metal layer. The method of claim 1, wherein the heat treatment is performed for 10-30 seconds at a temperature of 750-900 ° C. under a nitrogen atmosphere. The method of claim 1, wherein the heat treatment is performed for 30 to 60 minutes at a temperature of 650-850 ° C. under a nitrogen atmosphere. The method of claim 1, wherein the hard mask is formed of an oxide film or a nitride film having a thickness of 900 to 1200 Å. The method of claim 1, further comprising: forming a screen oxide film on the sidewalls of the gate and the substrate by performing a reoxidation process after forming the gate electrode; And forming a source / drain region in the substrate through a self-aligned contact method. The method of claim 12, wherein the screen oxide film is deposited at a thickness of 30 to 100 kPa at a temperature of 650 to 850 ℃. Forming a gate oxide film on the semiconductor substrate; Forming a doped amorphous SiGe layer and an amorphous silicon layer on the gate oxide film; Forming an amorphous transition metal layer on the amorphous silicon layer; Performing a heat treatment process to react the transition metal with silicon to form a crystalline transition metal silicide layer on the crystalline SiGe; Forming a hard mask on the transition metal silicide layer; And forming a gate electrode by patterning a hard mask and a transition metal silicide layer below, a crystalline SiGe layer, and a gate oxide film. The method of claim 14, wherein the amorphous SiGe layer and the amorphous silicon layer are successively formed in-situ using one of HVCVD, LPCVD, and APCVD methods. The method of claim 15, wherein the amorphous SiGe layer and the amorphous silicon layer is a thickness of 500 to 1500Å each in a temperature range of 500 to 550 ℃ or less using one of SiH ₄ or Si ₂ H ₆ gas and GeH ₄ gas source gas Method of manufacturing a MOS transistor characterized in that the deposition. 15. The method of claim 14, wherein the doped amorphous SiGe layer is formed by forming an amorphous SiGe layer followed by ion implantation of an n-type or p-type dopant to form a doped amorphous SiGe layer. Method for manufacturing a transistor. The method of claim 17, wherein the dopant is implanted into the amorphous SiGe layer with a dose of 2.0-5.0 × ^{10 15} / cm 2. 15. The method of claim 14, wherein the doped amorphous SiGe layer is deposited in-situ by adding a source gas containing a dopant. 15. The method of claim 14, wherein the amorphous transition metal layer is deposited to a thickness of 300 to 800 Å by physical vapor deposition. The method of claim 20, wherein tungsten, cobalt, nickel, or titanium is used as the transition metal for the transition metal layer. The method of claim 14, wherein the heat treatment is performed for 10-30 seconds at a temperature of 750-900 ° C. under a nitrogen atmosphere. 15. The method of claim 14, wherein the heat treatment is performed for 30-60 minutes in a furnace anneal at a temperature of 650-850 ℃ under a nitrogen atmosphere. 15. The method of claim 14, wherein the hard mask forms one of an oxide film and a nitride film in a thickness of 900 to 1200 kW. 15. The method of claim 14, further comprising: forming a screen oxide film on the sidewalls of the gate and the substrate by performing a reoxidation process after forming the gate electrode; And forming a source / drain region in the substrate through a self-aligned contact method. 27. The method of claim 25, wherein the screen oxide film is deposited to a thickness of 30 to 100 kPa at a temperature of 650 to 850 ° C. Forming a gate oxide film on the semiconductor substrate; Forming a doped SiGe layer on the gate oxide film; Forming an amorphous transition metal silicide layer; Performing a heat treatment process to form a crystalline transition metal silicide layer on the crystalline SiGe; Forming a hard mask on the transition metal silicide layer; A method of manufacturing a MOS transistor, comprising: forming a gate electrode by patterning a hard mask and a transition metal silicide layer, a crystalline SiGe layer, and a gate oxide film thereon. The method of claim 27, wherein the SiGe layer is amorphous in a temperature range of 500 to 550 ° C. or less by using one of SiH ₄ or Si ₂ H ₆ gas and GeH ₄ gas as a source gas using one of HVCVD, LPCVD, and APCVD methods. A method for manufacturing a MOS transistor, characterized in that the deposition in the state. 28. The crystalline state of claim 27, wherein the SiGe layer is formed of one of SiH ₄ or Si ₂ H ₆ gas and GeH ₄ gas by source gas using one of HVCVD, LPCVD, and APCVD methods. Method of manufacturing a MOS transistor characterized in that the deposition. 30. The method of claim 28 or 29, wherein the doped SiGe layer is formed by forming a crystalline SiGe layer followed by ion implantation of an n-type or p-type dopant to form a doped crystalline SIGe layer of 500-1500Å. Forming a MOS transistor. The method of claim 31, wherein the dopant is implanted into the crystalline SiGe layer with a dose of 2.0-5.0 × ^{10 15} / cm 2. 30. The method of claim 28 or 29, wherein the doped SiGe layer is deposited to a thickness of 500-1500 kV in-situ by adding a source gas containing a dopant. 28. The method of claim 27, wherein the transition metal silicide layer is deposited to a thickness of 500 to 1500 kW by physical vapor deposition. 34. The method of claim 33, wherein the transition metal silicide layer uses one of tungsten silicide, cobalt silicide, nickel silicide, and titanium silicide. 28. The method of claim 27, wherein the heat treatment is performed for 10-30 seconds at a temperature of 750-900 ° C. under a nitrogen atmosphere. 29. The method of claim 27, wherein the heat treatment is performed for 30-60 minutes at a temperature of 650-850 ° C. under a nitrogen atmosphere. 28. The method of claim 27, wherein the hard mask forms one of an oxide film and a nitride film in a thickness of 900 to 1200 kW. 30. The method of claim 27, further comprising: forming a screen oxide film on the sidewalls of the gate and the substrate by performing a reoxidation process after forming the gate electrode; And forming a source / drain region in the substrate through a self-aligned contact method. The method of claim 38, wherein the screen oxide film is deposited to a thickness of 30 to 100 kPa at a temperature of 650 to 850 ℃.