KR20030003380A - Poly SiGe Gate Electrode and Method of Manufacturing the Same - Google Patents

Poly SiGe Gate Electrode and Method of Manufacturing the Same Download PDF

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KR20030003380A
KR20030003380A KR1020010039117A KR20010039117A KR20030003380A KR 20030003380 A KR20030003380 A KR 20030003380A KR 1020010039117 A KR1020010039117 A KR 1020010039117A KR 20010039117 A KR20010039117 A KR 20010039117A KR 20030003380 A KR20030003380 A KR 20030003380A
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layer
amorphous silicon
gate electrode
poly sige
forming
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KR1020010039117A
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Korean (ko)
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차한섭
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주식회사 하이닉스반도체
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Publication of KR20030003380A publication Critical patent/KR20030003380A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A poly Si-Ge gate electrode and a method for fabricating the same are provided to prevent roughness of a surface by forming an amorphous silicon buffer layer under a poly Si-Ge layer and improve a characteristic of salicide by forming an amorphous silicon layer on the poly Si-Ge layer. CONSTITUTION: A gate oxide layer(20) is formed on an upper portion of a semiconductor substrate(10). An amorphous silicon buffer layer(30) is formed on an upper portion of a gate oxide layer(20). A poly SiGe layer(40) is formed on an upper portion of the amorphous silicon buffer layer(30). An amorphous silicon layer(50) is formed on an upper portion of the poly SiGe layer(40). A gate electrode is formed by patterning and etching a gate electrode pattern.

Description

폴리 ＳｉＧｅ 게이트 전극 및 그 제조 방법{Poly SiGe Gate Electrode and Method of Manufacturing the Same}Poly SiGe Gate Electrode and Method of Manufacturing the Same

본 발명은 게이트 전극 및 그 제조 방법에 관한 것으로서, 특히 비정질 실리콘 버퍼층을 이용한 폴리 SiGe 게이트 및 그 제조 방법에 관한 것이다.The present invention relates to a gate electrode and a method for manufacturing the same, and more particularly to a poly SiGe gate using an amorphous silicon buffer layer and a method for manufacturing the same.

종래의 폴리실리콘 전극은 보론 페너트레이션에 문제점이 있어 폴리 SiGe 게이트 전극이 사용되는데, 폴리 SiGe 게이트는 Ge의 농도가 증가할수록 표면이 거칠어진다는 문제점이 있으며, 폴리 SiGe층 상부에 샐리사이드를 형성하기 어렵다는 문제점이 있었다.The conventional polysilicon electrode has a problem in boron penetration, so a poly SiGe gate electrode is used, and the poly SiGe gate has a problem that the surface becomes rough as the concentration of Ge increases, and a salicide is formed on the poly SiGe layer. There was a problem that was difficult to do.

본 발명은 이러한 문제를 해결하기 위해 폴리 SiGe층 하부에 비정질 실리콘 버퍼층을 형성하여 표면이 거칠어 지는 것을 방지하고 폴리 SiGe층 상부에 비정질 실리콘층을 형성하여 샐리사이드 특성이 향상되는 폴리 SiGe 게이트 전극 및 그 제조 방법을 제공하는 것을 그 목적으로 한다.In order to solve this problem, the present invention provides an amorphous silicon buffer layer under the poly SiGe layer to prevent the surface from being rough, and forms an amorphous silicon layer on the poly SiGe layer to improve the salicide properties and the poly SiGe gate electrode. It aims at providing the manufacturing method.

도 1a 내지 도 1e는 본 발명에 따른 폴리 SiGe 게이트 전극의 제조 방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method of manufacturing a poly SiGe gate electrode according to the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10 : 반도체 기판20 : 게이트 산화막10 semiconductor substrate 20 gate oxide film

30 : 비정질 실리콘 버퍼층40 : 폴리 SiGe층30 amorphous silicon buffer layer 40 poly SiGe layer

50 : 비정질 실리콘층50: amorphous silicon layer

본 발명에 따른 폴리 SiGe 게이트 전극을 형성하는 방법은 반도체 기판 상부에 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막의 상부에 비정질 실리콘 버퍼층을 형성하는 단계와, 상기 비정질 실리콘 버퍼층의 상부에 폴리 SiGe층을 형성하는 단계와, 상기 폴리 SiGe층의 상부에 비정질 실리콘층을 형성하는 단계 및 게이트 전극 패턴을 패터닝하여 식각하는 단계를 포함하는 특징으로 한다.A method of forming a poly SiGe gate electrode according to the present invention includes forming a gate oxide film on a semiconductor substrate, forming an amorphous silicon buffer layer on the gate oxide film, and forming a poly SiGe layer on the amorphous silicon buffer layer. And forming an amorphous silicon layer on the poly SiGe layer, and etching the patterned gate electrode pattern.

또한 본 발명에 따른 폴리 SiGe 게이트 전극은 반도체 기판과, 상기 반도체 기판 상부의 소정 영역에 형성되는 게이트 산화막과, 상기 게이트 산화막의 상부에 형성되는 비정질 실리콘 버퍼층과, 상기 비정질 실리콘층의 상부에 형성되는 폴리 SiGe층 및 상기 폴리 SiGe층의 상부에 형성되는 비정질 실리콘층을 구비하는 것을 특징으로 한다.In addition, the poly SiGe gate electrode according to the present invention is formed on a semiconductor substrate, a gate oxide film formed on a predetermined region of the semiconductor substrate, an amorphous silicon buffer layer formed on the gate oxide film, and an upper portion of the amorphous silicon layer. It is characterized by comprising a poly SiGe layer and an amorphous silicon layer formed on top of the poly SiGe layer.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 1a 내지 도 1e는 본 발명에 따른 폴리 SiGe 게이트 전극의 제조 방법을 설명하기 위한 단면도들이다. 도 1a 내지 도 1e를 참조하면, 반도체 기판(10) 상부에 게이트 산화막(20)을 형성(도 1a 참조)하고 게이트 산화막(20)의 상부에 비정질 실리콘으로 구성되는 비정질 실리콘 버퍼층(30)을 형성한다(도 1b 참조). 비정질 실리콘 버퍼층(30)은 510 내지 590℃의 온도에서 20 내지 200Å의 두께로 형성하는 것이 바람직하다. 비정질 실리콘 버퍼층(30)의 상부에는 자연 산화막이 존재하므로 SC-1 세정 후 HF 세정 공정을 수행하여 제거하는 것이 바람직하다.1A to 1E are cross-sectional views illustrating a method of manufacturing a poly SiGe gate electrode according to the present invention. 1A to 1E, a gate oxide film 20 is formed on the semiconductor substrate 10 (see FIG. 1A), and an amorphous silicon buffer layer 30 formed of amorphous silicon is formed on the gate oxide film 20. (See FIG. 1B). The amorphous silicon buffer layer 30 is preferably formed to a thickness of 20 to 200 kPa at a temperature of 510 to 590 ℃. Since there is a natural oxide layer on the amorphous silicon buffer layer 30, it is preferable to remove the SC-1 by performing an HF cleaning process.

그 다음에 비정질 실리콘 버퍼층(30)의 상부에 폴리 SiGe층(40)을 형성한다(도 1c 참조). 폴리 SiGe층은 그 상부에 샐리사이드를 형성하기 어렵기 때문에 폴리 SiGe층(40)의 상부에 비정질 실리콘층(50)을 형성(도 1a 참조)하여 샐리사이드의 형성을 용이하게 한다. 이 경우 폴리 SiGe층(40)의 상부에는 자연 산화막이 존재하므로 SC-1 세정 후 HF 세정 공정을 수행하여 제거하는 것이 바람직하다.A poly SiGe layer 40 is then formed on top of the amorphous silicon buffer layer 30 (see FIG. 1C). Since the poly SiGe layer is difficult to form salicide on the top thereof, an amorphous silicon layer 50 is formed on the poly SiGe layer 40 (see FIG. 1A) to facilitate the formation of salicide. In this case, since a natural oxide film is present on the poly SiGe layer 40, it is preferable to remove the SC-1 by performing an HF cleaning process.

다음에는 게이트 전극 패턴을 패터닝하고 식각하여 게이트 전극을 형성한다(도 1e 참조).Next, the gate electrode pattern is patterned and etched to form a gate electrode (see FIG. 1E).

이상에서 설명한 바와 같이, 본 발명에 따른 폴리 SiGe 게이트 전극 및 그 제조 방법은 폴리 SiGe층 하부에 비정질 실리콘 버퍼층을 형성하여 표면이 거칠어 지는 것을 방지하고 폴리 SiGe층 상부에 비정질 실리콘층을 형성하여 샐리사이드 특성이 향상되는 효과가 있다.As described above, the poly SiGe gate electrode and the method of manufacturing the same according to the present invention form an amorphous silicon buffer layer under the poly SiGe layer to prevent the surface from being rough and form an amorphous silicon layer on the poly SiGe layer to form a salicide There is an effect that the characteristics are improved.

Claims (10)

폴리 SiGe 게이트 전극을 형성하는 방법에 있어서,In the method of forming a poly SiGe gate electrode, 반도체 기판 상부에 게이트 산화막을 형성하는 단계;Forming a gate oxide film on the semiconductor substrate; 상기 게이트 산화막의 상부에 비정질 실리콘 버퍼층을 형성하는 단계;Forming an amorphous silicon buffer layer on the gate oxide film; 상기 비정질 실리콘 버퍼층의 상부에 폴리 SiGe층을 형성하는 단계;Forming a poly SiGe layer on top of the amorphous silicon buffer layer; 상기 폴리 SiGe층의 상부에 비정질 실리콘층을 형성하는 단계; 및Forming an amorphous silicon layer on top of the poly SiGe layer; And 게이트 전극 패턴을 패터닝하여 식각하는 단계Patterning and etching the gate electrode pattern 를 포함하는 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.Poly SiGe gate electrode forming method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 비정질 실리콘 버퍼층을 형성하는 단계 다음에 상기 비정질 실리콘층의 상부의 자연 산화막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.And removing the native oxide film on top of the amorphous silicon layer after forming the amorphous silicon buffer layer. 제 2 항에 있어서,The method of claim 2, 상기 자연 산화막을 제거하는 단계는 SC-1 세정 후 HF를 이용하여 수행되는 세정 공정인 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.The removing of the natural oxide layer is a poly SiGe gate electrode forming method, characterized in that the cleaning process is performed using HF after SC-1 cleaning. 제 1 항에 있어서,The method of claim 1, 상기 비정질 실리콘 버퍼층을 형성하는 단계는 510 내지 590℃의 온도에서 수행되는 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.The forming of the amorphous silicon buffer layer is poly SiGe gate electrode forming method, characterized in that carried out at a temperature of 510 to 590 ℃. 제 1 항에 있어서,The method of claim 1, 상기 비정질 실리콘 버퍼층은 20 내지 200Å의 두께인 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.The amorphous silicon buffer layer is a poly SiGe gate electrode forming method, characterized in that the thickness of 20 to 200Å. 제 1 항에 있어서,The method of claim 1, 상기 비정질 실리콘층을 형성하는 단계는 510 내지 570℃의 온도에서 수행되는 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.The forming of the amorphous silicon layer is a poly SiGe gate electrode forming method, characterized in that performed at a temperature of 510 to 570 ℃. 제 1 항에 있어서,The method of claim 1, 상기 비정질 실리콘층은 100 내지 500Å의 두께인 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.The amorphous silicon layer is a poly SiGe gate electrode forming method, characterized in that the thickness of 100 to 500Å. 제 1 항에 있어서,The method of claim 1, 상기 폴리 SiGe층을 형성하는 단계 다음에 상기 폴리 SiGe층 상부의 자연 산화막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.And removing the native oxide film over the poly SiGe layer after forming the poly SiGe layer. 제 8 항에 있어서,The method of claim 8, 상기 자연 산화막을 제거하는 단계는 SC-1 세정 후 HF를 이용하여 수행되는 세정 공정인 것을 특징으로 하는 폴리 SiGe 게이트 전극 형성 방법.The removing of the natural oxide layer is a poly SiGe gate electrode forming method, characterized in that the cleaning process is performed using HF after SC-1 cleaning. 반도체 기판;Semiconductor substrates; 상기 반도체 기판 상부의 소정 영역에 형성되는 게이트 산화막;A gate oxide film formed on a predetermined region over the semiconductor substrate; 상기 게이트 산화막의 상부에 형성되는 비정질 실리콘 버퍼층;An amorphous silicon buffer layer formed on the gate oxide film; 상기 비정질 실리콘층의 상부에 형성되는 폴리 SiGe층; 및A poly SiGe layer formed on top of the amorphous silicon layer; And 상기 폴리 SiGe층의 상부에 형성되는 비정질 실리콘층을 구비하는 것을 특징으로 하는 폴리 SiGe 게이트 전극.A poly SiGe gate electrode, characterized in that it comprises an amorphous silicon layer formed on top of the poly SiGe layer.
KR1020010039117A 2001-06-30 2001-06-30 Poly SiGe Gate Electrode and Method of Manufacturing the Same KR20030003380A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7344999B2 (en) 2005-09-28 2008-03-18 Samsung Electronics Co., Ltd. Method for cleaning substrate having exposed silicon and silicon germanium layers and related method for fabricating semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999043024A1 (en) * 1998-02-19 1999-08-26 France Telecom Method for limiting internal diffusion in a semiconductor device with composite si/sige gate
KR20000055375A (en) * 1999-02-05 2000-09-05 윤종용 MOS transistor and manufacturing method thereof
KR20010061783A (en) * 1999-12-29 2001-07-07 박종섭 Method for fabricating mos transistor
JP2002043566A (en) * 2000-07-27 2002-02-08 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999043024A1 (en) * 1998-02-19 1999-08-26 France Telecom Method for limiting internal diffusion in a semiconductor device with composite si/sige gate
KR20000055375A (en) * 1999-02-05 2000-09-05 윤종용 MOS transistor and manufacturing method thereof
KR20010061783A (en) * 1999-12-29 2001-07-07 박종섭 Method for fabricating mos transistor
JP2002043566A (en) * 2000-07-27 2002-02-08 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7344999B2 (en) 2005-09-28 2008-03-18 Samsung Electronics Co., Ltd. Method for cleaning substrate having exposed silicon and silicon germanium layers and related method for fabricating semiconductor device

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