KR20230014931A - Fault detection display device and operation method thereof - Google Patents

Abstract

The present invention provides an integrated circuit panel for detecting a defect of a driving circuit controlling a display panel, which has an improved manufacturing yield. Specifically, according to the present invention, the integrated circuit panel comprises: a first and a second driving circuit; a data driver configured to output a first and a second input data signal; a switch driver configured to output a switching signal; and an error detection driver configured to receive a first and a second output data signal. The first driving circuit stores the first input data signal received through a first data line. The second driving circuit stores the second input data signal received through a second data line. The first driving circuit outputs the first output data signal based on the first input data signal through a first test line in response to the switching signal received through a switch line, and outputs the second output data signal based on the second input data signal through a second test line in response to the switching signal received through the switch line. The error detection driver can detect a fault occurrence of the first driving circuit based on the first output data signal and detect a fault occurrence of the second driving circuit based on the second output data signal.

Description

Display device for defect detection, and its operation method {FAULT DETECTION DISPLAY DEVICE AND OPERATION METHOD THEREOF}

The present disclosure relates to a method for detecting a defect in a display device. More particularly, it relates to a method of detecting a defect in each of driving circuits of a display device.

A display device is a device implemented to convert various information into a visual form and provide it to a user. In general, a display device is composed of a display panel including a plurality of pixel circuits implemented to express various visual information according to electrical signals, and an integrated circuit panel including a plurality of driving circuits for driving each of the plurality of pixel circuits. do. A defect in a display device may occur in both a pixel circuit or a driving circuit.

A defect in the display device may be visually detected by combining a plurality of pixel circuits and a plurality of driving circuits and applying an electrical signal. However, in this case, it is difficult to determine whether the cause of the defect is the pixel circuit or the driving circuit. Thus, the production yield of the display device may decrease.

The present disclosure is to solve the above-mentioned technical problems. More specifically, an object of the present disclosure is to provide a display device configured to detect defects in each of a plurality of driving circuits, and an operating method thereof.

According to an embodiment of the present disclosure, an integrated circuit panel for detecting a failure of a driving circuit for controlling a display panel includes a driving circuit array including a first driving circuit and a second driving circuit, and a first input data signal is transmitted to a first input data signal. A data driver configured to output through a data line and output a second input data signal through a second data line, a switch driver configured to output a first switching signal through a first switch line, and a second input data signal through a first test line. an error detection driver configured to receive one output data signal and receive a second output data signal through a second test line, wherein the first driving circuit comprises the first input data received through the first data line; a signal, the second driving circuit stores the second input data signal received through the second data line, and the first driving circuit stores the first switching signal received through the first switch line In response, the first output data signal based on the first input data signal is output through the first test line, and the second driving circuit outputs the first switching signal received through the first switch line. In response, the second output data signal based on the second input data signal is outputted through the second test line, and the error detection driver outputs the first driving circuit based on the first output data signal. The occurrence of a defect may be detected, and the occurrence of a defect in the second driving circuit may be detected based on the second output data signal.

According to an embodiment of the present disclosure, a method of operating an integrated circuit panel for detecting a defect in a driving circuit for controlling a display panel provides a first input data signal to a first driving circuit and transmits a second input data signal to a first driving circuit. 2 providing a driving circuit; storing the first input data signal by the first driving circuit and storing the second input data signal by the second driving circuit; providing a first switching signal to the first driving circuit and the second driving circuit; In response to the first switching signal, a first output data signal is output based on the stored first input data signal by the first driving circuit, and the stored second input data signal is output by the second driving circuit. outputting a second output data signal based on the signal; and determining whether a defect occurs in the first driving circuit based on the first output data signal, and determining whether a defect occurs in the second driving circuit based on the second output data signal.

A display device according to an embodiment of the present disclosure includes an integrated circuit panel and a display panel, wherein the display panel includes a first pixel circuit and a second pixel circuit, and the integrated circuit panel includes a first driving circuit and a second pixel circuit. A driving circuit array including two driving circuits, a data driver configured to output a first input data signal through a first data line and output a second input data signal through a second data line, and a switching signal through a switch line. a switch driver configured to output, and an error detection driver configured to receive a first output data signal through a first test line and receive a second output data signal through a second test line, wherein the first driving circuit comprises: stores the first input data signal received through the first data line, the second driving circuit stores the second input data signal received through the second data line, and the first driving circuit A first driving signal is output to the first pixel circuit based on the stored first input data signal, and the first output data signal is output to the error detection driver in response to the switching signal through the first test line. and the second driving circuit outputs a second driving signal to the second pixel circuit based on the stored second input data signal, and converts the second output data signal to the second pixel circuit in response to the switching signal. output to the error detection driver through a test line, the error detection driver determines a defect in the first driving circuit based on the first output data signal, and determines a defect in the second driving circuit based on the second output data signal Defects in the driving circuit can be determined.

According to the present disclosure, a defective driving circuit among a plurality of driving circuits may be detected. Accordingly, a display device for defect detection with improved manufacturing yield and an operating method thereof are provided.

1 is a structural diagram illustrating a display device according to an embodiment of the present disclosure.
FIG. 2 shows a detail of the integrated circuit panel of FIG. 1 .
FIG. 3 is a block diagram showing an integrated circuit panel for inspecting the driving circuit array of FIG. 2 in units of rows.
FIG. 4 is a circuit diagram showing the configuration of the driving circuit of FIG. 3 .
5 is a block diagram showing the structure of an integrated circuit panel according to an embodiment of the present disclosure.
FIG. 6 is a block diagram showing in detail portions indicated by dotted lines of the driving circuit array of FIG. 5 .
FIG. 7 is a circuit diagram illustrating an exemplary implementation of the driving circuit of FIG. 5 .
FIG. 8 shows a connection relationship between the integrated circuit panel and the display panel of FIG. 1 .
9 is a flowchart illustrating a method of operating a driving circuit according to an exemplary embodiment of the present disclosure.
10 is a flowchart illustrating a method of operating an integrated circuit panel according to an exemplary embodiment of the present disclosure.
FIG. 11 is a timing diagram exemplarily showing signals of the driving circuit array of FIG. 6 .
12 is a circuit diagram illustrating an embodiment in which the memory of FIG. 7 is implemented as a shift register.
FIG. 13 is a diagram illustrating a case in which a defect occurs in one of the driving circuits of FIG. 6 .
FIG. 14 is a timing diagram showing defect detection for the defective driving circuit of FIG. 13 .

Hereinafter, embodiments of the present disclosure will be described clearly and in detail to the extent that those skilled in the art can easily practice the present disclosure. Details, such as detailed configurations and structures, are provided merely to facilitate a general understanding of the embodiments of the present disclosure. Therefore, modifications of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the present disclosure. Moreover, descriptions of well-known functions and structures are omitted for clarity and conciseness. Components in the following drawings or detailed description may be connected with other components other than those shown in the drawings or described in the detailed description. The terms used in the text are terms defined in consideration of the functions of the present disclosure, and are not limited to specific functions. Definitions of terms may be determined based on the details described in the detailed description.

Components described with reference to terms such as a driver or a block used in the detailed description may be implemented in software, hardware, or a combination thereof. Illustratively, the software may be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuitry, electronic circuitry, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, micro electro mechanical systems (MEMS), passive components, or combinations thereof.

1 is a structural diagram illustrating a display device according to an embodiment of the present disclosure. Referring to FIG. 1 , the display device DA may be implemented as a combination of a display panel DP and an integrated circuit panel ICP. In FIG. 1 , the display device DA and the display panel DP are illustrated as being implemented on a flat surface, but the scope of the present disclosure is not limited thereto and may include a case where the display panel is implemented on a curved surface. For example, the technical idea of the present disclosure described below may also be applied to a flexible display apparatus unless otherwise explained in context.

The display panel DP may include a plurality of pixel circuits. Each of the plurality of pixels may include a light emitting element. For example, the light emitting device may include a light emitting diode (LED), a micro light emitting diode (micro LED), a laser diode, and/or the like. For more concise description below, each of the pixel circuits of the display panel DP is illustratively described as including micro light emitting diodes, but the scope of the present disclosure is not limited thereto.

In one embodiment, each of the plurality of pixel circuits may be arranged in a regular pattern on the display panel DP. For concise description, hereinafter, the display panel DP includes rows of pixel circuits arranged on a straight line extending in a first direction and columns of pixel circuits arranged on a straight line extending in a second direction. It is assumed to be composed of and described. However, the scope of the present disclosure is not limited thereto, and may include a case in which pixel circuits are arranged in a zigzag pattern in two dimensions or a case in which pixel circuits are arranged in three dimensions.

In an embodiment, the display panel DP is a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, or an electrowetting display panel. panel), etc., may include various display panels. However, the display panel according to the present disclosure is not limited thereto, and may be implemented to include the above-described display panel or a panel similar thereto.

The integrated circuit panel (ICP) may be coupled to the lower or rear surface of the display panel (DP). For example, the integrated circuit panel (ICP) may be combined with the display panel (DP) to configure the display device (DA).

In one embodiment, an integrated circuit panel (ICP) may include a plurality of driving circuits. A plurality of driving circuits may be respectively connected to a plurality of pixel circuits of the display panel DP. For example, each of the plurality of driving circuits may be a light emitting element (eg, a light emitting diode (LED), a micro light emitting diode (micro LED)), a laser diode (laser diode) of a corresponding pixel circuit. Diode), etc.) can provide voltage or signal. A connection relationship between the driving circuit and the pixel circuit will be described in detail with reference to FIG. 8 below.

In an embodiment, defects of the display device DA may independently occur in the display panel DP and/or the integrated circuit panel ICP. However, when a defect is visually detected in a coupled state of the display panel DP and the integrated circuit panel ICP, it is difficult to determine whether the display panel DP or the integrated circuit panel ICP is defective. Hereinafter, a method of driving a display panel (DP) of an integrated circuit panel (ICP) and a method of detecting defects in each of driving circuits included in the integrated circuit panel (ICP) according to an embodiment of the present disclosure are detailed. it is explained

FIG. 2 shows a detail of the integrated circuit panel of FIG. 1 . 1 and 2, an integrated circuit panel (ICP) may include a driving circuit array 1, a controller 2, a data driver 3, and a line driver 4. can In an embodiment, the data driver 3 and the line driver 4 may be implemented to control pixel circuits of the display panel DP through a plurality of driving circuits.

Hereinafter, for concise description, a controller 2, a data driver 3, and a line driver 4 are assumed to be components included in an integrated circuit panel (ICP) and described. However, the scope of the present disclosure is not limited thereto, and the controller, data driver, and line driver may be components existing outside the integrated circuit panel. For example, a controller, data driver, and line driver may be components included in the display device DA.

The driving circuit array 1 may include a plurality of driving circuits PXIC. For example, the plurality of driving circuits PXIC may be arranged on a 2D plane. Each of the plurality of driving circuits PXIC may provide a voltage or signal to a corresponding pixel circuit in response to a voltage or signal provided from the data driver 3 and the line driver 4 . A detailed embodiment of a method in which the driving circuit array 1 provides a voltage or signal to a corresponding pixel circuit will be described later with reference to FIG. 8 .

For concise description, it will be described that the plurality of driving circuits PXIC are arranged along the row and column directions. However, the scope of the present disclosure is not limited thereto, and may include a case in which the driving circuits PXIC are arranged in a zigzag pattern in 2D or a case in which the driving circuits PXIC are arranged in 3D. .

In an embodiment, each of the plurality of driving circuits PXIC may be controlled in an active matrix method. However, the scope of the present disclosure is not limited thereto, and the plurality of driving circuits PXIC may be controlled through various methods such as a passive matrix method and a segment method.

In an embodiment, each of the plurality of driving circuits PXIC may correspond to at least one or more of the plurality of pixel circuits included in the display panel DP of FIG. 1 . Accordingly, the number of driving circuits PXIC may be determined based on the number of pixels included in the display panel DP.

The controller 2 may control the data driver 3 and/or the line driver 4 to provide voltages or signals to the plurality of driving circuits PXIC.

The data driver 3 may be connected to the driving circuit array 1 through a plurality of data lines DL. The data driver 3 may control the plurality of driving circuits PXIC by providing an input data signal through the plurality of data lines DL in response to the control signal of the controller 2 .

The plurality of data lines DL may be connected to the plurality of driving circuits PXIC. For example, each of the plurality of data lines DL may be connected to the driving circuits PXIC located in the same column in the driving circuit array 1 . In this case, the driving circuits PXIC located in the same column of the driving circuit array 1 may be connected through the same data line DL as the data driver 3 and receive the same input data signal.

In an embodiment, an input data signal transmitted to the driving circuits PXIC from each of the plurality of data lines DL may be used to generate a signal to be transmitted to a pixel circuit corresponding to each driving circuit PXIC. there is. A method of providing a signal to the pixel circuit based on the input data signal received by the driving circuit PXIC from the data line DL will be described in detail with reference to FIG. 8 below.

The line driver 4 may be connected to the driving circuit array 1 through a plurality of clock lines CL. The line driver 4 may control the plurality of driving circuits PXIC by providing a clock signal through a plurality of clock lines CL in response to a control signal of the controller 2 .

The plurality of clock lines CL may be connected to the plurality of driving circuits PXIC. For example, each of the plurality of clock lines CL may be connected to the driving circuits PXIC positioned on the same row in the driving circuit array 1 . In this case, the driving circuits PXIC positioned on the same row of the driving circuit array 1 may be connected through the same clock line CL as the line driver 4 and receive the same clock signal. .

In an embodiment, the clock signal transmitted to the driving circuits PXIC from each of the plurality of clock lines CL is to designate the driving circuit PXIC to receive the input data signal through the data line DL. can be used For example, the driving circuits PXIC constituting the same column of the driving circuit array 1 may receive the same input data signal from the data driver 3, but the driving circuit receiving the clock signal ( PXIC) can operate in response to an input data signal. That is, when the driving circuit PXIC receives an input data signal through the data line DL and the driving circuit PXIC further receives a clock signal through the clock line CL, the driving circuit PXIC receives data An input data signal received through the line DL may be stored.

In one embodiment, the line driver 4 may sequentially or non-sequentially select driving circuits PXICs to operate in response to an input data signal in a row unit through a plurality of clock lines CL. . For example, the line driver 4 may cause an arbitrary driving circuit row to operate in response to an input data signal, regardless of the physical location of each driving circuit row, through a plurality of clock lines CL.

In an embodiment, the data driver 3, the plurality of data lines DL, the line driver 4, and the plurality of clock lines CL may be used to determine a defect of the corresponding driving circuit PXIC. there is.

FIG. 3 is a block diagram showing an integrated circuit panel for inspecting the driving circuit array of FIG. 2 in units of columns. 2 and 3, an integrated circuit panel (ICP) includes a driving circuit array 10, a controller 20, a data driver 30, and an error decision driver 60. can include For a more concise description of the defect detection method, the line driver 4 and the clock lines CL shown in FIG. 2 are not shown in FIG. 3, but the integrated circuit panel (ICP) of the present disclosure includes the line driver and It may further include clock lines. For example, each of the plurality of driving circuits PXIC may operate by receiving a clock signal from a line driver through a clock line.

Since configurations and functions of the driving circuit array 10, the controller 20, and the data driver 30 are similar to those described with reference to FIG. 2, detailed descriptions are omitted.

In the driving circuit array 10 , driving circuits PXICs located in the same column may be connected in series to each other. For example, driving circuits PXIC positioned in the same column may constitute a driving circuit column.

The driving circuit column may receive an input data signal from the data driver 30 and may continuously transfer the data signal to provide an output data signal to the error detection driver 60 . The configuration of the driving circuit PXIC and the connection relationship of the driving circuit columns will be described in detail with reference to FIG. 4 below.

The input data signal may be sequentially transferred to other driving circuits PXIC along the driving circuit column. For example, the driving circuit PXIC that directly receives the input data signal from the data driver 30 through the data line DL (eg, the first driving circuit) is connected to another driving circuit PXIC of the driving circuit column. (For example, the second driving circuit) may be provided with an output data signal. The driving circuit PXIC (eg, the k+1th driving circuit) receiving the output data signal from the other driving circuit PXIC (eg, the kth driving circuit), based on the provided output data signal, An output data signal may be provided to the subsequent driving circuit PXIC (eg, the k+2 th driving circuit). The last driving circuit (eg, the n-th driving circuit) of the driving circuit column outputs the test line TL based on the output data signal provided from the previous driving circuit PXIC (eg, the n−1-th driving circuit). Through this, an output data signal may be provided to the error detection driver 60.

In an embodiment, when a defect does not occur in a row of the driving circuit, output data provided to the error detection driver 60 by the last driving circuit (PXIC) (eg, the n-th driving circuit) of the row of the driving circuit. The signal may have the same or similar period or waveform to the input data signal provided by the data driver 30 to the driving circuit array.

In one embodiment, when a driving circuit having a defect is included in a column of driving circuits, a signal output from the last driving circuit (PXIC) (eg, an n-th driving circuit) of the row of driving circuits is the data driver 30 may not be the same as or similar to the input data signal provided to the driving circuit array.

In one embodiment, the data driver 30 may further transmit the input data signal transmitted to the driving circuit array 10 to the error detection driver 60 .

The error detection driver 60 may be connected to the driving circuit array 10 through a plurality of test lines TL. The error detection driver 60 may receive output data signals provided from a plurality of driving circuit columns through a plurality of test lines TL, and identify whether a defect has occurred in the driving circuit array.

In one embodiment, the error detection driver 60 may directly receive an input data signal from the data driver 30 . In this case, the error detection driver 60 may compare the output data signal transferred from the driving circuit column through the test line TL and the received input data signal to determine whether a defect occurs in the driving circuit column. For example, when a defect occurs in any driving circuit constituting a driving circuit column, the output data signal transmitted through the test line TL and the input data signal directly received from the data driver 30 may be different. . In this case, the error detection driver 60 applies to at least one driving circuit PXIC among the driving circuits PXIC of the driving circuit column corresponding to the test line TL for which the output data signal and the input data signal are determined to be different. It is possible to identify that a defect has occurred.

In one embodiment, the data driver 30 may perform the same or similar function as the data driver 3 of FIG. 2 . For example, an input data signal transmitted from the data driver 30 to the driving circuit array 10 when inspecting a display device for defects may be the same as or similar to a signal when the display device operates.

FIG. 4 is a circuit diagram showing the configuration of the driving circuit of FIG. 3 . Hereinafter, exemplary configurations and connection relationships of the driving circuit PXIC are described with reference to FIGS. 3 and 4 , but the scope of the present disclosure is not limited thereto.

3 and 4 , each of the plurality of driving circuits PXIC1 to PXICn may include a memory MM, a transistor TR, an AND gate AG, and a pad PAD. .

Each of the plurality of driving circuits PXIC1 to PXICn may receive an input data signal. Each of the plurality of driving circuits PXIC1 to PXICn may provide a driving voltage or a driving signal to a pixel circuit (not shown) through a pad PAD. The plurality of driving circuits PXIC1 to PXICn may be connected in series in response to the switch signal SW.

In an embodiment, each of the driving circuits PXIC2 to PXICn other than the first driving circuit PXIC1 directly receiving the input data signal through the data line DL receives the input data signal through the data line DL. Instead of receiving directly, an output data signal of another driving circuit (PXIC) connected thereto may be received. In this case, each of the second to nth driving circuits PXIC2 to PXICn may not receive the input data signal DIN from the data line DL.

The memory MM may receive an input data signal and store the received input data signal. For example, the memory MM of the first driving circuit PXIC1 may receive the input data signal DIN from the data driver 30 through the data line DL, and the second to nth driving circuits ( The memories MM of the PXIC2 to PXICn may receive an input data signal from a prior driving circuit (eg, a previous driving circuit constituting a driving circuit row). The memory MM may determine whether to store the input data signal based on the control of the controller 20 (eg, according to the control through the line driver 40). Signals or data stored in the memory MM may be transferred to the AND gate AG and/or the transistor TR.

In one embodiment, the memory MM may receive a clock signal through a clock line. The memory MM may store an input data signal received from the data line DL or another driving circuit in response to the received clock signal. For example, each of the plurality of driving circuits PXIC1 to PXICn may receive a clock signal from a clock line when a failure detection operation is performed. However, for a more concise description, illustration of a clock signal input through a clock line is omitted in FIG. 4 .

The AND gate AG may perform an AND operation on the signal stored in the memory MM and the PWM signal. A first input terminal of the AND gate AG may receive a Pulse Width Modulation (PWM) signal, and a second input terminal may receive a signal output from the memory MM. The AND gate AG may output a high level signal through an output terminal when both input signals are high level signals.

In one embodiment, the PWM signal may be provided directly or indirectly from the controller 20 to the AND gate AG. For example, the PWM signal is directly generated by the controller 20 and provided to the first input terminal of the AND gate, or from a separate driver that generates the PWM signal in response to a control signal of the controller 20. It may be provided as the first input terminal.

In an embodiment, the PWM signal may be a signal having an adjusted duty cycle of a pulse in which a high level and a low level are repeated in order to adjust the brightness of a light emitting element of a pixel circuit corresponding to the driving circuit PXIC. .

The pad PAD may receive a signal from the AND gate AG and output a voltage or signal to the pixel circuit. For example, the pad PAD may be connected to at least one or more of a plurality of pixel circuits constituting the display panel DP of FIG. 1 . In this case, whether or not the pixel circuit constituting the display panel DP is turned on and off and brightness may be controlled according to a signal input to the pad PAD. A connection method and signal transfer method between the display panel DP and the integrated circuit panel ICP through the pad PAD will be described in detail with reference to FIG. 8 below.

The transistor TR may perform a switch function to control whether a signal output from the memory MM is transferred to another driving circuit PXIC or the error detection driver 60 . For example, the gate terminal of the transistor TR may receive the switching signal SW through the switch line SL. Depending on whether the switching signal SW is input, the transistor TR may or may not transfer the signal output from the memory MM to a memory or error detection driver 60 of another driving circuit.

In one embodiment, the switching signal SW may be provided from the outside of the driving circuit PXIC. For example, the switching signal SW may be provided directly or indirectly from the controller 20 or may be provided from a switch driver (not shown).

In one embodiment, the switching signal SW may be provided differently for each of a plurality of driving circuit columns constituting the driving circuit array 10 . For example, the plurality of driving circuits PXIC1 to PXICn constituting one driving circuit column may receive the same switching signal SW. In this case, the input data signal provided to the first driving circuit PXIC1 through the data line DL is continuously transmitted, and is transmitted from the n-th driving circuit PXICn to the error detection driver 60 through the test line TL. can be provided. The error detection driver 60 may determine whether a defective driving circuit PXIC exists in a column of corresponding driving circuits through an output data signal provided from the nth driving circuit PXICn.

In one embodiment, the defect detection method according to FIGS. 3 and 4 may detect defects in units of columns of the driving circuit array 10 . However, in this case, the error detection driver 60 can determine which row of driving circuits has a defect, but cannot specify a driving circuit in which a defect has occurred.

5 is a block diagram showing the structure of an integrated circuit panel according to an embodiment of the present disclosure. Referring to FIG. 5 , an integrated circuit panel (ICP) includes a driving circuit array 100, a controller 200, a data driver 300, a line driver 400, and an error detection driver ( 600, error decision driver).

The driving circuit array 100 may include a plurality of driving circuits PXIC. The plurality of driving circuits PXIC may be arranged on a 2D plane to form the driving circuit array 100 . For example, the plurality of driving circuits PXIC may be arranged in an n by m structure. Each of the plurality of driving circuits PXIC may provide a voltage or signal to a corresponding pixel circuit in response to a voltage or signal provided from the data driver 300 and the line driver 400 .

Since the functions and operations of the controller 200, data driver 300, and line driver 400 have been described with reference to FIG. 2, detailed descriptions are omitted.

The data driver 300 may be connected to the first to nth driving circuit columns of the driving circuit array through the first to nth data lines DL1 to DLn, respectively. For example, in the case of the second driving circuit column, the data driver 300 may be connected to each of the driving circuits PXIC constituting the second driving circuit column through the second data line DL2. . In this case, the driving circuits PXIC positioned in the second driving circuit column of the driving circuit array 100 may receive the same input data signal through the second data line DL2.

In an embodiment, input data signals provided to the driving circuits PXIC through each of the plurality of data lines DL1 to DLn by the data driver 300 may be different from each other.

In an embodiment, an input data signal provided to the driving circuit array 100 by the data driver 300 may be a signal for selecting some driving circuits PXIC of the driving circuit array 100 . For example, when operating a pixel circuit or detecting a defect in the driving circuit PXIC, the input data signal may be a signal for selecting some driving circuits PXIC among a plurality of driving circuits. That is, In case of operating the pixel circuit, the input data signal may be a signal for selecting a driving circuit corresponding to a pixel circuit to emit light, and in case of detecting a defect in the driving circuit, it may be a signal for selecting a driving circuit to be inspected for occurrence of a defect. .

The line driver 400 may be connected to the first to m th driving circuit rows of the driving circuit array 100 through the first to m th clock lines CL1 to CLm, respectively. For example, in the case of the second driving circuit row, the line driver 400 may be connected to each of the driving circuits PXIC constituting the second driving circuit row through the second clock line CL2. . In this case, the driving circuits PXIC positioned in the second driving circuit row of the driving circuit array 100 may receive the same clock signal through the second clock line CL2.

In one embodiment, when the line driver 400 does not provide a clock signal to any driving circuit row, it may transmit a signal obtained by clock gating the clock signal. In this case, the clock gated signal may be a signal that does not toggle or a signal that maintains a low level.

In one embodiment, clock signals provided by the line driver 400 through each of the plurality of clock lines CL1 to CLm may be the same as or different from each other. For example, clock signals provided by the line driver 400 through each of the plurality of clock lines CL1 to CLm may be provided in different time periods.

In an embodiment, the driving circuit PXIC may selectively store an input data signal provided by the data driver 300 . For example, when a clock signal is received from the line driver 400 through the clock line CL, the driving circuit PXIC may store the input data signal received from the data driver 300 . The driving circuit PXIC may not store the input data signal received from the data driver 300 when the clock signal is not input from the line driver 400 . A selective data storage method of the driving circuit PXIC will be described in detail with reference to FIG. 7 below.

The switch driver 500 may receive a control signal from the controller 200 . The switch driver 500 may determine whether to output the input data signal received by the driving circuits PXIC to the error detection driver 600 in response to the received control signal. The switch driver 500 may be connected to the first to m th driving circuit rows of the driving circuit array 100 through the first to m th switch lines SL1 to SLm, respectively. For example, in the case of the second driving circuit row, the switch driver 500 may be connected to each of the driving circuits PXIC constituting the second driving circuit row through the second switch line SL2. . In this case, each of the driving circuits PXIC positioned in the second driving circuit row of the driving circuit array 100 may receive the same switching signal through the second switch line SL2 .

In one embodiment, the switching signal may activate a failure detection operation of the corresponding drive circuit row. For example, the switching signal may cause each of the driving circuits PXIC constituting a corresponding driving circuit row to transmit an output data signal to the error detection driver 600 . In this case, the output data signal may be a signal output via a driving circuit corresponding to the input data signal.

In an embodiment, switching signals provided to the driving circuits PXIC through each of the plurality of switch lines SL1 to SLm by the switch driver 500 may be provided in different time intervals. In this case, defect detection may be performed on a row of the driving circuit PXIC in a different time period for each row. A method of detecting a defect in each of the plurality of driving circuits PXIC through a switching signal will be described in detail with reference to FIGS. 6 and 7 below.

The error detection driver 600 may be connected to the driving circuit array 100 through a plurality of test lines TL1 to TLn. The error detection driver 600 may be connected to the first to nth driving circuit columns of the driving circuit array 100 through the first to nth test lines TL1 to TLn, respectively. For example, in the case of the second driving circuit column, the error detection driver 600 may be connected to each of the driving circuits PXIC constituting the second driving circuit column through the second test line TL2. there is. In this case, the error detection driver 600 may determine whether a defect has occurred in each driving circuit PXIC based on the output data signal received from the plurality of driving circuits PXIC.

In an embodiment, the error detection driver 600 may further receive an input data signal and a clock signal from the data driver 300 and the line driver 400 . For example, each of an input data signal and a clock signal that the error detection driver 600 directly receives from the data driver 300 and the line driver 400 is a driving circuit array that the data driver 300 and the line driver 400 receive. It may be the same as the signal output in (100) or a signal including information about it. The error detection driver may compare the received input data signal and clock signal with the output data signals received through the plurality of test lines TL1 to TLn. In this case, the error detection driver may determine which driving circuit has a defect based on the input data signal and the clock signal.

In an embodiment, the defect determination operation may be performed in units of rows of the driving circuits PXIC constituting the driving circuit array 100 . For example, when a switching signal requesting the output of the output data signal of the first driving circuit row is provided through the first switch line SL1, the driving circuit array is provided through the second to mth switch lines SL2 to SLm. The switching signal transmitted to 100 may be a signal requesting output cutoff of an output data signal of a corresponding driving circuit row. In this case, it may be determined whether the driving circuits included in the first driving circuit row of the driving circuit array 100 are defective.

In an embodiment, the defect determination operation may be performed in units of rows of the driving circuits PXIC constituting the driving circuit array 100 . For example, in response to the switching signal received through the first switch line SL1, each of the driving circuits PXIC of the first driving circuit row transmits an output data signal to an error through test lines TL1 to TLn. It can be provided by the detection driver 600. In this case, the error detection driver 600 may determine which driving circuit column has a defect, based on the output data signal received from each of the plurality of test lines TL1 to TLn.

In an embodiment, after the operation of determining a failure of one driving circuit row (eg, the first driving circuit row) is performed, the operation of determining a failure of another driving circuit row may be performed. Accordingly, when an output data signal from the driving circuit array 100 is provided to the error detection driver 600, the error detection driver 600 may determine which driving circuit PXIC outputs the output data signal. For example, the error detection driver 600 transmits an output data signal received from the driving circuit PXIC through the physically separated first to nth test lines TL1 to TLn of the driving circuit array 100. It is possible to determine which driving circuit column exists. And, since each of the driving circuit rows of the driving circuit array 100 receives switching signals divided in time series through the first to m th switch lines SL1 to SLm, the error detection driver 600 receives the received It is possible to determine which driving circuit row of the driving circuit array 100 has an output data signal. Therefore, according to one embodiment of the present disclosure, an integrated circuit panel capable of determining defects in each of a plurality of driving circuits and an operating method thereof may be provided.

FIG. 6 is a block diagram showing in detail some configurations of the driving circuit array of FIG. 5 . Referring to FIGS. 5 and 6 , the driving circuit array 100 may include a plurality of driving circuits PXIC11 to PXIC33.

Each of the plurality of driving circuits PXIC11 to PXIC33 may receive the input data signal DIN from the data driver 300 through the data line DL, and may receive the clock line CL from the line driver 400. The clock signal CLK may be received through the switch line SL, and the switching signal SW may be received from the switch driver 500 through the switch line SL. Each of the plurality of driving circuits PXIC11 to PXIC33 may provide a driving signal to a corresponding pixel circuit based on an input data signal and a clock signal, and when a switching signal is further input, through a test line TL. An output data signal may be provided to the error detection driver 600 .

The first to third data lines DL1 to DL3 may be connected to the plurality of driving circuits PXIC11 to PXIC33, respectively. For example, the first data line DL1 may be connected to the driving circuits PXIC11, PXIC21, and PXIC31, and the second data line DL2 may be connected to the driving circuits PXIC12, PXIC22, and PXIC32. The third data line DL3 may be connected to the driving circuits PXIC13 , PXIC23 , and PXIC33 . Through the first to third data lines DL1 to DL3, the first to third input data signals DIN1 to DIN3 may be provided to corresponding driving circuits PXIC11 to PXIC33, respectively.

The first to third clock lines CL1 to CL3 may be connected to the plurality of driving circuits PXIC11 to PXIC33, respectively. For example, the first clock line CL1 may be connected to the driving circuits PXIC11, PXIC12, and PXIC13, and the second clock line CL2 may be connected to the driving circuits PXIC21, PXIC22, and PXIC23, The third clock line CL3 may be connected to the driving circuits PXIC31, PXIC32, and PXIC33. Through the first to third clock lines CL1 to CL3, the first to third clock signals CLK1 to CLK3 may be provided to corresponding driving circuits PXIC11 to PXIC33, respectively.

The first to third switch lines SL1 to SL3 may be respectively connected to the plurality of driving circuits PXIC11 to PXIC33. For example, the first switch line SL1 may be connected to the driving circuits PXIC11, PXIC12, and PXIC13, and the second switch line SL2 may be connected to the driving circuits PXIC21, PXIC22, and PXIC23, The third switch line SL3 may be connected to the driving circuits PXIC31 , PXIC32 , and PXIC33 . Through the first to third switch lines SL1 to SL3, the first to third switching signals SW1 to SW3 may be provided to the driving circuits PXIC11 to PXIC33, respectively.

The first to third test lines TL1 to TL3 may be connected to the plurality of driving circuits PXIC11 to PXIC33 , respectively. For example, the first test line TL1 may be connected to the driving circuits PXIC11, PXIC21, and PXIC31, and the second test line TL2 may be connected to the driving circuits PXIC12, PXIC22, and PXIC32, The third test line TL3 may be connected to the driving circuits PXIC13 , PXIC23 , and PXIC33 . Through the first to third test lines TL1 to TL3, the error detection driver 600 may receive output data signals from the driving circuits PXIC11 to PXIC33, respectively.

For a more detailed description, the operation and connection relationship of the driving circuits PXIC32 included in the third driving circuit row and the second driving circuit column of the driving circuit array 100 will be described as a representative example. However, the scope of the present disclosure is not limited thereto, and other driving circuits of the driving circuit array 100 may perform the same or similar functions as the operation and function of the driving circuit PXIC32 described below.

5 and 6 , the driving circuit PXIC32 receives the second input data signal DIN2 through the second data line DL2 and receives the third clock signal through the third clock line CL3. Signal CLK3 may be received. The driving circuit PXIC32 stores the second data signal DIN2 in response to the third clock signal CLK3 and, based on the stored second data signal DIN2, transmits the driving signal or driving voltage to the corresponding pixel circuit. can supply The operation of the driving circuit PXIC will be described in detail with reference to FIGS. 7 and 8 below.

The driving circuit PXIC32 may receive the third switching signal SW3 through the third switch line SL3. The driving circuit PXIC32 may transmit an output data signal to the error detection driver 600 through the third test line TL3 in response to the third switching signal SW3. The output data signal output from the driving circuit PXIC32 may be used to determine whether the driving circuit PXIC32 is defective. For example, when a defect occurs in the driving circuit PXIC32, the error detection driver 600 cannot receive an output data signal corresponding to the driving circuit PXIC32 or receives an output data signal that does not correspond to the input data signal. can receive An output data signal when a failure occurs in the driving circuit PXIC will be described in detail with reference to FIGS. 13 and 14 below.

FIG. 7 is a block circuit diagram illustrating an exemplary implementation of the driving circuit of FIG. 5 . Referring to FIGS. 5 and 7 , the driving circuit PXIC may include a memory MM, an AND operator AG, a pad PAD, and a transistor TR.

For a more concise description, a detailed description of the functions and connection relationships of the memory MM, the AND operator AG, the pad PAD, and the transistor TR described with reference to FIG. 4 will be omitted.

The memory MM may receive an input data signal through the data line DL and store the input data signal in response to the clock signal CLK received through the clock line CL. For example, the memory MM may store the received input data signal DIN when the clock signal CLK is provided, and may store the received input data signal DIN when the clock signal CLK is not provided. ) may not be stored.

The memory MM may transfer the stored input data signal to the AND gate AG through the first node N1 or to the drain terminal of the transistor TR.

In one embodiment, the memory MM may be implemented with a shift register including a multiplexer, transistor, inverter, and/or a combination of the like. A memory MM implemented as a shift register is exemplarily described with reference to FIG. 12 below.

In one embodiment, the memory (MM) is a volatile memory such as static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and/or phase-change RAM (PRAM), magneto-resistive memory (MRAM). RAM), Resistive RAM (ReRAM), ferro-electric RAM (FRAM), and the like. However, the scope of the technical idea of the present disclosure is not limited thereto, and may include driving circuits having a memory including various elements capable of temporarily storing an input signal or a combination thereof.

In an embodiment, the operation of transmitting the input data signal DIN stored in the memory MM to the error detection driver 600 through the test line TL provides a driving signal to the pixel circuit through the pad PAD. It can be performed regardless of whether the operation is being performed. For example, an operation in which the driving circuit PXIC provides the stored input data signal to the drain terminal of the transistor TR through the first node N1 is performed by the driving circuit PXIC through the first node N1. An operation of providing an input data signal stored to the logical AND gate AG may be performed regardless of whether or not it is being performed. In this case, an integrated circuit panel capable of inspecting defects of a driving circuit even during operation of the display device may be provided. That is, according to one embodiment of the present disclosure, an integrated circuit panel in which a defect detection operation of a driving circuit is performed independently of driving a pixel circuit may be provided.

The first node N1 may be connected to the memory MM, the first input terminal of the AND operator AG, and the drain terminal of the transistor TR. That is, the same signal may be provided to the pixel circuit and the error detection driver through the first node N1.

A gate terminal of the transistor TR may be connected to the switch line SL, a drain terminal may be connected to the first node N1, and a source terminal of the transistor TR may be connected to the test line TL. A gate terminal of the transistor TR may receive the switching signal SW through the switch line SL. The transistor TR may transfer the signal received from the first node N1 to the error detection driver 600 through the test line TL in response to the received switching signal SW. In this case, a signal transmitted to the error detection driver 600 through the test line TL may be an output data signal.

In an embodiment, when the defect detection of the driving circuit PXIC is not performed, the transistor TR may be in a turned-off state. In this case, the output data signal may not be delivered to the error detection driver 600 .

FIG. 8 shows a connection relationship between the integrated circuit panel and the display panel of FIG. 1 . For concise description, only a partial configuration of one driving circuit PXIC and one pixel circuit PXC are shown in FIG. 8 . Referring to FIGS. 1 , 7 and 8 , the integrated circuit panel ICP and the display panel DP may be connected through the pad PAD of the driving circuit PXIC. For example, the driving circuit PXIC of the integrated circuit panel ICP may provide a driving signal to the pad PAD, and the pixel circuit PXC may receive the driving signal from the pad PAD.

The pixel circuit PXC may include a transistor TR and a light emitting device LED. A gate terminal of the transistor TR of the pixel circuit PXC may be connected to the pad PAD, and a drain terminal may receive the bias voltage VLED. The transistor TR may function as a current source when a driving voltage or a driving signal is provided from the pad PAD.

A source terminal of the transistor TR may be connected to the light emitting element LED. For example, the light emitting device (LED) may be a light emitting diode (LED), a micro light emitting diode (micro LED), a laser diode, and/or the like. In the present disclosure, it is assumed that the light emitting device (LED) is a micro light emitting diode.

When a driving voltage or a driving signal is input from the pad PAD to the pixel circuit PXC, current may be supplied to the light emitting element LED. In an embodiment, the brightness of the light emitting element LED may be adjusted according to the on-off ratio of the driving voltage or the driving signal supplied from the pad PAD to the pixel circuit PXC.

9 is a flowchart illustrating a method of operating a driving circuit according to an exemplary embodiment of the present disclosure. Referring to FIGS. 7 and 9 , in step S100, the driving circuit PXIC may receive the input data signal DIN. For example, the driving circuit PXIC may receive the input data signal DIN through the data line DL.

In step S110, the driving circuit PXIC may operate in response to the clock signal CLK. For example, the driving circuit PXIC may operate in response to the clock signal CLK received through the clock line CL. The driving circuit PXIC may perform step S120 when the clock signal CLK is received, and may not operate when the clock signal CLK is not received. That is, the driving circuit PXIC may be in an idle state when the clock signal CLK is not received.

In step S120, the driving circuit PXIC may store the input data signal DIN. For example, the memory MM of the driving circuit PXIC may store the received input data signal DIN in response to the clock signal CLK. The driving circuit PXIC may use the stored input data signal DIN to generate a driving signal through step S130 when the driving circuit drives the pixel circuit, and when a defect of the driving circuit is detected in step S140 below. It can be used to generate an output data signal through steps S150 to S150.

When the driving circuit PXIC drives the pixel circuit, step S130 may be performed. In step S130, the driving circuit PXIC may generate a driving signal based on the stored input data signal DIN. For example, the driving circuit PXIC may generate a driving signal through a AND operation of a stored input data signal DIN and a pulse width modulation (PWM) signal. The generated driving signal may be provided to the pixel circuit through the pad PAD. The driving circuit PXIC that outputs the driving signal may be in an idle state until receiving another signal.

When the defect detection of the driving circuit PXIC is performed, step S140 may be performed. In step S140, the driving circuit PXIC may operate in response to the switching signal SW. For example, the driving circuit PXIC may operate in response to the switching signal SW received through the switch line SL. The driving circuit PXIC may perform step S150 when the switching signal SW is received, and may not perform a defect detection operation when the switching signal SW is not received.

In step S150, the driving circuit PXIC may output an output data signal. For example, the driving circuit PXIC may output an output data signal generated based on the stored input data signal through the test line TL.

In one embodiment, step S130 may be performed independently of steps S140 to S150. For example, steps S140 to S150 may be performed even while step S130 is being performed, and step S130 may be performed even if the switching signal SW is not received in step S140.

10 is a flowchart illustrating a method of operating an integrated circuit panel according to an exemplary embodiment of the present disclosure. For concise description, in FIG. 10, among the driving circuits shown in FIG. A method of operating an integrated circuit panel (ICP) for detecting a defect of is described, but the scope of the present disclosure is not limited to the number of driving circuits (PXIC). Hereinafter, an operating method of the integrated circuit panel (ICP) for detecting defects in the driving circuits PXIC11, PXIC12, PXIC21, and PXIC22 will be described with reference to FIGS. 5, 6, and 10.

A method of operating the integrated circuit panel (ICP) for detecting defects in the driving circuits PXIC11, PXIC12, PXIC21, and PXIC22 may start from step S200. In step S200, the integrated circuit panel (ICP) may provide input data signals to a plurality of driving circuits through a plurality of data lines. For example, the integrated circuit panel ICP may provide the first input data signal DIN1 to the driving circuits PXIC11 and PXIC21 through the first data line DL1 and the second data line DL2. Through this, the first input data signal DIN2 may be provided to the driving circuits PXIC12 and PXIC22.

In step S210, the integrated circuit panel (ICP) provides a clock signal to each of the plurality of driving circuits through a plurality of clock lines to store the input data signal. For example, the integrated circuit panel (ICP) may provide the first clock signal CLK1 to the driving circuits PXIC11 and PXIC12 through a first clock line, and may provide the driving circuits PXIC21 through a second clock line. , the second clock signal CLK2 may be provided to the PXIC22. The driving circuits PXIC receiving the clock signal may store the input data signal.

In step S220 , the integrated circuit panel (ICP) may input the switching signal SW to the driving circuits PXIC11 and PXIC12 constituting the first driving circuit row of the driving circuit array 100 . For example, the integrated circuit panel ICP may input the first switching signal SW1 to the driving circuits PXIC11 and PXIC12 through the first switch line SL1.

In operation S230 , the integrated circuit panel (ICP) may detect a defect in the first driving circuit row through output data signals output from the driving circuits PXIC11 and PXIC12 constituting the first driving circuit row. For example, the integrated circuit panel (ICP) receives an output data signal from the driving circuit (PXIC11) through a first test line (TL1), and receives the first input data signal (DIN1) and the first clock signal (CLK1). By comparison, a defect in the driving circuit PXIC11 can be determined, an output data signal is received from the driving circuit PXIC12 through the second test line TL2, and the second input data signal DIN1 and the first clock signal are received. By comparing with the signal CLK1, a defect in the driving circuit PXIC12 can be determined. Accordingly, the integrated circuit panel ICP may detect defects in the driving circuits PXIC11 and PXIC12 of the first driving circuit row.

In step S240 , the integrated circuit panel (ICP) may input the switching signal SW to the driving circuits PXIC21 and PXIC22 constituting the second driving circuit row of the driving circuit array 100 . For example, the integrated circuit panel (ICP) may input the second switching signal SW2 to the driving circuits PXIC21 and PXIC22 through the second switch line SL2.

In step S230, the integrated circuit panel (ICP) may detect a defect in the second driving circuit row through output data signals output from the driving circuits PXIC21 and PXIC22 constituting the second driving circuit row. For example, the integrated circuit panel (ICP) receives the output data signal from the driving circuit (PXIC21) through the first test line (TL1), and receives the first input data signal (DIN1) and the second clock signal (CLK2). By comparison, a defect in the driving circuit PXIC21 can be determined, an output data signal is received from the driving circuit PXIC22 through the second test line TL2, and the second input data signal DIN2 and the second clock signal are received. By comparing with the signal CLK2, a defect in the driving circuit PXIC22 can be determined. Accordingly, the integrated circuit panel ICP may detect defects in the driving circuits PXIC21 and PXIC22 of the second driving circuit row.

In one embodiment, the integrated circuit panel (ICP) may operate by changing the order of steps S220 to S230 and steps S240 to S250.

11 is a timing diagram exemplarily showing signals for driving circuits of FIG. 6 . For concise description, in FIG. 11, among the driving circuits shown in FIG. However, the scope of the present disclosure is not limited to the number of driving circuits. In the following, signals corresponding to the driving circuits are described with reference to FIGS. 5 to 11 .

In the first time period t1 , an input data signal DIN may be provided to each of the driving circuits PXIC to detect a defect in the driving circuit array 100 . For example, the driving circuits PXIC11 and PXIC 21 may receive the first input data signal DIN1 through the first data line DL1, and the driving circuits PXIC12 and PXIC 22 may receive the second data signal DIN1. The second input data signal DIN2 may be received through the line DL2.

An operation of the driving circuits PXIC11 and PXIC22 to store the received input data signal may be controlled by the clock signals CLK1 and CLK2. For example, in the first to third time periods t1 to t3, the driving circuits PXIC11 and PXIC12 may receive the first clock signal CLK1 through the first clock line CL1, and the driving circuit PXIC21 and PXIC22 may not receive a clock signal. In this case, the memory MM of each of the driving circuits PXIC21 and PXIC22 not receiving the clock signal may not store the input data signal provided from the corresponding data line DL. Therefore, the input data signal DIN may be stored only in the driving circuits PXIC11 and PXIC12 during the first to third time periods t1 to t3.

After storing the input data signal DIN, each of the driving circuits detects an error in the output data signal through the corresponding test line TL when the switch signal SW is input through the corresponding switch line SL. It can be provided by the driver 600. For example, when the first switch signal SW1 is received through the first switch line SL1 after the input data signals DIN1 and DIN2 are stored in the driving circuits PXIC11 and PXIC12, respectively, the driving circuits (PXIC11, PXIC12) may provide output data signals to the error detection driver 600 through the first and second test lines TL1 and TL2, respectively, in the third time period t3.

In an embodiment, when the first switch signal SW1 is input to the driving circuits PXIC11 and PXIC12, the switch signal (eg, the second switch signal SW2) is provided to the driving circuits PXIC21 and PXIC22. may not be entered.

In one embodiment, when no defect occurs in the driving circuits PXIC11 and PXIC12, the output data signals output to the error detection driver 600 through the first and second test lines TL1 to TL2 are: The first input data signal and the second input data signal may be the same as or similar to each other. For example, the output data signal provided to the error detection driver 600 through the test line TL may have the same cycle and waveform as the input data signal DIN provided through the data line DL.

In an embodiment, after detection of defects in the driving circuits PXIC11 and PXIC12 is completed, detection of defects in the driving circuits PXIC21 and PXIC22 may be performed. In this case, the operation of storing the input data signal in the driving circuits PXIC21 and PXIC22 and providing the output data signal to the error detection driver 600 through the first and second test lines TL1 to TL2 has been described above. Since it is similar to the defect detection operation for the driven driving circuits PXIC11 and PXIC12, a detailed description thereof will be omitted.

In an embodiment, defect detection is sequentially performed for each driving circuit row, and an output data signal is provided to the error detection driver 600 through different test lines TL for driving circuit columns. Therefore, the error detection driver 600 can detect defects in each of the driving circuits PXIC constituting the driving circuit array 100 . For example, the error detection driver 600 determines whether the output data signal is transmitted through which test line TL, and compares it with the input data signal and clock signal directly provided from the data driver 300 and the line driver 400. A defect in each of the driving circuits PXIC may be detected based on a time interval in which an error occurs in the output data signal. Signals of the driving circuit array 100 when a failure occurs in one of the plurality of driving circuits PXIC will be described in detail with reference to FIGS. 13 and 14 below.

FIG. 12 is a block circuit diagram showing an embodiment in which the memory of FIG. 7 is implemented as a shift register. Referring to FIG. 12 , the driving circuit PXIC may include a memory MM, an AND operator AG, a pad PAD, and a transistor TR. Since connection relationships and functions of the memory MM, the AND operator AG, the pad PAD, and the transistor TR have been described with reference to FIG. 7 , detailed descriptions thereof are omitted.

The memory MM may be implemented by including a multiplexer MUX and a buffer string BF.

A first input terminal of the multiplexer MUX may receive the input data signal DIN through the data line DL. A second input terminal of the multiplexer MUX may be connected to the first node N1. An output terminal of the multiplexer MUX may be connected to the buffer column.

The buffer string may include one or more buffers BFs. For example, the buffer string may include one or more buffers BF connected in series.

The buffer BF may include first and second transistors TR1 and TR2 and inverters IV. The first transistor TR1 may receive the first clock CLKa from a gate terminal, a source terminal may be connected to an output terminal of the multiplexer MUX, and a drain terminal may be connected to an input terminal of the inverter IV. The inverters IV may be connected in series to form an inverter train, and may be connected in parallel with the second transistor TR2. The second transistor TR2 may receive the second clock CLKb from a gate terminal, and a drain terminal may be connected to the output of the inverter IV. In this case, the buffer BF may perform a function of time delaying a signal received through the source terminal of the first transistor TR1.

In one embodiment, the first and second clocks CLKa and CLKb may be provided through the clock line CL of FIG. 7 . For example, the first and second clocks CLKa and CLKb are the same signals as the clock signal CLK received through the clock line CL, or the clock signal CLK received through the clock line CL. may be a signal generated via a phase-locked loop (PLL).

An output terminal of the buffer BF (eg, an output terminal of an inverter column or a drain terminal of the second transistor TR2) is an input terminal of another buffer BF (eg, a source terminal of the first transistor TR1). ) can be associated with An output terminal of the last buffer BF constituting the buffer string may be connected to the first node N1.

In one embodiment, unlike shown in FIG. 12 , the driving circuit PXIC may further include one or more buffers BF between the first node N1 and the transistor TR. However, the scope of the present disclosure is not limited to the number of buffers BF included in the driving circuit PXIC or memory MM.

13 and 14 are diagrams illustrating a defect detection operation when a defect occurs in one of the driving circuits of FIG. 6 . The functions and connection relationships of the plurality of data lines DL, the plurality of clock lines CL, the plurality of switch lines SL, the plurality of test lines TL, and the driving circuits PXIC are described in FIG. Since it has been described with reference to 6, detailed descriptions are described.

Hereinafter, with reference to FIGS. 13 and 14, a signal and a defect detection operation when a defect occurs in the driving circuit PXIC12 included in the row of the first driving circuit and the column of the second driving circuit will be described in detail. . However, for concise description, the signals of the first to second time intervals t1 to t2 and the fourth to sixth time intervals t4 to t6 in which the same signals as when the driving circuit does not have a defect occur are generated. A description thereof is omitted since it has been described in detail with reference to FIG. 11 .

In one embodiment, when a defect occurs in the driving circuit PXIC, the driving voltage corresponding to the input data signal DIN may not be supplied to the pad PAD. For example, referring to FIG. 7 , when a defect occurs in the driving circuit PXIC, the memory MM does not provide a voltage or signal to the first node N1 or the memory MM receives a clock signal. In response to (CLK), the input data signal DIN may not be stored. In this case, even if the clock signal CLK and the switching signal SW are provided to the driving circuit in which the failure occurs, the failure driving circuit may not transmit an output data signal through the test line TL. For example, the failure driving circuit FAULT, PXIC12 of FIG. 13 responds to the first clock signal CLK1 received through the first clock line CL1 and receives the second signal received through the second data line DL2. The input data signal DIN2 may not be stored, or the memory MM may not provide a voltage or signal to the first node N1. Therefore, the defective driving circuit PXIC12 may fail to transmit an output data signal to the second test line TL2 in response to the first switching signal SW1 provided from the first switch line SL1.

Referring continuously to FIG. 14 , in the first to second time intervals t1 to t2 and the fourth to sixth time intervals t4 to t6, the defective driving circuit PXIC12 receives or transmits. Signals that do may be the same as those shown in FIG. 11 . However, in the third time period t3, the defective driving circuit PXIC12 may not output an output data signal through the second test line TL2.

In an exemplary embodiment, the error detection driver 600 may include an output data signal of the defective driving circuit PXIC12 received through the second test line TL2 and inputs received from the data driver 300 and the line driver 400. A defective driving circuit may be determined based on the data signal and the output data signal. For example, the error detecting driver 600 detects an error in the third time period t3 when the first switch signal SW1 is input to the driving circuit array 100, so that the driving circuit having a defect occurs in the driving circuit array 100. It can be confirmed that it exists in the first driving circuit row of (100). In addition, the error detection driver 600 detects a defect through the output data signal received through the second test line TL2, so that the driving circuit in which the defect occurs is displayed in the second driving circuit column of the driving circuit array 100. existence can be confirmed. Accordingly, the driving circuit PXIC12 having a defect in the driving circuit array 100 including a plurality of driving circuits may be identified.

The foregoing are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments and should be defined by not only the claims to be described later but also those equivalent to the claims of the present disclosure.

DA: display device
DP: display panel
ICP: Integrated Circuit Panel
100: driving circuit array
200: controller
300: data driver
400: line driver
500: switch driver
600: error detection driver
PXIC: drive circuit
DL: data line
CL: clock line
SL: switch line
TL: test line

Claims (10)

In an integrated circuit panel for detecting a defect in a driving circuit that controls a display panel,
a drive circuit array including a first drive circuit and a second drive circuit;
a data driver configured to output a first input data signal through the first data line and output a second input data signal through the second data line;
a switch driver configured to output a first switching signal through the first switch line; and
an error detection driver configured to receive a first output data signal through a first test line and receive a second output data signal through a second test line;
The first driving circuit stores the first input data signal received through the first data line;
The second driving circuit stores the second input data signal received through the second data line;
The first driving circuit outputs the first output data signal based on the first input data signal through the first test line in response to the first switching signal received through the first switch line;
The second driving circuit outputs the second output data signal based on the second input data signal through the second test line in response to the first switching signal received through the first switch line;
wherein the error detection driver detects occurrence of a defect in the first driving circuit based on the first output data signal, and detects occurrence of a failure in the second driving circuit based on the second output data signal. According to claim 1,
Further comprising a line driver outputting a first clock signal through a first clock line;
The first driving circuit stores the first input data signal in response to the first clock signal received through the first clock line;
wherein the second driving circuit stores the first input data signal in response to the first clock signal received through the first clock line. According to claim 2,
the data driver further outputs the first and second input data signals to the error detection driver;
The line driver further outputs the first clock signal to the error detection driver;
The error detection driver compares the received first input data signal and the first clock signal with the first output data signal to detect the occurrence of a defect in the first driving circuit, and to detect the occurrence of a defect in the first driving circuit, and to detect the occurrence of a defect in the received second input data signal. and an integrated circuit panel that compares the first clock signal with the second output data signal to detect the occurrence of a defect in the second driving circuit. According to claim 1,
The first driving circuit generates a first driving signal for controlling the display panel based on the stored first input data signal;
wherein the second driving circuit generates a second driving signal for controlling the display panel based on the stored second input data signal. According to claim 4,
The first driving signal is generated through logical product of the stored first input data signal and a first pulse width modulation (PWM) signal,
The second driving signal is generated through a logical product of the stored second input data signal and the second PWM signal. According to claim 4,
The first driving circuit performs an operation of outputting the first output data signal through a test line during generation of the driving signal. According to claim 1,
the driving circuit array further includes a third driving circuit and a fourth driving circuit;
the switch driver is further configured to output a second switching signal through a second switch line;
The third driving circuit stores the first input data signal received through the first data line;
The fourth driving circuit stores the second input data signal received through the second data line;
The third driving circuit outputs a third output data signal based on the first input data signal through the first test line in response to the second switching signal received through the second switch line;
The fourth driving circuit outputs a fourth output data signal based on the second input data signal through the second test line in response to the second switching signal received through the second switch line;
The error detection driver is an integrated circuit further configured to detect occurrence of a failure in the third driving circuit based on the third output data signal, and detect occurrence of a failure in the fourth driving circuit based on the fourth output data signal. panel. According to claim 7,
a line driver outputting a first clock signal through a first clock line and a second clock signal through a second clock line;
The operation of storing input data by the first driving circuit and the second driving circuit is performed in response to the first clock signal;
The third driving circuit and the fourth driving circuit store input data in response to the second clock signal. According to claim 7,
The integrated circuit panel of claim 1 , wherein the output of the first switching signal and the output of the second switching signal of the switch driver are performed in different time intervals. A method of operating an integrated circuit panel for detecting a defect in a driving circuit for controlling a display panel, comprising:
providing a first input data signal to a first driving circuit and providing a second input data signal to a second driving circuit;
storing the first input data signal by the first driving circuit and storing the second input data signal by the second driving circuit;
providing a first switching signal to the first driving circuit and the second driving circuit;
In response to the first switching signal, a first output data signal is output based on the stored first input data signal by the first driving circuit, and the stored second input data signal is output by the second driving circuit. outputting a second output data signal based on the signal; and
and determining whether a defect occurs in the first driving circuit based on the first output data signal, and determining whether a defect occurs in the second driving circuit based on the second output data signal.

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