KR102147401B1 - Micro Display and Test Method thereof - Google Patents

Abstract

According to the above-stated need, a purpose of the present invention is to provide a micro display device for determining whether there is a defect per pixel with respect to a result of bonding a micro light emitting element. The micro display device includes: a plurality of pixels arranged in a display area; and a power supply part provided around the display area and outputting a power voltage to a power line connected with the plurality of pixels. Each of the plurality of pixels includes: at least one light emitting element including first and second electrodes, wherein the first electrode is connected with the power line; and an AND gate having an input terminal to which the second electrode of the at least one light emitting element is connected. An input terminal of a first AND gate included in a first pixel of the plurality of pixels receives a test pulse signal and a node voltage applied to the second electrode of the at least one light emitting element included in the first pixel. An output terminal of the first AND gate outputs an operation result of performing an AND operation based on the test pulse signal and the node voltage and transmits the operation result by being connected with an input terminal of a second AND gate included in a second pixel, which is arranged adjacently in the same row as the first pixel, of the plurality of pixels.

Description

Micro display device and its inspection method TECHNICAL FIELD

Embodiments of the present invention relate to a micro display device and a test method thereof.

Along with the rapid growth of the AR and MR markets in recent years, the growth of the micro-display device (or micro-display) market using Cu-Cu bonding and micro LED is expected on the back of low power consumption characteristics and excellent luminance characteristics.

In the case of PWM (digital) driving of a pixel circuit with a built-in memory, a large number of wirings are required in an active area of a display device because connection to the pixel circuit is required for a plurality of gray expression signals. Therefore, in order to test for defective bonding in the related art, in particular, in the case of a large display panel in which a pixel driving circuit (IC) and a scan/data driver driving circuit (Scan/Data Driver IC) are separately assembled, a plurality of input pads are provided in the pixel driving circuit (Input PAD) is required.

In this way, when a plurality of micro light-emitting devices (LEDs) are bonded and attached to one display device as the display resolution increases, since defective bonding inevitably occurs, countermeasures are required. In order to check the presence/absence of a pixel including a defective bonding of a micro light emitting device, information on a pixel including a defective bonding is required.

Conventionally, there is a method of disposing a daisy chain in a region adjacent to the micro display device and indirectly checking the bonding characteristics, but there is a disadvantage in that it is impossible to accurately identify the defective bonding location.

The present invention is in accordance with the above-described necessity, and an object of the present invention is to provide a micro display device and a method for inspecting the same for determining whether or not there is a defect for each pixel of a result of bonding a micro light emitting device substrate and a CMOS driver substrate.

However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A micro-display device according to an exemplary embodiment of the present invention includes a plurality of pixels arranged in a display area; And a power supply unit disposed around the display area and outputting a power voltage through a power line connected to the plurality of pixels, wherein each of the plurality of pixels includes a first electrode and a second electrode, and the At least one light emitting device having a first electrode connected to the power line; And an AND gate in which the second electrode of the at least one light emitting device is connected to an input terminal, wherein an input terminal of a first AND gate included in a first pixel among the plurality of pixels is at least one included in the first pixel. A node voltage and a test pulse signal applied to the second electrode of the light emitting device of are input, and the output terminal of the first AND gate outputs an operation result of performing an AND operation based on the node voltage and the test pulse signal, and the Among a plurality of pixels, the operation result may be transmitted by being connected to an input terminal of a second AND gate included in a second pixel arranged adjacent to the same row as the first pixel.

In addition, the micro-display device may include: a measuring unit that measures a current to test whether or not a bonding is defective; A first switch for connecting the plurality of pixels arranged in the display area in row units; And a second switch for sequentially connecting the plurality of pixels arranged in the display area in column units. The measuring unit may further include a plurality of pixels included in a row to which the first switch is connected, and sequentially connect through the second switch to measure a current corresponding to an AND gate operation result.

In addition, the display area is divided into a predetermined number of sub-areas per column, the second switch is provided for each of the sub-areas, and a plurality of pixels included in a row to which the first switch is connected are separated from the sub-area. Each can be connected sequentially.

In addition, the micro-display device includes: an inspection unit for testing a defect in a pixel circuit; And a third switch connected to the inspection unit, wherein the first switch includes a first pole and a second pole, and the first pole is connected to a second electrode of the plurality of light emitting devices, and the The second switch connects the measurement unit and the second pole of the first switch, the third switch connects the inspection unit and the second pole of the first switch, and in a first test mode, the first switch and The second switch is turned on, and the measurement unit tests for a bonding failure based on a current flowing through the first switch and the second switch, and in a second inspection mode, the first switch and the third The switch is turned on, and the inspection unit may test a defect in the pixel circuit based on a current flowing through the first switch and the third switch.

Other aspects, features, and advantages other than those described above will become apparent from the detailed content, claims and drawings for carrying out the following invention.

According to an embodiment of the present invention made as described above, it is possible to easily detect the defective bonding of the micro LED, and thus other productivity improvement may be possible.

In addition, according to the present invention, when performing a repair operation, it is possible to accurately identify a defective joint position, and thus, a yield may be improved.

Of course, the scope of the present invention is not limited by these effects.

1 is a schematic diagram illustrating a manufacturing process of a display device according to an exemplary embodiment of the present invention.
2 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.
FIG. 3 is a block diagram illustrating a method of inspecting for a defect in units of rows (lines) according to an embodiment of the present invention.
4 is a view for explaining a gate chain of a pixel unit according to an exemplary embodiment of the present invention.
5A and 5B are diagrams for explaining a structure of a gate of a pixel circuit according to an exemplary embodiment of the present invention.
6 is a voltage-current graph in a common anode type to explain an operation of a gate of a pixel circuit according to an exemplary embodiment of the present invention.
7 is a schematic diagram of a display device 30B for inspecting defective pixels based on current according to an exemplary embodiment of the present invention.
8 is a diagram illustrating a configuration for driving a test mode according to an embodiment of the present invention.
9 is an example of a pixel of the display device 30B according to an embodiment of the present invention.
10 is a timing diagram for explaining timing in a first test mode according to an embodiment of the present invention.

Hereinafter, various embodiments of the present disclosure will be described in connection with the accompanying drawings. Various embodiments of the present disclosure may be subjected to various changes and may have various embodiments, and specific embodiments are illustrated in the drawings and related detailed descriptions are described. However, this is not intended to limit the various embodiments of the present disclosure to a specific embodiment, and it should be understood that all changes and/or equivalents or substitutes included in the spirit and scope of the various embodiments of the present disclosure are included. In connection with the description of the drawings, similar reference numerals have been used for similar elements.

In various embodiments of the present disclosure, expressions such as "or" include any and all combinations of words listed together. For example, "A or B" may include A, may include B, or may include both A and B.

In the following embodiments, terms such as first and second are not used in a limiting meaning, but are used for the purpose of distinguishing one component from another component. In addition, in the following embodiments, expressions in the singular include plural expressions unless the context clearly indicates otherwise.

In the following embodiments, when X and Y are connected, X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. I can. Here, X and Y may be objects (eg, devices, devices, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship indicated in the drawings or detailed description, and may include anything other than the connection relationship indicated in the drawing or detailed description.

When X and Y are electrically connected, for example, an element (e.g., a switch, a transistor, a capacitor element, an inductor, a resistance element, a diode, etc.) that enables the electrical connection of X and Y, It may include a case in which at least one is connected between X and Y.

In the following embodiments, "ON" used in connection with the device state may refer to an activated state of the device, and "OFF" may refer to an inactive state of the device. "On" used in connection with a signal received by the device may refer to a signal that activates the device, and "off" may refer to a signal that disables the device. The device can be activated by a high voltage or a low voltage. For example, a P-type transistor is activated by a low voltage, and an N-type transistor is activated by a high voltage. Therefore, it should be understood that the "on" voltage for the P-type and N-type transistors is at opposite (low vs. high) voltage levels.

In the following embodiments, terms such as include or have means that the features or elements described in the specification are present, and do not preclude the possibility of adding one or more other features or elements in advance. Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram illustrating a manufacturing process of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device 30 according to an exemplary embodiment may include a light emitting device array 10 and a driving circuit board 20. The light emitting device array 10 may be coupled to the driving circuit board 20. The display device 30 may be a micro display device.

The light emitting device array 10 may include a plurality of light emitting devices. The light emitting device may be a light emitting diode (LED). The light emitting device may be a light emitting diode (LED) having a micro to nano unit size. At least one light emitting device array 10 may be manufactured by growing a plurality of light emitting diodes on a semiconductor wafer. Accordingly, the display device 30 can be manufactured by combining the light emitting device array 10 with the driving circuit board 20 without the need to individually transfer the light emitting diodes to the driving circuit board 20.

Pixel circuits corresponding to each of the light emitting diodes on the light emitting device array 10 may be arranged on the driving circuit board 20. The light emitting diodes on the light emitting device array 10 and the pixel circuits on the driving circuit board 20 may be electrically connected to each other to form a pixel.

2 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a display device 30A according to an exemplary embodiment may include a pixel unit 110 and a driver.

The pixel unit 110 may be disposed in a display area displaying an image. The pixel unit 110 may include a plurality of pixels PX arranged in various patterns such as a predetermined pattern, for example, a matrix type and a zigzag type. The pixel PX emits one color and, for example, may emit one color of red, blue, green, and white. The pixel PX may emit colors other than red, blue, green, and white.

The pixel PX may include a light emitting device. The light emitting device may be a self-luminous device. For example, the light emitting device may be a light emitting diode (LED). The light emitting device may emit light with a single peak wavelength or may emit light with a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting device. The pixel circuit may include at least one thin film transistor and at least one capacitor. The pixel circuit may be implemented by a semiconductor stack structure on a substrate.

The pixel unit 110 includes scan lines SL1 to SLn for applying a scan signal to the pixels PX, emission control lines EL1 to ELn for applying a light emission control signal to the pixels PX, and pixels PX. ) May include data lines DL1 to DLm for applying a data signal. In addition, the pixel unit 110 may include test pulse lines TL1 -TLn for applying a test pulse signal to the pixels PX and bias application lines BL1-BLn for applying a bias voltage.

The scan lines SL1-SLn, the emission control lines EL1-ELn, the test pulse lines TL1-TLn, and the bias application lines BL1-BLn are each connected to the pixels PX arranged in the same row. , Each of the day lines DL1 to DLm may be connected to the pixels PX arranged in the same column.

The driving unit and the generation unit are provided in a non-display area around the pixel unit 110 and may drive and control the pixel unit 110. The driving unit and the generation unit may include a control unit 121, a scan driving unit 122, a data driving unit 123, a power supply unit 124, a test pulse generation unit 125, and a bias voltage driving unit 126. The driving unit may operate according to the driving mode and the inspection mode.

In the driving mode, under the control of the controller 121, the scan driver 122 sequentially applies scan signals to the scan lines SL1 to SLn, and the data driver 123 applies a data signal to each pixel PX. Can be approved. Under the control of the controller 121, the scan driver 122 may sequentially apply the emission control signal to the emission control lines EL1 to ELn. The pixels PX emit light with a brightness corresponding to a voltage level or a current level of a data signal received through the data lines DL1 to DLm in response to a scan signal received through the scan lines SL1 to SLn.

In the inspection mode, under the control of the controller 121, the scan driver 122 sequentially applies a scan signal to the scan lines SL1 to SLn, and the data driver 123 applies a scan signal to each pixel PX. Can be approved. Under the control of the controller 121, the scan driver 122 may sequentially apply the emission control signal to the emission control lines EL1 to ELn. Under the control of the controller 121, the test pulse generator 125 may apply a test pulse signal to each pixel PX.

The power supply unit 124 receives external power and/or internal power, converts the voltage to various levels required for operation of each component, and converts the corresponding voltage to the pixel unit according to the power control signal input from the controller 121. (110) can be supplied.

The power supply unit 124 may generate a power voltage and apply it to the pixel unit 110. The power supply unit 124 may generate a driving voltage and apply it to the scan driver 122, the data driver 123, and the bias voltage driver 126.

The test pulse generator 125 may generate a test pulse in the test mode and apply it to the pixel unit 110. The test data processing unit 130 measures the output test pulse in units of each row (line) of the pixel unit 110, and based on the measured value, at least one pixel PX of the pixels PX in the corresponding row is It can be determined that the pixel circuit is defective.

The control unit 121, the scan driver 122, the data driver 123, the power supply unit 124, the test pulse generator 125, and the bias voltage driver 126 are separate integrated circuit chips or one integrated circuit chip, respectively. It is formed in the form of, mounted directly on the substrate on which the pixel portion 110 is formed, mounted on a flexible printed circuit film, attached to the substrate in the form of a tape carrier package (TCP), or formed directly on the substrate. May be.

FIG. 3 is a block diagram illustrating a method of inspecting for a defect in units of rows (lines) according to an embodiment of the present invention.

Referring to FIG. 3, the test data processing unit 130 may include a test data latch 131 and a shift register 132.

When a test signal is input from the control unit 121, the test pulse generation unit 125 generates a test pulse signal and generates a test pulse signal in units of rows (lines) of the pixel unit 110 through the test pulse lines TL1 to TLn. Can be transmitted.

The test data latch 131 may store a test pulse signal passing through a gate chain of pixels (eg, P11 to P1m) included in one row in the pixel unit 110. Thereafter, the shift register 132 of the present invention can be sequentially checked in row (line) units through a test pulse signal stored in the test data latch 131.

For example, when a test signal is input from the control unit 121, the test pulse generation unit 125 generates a test pulse and applies the test pulse to the pixel unit 110 through the first test pulse line TL1. I can. In this case, the test pulse applied to the first row of the pixel unit 110 may pass through P11, P12, and P13 to P1m to be output. The test data latch 131 may store a test pulse passed through and output, and may be sequentially transferred to the shift register 132.

Each pixel (eg, P11 to P1m) may include a logic device such as an AND gate therein, and each logic device may form a gate chain to pass a test pulse. The detailed structure of the gate chain will be described with reference to FIG. 4.

4 is a view for explaining a gate chain of a pixel unit according to an exemplary embodiment of the present invention.

The pixels included in each row (line) of the pixel unit 110 may each include an AND gate. The AND gates included in each pixel may include terminals corresponding to R, G, and B node voltages as input terminals.

Referring to FIG. 4, a test pulse 410 input through a first test pulse line TL1 may be input through one of input terminals of an AND gate included in the first pixel P11. Also, an output terminal of an AND gate included in the first pixel P11 may be connected to an input terminal of an AND gate included in the second pixel P12.

Specifically, the first test pulse 410 through the first test pulse line TL1 may be input to the first row of the pixel unit 110. At this time, the high state of the output voltage is referred to as 1, that is, true, and the low state is referred to as 0, that is, false. That is, when there is no defect in the junction and the voltage states of the R, G, and B nodes are all true (1), as a result of performing the AND operation between the voltage of each node and the test pulse signal, the test pulse signal is the first in the first row. It may pass through the pixel P11. In other words, when the test pulse signal is true (1), the operation result output from the AND gate may also be true (1).

The operation result output from the first pixel P11 may be input to an input terminal of an AND gate included in the second pixel P12 distributed adjacent to the same row as the first pixel P11. The AND gate included in the second pixel P12 is the voltage of the node corresponding to the sub-pixels (for example, R, G, B) included in the second pixel P12 and received from the AND gate of the first pixel P11. The AND operation can be performed based on the operation result.

Similarly, the operation result output from the second pixel P12 may be transmitted to the AND gate included in the third pixel P13, and sub-pixels (for example, R, G, B) included in the third pixel P13 The AND operation may be performed based on the voltage of the node corresponding to and the operation result output from the second pixel P12.

That is, when the junction of all pixels (eg P11 to P1m) included in the first row is not defective, if the test pulse 410 input to the first pixel P11 is true, the output from the mth pixel P1m The pulse 411 that becomes true may also be true (1). Conversely, if there is a defective junction in any one of the pixels included in the line, the output pulse may be false (0).

For example, when any one of the pixels P21 to P2m included in the second row (for example, P22) is a defective junction FAIL, the test pulse 420 input through the second test pulse line TL2 While) is true (1), the output pulse 421 may be false (0). Through this, it can be determined that at least one pixel among the pixels included in the second row is in a FAIL state.

5A and 5B are diagrams for explaining a structure of a gate of a pixel circuit according to an exemplary embodiment of the present invention. In particular, FIG. 5A shows a common anode type pixel circuit, and 5B shows a common cathode type pixel circuit.

5A and 5B, the bias voltage driver 126 may apply a bias voltage through the bias voltage line BLn to test whether the sub-pixels (eg, LED_R, LED_G, and LED_B) are defective. have. That is, when the transistor is turned on according to the bias voltage, V_R, V_G, and V_B node values corresponding to R, G, and B may be input to the AND gate.

The AND gate may determine whether to pass the test pulse signal input through the test pulse line TLn based on the values of the V_R, V_G, and V_B nodes. Specifically, in a normal circuit without a bad junction, when the transistor is turned on by applying a bias voltage for testing, the true (1) V_R, V_G, and V_B node values can be input to the AND gate. , Accordingly, a test pulse signal of a true (1) value can be passed.

On the other hand, when any one of the PADs of the LEDs corresponding to R, G, and B is defective, the corresponding node value may be false (0). For example, if the PAD junction corresponding to B is defective, the V_B node value becomes false (0), and the output from the AND gate is also false (0).

6 is a voltage-current graph in a common anode type to explain an operation of a gate of a pixel circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the current Id flowing through the LED corresponding to each of V_R, V_G, and V_B may vary according to the V_R, V_G, and V_B node voltage values Vds input to the AND gate. For example, a current graph indicates a linear region up to a specific voltage value, and a saturation region from a voltage value thereafter.

In other words, the V_R, V_G, and V_B node voltage values (Vds) are variable according to the current (Id), and the pixel according to an embodiment of the present invention has a voltage value (Vds) of each of the V_R, V_G, and V_B nodes. A bias and a pixel circuit can be set to have an appropriate logic value according to the current Id.

When the voltage values Vds of the nodes V_R, V_G, and V_B enter the saturation region, the AND gate may determine that the corresponding node is true (1, High). That is, if all the junctions of the light emitting diode (LED) pads (PAD) corresponding to the V_R, V_G, and V_B nodes are normal, when all nodes enter the saturation region, the logic values of all nodes are true (1, High). It is determined that it is, and the test pulse signal can be passed (PASS).

On the other hand, if any one of the light emitting diode (LED) pads PAD corresponding to the V_R, V_G, and V_B nodes is defective, the value of the node corresponding to the defective pad is saturated according to the settings of the bias and the pixel circuit. saturation) area. That is, since one of the input terminals of the AND gate is false (0, low), the output of the AND gate is also false (0, low), and the test pulse signal may not pass (Fail).

7 is a schematic diagram of a display device 30B for inspecting defective pixels based on current according to an exemplary embodiment of the present invention.

The pixel unit 210 may be disposed in a display area displaying an image. The pixel unit 210 may include a plurality of pixels PX arranged in various patterns such as a predetermined pattern, for example, a matrix type or a zigzag type. The pixel PX emits one color and, for example, may emit one color of red, blue, green, and white. The pixel PX may emit colors other than red, blue, green, and white.

The pixel PX may include a light emitting device. The light emitting device may be a self-luminous device. For example, the light emitting device may be a light emitting diode (LED). The light emitting device may emit light with a single peak wavelength or may emit light with a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting device. The pixel circuit may include at least one thin film transistor and at least one capacitor. The pixel circuit may be implemented by a semiconductor stack structure on a substrate.

The pixel unit 210 includes scan lines SL1 to SLn for applying a scan signal to the pixels PX, emission control lines EL1 to ELn for applying a light emission control signal to the pixels PX, and pixels PX. ) May include data lines DL1 to DLm for applying a data signal. Further, the pixel unit 110 may include bias application lines BL1 -BLn for applying a bias voltage to the pixels PX.

The scan lines SL1 to SLn, emission control lines EL1 to ELn, and bias application lines BL1 to BLn are connected to the pixels PX arranged in the same row, and the day lines DL1 to DLm are respectively May be connected to the pixels PX arranged in the same column.

The driving unit is provided in a non-display area around the pixel unit 210, and may drive and control the pixel unit 210. The driving unit may include a control unit 221, a scan driving unit 222, a data driving unit 223, a power supply unit 224, a test switch driving unit 225, and a bias voltage driving unit 227. The driving unit may operate according to the driving mode and the inspection mode.

In the driving mode, under the control of the controller 221, the scan driver 222 sequentially applies scan signals to the scan lines SL1 to SLn, and the data driver 223 applies a data signal to each pixel PX. Can be approved. Under the control of the controller 221, the scan driver 222 may sequentially apply the emission control signal to the emission control lines EL1-ELn. The pixels PX emit light with a brightness corresponding to a voltage level or a current level of a data signal received through the data lines DL1 to DLm in response to a scan signal received through the scan lines SL1 to SLn.

In the inspection mode, under the control of the controller 221, the scan driver 222 sequentially applies scan signals to the scan lines SL1 to SLn, and the data driver 223 applies the inspection signals to each pixel PX. Can be approved. Under the control of the controller 221, the scan driver 222 may sequentially apply the emission control signal to the emission control lines EL1-ELn. Under the control of the controller 221, the test switch driver 225 may apply a signal for turning on the test switch to each pixel.

Meanwhile, the inspection mode may be classified into a first inspection mode for inspecting whether or not a pad bonding is defective, and a second inspection mode for inspecting the chip itself.

In the first inspection mode, under the control of the controller 221, the multiplexer driving unit 228 may sequentially control the connection of the multiplexer in order to check whether the pad bonding is defective in units of lines. The multiplexer driver 228 measures the current flowing through the pixel unit 110 in units of lines of the pixel unit 110, and based on the measured current value, at least one pixel PX among the pixels PX of the corresponding line is It can be determined that the pixel circuit of) is defective.

In the second inspection mode, under the control of the controller 221, the chip inspection unit 226 may apply a signal for turning on a switch for chip inspection. In the second test mode, the circuit of the chip itself may be tested based on the second power voltage VDD_2 flowing through the second power line VL2.

The power supply unit 224 receives external power and/or internal power, converts the voltage into various levels required for operation of each component, and converts the corresponding voltage to the pixel unit according to a power control signal input from the control unit 221. It can be supplied as 210.

The power supply unit 224 may generate the first power voltage VDD_1 and apply it to the pixel unit 210 through the first power line VL1. The power supply unit 224 may generate a driving voltage and apply it to the scan driver 222, the data driver 223, and the bias voltage driver 226. The power supply unit 224 may generate the second power voltage VDD_2 and apply it to the chip inspection unit 226. The control unit 221, the scan driving unit 222, the data driving unit 223, the power supply unit 224, the test switch driving unit 225, the chip inspection unit 226 and the bias voltage driving unit 227 are each a separate integrated circuit chip or It is formed in the form of one integrated circuit chip and mounted directly on the substrate on which the pixel portion 210 is formed, mounted on a flexible printed circuit film, or attached to the substrate in the form of a TCP (tape carrier package), It can also be formed directly on the substrate.

8 is a diagram illustrating a configuration for driving a test mode according to an embodiment of the present invention.

The multiplexer according to an embodiment of the present invention may include at least one multiplexer 228-1, 228-2 to 228-n that is connected to the output terminal of each section by dividing the entire pixel unit 210 into at least one section. have. The multiplexer driver 228 may control the connection of each of the at least one multiplexer 228-1, 228-2 to 228-n to the pixel unit 210 so as to sequentially measure the current for each line of the output terminal.

When the measurement unit 230 receives a current flowing through the pixel unit 210 from at least one multiplexer 228-1, 228-2 to 228-n, at least one multiplexer 228-1, 228-2 to 228 The current value of the pixel selected by -n) can be directly measured, and based on this, it is possible to test for a bonding failure.

The measuring unit 230 according to an embodiment of the present invention may further include a current-voltage converter (not shown), and through this, converting current into voltage and then measuring it. As another example, the measurement unit 230 may further include a signal amplification unit (not shown), through which a signal may be amplified and measured.

Meanwhile, in the test mode of the present invention, the test switch driver 225 may control the first switch to be connected to the pixel unit 210. When the first switch is turned on, the pixel unit 210 may be connected to a configuration for testing a circuit itself and a configuration for testing a micro LED junction state. In this case, the first switch may be implemented as a transistor, but is not limited thereto.

In the first test mode, the test switch driving unit 225 may turn on the first switch, and the multiplexer driving unit 228 may perform at least one of the multiplexers 228-1, 228-2 to 228-n. The second switch may be controlled to be connected to the pixel unit 210. That is, in the first inspection mode, the measurement unit 230 may determine whether or not the micro LED bonding is defective for each line based on the current value input through the multiplexer.

Specifically, the first switch may connect a plurality of pixels arranged in the pixel unit 210 in units of rows. According to an embodiment of the present invention, when receiving a test signal from the control unit 221, the test switch driver 225 may drive the first switch so that the test pulse signal is input in units of rows (lines).

Meanwhile, the second switch may connect a plurality of pixels arranged in the pixel unit 210 in units of columns. According to an embodiment of the present invention, in the first test mode, the multiplexer driver 228 controls the second switch to sequentially connect a plurality of pixels included in a row connected by one switch through the second switch. I can.

For example, when the first row of the pixel unit 210 is connected by the first switch, the second switch may be connected to the pixels in the first row and the first column, and the measurement unit 230 is connected to the pixels in the first row and the first column. A current corresponding to the result of the AND gate operation included can be measured. Thereafter, the second switch may be sequentially connected to the pixels in the first row and the second column, and the measurement unit 230 may measure a current corresponding to an operation result of the AND gate included in the pixels in the first row and second column.

According to an embodiment of the present invention, the pixel unit 210 may be divided into a predetermined number of sub-areas (eg, n) in a column unit, and multiplexers 228-1 and 228-2 to each of the sub-areas 228-n) may correspond. In this case, each multiplexer may control the second switch to sequentially connect the plurality of pixels in column units in the sub-region.

For example, when the first multiplexer 228-1 corresponds to columns 1 to 5 and the second multiplexer 228-2 corresponds to columns 6 to 10, the first multiplexer 228-1 When) is connected to the first column, the second multiplexer 228-2 may connect to the sixth column. Thereafter, each multiplexer can be sequentially connected in 2 rows, 6 rows, and the like.

According to the above-described embodiment, there is an effect that it is possible to quickly check whether a bonding defect for all the pixel units 210 is defective, and to grasp an exact defect location.

In this case, the second switch may be implemented as an analog or digital logic circuit included in the multiplexers 228-1, 228-2 to 228-n to connect to at least one line of the pixel unit 210, but is limited thereto. I never do that.

In the second inspection mode, the test switch driver 225 can turn on the first switch, and the control unit 221 controls the third switch included in the chip inspection unit 226 to control the chip inspection unit 226 and the pixel. The unit 210 may be electrically connected. That is, in the second inspection mode, the chip inspection unit 226 may determine whether the pixel driving circuit chip itself has an error based on the current value. In this case, the third switch may be implemented as a transistor, but is not limited thereto.

9 is an example of a pixel of the display device 30B according to an embodiment of the present invention.

In the embodiment of FIG. 9, for convenience of description, the pixels Pnm in the n-th row and m-th column will be described as an example. The pixel Pnm is one of a plurality of pixels included in the n-th row, and is connected to the scanning line SLn corresponding to the n-th row and the data line DLm corresponding to the m-th column.

The pixel Pnm crosses the scan line SLn for transmitting the scan signal, the data line DLm for transmitting the data signal by crossing the scan line SLn, and transfers the first power voltage VDD_1 and the second power voltage VDD_L. Can be connected to a power line.

The pixel Pnm may include a light emitting diode (LED) and a pixel circuit connected to the light emitting diode (LED). The pixel circuit may include first to third transistors T1 to T3, a capacitor C, a test transistor TT, and a bias transistor BT. The first electrode or the first terminal of each of the first to third transistors T1 to T3 and the bias transistor BT may be a drain terminal, and the second electrode or the second terminal may be a source terminal.

The first transistor T1 includes a gate electrode connected to the first electrode of the capacitor C, a first electrode connected to the light emitting diode LED through the third transistor T3, and a second electrode connected to the third power voltage VSS. It may include an electrode. The third power voltage VSS may be a ground voltage GND. The first transistor T1 serves as a driving transistor and may receive a data signal according to a switching operation of the second transistor T2 and supply current to the light emitting diode LED.

The first transistor T1 according to an embodiment of the present invention may operate in a low voltage region. For example, the first transistor T1 may operate in a triode region.

The second transistor T2 may include a gate electrode connected to the scan line SLn, a first electrode connected to the data line DLm, and a second electrode connected to the gate electrode of the first transistor T1. The second transistor T2 is turned on according to the scan signal transmitted through the scan line SLn and serves as a switching transistor that transmits the data signal transmitted to the data line DLm to the gate electrode of the first transistor T1. can do.

The second transistor T2 according to the exemplary embodiment of the present invention may operate in a low voltage region together with the first transistor T1. That is, the second transistor T2 may operate in a triode region. In this case, the data signal may be converted into a voltage range corresponding to the low voltage operation of the first transistor T1 and the second transistor T2.

The third transistor T3 includes a gate electrode connected to the emission control line ELn, a first electrode connected to the second electrode of the bias transistor BT, and a second electrode connected to the first electrode of the first transistor T1. can do. The third transistor T3 may be turned on according to the emission control signal transmitted through the emission control line ELn so that the driving current of the first transistor T1 flows through the light emitting diode LED. In the embodiment of FIG. 9, the emission control line ELn is connected to the scan driver 222 and may receive an emission control signal from the scan driver 222. In another embodiment, the emission control line ELn may be connected to the scan driver 122 and a separate emission control driver (not shown) to receive the emission control signal.

The bias transistor BT may include a gate terminal connected to the bias line BLn, a first electrode connected to the second electrode of the light emitting diode LED, and a second terminal connected to the first terminal of the third transistor T3. have. The bias transistor BT may be a voltage control transistor that maintains a turn-on state in a driving mode by a bias voltage applied to the gate terminal and controls a drain voltage of the first transistor T1.

According to an embodiment of the present invention, the drain voltage of the first transistor T1 is controlled by the bias transistor BT, so that the first to third transistors T1 to T3 can function as low voltage transistors. have. That is, the bias transistor BT may control the drain voltage of the first transistor T1 so that the first transistor T1 operates in the triode region.

The bias transistor BT may be turned on by a bias voltage applied through the bias line BLn. The bias voltage may be a direct current voltage DC of a predetermined level to keep the bias transistor BT always turned on. The node voltage Vx between the third transistor T3 and the bias transistor BT, that is, the drain voltage of the third transistor T3, may be controlled according to the turn-on state of the bias transistor BT. The channel resistance of the bias transistor BT may vary depending on the bias voltage. That is, the bias transistor BT may operate as a variable linear resistor.

The node voltage Vx, that is, the drain voltage of the third transistor T3, may be determined according to the channel resistance of the bias transistor BT. Accordingly, by controlling the bias voltage, the drain voltage of the third transistor T3 can be controlled to a voltage that satisfies the condition that the third transistor T3 operates in the triode region.

The capacitor C may include a first electrode connected to the gate electrode of the first transistor T1 and a second electrode connected to the third power voltage VSS.

The first electrode of the light emitting diode LED may receive the first power voltage VDD_1. The second electrode of the light emitting diode LED may be connected to the first electrode of the bias transistor BT. A light-emitting diode (LED) can display an image by emitting light with a luminance corresponding to a data signal. In the inspection mode, the light emitting diode (LED) may not emit light.

The first switch SW1 may be connected to the second electrode of the bias transistor BT and the first electrode of the third transistor T3. In this case, the first switch SW1 is controlled by the test switch driver 225 and may be turned on in the test mode (the first test mode and the second test mode). Specifically, the first switch may include a first pole and a second pole, and the first pole may be connected to the second electrode of the bias transistor BT connected to the second electrode of the plurality of light emitting devices, and the second The pole may be connected to a node corresponding to the second switch SW2 and the third switch SW3.

In the first test mode, the second switch SW2 included in the multiplexer and implemented may be turned on by the multiplexer driver 228. That is, in the first test mode, the first switch SW1 and the second switch SW2 may be turned on.

In this case, the current flowing through the first power line VL1 may flow sequentially through the light emitting diode (LED), the bias transistor (BT), the first switch (SW1), and the second switch (SW2), and the measurement unit By measuring the current value, 230 may measure whether or not bonding of the pad PAD is defective.

According to an embodiment of the present invention, the light emitting device (LED) may be an LED included in a sub-pixel of a pixel. In this case, the multiplexer driver 228 may control the second switch SW2 to inspect each sub-pixel.

In the second inspection mode, the third switch SW3 implemented by being included in the chip inspection unit 226 may be turned on by the control unit 221. The third switch SW3 may be connected to the second power line VL2 to be turned on in the second test mode, and may be turned off in the driving mode and the first test mode. That is, in the second test mode, the first switch SW1 and the third switch SW3 may be turned on.

In units of rows, a scan signal may be applied to the second transistor T2 through the scan line SLn, and a data signal may be applied to the data line DLm in response to the scan signal. Subsequently, the emission control signal may be applied to the third transistor T3 through the emission control line ELn. The inspection control signal from the control unit 221 may be applied to the third switch SW3. In this case, when the third switch SW3 is implemented as a separate transistor, a separate inspection control line may be included.

The test control signal may be applied to the third switch SW3 while the scan signal is applied to the second transistor T2 through the scan line SLn. The third switch SW3 is turned on by the inspection control signal, and the current flowing through the second power line VL2 passes through the third switch SW3, the third transistor T3, and the first transistor T1. Thus, current can flow. The current measuring circuit of the inspection unit 226 may measure a current flowing through the second power line VL2 to which the second power voltage VDD_2 is applied.

That is, in the second test mode, the first to third transistors T1 to T3 are applied by applying the second power voltage VDD_2 through the second power line VL2 to the pixel circuit using the third switch SW3. It is possible to check whether the pixel circuit including) is operating normally.

10 is a timing diagram for explaining timing in a first test mode according to an embodiment of the present invention.

Referring to FIG. 10, during the test time for each line (SCAN_OUT1, SCAN_OUT2, etc.), at least one multiplexer 228-1 to 228-n allows current to pass through the first switch SW1 and the second switch SW2. It is possible to connect by sequentially changing the multiplexer code (MUX code). The measuring unit 230 may determine whether or not bonding of the pads is defective by measuring the current that has been passed through.

Specifically, in response to the test signal TEST_SCAN signal, when a test pulse signal is applied to each row of the pixel unit 210 during a line-by-line test time (1 Line Test Time), the multiplexers 228-1 to 228-n May change the second switch SW2 to sequentially change the multiplexer code (MUX code) to sequentially connect the pixels included in the corresponding row according to the column order.

For example, when the test pulse signal for the first row is applied during the first test time (SCAN_OUT1), the multiplexers 228-1 to 228-n sequentially sequentially select the pixels included in the first row in the corresponding subregions. Can be connected by

According to an exemplary embodiment of the present invention, 1 Line Test Time may be flexibly set to correspond to the resolution of the display device 30 or the number of sections of the pixel unit.

Meanwhile, according to an embodiment of the present invention, the display device 30A of FIG. 2 and the display device 30B of FIG. 7 may be implemented as one display device. The display device according to an example may detect a row-by-row pad bonding failure through a test pulse signal in a first inspection mode, and may detect a pad bonding failure for each section through a multiplexer.

However, the above-described example is only an example, and the display device may detect a row-by-row pad bonding failure through a test pulse signal in the first inspection mode, and the pads for each section in column units through a multiplexer in the second inspection mode. The bonding failure can be detected, and the circuit of the chip itself can be inspected in the third inspection mode, but is not limited thereto.

As described above, the present invention has been described with reference to the embodiments shown in the drawings, but these are only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

10: light emitting element array
20: driver circuit board
30: display device
110: pixel portion
121: control unit
122: scan driver
123: data driver
124: power supply
125: test pulse generator
126: bias voltage driver
130: test data processing unit
131: test data latch
132: shift register

Claims (4)

A plurality of pixels arranged in the display area; And
A power supply unit disposed around the display area and outputting a power voltage to a power line connected to the plurality of pixels; and
Each of the plurality of pixels,
At least one light emitting device comprising a first electrode and a second electrode, the first electrode connected to the power line; And
And an AND gate connected to an input terminal of the second electrode of the at least one light emitting device,
The input terminal of the first AND gate included in the first pixel among the plurality of pixels receives a node voltage and a test pulse signal applied to the second electrode of at least one light emitting device included in the first pixel.
The output terminal of the first AND gate outputs an AND operation result based on the node voltage and the test pulse signal, and a second among the plurality of pixels arranged adjacent to the same row as the first pixel A micro display device connected to an input terminal of a second AND gate included in a pixel to transmit the operation result. The method of claim 1,
The micro display device,
A measuring unit that measures a current to test whether or not a joint is defective;
A first switch for connecting the plurality of pixels arranged in the display area in row units; And
A second switch for sequentially connecting the plurality of pixels arranged in the display area in column units; Including more,
The measuring unit measures a current corresponding to an AND gate operation result by sequentially connecting a plurality of pixels included in a row to which the first switch is connected through the second switch. The method of claim 2,
The display area is divided into a predetermined number of sub-areas per column,
The second switch is provided for each of the sub-regions, and sequentially connects a plurality of pixels included in a row to which the first switch is connected in the sub-region. The method of claim 2,
The micro display device,
An inspection unit testing defects in the pixel circuit; And
Further comprising a third switch connected to the inspection unit,
The first switch includes a first pole and a second pole, the first pole is connected to the second electrode of the plurality of light emitting devices,
The second switch connects the measurement unit and the second pole of the first switch,
The third switch connects the inspection unit and the second pole of the first switch,
In a first inspection mode, the first switch and the second switch are turned on, and the measurement unit tests whether or not there is a bonding failure based on a current flowing through the first switch and the second switch,
In a second inspection mode, the first switch and the third switch are turned on, and the inspection unit tests a defect in a pixel circuit based on a current flowing through the first switch and the third switch. .

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