KR20220150234A - Display Device - Google Patents
Display Device Download PDFInfo
- Publication number
- KR20220150234A KR20220150234A KR1020220136112A KR20220136112A KR20220150234A KR 20220150234 A KR20220150234 A KR 20220150234A KR 1020220136112 A KR1020220136112 A KR 1020220136112A KR 20220136112 A KR20220136112 A KR 20220136112A KR 20220150234 A KR20220150234 A KR 20220150234A
- Authority
- KR
- South Korea
- Prior art keywords
- pixel
- line
- gate
- gate line
- transistor
- Prior art date
Links
- 238000000034 method Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 3
- 208000015953 X-linked Emery-Dreifuss muscular dystrophy Diseases 0.000 description 1
- 201000001520 X-linked Emery-Dreifuss muscular dystrophy 1 Diseases 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
본 발명은 표시장치에 관한 것이다.The present invention relates to a display device.
평판 표시장치(FPD; Flat Panel Display)는 소형화 및 경량화에 유리한 장점으로 인해서 데스크탑 컴퓨터의 모니터뿐만 아니라, 노트북컴퓨터, 태블릿 등의 휴대용 컴퓨터나 휴대 전화 단말기 등에 폭넓게 이용되고 있다. 이러한 평판 표시장치는 액정표시장치{Liquid Crystal Display; LCD), 플라즈마 표시장치(Plasma Display Panel; PDP), 전계 방출표시장치{Field Emission Display; FED) 및 유기발광다이오드 표시장치(Organic Light Emitting diode Display; 이하, OLED) 등이 있다. Flat panel displays (FPDs) are widely used in portable computers such as notebook computers and tablets, mobile phone terminals, etc. as well as monitors of desktop computers due to their advantages in miniaturization and weight reduction. Such a flat panel display device is a liquid crystal display device; LCD), Plasma Display Panel (PDP), Field Emission Display; FED) and organic light emitting diode display (OLED).
일반적으로 표시장치는 게이트신호에 의해서 턴-온 되는 트랜지스터를 이용하여 데이터전압을 픽셀에 공급한다. 표시패널의 사이즈가 커지고 해상도가 높아지면서 게이트라인의 길이가 길어지고 게이트라인에 연결되는 트랜지스터들이 많아지면서, 게이트신호의 지연 현상으로 인하여 휘도 불균일에 의한 문제점이 나타타고 있다. In general, a display device supplies a data voltage to a pixel using a transistor turned on by a gate signal. As the size of the display panel increases and the resolution increases, the length of the gate line increases and the number of transistors connected to the gate line increases, resulting in a problem of luminance non-uniformity due to a delay of the gate signal.
본 발명은 게이트신호의 지연 현상을 개선할 수 있는 표시장치를 제공하기 위한 것이다.An object of the present invention is to provide a display device capable of improving the delay of a gate signal.
본 발명에 의한 표시장치는 하나 이상의 트랜지스터를 포함하는 픽셀 및 트랜지스터의 게이트전극과 연결되는 게이트라인을 포함한다. 게이트라인은 적어도 일부 영역에서 동일한 게이트신호를 공급받는 두 개의 게이트라인로 분리된다. A display device according to the present invention includes a pixel including one or more transistors and a gate line connected to a gate electrode of the transistor. The gate line is divided into two gate lines receiving the same gate signal in at least some regions.
본 발명의 실시 예에 의한 표시장치는 제1 게이트신호에 의해서 제어되는 제1 트랜지스터, 제2 게이트신호에 의해서 제어되는 제2 및 제3 트랜지스터를 포함한다. 제1 게이트신호는 제1 게이트라인를 통해서 공급된다. 메인 제2 게이트라인은 제2 게이트신호를 공급하며, 제2 트랜지스터와 연결된다. 서브 제2 게이트라인은 제2 게이트신호를 공급하며, 제3 트랜지스터와 연결된다.A display device according to an embodiment of the present invention includes a first transistor controlled by a first gate signal, and second and third transistors controlled by a second gate signal. The first gate signal is supplied through the first gate line. The main second gate line supplies a second gate signal and is connected to the second transistor. The sub-second gate line supplies a second gate signal and is connected to the third transistor.
본 발명에 의한 표시장치는 동일한 게이트신호를 인가하는 게이트라인을 적어도 일부 구간에서는 이중 라인으로 형성하기 때문에, 게이트신호의 지연 현상을 개선할 수 있다. In the display device according to the present invention, since the gate line to which the same gate signal is applied is formed as a double line in at least some sections, the delay of the gate signal can be improved.
본 발명은 이중 라인 중에서 어느 하나의 게이트라인에 오픈 불량이 발생하여도 동작 불능 상태가 안되기 때문에, 오픈 불량으로 인해서 생산 수율이 낮아지는 것을 개선할 수 있다. According to the present invention, since the operation is not inoperable even when an open defect occurs in any one of the double lines, it is possible to improve the production yield due to the open defect.
본 발명은 게이트라인을 이중 라인으로 형성하기 때문에, 게이트라인의 폭을 넓히지 않으면서도 게이트신호의 지연 현상을 개선할 수 있다. 본 발명은 게이트라인의 폭을 기존의 설계에서와 동일하게 설정할 수 있기 때문에, 트랜지스터의 소자 특성이 변할 가능성을 배제할 수 있다.In the present invention, since the gate line is formed as a double line, the delay of the gate signal can be improved without increasing the width of the gate line. In the present invention, since the width of the gate line can be set to be the same as in the conventional design, the possibility of changing the device characteristics of the transistor can be excluded.
도 1은 본 발명에 의한 표시장치의 구성을 나타내는 도면이다.
도 2는 제1 실시 예에 의한 게이트라인을 나타내는 도면이다.
도 3은 제2 실시 예에 의한 게이트라인을 나타내는 도면이다.
도 4는 시프트레지스터의 구성을 나타내는 도면이다.
도 5는 본 발명에 의한 픽셀 구조를 나타내는 도면이다.
도 6은 제1 실시 예에 의한 픽셀 어레이를 나타내는 도면이다.
도 7은 제1 실시 예에 의한 픽셀 어레이의 단면을 나타내는 도면이다.
도 8은 제2 실시 예에 의한 픽셀 어레이를 나타내는 도면이다.
도 9는 제2 실시 예에 의한 픽셀 어레이의 단면을 나타내는 도면이다.
도 10은 본 발명에 의한 쇼트 불량을 리페어하는 방법을 나타내는 도면이다.1 is a diagram showing the configuration of a display device according to the present invention.
2 is a diagram illustrating a gate line according to the first embodiment.
3 is a view showing a gate line according to the second embodiment.
4 is a diagram showing the configuration of a shift register.
5 is a diagram illustrating a pixel structure according to the present invention.
6 is a diagram illustrating a pixel array according to the first embodiment.
7 is a diagram illustrating a cross-section of the pixel array according to the first embodiment.
8 is a diagram illustrating a pixel array according to a second embodiment.
9 is a diagram illustrating a cross-section of a pixel array according to a second embodiment.
10 is a view showing a method for repairing a short-circuit defect according to the present invention.
를 다시 하여야 한다. 하지만, 본 발명은 게이트라인의 폭을 기존의 설계에서와 동일하게 설정할 수 있기 때문에, 트랜지스터의 소자 특성이 변할 가능성을 배제할 수 있다.should be done again. However, in the present invention, since the width of the gate line can be set to be the same as in the conventional design, the possibility of changing the device characteristics of the transistor can be excluded.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야만 할 것이다.Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.
100: 표시패널
110: 타이밍 콘트롤러
120: 데이터 구동회로
130,140: 게이트 구동회로
EMD1~EMD(n): 에미션 드라이버
SD1~SD(n): 스캔 드라이버
RP: 보조패턴100: display panel 110: timing controller
120:
EMD1~EMD(n): Emission Driver
SD1~SD(n): Scan Driver
RP: auxiliary pattern
Claims (10)
적어도 하나의 트랜지스터와 연결되고, 상기 픽셀의 외곽에서 복수의 라인으로 분리되고, 상기 픽셀의 내부에서 하나의 라인으로 상기 픽셀을 가로지르는 게이트라인; 및
상기 픽셀의 외곽에서 상기 게이트라인과 수직으로 배치되는 고전위전압라인 및 데이터라인을 포함하는 표시장치.a pixel comprising at least one transistor; and
a gate line connected to at least one transistor, separated into a plurality of lines outside the pixel, and crossing the pixel with one line inside the pixel; and
and a high-potential voltage line and a data line disposed perpendicular to the gate line outside the pixel.
상기 픽셀의 내부에서 하나의 라인으로 상기 픽셀의 내부를 가로지르고, 상기 픽셀의 외곽에서 2개의 라인으로 분리되고, 상기 픽셀에 인접한 다른 픽셀의 내부에서 다시 하나의 라인으로 상기 다른 픽셀의 내부를 가로지르는 표시 장치.The method of claim 1, wherein the gate line comprises:
One line crosses the inside of the pixel from the inside of the pixel, is divided into two lines at the outside of the pixel, and another line crosses the inside of the other pixel from inside another pixel adjacent to the pixel squeaking display device.
상기 고전위전압라인 및 상기 데이터라인은 상기 픽셀의 양측에 배치되는 표시장치.According to claim 1,
The high potential voltage line and the data line are disposed on both sides of the pixel.
상기 픽셀의 양측에서 상기 게이트라인은 상기 복수의 라인으로 분리되고,
상기 고전위전압라인은 상기 픽셀의 일측에서 상기 게이트라인과 중첩되고,
상기 데이터라인은 상기 픽셀의 타측에서 상기 게이트라인과 중첩되는 표시장치.4. The method of claim 3,
The gate line is divided into the plurality of lines on both sides of the pixel,
the high potential voltage line overlaps the gate line at one side of the pixel;
The data line overlaps the gate line at the other side of the pixel.
상기 게이트라인은 게이트 구동부의 시프트레지스터에 연결되는 표시장치.According to claim 1,
The gate line is connected to the shift register of the gate driver.
상기 게이트라인은 에미션 라인 및 스캔라인 중 적어도 하나를 포함하는 표시장치.According to claim 1,
and the gate line includes at least one of an emission line and a scan line.
기판; 및
상기 기판 상에 배치되는 쉴드층을 포함하는 표시장치.The method of claim 1, wherein the transistor comprises:
Board; and
and a shield layer disposed on the substrate.
상기 쉴드층 상에 형성되는 반도체층; 및
상기 반도체층 상에 형성되는 게이트전극을 더 포함하는 표시장치. The method of claim 7, wherein the transistor comprises:
a semiconductor layer formed on the shield layer; and
and a gate electrode formed on the semiconductor layer.
상기 게이트전극 상에 형성되는 소스/드레인 전극을 더 포함하고,
상기 쉴드층은 컨택홀을 통해 상기 소스/드레인 전극에 연결되는 표시장치.The method of claim 8, wherein the transistor comprises:
Further comprising a source/drain electrode formed on the gate electrode,
The shield layer is connected to the source/drain electrodes through a contact hole.
상기 게이트전극은 상기 게이트라인에 연결되는 표시장치.9. The method of claim 8,
and the gate electrode is connected to the gate line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020220136112A KR102670408B1 (en) | 2022-10-21 | Display Device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170128230A KR102459073B1 (en) | 2017-09-29 | 2017-09-29 | Display Device |
KR1020220136112A KR102670408B1 (en) | 2022-10-21 | Display Device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020170128230A Division KR102459073B1 (en) | 2017-09-29 | 2017-09-29 | Display Device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20220150234A true KR20220150234A (en) | 2022-11-10 |
KR102670408B1 KR102670408B1 (en) | 2024-05-30 |
Family
ID=
Also Published As
Publication number | Publication date |
---|---|
KR102459073B1 (en) | 2022-10-26 |
KR20190038142A (en) | 2019-04-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102034112B1 (en) | Liquid crystal display device and method of driving the same | |
US10878764B2 (en) | Array substrate | |
US11444143B2 (en) | AMOLED display panel and corresponding display device | |
US9691793B2 (en) | Array substrate and display panel | |
KR20240054939A (en) | Display device | |
US9437142B2 (en) | Pixel circuit and display apparatus | |
KR101421288B1 (en) | Thin Film Transistor Substrate Having Metal Oxide Semiconductor | |
KR102627214B1 (en) | Organic light emitting display device | |
US20190294280A1 (en) | Manufacturing method for display panel, display panel and display device | |
WO2022082773A1 (en) | Display panel and display device | |
WO2016004713A1 (en) | Pixel circuit and display device | |
WO2021042523A1 (en) | Display panel | |
US20130271715A1 (en) | Liquid crystal display device | |
KR102096993B1 (en) | Charge discharging circuit, display substrate, display device, and method for discharging charge thereof | |
US9905177B2 (en) | Pixel structure, array substrate, display panel and display device | |
US20110267572A1 (en) | Active device array substrate | |
US11335242B2 (en) | Display substrate and display device | |
US20230189596A1 (en) | Display panel and display device | |
KR20220150234A (en) | Display Device | |
KR102052741B1 (en) | Liquid crystal display device | |
US20210159301A1 (en) | Display apparatus | |
KR102118460B1 (en) | display device and Method for manufacturing the same | |
KR102185256B1 (en) | Display device | |
KR102181298B1 (en) | Display device | |
US11963418B2 (en) | Display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A107 | Divisional application of patent | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
AMND | Amendment | ||
E601 | Decision to refuse application | ||
AMND | Amendment | ||
X701 | Decision to grant (after re-examination) |