KR20190038142A - Display Device - Google Patents

Abstract

A display device according to the present invention includes a pixel including one or more transistors and a gate line connected to a gate electrode of the one or more transistors. The gate line is divided into two gate lines receiving the same gate signal in at least some regions. The display device according to an embodiment of the present invention includes a first transistor controlled by a first gate signal and second and third transistors controlled by a second gate signal. The first gate signal is supplied through the first gate line. A main second gate line supplies the second gate signal, and is connected to the second transistor. A sub second gate line supplies the second gate signal and is connected to the third transistor.

Description

[0001]

The present invention relates to a display device.

2. Description of the Related Art Flat panel displays (FPDs) are widely used not only for monitors of desktop computers but also for portable computers such as notebook computers and tablets, as well as mobile phone terminals, because they are advantageous in miniaturization and weight reduction. Such a flat panel display device includes a liquid crystal display (LCD) (LCD), a plasma display panel (PDP), a field emission display (FED) and an organic light emitting diode display (OLED).

Generally, a display device uses a transistor that is turned on by a gate signal to supply a data voltage to a pixel. As the size of the display panel is increased and the resolution is increased, the length of the gate line becomes longer and the number of transistors connected to the gate line becomes larger. Thus, a problem arises due to the luminance unevenness due to the delay of the gate signal.

The present invention is intended to provide a display device capable of improving the delay of a gate signal.

A display device according to the present invention includes a pixel including one or more transistors and a gate line connected to a gate electrode of the transistor. The gate line is divided into two gate lines which receive the same gate signal in at least some regions.

A display device according to an embodiment of the present invention includes a first transistor controlled by a first gate signal, and a second transistor and a third transistor controlled by a second gate signal. The first gate signal is supplied through the first gate line. The main second gate line supplies the second gate signal and is connected to the second transistor. The sub second gate line supplies the second gate signal and is connected to the third transistor.

The display device according to the present invention can improve the delay of the gate signal because the gate line applying the same gate signal is formed as a double line in at least a part of the section.

In the present invention, even if an open defect occurs in any one gate line among the double lines, an operation failure state is not attained. Thus, it is possible to improve the production yield due to the open defect.

Since the gate line is formed as a double line in the present invention, the delay of the gate signal can be improved without widening the width of the gate line. Since the width of the gate line can be set to be the same as in the conventional design, the present invention can eliminate the possibility that the device characteristics of the transistor are changed.

1 is a view showing a configuration of a display device according to the present invention.
2 is a view showing a gate line according to the first embodiment.
3 is a view showing a gate line according to the second embodiment.
4 is a diagram showing a configuration of a shift register.
5 is a diagram showing a pixel structure according to the present invention.
6 is a view showing a pixel array according to the first embodiment.
7 is a cross-sectional view of a pixel array according to the first embodiment.
8 is a view showing a pixel array according to the second embodiment.
9 is a cross-sectional view of a pixel array according to the second embodiment.
Fig. 10 is a diagram showing a method for repairing short defects according to the present invention. Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the circuit diagram shown in the present invention, the switch elements may be implemented as transistors of an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. In the following embodiments, a p-type transistor is exemplified, but it should be noted that the present invention is not limited to this. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention should not be limited to the source and drain of the transistor.

1 is a view showing a configuration of a display device according to the present invention.

1, the organic light emitting diode display according to the present invention includes a display panel 100, a data driver 120, gate drivers 130 and 140, and a timing controller 110 in which pixels P are arranged in a matrix. Respectively.

The display panel 100 includes a pixel array 100A in which pixels P are disposed and displays an image and a non-display portion 100B in which a shift register 140 is disposed and an image is not displayed.

The pixel array 100A includes a plurality of pixels P, and displays an image based on the gradation displayed by each of the pixels P. [ The pixels P are arranged along the first to n-th pixel lines HL1 to HL (n). Each pixel P is connected to any one of the data lines DL1 to DL (m) arranged along a column line and connected to the gate lines GL1 to GL4 arranged along the pixel line HL. GL (n)). The pixels P arranged in the first pixel line HL1 are connected to the first gate line GL1 and the pixels P arranged in the nth pixel line HL (n).

The timing controller 110 is for controlling the driving timings of the data driver 120 and the gate drivers 130 and 140. To this end, the timing controller 110 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 100 and supplies the digital video data RGB to the data driver 120. The timing controller 110 is also connected to the data driver 120 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate drivers 130 and 140 are generated.

The data driver 120 drives the data line unit DL. To this end, the data driver 120 converts the digital video data RGB input from the timing controller 110 into analog data voltages based on the data control signal DDC and supplies the analog data voltages to the data lines DL.

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in an IC form and the shift register 140 is connected to the gate (Gate In Panel: GIP) method.

The level shifter 130 level-shifts the clock signals and the gate control signal GDC such as the start signal VST under the control of the timing controller 110, and supplies the level shift signal to the shift register 140. The shift register 140 buffers the gate signal based on the gate control signal GDC supplied from the level shifter 130.

FIGS. 2 and 3 are views showing an embodiment of a gate line to which a gate signal is applied. In particular, Figs. 2 and 3 show a gate line GL (n) to which a gate signal GS (n) applied to a pixel P arranged in an nth pixel line HL (n) is applied have.

Referring to FIG. 2, pixels P1, P2, and P3 according to the first embodiment include a first switching transistor ST1 that operates in response to a gate signal GS (n). In this specification, each of the pixels P1, P2, and P3 may be defined as an area where transistors connected to the gate line, for example, the first switching transistor ST1 as shown in FIG. The gate line GL (n) according to the first embodiment traverses the pixels P1, P2 and P3 and is connected to the main gate line GL (n) a and the sub- (GL (n) b). In this specification, the main gate line GL (n) a and the sub gate line GL (n) b are not functionally distinguished, but are connected to the gate line GS (n) .

Since the gate line GL (n) of the first embodiment is formed as a double line in a certain section, the delay phenomenon of the gate signal GS (n) can be improved. In the first embodiment, since the gate line GL (n) is formed as a double line at a position outside the inner area of the pixel P, the pixel P inner array design can be made the same as before. Thus, the delay of the gate signal GS (n) can be improved without significantly changing the array design.

Referring to FIG. 3, the pixels P1, P2, and P3 according to the second embodiment include a second switching transistor ST2 and a third switching transistor ST3 responsive to the gate signal GS (n) do. The gate line GL (n) according to the second embodiment includes the main gate line GL (n) a and the sub gate line GL (n) b. The main gate line GL (n) a applies the gate signal GS (n) to the second switching transistor ST2 and the sub gate line GL (n) b is applied to the third switching transistor ST3 And applies the gate signal GS (n).

The main gate line GL (n) a and the sub gate line GL (n) b may be connected to each other via the auxiliary pattern RP at a position outside the pixel P region. In FIG. 3, the auxiliary patterns RP are located between the pixels P1, P2, and P3. However, the number of the auxiliary patterns RP is not limited thereto. Particularly, the auxiliary pattern RP may be formed in a structure in which one gate line GL (n) is connected to the output terminal of the shift register 140 while the non-display portion 100B in which the shift register 140 is disposed have.

The second switching transistor ST2 and the third switching transistor ST3 receiving the same gate signal are connected to the main gate line GL (n) a and the sub gate line GL (n) b, respectively, Since the gate signal GS (n) is applied through the gate signal GS (n), it is more advantageous to improve the delay phenomenon of the gate signal GS (n). The more transistors connected to the gate line, the more the load that affects the gate signal increases and the delay of the gate signal increases. In particular, since the pixels of the organic light emitting diode often have two or more transistors receiving the same gate signal, the delay problem of the gate signals becomes more serious. The present invention can relax the delay of the gate signal by separating the gate line connected to the transistors receiving the same gate signal.

As described above, according to the present invention, the gate line GL (n) supplying the same gate signal GS (n) is connected to the main gate line GL (n) a and the sub gate line GL (n) b, it is possible to improve the phenomenon that the gate signal GS (n) is delayed.

(N) a and the subgate line GL (n) b even if an open defect occurs in the main gate line GL (n) a or the subgate line GL (GL (n) b) is connected through the auxiliary pattern RP, driving failure can be prevented.

Further, even if the main gate line GL (n) a or the sub gate line GL (n) b is short-circuited with another metal layer, the gate signal can be smoothly applied through the repair process. The method for repairing the short phenomenon will be described later with reference to specific embodiments.

Hereinafter, a specific embodiment of the organic light emitting display device to which the present invention is applied will be described.

4 is a diagram showing a configuration of a shift register according to the present invention. Fig. 4 is a timing chart showing a case where the gate signal for driving the pixels P arranged in the nth pixel line HL (n) is the emission signal EM (n), the first scan signal SCAN1 (n) And a scan signal SCAN2 (n).

Referring to FIG. 4, the shift register according to the present invention includes an emission signal generator 141 and a scan signal generator 143.

The emission signal generation section 141 includes first through nth emission drivers EMD1 through EMD (n). The first emission drive EMD1 generates the first emission signal EM1 and applies it to the emission line EML (1) of the first pixel line HL1. The second emission driver EMD2 generates the emission signal EM2 and applies it to the emission line EML (2) of the second pixel line HL2. The nth emission driver EMD (n) generates the emission signal EM (n) and applies it to the emission line EML (n) of the nth pixel line HL (n).

The scan signal generating unit 143 includes first to nth scan drivers SD1 to SD (n). The first scan driver SD1 generates and applies a first scan signal SCAN1 (1) to the first scan line SL1 (1) of the first pixel line HL1 and a second scan signal SCAN2 1) and applies it to the second scan line SL2 (1) of the first pixel line HL1. The second scan driver SD2 generates and applies the first scan signal SCAN1 (2) to the first scan line SL1 (2) of the second pixel line HL2, and the second scan signal SCAN2 2) to the second scan line SL2 (2) of the second pixel line HL2. The nth scan driver SD (n) generates and applies the first scan signal SCAN1 (n) to the first scan line SL1 (n) of the nth pixel line HL (n) 2 scan signal SCAN2 (n) and applies it to the second scan line SL2 (n) of the n-th pixel line HL (n).

4, each of the scan drivers SD1 to SD (n) generates the first scan signal SCAN1 and the second scan signal SCAN2. However, the first scan signals SCAN1 and SCAN2 The two scan signals SCAN2 may be output from the respective scan drivers, respectively.

The first scan lines SL1 (1) to SL1 (n) and the second scan lines SL2 (1) to SL2 (n) shown in FIG. 4, Are separated from each other in the region of the pixel array 100A. (EML (1) to EML (n)), the first scan lines SL1 (1) to SL1 (n), and the second scan lines SL2 SL2 (n)) are separated as follows.

5 is a diagram showing a pixel structure according to the present invention. The pixel shown in Fig. 5 shows pixels arranged in the nth pixel line HL (n).

Referring to FIG. 5, a pixel includes an organic light emitting diode (OLED), a driving transistor DT, first through fifth transistors T1 through T5, and a storage capacitor Cst.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. The anode electrode of the organic light emitting diode (OLED) is connected to the fifth node (N5), and the cathode electrode is connected to the input terminal of the low potential voltage (VSS).

The driving transistor DT controls the driving current applied to the organic light emitting diode OLED according to its source-gate voltage Vsg. The driving transistor DT includes a gate electrode connected to the first node N1, a source electrode connected to the third node N3, and a drain electrode connected to the second node N2.

The first transistor T1 includes a gate electrode connected to the first scan line SL1 (n), a source electrode connected to the first data line DL1, and a drain electrode connected to the fourth node N4 do. The first transistor T1 applies the data voltage Vdata to the fourth node N4 in response to the first scan signal SCAN1 (n).

The second transistor T2 includes a gate electrode connected to the main second scan line SL2 (n) a, a drain electrode connected to the first node N1, and a source electrode connected to the second node N2 . The second transistor T2 diode-couples the first node N1 and the first node N1 in response to the second scan signal SCAN2 (n).

The third transistor T3 includes a gate electrode connected to the main emission line EML (n) a, a source electrode connected to the fourth node N4, and a drain electrode connected to the initialization voltage line VL do. The third transistor T3 applies the initialization voltage Vini to the fourth node N4 in response to the emission signal EM (n).

The fourth transistor T4 includes a gate electrode connected to the sub-emission line EML (n) b, a source electrode connected to the second node N2, and a drain electrode connected to the fifth node N5 do. The fourth transistor T4 couples the second node N2 and the fifth node N5 in response to the emission signal EM (n).

The fifth transistor T5 includes a gate electrode connected to the sub second scan line SL2 (n) b, a drain electrode connected to the initialization voltage line VL, and a source electrode connected to the fifth node N5 . The fifth transistor T5 applies an initial voltage Vinit to the fifth node N5 in response to the second scan signal SCAN2 (n).

The storage capacitor Cst is connected between the first node N1 and the fourth node N4. The auxiliary capacitor Cgv is connected between the first node N1 and the third node N3. The third node N3 of the auxiliary capacitor Cgv is connected to the high potential voltage line VDDL caused by the constant voltage to prevent the voltage of the gate electrode of the driving transistor DT from being changed by an undesired coupling phenomenon.

5, the pixel circuit according to the present invention is characterized in that an emission line EML (n) for supplying an emission signal EM (n) is divided into a main emission line EML (n) a and a sub- And an emission line (EML (n) b). The third transistor T3 receives the emission signal EM (n) through the main emission line EML (n) a and the fourth transistor T4 receives the emission signal EM (n) (n) via the transmission line EM (b).

The second scan line SL (n) for supplying the second scan signal SCAN2 (n) is connected to the main second scan line SL2 (n) a and the sub second scan line SL2 (n) b Separated. The second transistor T2 is supplied with the second scan signal SCAN2 (n) through the main second scan line SL2 (n) a and the fifth transistor T5 is supplied to the sub second scan line SL2 (n) b through the second scan signal SCAN2 (n).

6 is a view showing a pixel array according to the first embodiment. In particular, FIG. 6 shows a pixel array of an n-th pixel line consisting of the pixel shown in FIG.

6, the data lines DL1 to DL3, the high potential voltage lines VDDLs, and the initialization voltage VDD are provided on the sides of the pixels P1, P2, and P3 disposed in the nth pixel line HL (n) Lines VL are arranged. A semiconductor layer (not shown) is formed in the inner region of the pixels P1, P2 and P3 and the semiconductor layer and the gate lines SL1 (n), EML (n) ) a and SL2 (n) b) overlap each other, the gate electrode of the transistor is formed.

The first data line DL1 is disposed on one side of the first pixel P1 and the initialization voltage line VL is disposed on the other side. The second data line DL2 is disposed on one side of the second pixel P2 and the initialization voltage line VL is disposed on the other side. Each of the first to third data lines DL1 to DL3 is disposed adjacent to the first to third pixels P1 to P3 and the first to third pixels P1 to P3, One to one. As shown in the figure, each initialization voltage line VL may be connected one-to-one with the first through third pixels P1, P2, and P3. Or one initializing voltage line VL is connected to a plurality of pixels (not shown) through a horizontal initializing voltage line (not shown) arranged in the same direction as the gate lines SL1 (n), EML P1, P2, P3). The high potential voltage line VDDL may be disposed on the side of the initialization voltage line VL. The high potential voltage line VDDL may supply a high potential voltage to two or more pixels P among the pixels P arranged in the nth pixel line HL (n).

The first scan line SL1 (n) traverses the inner area of the pixels P1, P2 and P3 and is connected to the main first scan line SL1 (n) a And the sub first scan line SL1 (n) b. The region where the first scan line SL1 (n) and the semiconductor layer are overlapped becomes the gate electrode T1_G of the first transistor. That is, the first scan line SL1 (n) may be implemented based on the first embodiment shown in FIG.

The emission line EML (n) includes a main emission line EML (n) a and a sub-emission line EML (n) b. The main emission line EML (n) a and the sub-emission line EML (n) b are disposed side by side to cross the inner area of the pixels P1, P2, and P3. The main emission line EML (n) a and the sub-emission line EML (n) b are connected to each other through the emission assist pattern RP_E. The main emission line EML (n) a and the sub-emission line EML (n) b receive the same emission signal EM (n). The region where the main emission line EML (n) a and the semiconductor layer overlap is the gate electrode T3_G of the third transistor. The region where the subemission line EML (n) b and the semiconductor layer overlap is the gate electrode T4_G of the fourth transistor.

The second scan line SL2 (n) includes a main second scan line SL2 (n) a and a sub second scan line SL2 (n) b. The main second scan line SL2 (n) a and the sub second scan line SL2 (n) b are arranged side by side to cross the inner area of the pixels P1, P2, and P3. The main second scan line SL2 (n) a and the sub second scan line SL2 (n) b are connected to each other via the scan assist pattern RP_S. The main second scan line SL2 (n) a and the sub second scan line SL2 (n) b receive the same second scan signal SCAN2 (n). The region where the main second scan line SL2 (n) a and the semiconductor layer are overlapped becomes the gate electrode T2_G of the second transistor. The region where the sub second scan line SL2 (n) b and the semiconductor layer are overlapped becomes the gate electrode T5_G of the fifth transistor.

That is, the emission line EML (n) and the second scan line SL2 (n) may be implemented based on the embodiment shown in FIG.

7 is a cross-sectional view taken along line I-I '.

Referring to FIG. 7, a cross-sectional structure of an area where the emission assist pattern and the scan assist pattern are arranged will be described.

The first buffer layer BUF1 is located on the substrate PI. The substrate (PI) may be made of polyimide for flexibility. A shield layer BSM is located on the first buffer layer BUF1. The shield layer BSM serves to prevent the current amount of the semiconductor layer ACT from decreasing due to the charge flow of the polyimide (PI) layer. The shield layer BSM may be connected to the source / drain electrodes S / D through the contact holes. A second buffer layer BUF2 is located on the shield layer BSM. The second buffer layer BUF2 serves to protect the transistors formed in the subsequent process from impurities such as alkali ions or the like that flow out from the shield layer BSM. The second buffer layer BUF2 may be silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof. The semiconductor layer ACT is located on the second buffer layer BUF2. The semiconductor layer ACT may be formed of a silicon semiconductor or an oxide semiconductor. The semiconductor layer ACT includes a source region and a drain region including a p-type or n-type impurity and includes a channel therebetween. A gate insulating film GI is located on the semiconductor layer ACT. The gate insulating film GI may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof.

A gate electrode GATE and an emission assist pattern RP_E are located on the gate insulating film GI. The gate electrode GATE is located in a region overlapping with the semiconductor layer ACT in a plane. The emission assist pattern RP_E may be located in a region overlapping with the high potential voltage line VDDL in a plane, but the position of the emission assist pattern RP_E is not limited thereto. The gate electrode GATE and the emission assist pattern RP_E may be formed of any one of Mo, Al, Cr, Au, Ti, Ni, (Cu), or an alloy thereof.

A first interlayer insulating film ILD1 and a second interlayer insulating film ILD2 are sequentially disposed on the gate electrode GATE for insulating the gate electrode GATE. Although not shown in the drawing, a capacitor metal layer for forming the storage capacitor Cst shown in FIG. 5 may be formed between the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2. A high potential voltage line VDDL, a second data line DL2 and a source / drain electrode S / D may be formed on the second interlayer insulating film ILD. The source / drain electrodes S / D are connected to the semiconductor layer ACT through contact holes. A passivation layer PAS is located on the high potential voltage line VDDL, the second data line DL2, and the source / drain electrodes S / D.

8 is a view showing a pixel array according to the second embodiment. 9 is a cross-sectional view taken along line I-I 'shown in FIG. In particular, FIG. 8 shows a pixel array of the n-th pixel line consisting of the pixel shown in FIG.

Referring to FIGS. 8 and 9, the pixel array according to the second embodiment will be described as follows. In the second embodiment, detailed description of the same configuration as that of the above-described embodiment will be omitted.

The first data line DL1 is disposed on one side of the first pixel P1 and the initialization voltage line VL is disposed on the other side. The second data line DL2 is disposed on one side of the second pixel P2 and the initialization voltage line VL is disposed on the other side. Each of the first to third data lines DL1 to DL3 is disposed adjacent to the first to third pixels P1 to P3 and the first to third pixels P1 to P3, One to one. As shown in the figure, each initialization voltage line VL may be connected one-to-one with the first through third pixels P1, P2, and P3.

The first scan line SL1 (n) and the second scan line SL2 (n) are positioned on the gate insulating film GL and the auxiliary patterns RP_E and RP_S are positioned on the gate insulating film GL. The initialization voltage line VL, and the high-potential voltage line VDDL. Each of the auxiliary patterns RP_E and RP_S is connected to the main emission line EML (n) a or the subemission line EML (n) b or the main second scan line SL2 (n) a through the contact hole CNT, ) a) or the sub second scan line SL2 (n) b.

A constant voltage line may be disposed between the auxiliary patterns RP_E and RP_S and the data line DL2. 8 and 9 illustrate an embodiment in which the high potential voltage line VDDL is disposed between the auxiliary patterns RP_E and RP_S and the second data line DL2. However, the initialization voltage line VL and the high potential The position of the voltage line VDDL may be varied. The initialization voltage line VL and the high potential voltage line VDDL may both be located between the auxiliary patterns RP_E and RP_S and the second data line DL2, One of the lines VDDL may be omitted.

Since the auxiliary patterns RP_E and RP_S according to the second embodiment are located in the same metal layer as the second data line DL2, the influence of the parasitic capacitors of the auxiliary patterns RP_E and RP_S and the data line DL2 . In particular, since at least one constant voltage supply line such as the initialization voltage line VL and the high potential voltage line VDDL is arranged between the auxiliary patterns RP_E and RP_S and the second data line DL2 in the second embodiment , The influence of parasitic capacitors which may occur between the auxiliary patterns RP_E and RP_S and the second data line DL2 can be eliminated.

A parasitic capacitor may be formed between the auxiliary patterns RP_E and RP_S and the adjacent second data line DL2 and the reliability of the operation of the surrounding pixels P may be degraded by the parasitic capacitor. However, since the second embodiment can suppress the parasitic capacitors that can generate the auxiliary patterns RP_E and RP_S between the second data lines DL2, the driving reliability can be enhanced.

10 is a view for explaining a method for repairing short defects of gate lines according to the present invention. 8 shows a state in which a short defect occurs between the sub-emission line EML (n) b and the third data line DL3.

The sub-emission line EML (n) b is formed in order to improve a shot defect when a short phenomenon occurs between the sub-emission line EML (n) b and the third data line DL3, Open both sides of the shot point. A known technique such as a laser process or the like can be used as a method of opening the subemission line EML (n) b. The sub-emission line EML (n) b is formed on the main emission line EML (n) through the emission assist pattern RP_E even if a part of the sub-emission line EML (n) b is opened. a). As a result, the gate electrode T4_G of the fourth transistor connected to the sub-emission line EML (n) b can receive the emission signal EM (n).

In order to facilitate the opening process of the sub-emission line EML (n) b or the main emission line EML (n) a), the sub-emission line EML (n) b or the main emission line EML EML (n) a) Open regions may be provided on both sides of a region overlapping in a plane with a voltage supply line such as a data line (DL) or the like. The open area can be defined as an area where no other metal pattern is disposed on the subemission line EML (n) b or the main emission line EML (n) a, The cutting process can be carried out easily.

As described above, the present invention can improve the production yield because the entire display panel 100 can be normalized without being treated as defective even if short-circuiting occurs between the metal lines located in different layers among the gate lines.

As described above, the display device according to the present invention can improve the delay of the gate signal because the gate line applying the same gate signal is formed as a double line in at least a part of the section.

Even if an open defect occurs in any one gate line among the double lines, the operation can not be disabled. Therefore, it is possible to improve the production yield due to the open defect.

In particular, since the present invention forms the gate line in a double line, the delay of the gate signal can be improved without increasing the width of the gate line. Since the gate line forms the gate electrode of the transistors disposed in the pixel P, the device characteristics of the transistor are changed when the width of the gate line is changed. Therefore, if the width of the gate line is widened, a pixel circuit or an existing array design that meets the characteristics of the transistor must be re-designed. However, in the present invention, since the width of the gate line can be set to be the same as in the conventional design, the possibility that the device characteristic of the transistor is changed can be excluded.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: Data driving circuit 130, 140: Gate driving circuit
EMD1 to EMD (n): Emission driver
SD1 to SD (n): scan driver
RP: auxiliary pattern

Claims (16)

A pixel comprising at least one transistor; And
And a gate line connected to a gate electrode of the transistor,
And the gate line is divided into a main gate line and a sub gate line which are supplied with the same gate signal in at least some regions. The method according to claim 1,
Wherein the gate line is separated into a main gate line and a sub gate line at an area outside the pixel internal area, and is arranged in one line in the pixel internal area. The method according to claim 1,
Wherein the gate line includes a main gate line and a sub gate line,
Wherein the main gate line and the subgate line cross an inner region of the pixel. The method of claim 3,
The pixel including first and second switching transistors supplied with the gate signal,
A gate electrode of the first switching transistor is connected to the main gate line,
And a gate electrode of the second switching transistor is connected to the sub-gate line. The method of claim 3,
And the main gate line and the sub gate line are located in the same metal layer. The method of claim 3,
Wherein the main gate line and the sub gate line are electrically connected through an auxiliary pattern. The method according to claim 6,
And the auxiliary pattern is located in the same metal layer as the main gate line and the sub gate line. The method according to claim 6,
Further comprising a data line for supplying a data voltage to the pixel,
Wherein the auxiliary pattern is located in the same metal layer as the data line. 9. The method of claim 8,
And at least one constant voltage supply line for supplying a constant voltage to the pixel is disposed between the auxiliary pattern and the data line. The method according to claim 1,
Further comprising a voltage supply line for supplying a predetermined voltage to the pixel,
Wherein the main gate line or the subgate line has an open region where a cutting process is performed at a position spaced apart from a region overlapping with the voltage supply line. The method according to claim 6,
Wherein the auxiliary pattern is disposed in an outer region of the pixel. A first transistor controlled by a first gate signal;
Second and third transistors controlled by a second gate signal;
A first gate line supplying the first gate signal;
A main second gate line supplying the second gate signal and connected to the second transistor; And
And a second sub-gate line connected to the third transistor for supplying the second gate signal. 13. The method of claim 12,
Wherein the first gate line is divided into two gate lines in at least a part of the section. 13. The method of claim 12,
And the main second gate line and the sub second gate line are located in the same metal layer. 15. The method of claim 14,
Wherein the main second gate line and the sub second gate lines are connected to each other through an auxiliary pattern. 13. The method of claim 12,
And the widths of the main second gate line and the sub second gate line are set equal to the width of the first gate line.

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