KR20230079968A - Pixel and display device including the same - Google Patents

Abstract

According to one embodiment of the present disclosure, a driving transistor for supplying a driving current from the second node to a third node in response to a voltage of the first node, a light emitting device receiving the driving current and emitting light, and a first node A first capacitor for maintaining a voltage of , a first transistor for selectively connecting a first node and a third node in response to a first gate signal, and a second node for selectively connecting a data line and a second node in response to a second gate signal A second transistor, a third transistor for selectively connecting the first power line and the second node in response to the emission signal, a fourth transistor for connecting the third node and the light emitting element in response to the emission signal, and a third gate signal A pixel including a fifth transistor for supplying a first initialization voltage to the third node and a second capacitor for changing the voltage of the third node in response to the voltage level of the emission signal and a display device including the same can do.

Description

Pixel and display device including the same {PIXEL AND DISPLAY DEVICE INCLUDING THE SAME}

The present disclosure relates to a pixel and a display device including the same, and more particularly, to providing a pixel capable of improving image quality and a display device including the same.

As the information society develops, demands for display devices for displaying images are increasing in various forms. As the display device, various types of display devices such as a liquid crystal display device (LCD) and an electroluminescence display device (ELD) are being used.

In addition, the electroluminescent display device (ELD) includes a quantum-dot light emitting display device including a quantum dot (QD), an inorganic light emitting display device, and an organic light emitting display device. An organic light emitting display device and the like may be included.

If the contrast ratio of the display device is high, an image displayed on the display device may be clearer. In order to increase the contrast ratio, it is necessary to display black more clearly in a display device. In addition, when the display device generates a driving current in a driving transistor and emits light in response to the magnitude of the driving current, if the supply of the pixel driving current is blocked, black appears more clearly. As a result, the contrast ratio of the display device becomes very high.

In addition, a voltage is continuously applied to the driving transistor, and the characteristics of the driving transistor deteriorate due to the applied voltage, thereby deteriorating the image quality of the display device. In particular, when the display device is driven at a low frequency, if the time for which a constant voltage is applied to the driving transistor is long, the characteristics of the driving transistor deteriorate further.

Accordingly, the inventors of the present disclosure intend to provide a pixel capable of improving image quality and a display device including the same by displaying black more clearly and preventing deterioration of characteristics of the driving transistor.

Solving problems according to embodiments of the present disclosure to be described below are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A pixel according to an embodiment of the present disclosure includes a driving transistor supplying a driving current from a second node to a third node in response to a voltage of a first node, a light emitting element receiving the driving current and emitting light, and a first node. A first capacitor for maintaining a voltage of , a first transistor for selectively connecting the first node and the third node in response to the first gate signal, and selectively transferring a data signal to the second node in response to the second gate signal The second transistor, the third transistor for selectively transferring the driving voltage to the second node in response to the emission signal, the fourth transistor for connecting the third node and the light emitting element in response to the emission signal, and the third gate signal It may include a fifth transistor for supplying a first initialization voltage to the third node and a second capacitor for changing the voltage of the third node in response to the voltage level of the emission signal.

A pixel according to an embodiment of the present disclosure includes a driving transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, and a gate electrode connected to a first gate line. a first transistor having a first electrode connected to a first node, a second electrode connected to a third node, a gate electrode connected to a second gate line, a first electrode connected to a data line, and a second electrode connected to a third node. The second transistor connected to node 2, the gate electrode is connected to the emission line, the first electrode is connected to the first power line, the second electrode is connected to the second node, and the third transistor, the gate electrode is connected to the emission line The first electrode is connected to the third node, the second electrode is connected to the fourth node, the fourth transistor and the gate electrode are connected to the third gate line, the first electrode is connected to the first initialization voltage line, and the second A fifth transistor having an electrode connected to a third node and a gate electrode connected to a third gate line, a gate electrode connected to a third gate line, a first electrode connected to a second initialization voltage line, and a second electrode connected to a light emitting element A sixth transistor is connected to the anode electrode of the first capacitor, the first electrode is connected to the first node and the second electrode is connected to the first power line, the first electrode is connected to the third node and the second electrode is A second capacitor connected to the seam line and a light emitting element disposed between the fourth node and the second power line may be included.

A display device according to an embodiment of the present disclosure includes a plurality of data lines, a plurality of gate lines, a plurality of emission lines, and a plurality of pixels connected to the plurality of data lines, the plurality of gate lines, and the plurality of emission lines. A display panel, a data driver circuit connected to a plurality of data lines to apply data signals, and a gate driver circuit connected to a plurality of gate lines to apply gate signals, wherein the plurality of pixels correspond to a voltage of a first node. A driving transistor for supplying a driving current from the second node to a third node, a light emitting element for emitting light by receiving the driving current, and a first node and a third node for selectively connecting the first node and the third node in response to the first gate signal. 1 transistor, a second transistor for selectively connecting the data line and the second node in response to the second gate signal, and a third transistor for selectively connecting the first power line and the second node in response to the emission signal, emission A fourth transistor connecting the third node and the light emitting element in response to a signal, a fifth transistor supplying a first initialization voltage to the third node by a third gate signal, a first capacitor maintaining the voltage of the first node, and A second capacitor may be included to change the voltage of the third node in response to the voltage level of the emission signal.

A display device according to an exemplary embodiment of the present disclosure includes a substrate, a first buffer layer disposed on the substrate, a first active layer disposed on the substrate, a gate insulating layer disposed on the active layer, and a first buffer layer disposed on the gate insulating layer. An emission line disposed to overlap with the active layer, a gate line disposed not to overlap with the first active layer, a first interlayer insulating film disposed on the emission line and the gate line, and an emission line disposed on the first interlayer insulating film A conductive film overlapping with the conductive film, a second buffer layer disposed on the interlayer insulating film on which the conductive film is disposed, a second active layer disposed on the second buffer layer and disposed not to overlap the first active layer, and a second active layer disposed on the second buffer layer. A second interlayer insulating film disposed on the second buffer layer, disposed on the second interlayer insulating film, connected to the conductive film through a first contact hole, connected to the first active layer through a second contact hole, and connected through a third contact hole. A first source-drain metal connected to the second active layer and a planarization layer disposed on the second interlayer insulating layer on which the first source-drain metal is disposed.

According to the exemplary embodiments of the present disclosure, by applying a high voltage to the driving transistor of each pixel to prevent deterioration of characteristics of the driving transistor, the problem of deterioration in image quality can be solved. In addition, the picture quality can be improved by more clearly displaying the case where the display device expresses black.

Effects of the embodiments of the present disclosure are not limited to the effects mentioned above. In addition, the embodiments disclosed herein may produce another effect not mentioned above, which will be clearly understood by those skilled in the art from the description below.

1 is a structural diagram illustrating a display device according to an exemplary embodiment of the present disclosure.
2 is a circuit diagram illustrating pixels employed in a display device according to example embodiments.
3A and 3B are timing diagrams illustrating operations of the pixels shown in FIG. 2 .
FIG. 4 is a layout diagram illustrating pixels shown in FIG. 3 .
FIG. 5 is a cross-sectional view showing a section V-V′ shown in FIG. 4 .
6 is a graph showing a voltage applied to a third node of a pixel when a data signal representing black is transmitted to the pixel.

Advantages and features of the present disclosure, and methods of achieving them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and will be implemented in various different forms, and only the embodiments of the present disclosure make the disclosure complete, and those skilled in the art in the art to which the present disclosure belongs It is provided to fully inform the person of the scope of the present disclosure, and the present disclosure is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present disclosure are illustrative, so the present disclosure is not limited to the illustrated details. Like reference numbers designate like elements throughout this disclosure. In addition, in describing the present disclosure, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. When "comprises", "has", "consists of", etc. mentioned above is used, other parts may be added unless "only" is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as "on", "upper", "underward", "next to", etc., "immediately" Or, unless "directly" is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, "immediately" or "directly" when a temporal precedence relationship is described by "after", "following", "after", "before", etc. As long as " is not used, non-consecutive cases may also be included.

In the case of a description of the flow relationship of a signal, for example, even if "a signal is passed from node A to node B", it goes from node A to another node unless "directly" or "direct" is used. This may include a case where a signal is transmitted to the B node.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present disclosure.

Each feature of the various embodiments of the present disclosure can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other, or can be implemented together in an association relationship. may be

In embodiments of the present disclosure, a driving transistor for supplying a driving current from a second node to a third node in response to a voltage of a first node, a light emitting device receiving the driving current and emitting light, and a voltage of the first node A first capacitor for holding, a first transistor for selectively connecting the first node and a third node in response to the first gate signal, and a second transistor for selectively transferring a data signal to the second node in response to the second gate signal , a third transistor for selectively transmitting a driving voltage to the second node in response to an emission signal, a fourth transistor for connecting the third node and a light emitting element in response to an emission signal, and a third node by a third gate signal It is possible to provide a pixel including a fifth transistor for supplying a first initialization voltage to and a second capacitor for changing the voltage of the third node in response to the voltage level of the emission signal.

In addition, the pixel may supply the second initialization voltage to the anode electrode of the light emitting device by the third gate signal.

In addition, the pixel operates by being divided into a sampling period in which the emission signal maintains a high state and an emission period in which the emission signal maintains a low state, and the sampling period supplies a first initialization voltage to a third node It may include a first period of writing a data signal and a voltage corresponding to the threshold voltage of the driving transistor to the first node, and a third period of supplying the first initialization voltage to the third node.

In addition, the pixel may further include a sixth transistor for transferring a second initialization voltage to an anode electrode of the light emitting device in response to the first gate signal.

Also, the first initialization voltage supplied in the first period and the third period may have a first voltage level higher than the driving voltage supplied to the first power line.

In one embodiment of the present disclosure, a driving transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a gate electrode connected to a first gate line; A first transistor having a first electrode connected to a first node and a second electrode connected to a third node, a gate electrode connected to a second gate line, a first electrode connected to a data line, and a second electrode connected to a second node The connected second transistor, the gate electrode is connected to the emission line, the first electrode is connected to the first power line, the second electrode is connected to the second node, and the third transistor, the gate electrode is connected to the emission line, The first electrode is connected to the third node, the second electrode is connected to the fourth node, the fourth transistor and the gate electrode are connected to the third gate line, the first electrode is connected to the first initialization voltage line, and the second electrode is connected to the third gate line. A fifth transistor connected to 3 nodes and having a gate electrode connected to a third gate line, a gate electrode connected to a third gate line, a first electrode connected to a second initialization voltage line, and a second electrode connected to an anode electrode of a light emitting element A sixth transistor, a first capacitor having a first electrode connected to a first node and a second electrode connected to a first power line, a first electrode connected to a third node and a second electrode connected to an emission line. A pixel including a connected second capacitor and a light emitting element disposed between the fourth node and the second power line may be provided.

Embodiments of the present disclosure are a display panel including a plurality of data lines, a plurality of gate lines, a plurality of emission lines and a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of emission lines; a data driver circuit connected to a data line to apply a data signal and a gate driver circuit connected to a plurality of gate lines to apply a gate signal;

The plurality of pixels may include a driving transistor supplying driving current from the second node to the third node in response to the voltage of the first node, a light emitting element receiving the driving current and emitting light, and corresponding to a first gate signal. A first transistor selectively connecting the first node and the third node, a second transistor selectively connecting a data line and the second node in response to a second gate signal, and a first power supply corresponding to an emission signal A third transistor selectively connecting the line and the second node, a fourth transistor connecting the third node and the light emitting element in response to an emission signal, and supplying a first initialization voltage to the third node by a third gate signal. It may include a fifth transistor, a first capacitor for maintaining the voltage of the first node, and a second capacitor for changing the voltage of the third node in response to the voltage level of the emission signal.

Also, the display device may supply the second initialization voltage to the anode electrode of the light emitting device by the third gate signal.

In addition, the display device operates by dividing into a sampling period in which the emission signal maintains a high state and an emission period in which the emission signal maintains a low state, and the sampling period supplies the first initialization voltage to a third node. It may include a first period of writing a data signal and a voltage corresponding to the threshold voltage of the driving transistor to the first node, and a third period of supplying the first initialization voltage to the third node.

Also, in the first period and the third period, the first initialization voltage may have a first voltage level higher than the driving voltage supplied to the first power line.

Also, in the display device, the second capacitor may have a first electrode connected to a third node and a second electrode connected to an emission signal line supplying an image transmission signal.

Embodiments of the present disclosure include a substrate, a first buffer layer disposed on the substrate, a first active layer disposed on the substrate, a gate insulating film disposed on the active layer, disposed on the gate insulating film, and overlapping the first active layer. A gate line disposed not to overlap the emission line and the first active layer, a first interlayer insulating film disposed on the emission line and the gate line, and a conductive film disposed on the first interlayer insulating film and overlapping the emission line , a second buffer layer disposed on the interlayer insulating film on which the conductive film is disposed, a second active layer disposed on the second buffer layer and disposed not to overlap with the first active layer, and on the second buffer layer disposed on the second active layer It is disposed on the second interlayer insulating film, the first source drain metal disposed on the second interlayer insulating film, and connected to the first active layer through the first contact hole, and the second interlayer insulating film, through the second contact hole. A second source-drain metal connected to the conductive layer, connected to the first active layer through a third contact hole, connected to the first active layer through a fourth contact hole, and connected to the second active layer through a fifth contact hole. and a planarization layer disposed on the second interlayer insulating layer on which the first source-drain metal and the second source-drain metal are disposed.

Also, the second active layer may include an oxide semiconductor.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a structural diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a display device 100 may include a display panel 110 , a data driver 120 , and a gate driver 130 . Also, the display device 100 may include a timing controller 140 .

The display panel 110 may include a plurality of gate lines GL1 to GLn extending in a first direction and a plurality of data lines DL1 to DLm extending in a second direction. Here, the first direction and the second direction may be orthogonal. However, it is not limited thereto.

Also, the display panel 110 may include a plurality of pixels 101 . The plurality of pixels 101 receive data signals transmitted through data lines DL1 to DLm in response to gate signals transmitted through gate lines GL1 to GLn, and display images on the display panel 110. can Also, the plurality of pixels 101 may be initialized in response to the first initialization signal and the second initialization signal.

The data driver 120 may be connected to the plurality of data lines DL1 to DLm and supply data signals to the plurality of pixels 101 through the plurality of data lines DL1 to DLm. The data driver 120 may include a plurality of source drivers. Each of the plurality of source drivers may be implemented as an integrated circuit.

The gate driver 130 is connected to the plurality of gate lines GL1 to GLn and may supply gate signals to the plurality of gate lines GL1 to GLn. A pixel receiving a gate signal through a gate line may receive a data signal.

The gate driver 130 is illustrated as being disposed outside the display panel 110 , but is not limited thereto, and the gate driver 130 may be disposed on the display panel 110 . In addition, the gate driver 130 may include a gate signal generator disposed on the display panel 110 to output a gate signal and a level shifter to supply voltage and clock to the gate signal generator. Also, the gate driver 130 may be implemented with a plurality of integrated circuits.

In addition, the gate driver 130 is illustrated as being disposed on one side of the display panel 110, but is not limited thereto and may be disposed on both sides of the display panel 110. In addition, the gate driver disposed on the left side may be connected to odd-numbered gate lines, and the gate driver disposed on the right side of the display panel 110 may be connected to even-numbered gate lines.

Also, the timing controller 140 may control the data driver 120 and the gate driver 130 . The timing controller 140 may supply a data control signal to the data driver 120 and a gate control signal to the gate driver 130 . The data control signal or gate control signal may include a clock, a vertical synchronization signal, a horizontal synchronization signal, and a start pulse. However, the signal output from the timing controller 140 is not limited thereto.

The timing controller 140 may supply an image signal to the data driver 120 . The data driver 120 may generate a data signal through the video signal and the data control signal received from the timing controller 140 and supply the data signal to the plurality of data lines DL1 to DLm.

In addition, a plurality of emission lines may be further disposed on the display panel 110 . Emission signals are applied to the plurality of emission lines, and the gate driver 130 may apply the emission signals to the plurality of emission lines. Also, a plurality of initialization voltage lines may be disposed on the display panel 110 . The plurality of initialization voltage lines may be divided into first initialization voltage lines that transmit the first initialization voltage and second initialization voltage lines that transmit the second initialization voltage. The first initialization voltage may be supplied from the gate driver 130 . The first initialization voltage may be sequentially supplied to the plurality of first initialization voltage lines. Also, the second initialization voltage line may be supplied from a separate power supply circuit.

2 is a circuit diagram illustrating pixels employed in a display device according to example embodiments.

Referring to FIG. 2 , the pixel 101 may include a driving transistor MD, a light emitting device ED, and a first capacitor Cst.

The driving transistor MD may generate a driving current flowing from the second node N2 to the third node N3 in response to the voltage of the first node N1. The voltage transmitted to the first node N1 may be a voltage obtained by adding or subtracting the voltage level of the threshold voltage of the driving transistor MD to the voltage level of the data signal Vdata.

The driving transistor MD may have a first electrode connected to the second node N2 , a second electrode connected to the third node N3 , and a gate electrode connected to the first node N1 . In addition, the data signal Vdata is selectively transmitted to the second node N2, and the data signal Vdata transmitted to the second node N2 is transmitted to the first node N1 via the third node N3. can be conveyed The driving transistor MD may be an N MOS type transistor.

The driving transistor MD may allow a driving current to flow from the second node N2 to the third node N3 in response to the data signal Vdata transmitted to the first node N1.

The light emitting element ED may emit light by receiving a driving current flowing from the second node N2 to the third node N3. The light emitting device ED may include an anode electrode, a cathode electrode, and a light emitting layer disposed between the anode electrode and the cathode electrode. In the light emitting element ED, the low state second driving voltage EVSS is applied to the cathode electrode, and when a high state voltage is applied to the anode electrode, a current flows from the anode electrode of the light emitting element ED to the cathode electrode. it flows The light emitting device ED may emit light by a current flowing from the anode electrode toward the cathode electrode.

In order to supply the second driving voltage EVSS to the cathode electrode of the light emitting device ED, the cathode electrode of the light emitting device ED may be connected to a second power line supplying the second driving voltage EVSS. The second power line may be commonly supplied to a plurality of pixels.

The light emitting device ED may be an organic light emitting diode (OLED), an inorganic light emitting diode, or a quantum dot light emitting device. In this case, when the light emitting device ED is an organic light emitting diode, the light emitting layer EL of the light emitting device ED may include an organic light emitting layer containing an organic material.

The first capacitor Cst may maintain the voltage of the first node N1. The first capacitor Cst may be disposed between the first node N1 and the driving power line VLd supplying the driving voltage EVDD.

In addition, the pixel 101 includes a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , and a second transistor M6 . It may include 2 capacitors (C2).

The first transistor M1 may cause the driving transistor MD to be in a diode connection state. The first transistor M1 may have a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode connected to the first gate line GL3. The first transistor M1 may be turned on/off in response to the first gate signal gate1 transmitted through the first gate line GL1. The first transistor M1 may be a P MOS type transistor.

The second transistor M2 may selectively transfer the data signal Vdata flowing through the data line DL to the second node N2. The second transistor M2 may have a first electrode connected to the data line DL, a second electrode connected to the second node N2, and a gate electrode connected to the second gate line GL2. The second transistor M2 may be turned on/off in response to the second gate signal gate2 transmitted through the second gate line GL2. The second transistor M2 may be an N MOS type transistor.

The third transistor M3 may selectively transmit the driving voltage EVDD to the second node N2. The third transistor M3 has a first electrode connected to the driving power line VLd supplying the driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode connected to the emission line EML. can be connected to The third transistor M3 may be turned on/off in response to the emission signal ems transmitted through the emission line EML. The third transistor M3 may be an N MOS type transistor.

The fourth transistor M4 may selectively transfer the driving current flowing through the driving transistor MD to the light emitting device ED. The fourth transistor M4 may have a first electrode connected to the third node N3, a second electrode connected to the anode electrode of the light emitting element ED, and a gate electrode connected to the emission line EML. Also, the second electrode of the fourth transistor may be connected to the fourth node N4 and the anode electrode of the light emitting element ED may be connected to the fourth node N4. The fourth transistor M4 may be turned on/off in response to the emission signal ems transmitted through the emission line EML. The fourth transistor M4 may be an N MOS type transistor.

The fifth transistor M5 may selectively transfer the first initialization voltage Vini to the third node N3. The fifth transistor M5 has a first electrode connected to the first initialization voltage line VL1 delivering the first initialization voltage Vini, a second electrode connected to the third node N3, and a gate electrode connected to the third node N3. It may be connected to the gate line GL3. The fifth transistor M5 may be turned on/off by the third gate signal gate3 transmitted to the third gate line GL3. The fifth transistor M5 may have a double gate structure, thereby reducing generation of leakage current and suppressing the voltage of the third node N3 from being lowered. The fifth transistor M5 may be an N MOS type transistor. The voltage level of the first initialization voltage Vini may be higher than that of the driving voltage.

The sixth transistor M6 may selectively transmit the second initialization voltage VAR to the anode electrode of the light emitting device ED. The sixth transistor M6 has a first electrode connected to the second initialization voltage line VL2 delivering the second initialization voltage VAR, a second electrode connected to the anode electrode of the light emitting element ED, and a gate electrode. It may be connected to the third gate line GL3. The sixth transistor M6 may be turned on/off by the third gate signal gate3 transmitted to the third gate line GL3.

The voltage level of the second initialization voltage VAR may be lower than the threshold voltage of the light emitting device ED. The sixth transistor M6 may be an N MOS type transistor.

The second capacitor C2 may change the voltage of the third node N3 in response to the voltage level of the emission signal. The first electrode of the second capacitor C2 may be connected to the third node N3 and the second electrode may be connected to the emission line EML. And, when the voltage level of the emission signal is changed from a high state to a low state, the voltage of the first electrode of the second capacitor C2 connected to the emission line EML is lowered, thereby reducing the voltage of the second capacitor C2. A voltage of the third node N3 connected to the first electrode may decrease.

Transistors using oxide semiconductors have less leakage current than transistors using low-temperature polysilicon, but their electron mobility is low. Therefore, the first transistor M1 requiring a small leakage current is a transistor using an oxide semiconductor, and the second to sixth transistors M2 to M6 that need to be turned on/off quickly are low-temperature polysilicon. It may be a transistor using .

3A and 3B are timing diagrams illustrating operations of the pixels shown in FIG. 2 .

Referring to FIGS. 3A and 3B , the pixel 101 may operate by dividing into a sampling period Ts and an emission period Te. During the sampling period Ts, the data signal is written to the first capacitor C1 connected to the first node N1 of the pixel 101, and during the emission period Te, the data signal written to the first capacitor C1 Correspondingly, the driving transistor MD allows the driving current to flow from the second node N2 to the third node N3 so that the light emitting element ED can emit light.

During the sampling period Ts, the emission signal ems may maintain a high state, and during the emission period Te, the emission signal ems may maintain a low state. In the sampling period Ts, the third transistor M3 and the fourth transistor M4 may be turned off by the emission signal ems, and in the emission period Te, by the emission signal ems. The third transistor M3 and the fourth transistor M4 may be turned on.

When the data signal Vdata is written to the first node N1 in the sampling period Ts, the voltage written to the first node N1 is compensated by the threshold voltage of the driving transistor MD in the data signal Vdata. voltage may be A voltage written to the first node N1 may be maintained by the first capacitor C1.

The sampling period Ts may include a first period T1, a second period T2, and a third period T3.

The first period T1 is a period in which hysteresis of the driving transistor MD is improved by applying a high voltage to the driving transistor MD of the pixel 101, and the first voltage level V1 is applied to the third node N3. A first initialization voltage Vini having may be supplied. The first voltage level V1 may be higher than the driving voltage EVDD supplied from the driving power line VLd.

In the first period T1, the first gate signal gate1 and the third gate signal gate3 may be in a low state and the second gate signal gate2 may be in a high state. Accordingly, the first transistor M1 connected to the first gate line GL1 and the second transistor M2 connected to the second gate line GL2 may be in an off state. Also, the third transistor M3 and the fourth transistor M4 connected to the emission line EML may be in an off state. Also, the fifth transistor M5 and the sixth transistor M6 connected to the third gate line GL3 may be in an on state.

When the fifth transistor M5 is in an on state, the first initialization voltage Vini1 may be transferred to the third node N3. At this time, since the voltage level of the first initialization voltage Vini1 has a first voltage level higher than the driving voltage EVDD, a high voltage can be applied to the third node N3. On bias stress may be applied to the driving transistor MD by the high voltage applied to the third node N3. Hysteresis of the driving transistor MD may be improved by on bias stress to which a voltage higher than a voltage required for driving is applied.

When the sixth transistor M6 is in an on state, the second initialization voltage VAR is applied to the anode electrode of the light emitting device ED so that the anode electrode of the light emitting device ED is initialized by the second initialization voltage VAR. can do. The voltage level of the second initialization voltage VAR is lower than the threshold voltage of the light emitting device ED, so that the light emitting device ED does not emit light.

In the second period T2, the data voltage Vdata is supplied to the first node N1 of the pixel 101, and the first gate signal gate1 changes from a low state to a high state, and the second gate signal (gate2) may become low for a while after maintaining a high state. Also, the third gate signal gate3 may change from a low state to a high state. Here, the period during which the second gate signal gate2 is in a low state may be one horizontal period (1H).

When the third gate signal gate3 is in a low state, the fifth transistor M5 may be in an on state. At this time, the voltage level of the first initialization voltage Vini1 may be the second voltage level V2 which is in a low state. A low state voltage may correspond to ground. However, it is not limited thereto. Therefore, the first initialization voltage Vini1 having the second voltage level V2 is transmitted to the third node N3, and the voltage of the third node N3 can be initialized by the second voltage level V2. .

Also, when the first gate signal gate1 changes from a low state to a high state, the first transistor M1 may be turned on. When the first transistor M1 is turned on, the first node N1 and the third node N3 are connected so that the driving transistor MD may be connected with a diode. Accordingly, current may flow from the second node N2 to the first node N1 via the third node N3.

When the first transistor M1 is turned on by the first gate signal gate1, the second gate signal gate2 may be in a low state. When the second gate signal gate2 is in a low state, the data line DL and the second node N2 are connected so that the data signal Vdata flowing through the data line DL can be transferred to the second node N2. there is.

When the data signal Vdata2 is applied to the second node N2, the first transistor M1 maintains an on state, so that the second node N2 to the third node N3 are connected by the data signal Vdata2. ), current flows through the first node N1, the data signal Vdata is written to the first node N1, and a voltage corresponding to the data signal can be maintained at the first node N1. When the data signal Vdata is written to the first node N1, the voltage written to the first node N1 may be a voltage obtained by subtracting the threshold voltage of the driving transistor MD from the data signal Vdata. Accordingly, the voltage corresponding to the data signal Vdata may be a voltage obtained by compensating for the threshold voltage in the data signal Vdata.

After the second gate signal gate2 becomes high in the second period T2, the first gate signal gate1 becomes low and the third gate signal gate3 remains high. When the second gate signal gate2 becomes high, the connection between the data line DL and the second node N2 is cut off, but the voltage of the first node N1 can be maintained by the first capacitor C1. Therefore, a voltage corresponding to the data signal Vdata may be maintained at the gate electrode of the driving transistor MD.

In the second period T2, the period during which the third gate signal gate3 remains low is called the initialization period Tini, and the period during which the third gate signal gate3 remains high is called the program period Tp. can be distinguished.

The third period T3 is a period in which the hysteresis of the driving transistor MD is improved by once again applying a high voltage to the driving transistor MD of the pixel 101, and the third node N3 has a first voltage level V1. ) may be supplied. In the third period T3, the first gate signal gate1 and the third gate signal gate3 may be in a low state, and the second gate signal gate2 may be in a high state. By the first gate signal gate1 to the third gate signal gate3, the first transistor M1 and the second transistor M2 are turned off and the fifth transistor M5 is turned on to generate the first voltage The first initialization voltage Vini having the level V1 may be transferred to the third node N3.

Since the first initialization voltage Vini has the first voltage level V1, a high voltage can be applied to the third node N3. Due to this, the drive transistor MD may receive an on bias stress. Hysteresis of the drive transistor MD may be improved by on bias stress.

Then, the emission period Te may start after the third period T3. During the emission period Te, the emission signal ems may be in a low state. During the emission period Te, the third transistor M3 and the fourth transistor M4 may be in an on state. Also, the first to sixth transistors M1 to M6 may be turned off.

When the third and fourth transistors M3 and M4 are on, the driving power line VLd supplying the driving voltage EVDD is connected to the second node N2 and the second node N2 is driven. When the voltage EVDD is applied, a driving current corresponding to the data signal may flow through the driving transistor MD from the second node N2 to the third node N3. At this time, since the fourth transistor M4 is in an on state, the driving current flows to the light emitting element ED, so that the light emitting element ED can emit light in response to the driving current.

Before the emission period Te starts, a high voltage is applied to the third node N3 by the first initialization voltage Vini1, so that when the fourth transistor M4 is turned on, the anode of the light emitting element ED A high voltage is applied to the electrodes. When the data signal corresponds to low gradation or black, the high voltage applied to the anode electrode of the light emitting device ED increases the magnitude of the current flowing through the light emitting device ED, so that the display device 100 displays low gradation or black. There may be problems with not being able to do it.

When the emission period Te starts, the emission signal ems is converted from a high state to a low state, so that the voltage level of the third node N3 corresponds to the voltage level of the emission signal ems. When the 4th transistor M4 is turned on, the high voltage at the anode electrode of the light emitting element ED may be lowered in response to the emission signal ems.

In FIG. 3B, (i) is the voltage of the anode electrode VA of the light emitting element ED when the second capacitor C2 is not disposed between the emission line EML and the third node N3. (ii) is the voltage of the anode electrode VA of the light emitting element ED when the second capacitor C2 is disposed between the emission line EML and the third node N3 indicates change.

When the second capacitor C2 is not disposed between the emission line EML and the third node N3, a parasitic capacitor may be formed between the emission line EML and the third node N3. . When the voltage level of the emission line EML is lowered by the parasitic capacitor, the voltage level VN3 of the third node N3 may be lowered.

Since the capacitance of the parasitic capacitor between the emission line (EML) and the third node (N3) is very small, the voltage level (VN3) of the third node (N3) is not sufficiently low, resulting in light emission as shown in (i). The voltage of the voltage VA of the anode electrode of the device ED is greatly increased. When the voltage of the voltage VA of the anode electrode of the light emitting element ED is greatly increased, a driving current flows through the light emitting element ED so that the light emitting element ED emits light and black is not expressed.

On the other hand, if the capacitance between the emission line EML and the third node N3 is large, the voltage level VN3 of the third node N3 is greatly reduced when the voltage level of the emission line EML decreases. can

The voltage level (VN3) of the third node (N3) between the emission line (EML) and the third node (N3) in order to increase the size of the capacitance between the emission line (EML) and the third node (N3) A second capacitor (C2) having a capacitance capable of significantly lowering can be disposed.

When the second capacitor (C2) is disposed, the voltage level (VN3) of the third node (N3) is sufficiently low, and the voltage of the voltage (VA) of the anode electrode of the light emitting element (ED) rises slightly as shown in (ii). will do When the voltage of the voltage VA of the anode electrode of the light emitting element (ED) rises a little, a driving current flows through the light emitting element (ED) and the light emitting element (ED) emits light so that the black color is better than in the case of (i). can be expressed

For the above reasons, if the second capacitor C2 is formed between the emission line EML and the third node N3, the display device 100 can more clearly display low gray levels or black in an image. there is.

Also, when the display device 100 is driven at a low frequency, the voltage between the gate electrode of the driving transistor MD connected to the first node N1 and the source electrode of the driving transistor M2 connected to the second node N3 This can be maintained for a long time. If the voltage applied to the gate electrode and the source electrode of the driving transistor MD is maintained for a long time, the characteristics of the driving transistor MD deteriorate. On bias stress may be applied to the drive transistor MD. Therefore, even when the display device 100 is driven at a low frequency, the hysteresis of the drive transistor MD is improved, so that the characteristics of the drive transistor MD can be improved.

FIG. 4 is a layout diagram illustrating pixels shown in FIG. 3 .

Referring to FIG. 4 , first active layers 420a, 420b, 420c, and 420d may be disposed on the substrate. The first active layers 420a, 420b, 420c, and 420d may include active layers of the driving transistor MD and the second to sixth transistors M2 to M6.

A second active layer 450 may be disposed on the substrate. In addition, first source-drain metals 440a, 440b, 440c, and 440d may be disposed on the substrate. In addition, conductive films 430a and 430b may be disposed on the substrate.

an emission line EML extending in a first direction F1 on the substrate on which the first active layers 420a, 420b, 420c, and 420d are disposed, a second gate line GL2, a first gate line GL1, The third gate lines GL3 may be spaced apart from each other in the second direction F2 . The first gate line GL1 is formed by overlapping two lines GL1a and GL1b. One of the two lines GL1a and GL1b of the first gate line GL1 (GL1b) is disposed under the first active layers 420a, 420b, 420c, and 420d to form the first active layers 420a, 420b, 420c, 420d) may be placed closer to the substrate.

A gate electrode 410 of the driving transistor MD may be disposed between the second gate line GL2 and the emission line EML on the substrate. The first active layer 420a may be disposed to overlap the gate electrode 410 of the driving transistor MD.

A first initialization voltage line VL1 extending in the first direction F1 and spaced apart from the third gate line GL3 in the second direction F2 may be disposed on the substrate.

In addition, a second initialization voltage line VL2 is disposed between the first gate line GL1 and the third gate line GL3 on the substrate, and the second initialization voltage line VL2 extends in the first direction F1. is extended The first initialization voltage line VL1 may extend in the first direction F1. The second initialization voltage line VL2 may be disposed under the first active layers 420a, 420b, 420c, and 420d closer to the substrate than the first active layers 420a, 420b, 420c, and 420d.

The conductive layer 430a may be disposed to overlap the gate electrode 410 . The conductive layer 430a may correspond to the first electrode of the first capacitor C1.

The gate electrode 410 may be connected to the source drain metal 440a through the contact hole CH1.

Also, the conductive layer 430b may be disposed at a position overlapping the emission line EML. The conductive layer 430b may be connected to the source-drain metal 440b through the contact hole CH2. The conductive layer 430b may be a first electrode of the second capacitor C2 connected to the third node N3.

The first source drain metal 440b may extend in the second direction F2 and overlap the second gate line GL2 and the first gate line GL1. Also, the first source drain metal 440b may be connected to the first active layer 420b through the contact hole CH3. A portion where the first source drain metal 440b and the first active layer 420b are connected may correspond to the third node N3 shown in the pixel 101 shown in FIG. 2 .

Also, in the first active layer 420c, the second initialization voltage line VL2 is disposed to overlap the third gate line GL3 and may be connected to the first initialization voltage line VL1 through the contact hole CH5. .

The second active layer 450 may be disposed between the second gate line GL2 and the first gate line GL1. Also, the second active layer 450 may overlap the protruding portion of the first gate line GL1 protruding in the opposite direction to the second direction F2 . A protruding portion of the first gate line GL1 may become a gate electrode of the first transistor M1. The first source-drain metal 440b may be connected to the second active layer 450 through the contact hole CH6 .

In addition, the first source-drain metal 440a may extend in the second direction F2 and be connected to the second active layer 450 through the contact hole CH7 . A portion where the first source-drain metal 440a is connected to the second active layer 450 through the contact hole CH7 may be the first node N1.

The first active layer 420b extends from the left side of the gate electrode in the second direction F2 and overlaps the second gate line GL2. A portion of the second gate electrode GL2 overlapping the first active layer 420b is the gate electrode of the second transistor M2. Also, the first active layer 420b may overlap the emission line EML. The overlapping portion of the emission line EML with the first active layer 420b is the gate electrode of the third transistor M3.

The first active layer 420c may overlap a protruding portion of the third gate line GL3 protruding in the opposite direction to the second direction F2 and a portion extending in the second direction of the third gate line GL3. there is. A portion where the first active layer 420c and the third gate line GL3 overlap may become a gate electrode of the fifth transistor M5. Since the first active layer 420c overlaps the third gate line GL3 in two parts, the fifth transistor M5 may have a double gate structure.

Also, the first active layer 420d overlaps the third gate line GL3 and may be connected to the second initialization voltage line VL2 through the contact hole CH7. A portion of the third gate line GL3 overlapping the first active layer 420d may become a gate electrode of the sixth transistor M6.

A portion of the first initialization voltage line VL1 may include the same material as the first source-drain metals 440a, 440b, 440c, and 440d, and another portion may include the same material as the conductive layers 430a and 430b. there is. A part of the first initialization voltage line VL1 and another part may be connected through the contact hole CH10.

FIG. 5 is a cross-sectional view showing a section V-V′ shown in FIG. 4 .

Referring to FIG. 5 , a driving transistor (MD) supplying driving current from the second node (N2) to the third node (N3) in response to the voltage of the first node (N1) on the substrate 400, driving A light emitting element (ED) for emitting light by receiving current, a first capacitor (C1) for maintaining the voltage of the first node (N1), a first node (N1) and a third node (in response to the first gate signal) N3), a second transistor M2 selectively connecting the data line DL and the second node N2 in response to the second gate signal, and corresponding to the emission signal A third transistor M3 selectively connects the driving power line VLd and the second node N2, and a fourth transistor connects the third node N3 and the light emitting element ED in response to an emission signal. (M4), a fifth transistor (M5) for supplying a first initialization voltage to the third node (N3) by a third gate signal, and changing the voltage of the third node in response to the voltage level of the emission signal. The pixel 101 including the second capacitor C2 may be disposed.

A plurality of layers may be deposited and patterned on the substrate 400 to arrange the pixel 101 .

First, a first buffer layer 401 may be disposed on the substrate 400 . A first active layer 440b may be disposed on the first buffer layer 401 . A gate insulating layer 402 may be disposed on the first buffer layer 401 on which the first active layer 440b is disposed.

An emission line EML and a second gate line GL2 may be disposed on the gate insulating layer 402 . A first interlayer insulating layer 403 may be disposed on the gate insulating layer 402 on which the emission line EML and the second gate line GL2 are disposed. A conductive layer 430b may be disposed on the first interlayer insulating layer 403 . The conductive layer 430b is disposed to partially overlap the emission line EML, so that the second capacitor C2 may be formed between the conductive layer 430b and the emission line EML.

A second buffer layer 404 may be disposed on the first interlayer insulating layer 403 on which the conductive layer 430b is disposed. After the second buffer layer 404 is formed, a second active layer 450 may be disposed on the second buffer layer 404 . The second active layer 450 may correspond to the active layer of the first transistor T1 of the pixel 101 shown in FIG. 3 . The second active layer 450 may include an oxide semiconductor.

Since the active layer of the first transistor T1 includes an oxide semiconductor, a leakage current generated in the first transistor T1 may be smaller than that of other transistors of the pixel 101 . Therefore, it is possible to prevent the image quality of the display device 100 from being lowered by suppressing the voltage of the first node N1 from being lowered.

Also, a second interlayer insulating layer 405 may be disposed on the second buffer layer 404 on which the second active layer 450 is disposed. Also, first source-drain metals 440b and 440d may be formed on the second interlayer insulating layer 405 .

The first source-drain metals 440b and 440d form contact holes CH9 in the conductive layer 430b, the first active layer 420a, and the second active layer 450 through the contact holes CH2, CH3, and CH6. Through this, it may be connected to the first active layer 420a. The second active layer 450 is connected to the first active layer 420a through the first source-drain metal 440b and may be connected to the third node N3 of FIG. 3 .

The conductive film 430b connected to the third node N3 through the first source-drain metal 440b has a predetermined distance from the emission line EML, so that the second capacitor C2 shown in FIG. 3 is formed on the substrate ( 400) can be placed on. When the voltage level of the emission signal transferred to the emission line EML is lowered by the second capacitor C2 formed by the emission line EML and the conductive layer 430b, the third node N3 The voltage level may be lowered.

A first planarization layer 406 may be disposed on the first source and drain metals 440b and 440d. A second source-drain metal 460 may be disposed on the first planarization layer 406 . In addition, a second planarization layer 407 may be disposed on the first planarization layer 406 on which the second source-drain metal 460 is disposed.

6 is a graph showing a voltage applied to a third node of a pixel when a data signal representing black is transmitted to the pixel.

Referring to FIG. 6 , (a) shows that the conductive film 430b is not disposed on the substrate 400, and (b) shows that the conductive film 430b is disposed on the substrate 400. As shown in (a), when the conductive film 430b is not disposed on the substrate 400, the capacitance formed between the third node N3 and the emission line EML is 0.5 pF. In addition, when the conductive film 430b is disposed on the substrate 400, the capacitance formed between the emission lines EML of the third node N3 is 10 pF.

And, when the voltage of the emission signal goes from a high state to a low state while the data signal representing black is applied, in the case of (a), the voltage level VN3 of the third node N3 is 6.7V, ( In the case of b), the voltage level VN3 of the third node N3 is lowered to 6.2 V.

Therefore, when the second capacitor C2 is formed by the conductive layer 430b disposed on the substrate N3 to overlap the emission line EML, the third capacitor C2 is larger than the case where the second capacitor C2 is not formed. It can be seen that the voltage level of the node N3 is lowered by about 7.5%.

For the same reason, it can be seen that the pixel 101 displayed in black on the display device 100 can be displayed blacker, so that the image quality of the display device 100 is improved.

Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present disclosure. . Therefore, the embodiments of the present disclosure are not intended to limit the technical idea of the present disclosure, but to explain, and the scope of the technical idea of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of protection of the present disclosure should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present disclosure.

100: display device
101: pixel
110: display panel
120: data driver
130: gate driver
140; timing controller

Claims (15)

a driving transistor supplying driving current from the second node to the third node in response to the voltage of the first node;
a light emitting device receiving the driving current and emitting light;
a first capacitor for maintaining the voltage of the first node;
a first transistor selectively connecting the first node and the third node in response to a first gate signal;
a second transistor selectively transferring a data signal to the second node in response to a second gate signal;
a third transistor selectively transferring a driving voltage to the second node in response to an emission signal;
a fourth transistor connecting the third node and the light emitting element in response to the emission signal;
a fifth transistor supplying a first initialization voltage to the third node in response to a third gate signal; and
A pixel comprising a second capacitor that changes the voltage of the third node in response to the voltage level of the emission signal.
According to claim 1,
A pixel supplying a second initialization voltage to an anode electrode of the light emitting device in response to the third gate signal.
According to claim 1,
Operation is divided into a sampling period in which the emission signal maintains a high state and an emission period in which the emission signal maintains a low state,
The sampling period,
a first period of supplying the first initialization voltage to the third node;
a second period of writing a voltage corresponding to the data signal and the threshold voltage of the driving transistor to the first node; and
A pixel including a third period of supplying the first initialization voltage to the third node.
According to claim 3,
The first initialization voltage supplied in the first period and the third period has a first voltage level higher than a driving voltage supplied to the first power line.
a driving transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a first transistor having a gate electrode connected to a first gate line, a first electrode connected to the first node, and a second electrode connected to the third node;
a second transistor having a gate electrode connected to a second gate line, a first electrode connected to a data line, and a second electrode connected to the second node;
a third transistor having a gate electrode connected to an emission line, a first electrode connected to a first power line, and a second electrode connected to the second node;
a fourth transistor having a gate electrode connected to the emission line, a first electrode connected to the third node, and a second electrode connected to the fourth node;
a fifth transistor having a gate electrode connected to a third gate line, a first electrode connected to a first initialization voltage line, a second electrode connected to the third node, and a gate electrode connected to a third gate line;
a sixth transistor having a gate electrode connected to the third gate line, a first electrode connected to a second initialization voltage line, and a second electrode connected to the anode electrode of the light emitting device;
a first capacitor having a first electrode connected to the first node and a second electrode connected to the first power line;
a second capacitor having a first electrode connected to the third node and a second electrode connected to the emission line; and
A pixel including a light emitting element disposed between the fourth node and the second power supply line.
According to claim 5,
Operation is divided into a sampling period in which the emission signal maintains a high state and an emission period in which the emission signal maintains a low state,
The sampling period,
a first period of supplying the first initialization voltage to the third node;
a second period of writing a voltage corresponding to the data signal and the threshold voltage of the driving transistor to the first node; and
A pixel including a third period of supplying the first initialization voltage to the third node.
According to claim 6,
The first initialization voltage supplied in the first period and the third period has a first voltage level higher than a driving voltage supplied to the first power line.
a display panel including a plurality of data lines, a plurality of gate lines, a plurality of emission lines, and a plurality of pixels connected to the plurality of data lines, the plurality of gate lines, and the plurality of emission lines;
a data driver circuit connected to the plurality of data lines to apply data signals; and
a gate driver circuit connected to the plurality of gate lines and applying a gate signal;
The plurality of pixels,
a driving transistor supplying driving current from the second node to the third node in response to the voltage of the first node;
a light emitting device receiving the driving current and emitting light;
a first transistor selectively connecting the first node and the third node in response to a first gate signal;
a second transistor selectively connecting a data line and the second node in response to a second gate signal;
a third transistor selectively connecting a first power line and the second node in response to an emission signal;
a fourth transistor connecting the third node and the light emitting element in response to the emission signal;
a fifth transistor supplying a first initialization voltage to the third node in response to a third gate signal;
a first capacitor for maintaining the voltage of the first node; and
and a second capacitor configured to change the voltage of the third node in response to the voltage level of the emission signal.
According to claim 8,
A display device supplying a second initialization voltage to an anode electrode of the light emitting element in response to the third gate signal.
According to claim 8,
Operation is divided into a sampling period in which the emission signal maintains a high state and an emission period in which the emission signal maintains a low state,
The sampling period,
a first period of supplying the first initialization voltage to the third node;
a second period of writing a voltage corresponding to the data signal and the threshold voltage of the driving transistor to the first node; and
and a third period of supplying the first initialization voltage to the third node.
According to claim 10,
In the first period and the third period, the first initialization voltage has a first voltage level higher than a driving voltage supplied to the first power line.
According to claim 8,
The second capacitor has a first electrode connected to the third node and a second electrode connected to an emission signal line supplying the emission signal.
Board;
a first buffer layer disposed on the substrate;
a first active layer disposed on the substrate;
a gate insulating layer disposed on the active layer;
an emission line disposed on the gate insulating layer and disposed to overlap the first active layer and a gate line disposed not to overlap the first active layer;
a first interlayer insulating film disposed on the emission line and the gate line;
a conductive layer disposed on the first interlayer insulating layer and overlapping the first active layer;
a second buffer layer disposed on the interlayer insulating film on which the conductive film is disposed;
a second active layer disposed on the second buffer layer and not overlapped with the first active layer;
a second interlayer insulating film disposed on the second buffer layer on which the second active layer is disposed;
Disposed on the second interlayer insulating film, connected to the conductive film through a first contact hole, connected to the first active layer through a second contact hole, and connected to the second active layer through a third contact hole. a first source drain metal; and
A display device comprising a planarization layer disposed on the second interlayer insulating layer on which the first source-drain metal is disposed.
According to claim 13,
The second active layer includes an oxide semiconductor.
According to claim 13,
a first planarization layer disposed on the first source-drain metal;
a second source-drain metal disposed on the first planarization layer; and
A display device comprising a second planarization layer disposed on the second source-drain metal.

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