KR20220134199A - Coding/decoding apparatus and method for correcting frame concatenated error - Google Patents

Abstract

Disclosed are an encoding and decoding device and an encoding and decoding method for correcting a frame concatenation error. The encoder for correcting a frame concatenation error according to an aspect of the present invention comprises: an external encoder for generating parity bits by performing a hamming encoding operation on an input bit sequence for each frame, and generating a parity frame by adding the parity bits to an encoded frame; a frame block interpreter for dividing the parity frame into constant block units, arranging the frame, which has been divided into block units, in the shape of a matrix, and rearranging the order of the frame arranged in the shape of a matrix; and an internal encoder for performing a turbo encoding operation on the rearranged frame. Therefore, BER and FER performance can be improved in a poor channel environment when the channel environment has high correlation between a transmitting device and a receiving device.

Description

Encoder/decoder and encoding/decoding method for frame sequence error correction

The present invention relates to an encoder/decoder and an encoding/decoding method for frame burst error correction, and more particularly, to an encoder/decoder and an encoding/decoding method capable of correcting a burst sequence error in a correlation channel.

The method of correcting the frame error is to notify the sender of the error and retransmit the transmit signal when an error in the frame is detected through the Cylic Redundancy Check (CRC) adopted in Part 5 of the Narrowband Wireless Communication Physical Layer Specification. There is a method using an adjacent code combining an outer block code and a turbo code, which is an inner code. If a frame error is detected using an automatic repeat request (ARQ) such as CRC, a retransmission is requested from the transmitting side, resulting in cost. Even if an error occurring in a received frame is corrected using forward error correction (FEC) such as turbo code, the improvement of error correction performance through adjacent code is insignificant in the quasi-static rayleigh fading channel environment with inter-frame correlation. This is because, in such a correlated channel, the length of the frame sequence error increases because consecutive frames are placed in a poor channel environment. In addition, since the rate of errors occurring in each frame also increases, it is difficult to expect improvement in performance of a system for correcting frame errors through conventional bit-unit interleaving.

Background art of the present invention is disclosed in Korean Patent Publication No. 10-2014-0128605 (published on November 6, 2014).

The present invention has been devised to solve the above problems, and an object of the present invention is to provide an encoder/decoder and an encoding/decoding method capable of correcting a frame burst error in a correlation channel.

Another object of the present invention is an encoder/decoder and encoding/decoding for frame sequence error correction that can improve BER and FER performance even in a poor channel environment when a channel environment between a transmitter and a receiver has a high correlation to provide a way

The problem to be solved by the present invention is not limited to the problem(s) mentioned above, and another problem(s) not mentioned will be clearly understood by those skilled in the art from the following description.

An encoder for frame burst error correction according to an aspect of the present invention generates a parity bit by performing a Hamming encoding operation on an input bit sequence in units of frames, and adds the parity bit to an coded frame to generate a parity frame a frame block interleaver that divides the parity frame into a block unit, arranges the frame divided by the block unit in a matrix form, and rearranges the order of the frames arranged in the matrix form, and the rearrangement It includes an internal encoder that performs turbo encoding operation on the frame.

개를 묶어

배열의 프레임 블록으로 구성하고, 각 프레임 블록 내에서 N번의 해밍 부호화 과정을 수행하여 P개의 패리티 비트들을 생성하며, 상기 생성된 패리티 비트들을 같은 열에 배열하여 길이가 N인 P개의 패리티 프레임이 생성할 수 있다. In the present invention, the external encoder includes a frame having a length of N.

tie the dog

It consists of an array of frame blocks, performs N Hamming encoding processes in each frame block to generate P parity bits, and arranges the generated parity bits in the same column to generate P parity frames of length N. can

In the present invention, the frame block interleaver may have an α×β matrix structure, α may be the number of inputs of the internal encoder, and β may be a value set according to a channel environment.

In the present invention, the frame block interleaver may rearrange the order of the frames so that at most one error exists in the frame divided by the block unit.

In the present invention, the internal encoder includes a plurality of recursive systematic convolutional (RSC) encoders and one internal interleaver connected in parallel, and the internal interleaver may be a random interleaver.

A decoder for frame sequencing error correction according to an aspect of the present invention includes an internal decoder that performs a turbo decoding operation on a received frame, divides the turbo-decoded frame into a predetermined block unit, and divides the frame divided into block units. A frame block deinterleaver arranged in a matrix form and rearranging the order of the frames arranged in a matrix form, and an external decoder performing a Hamming decoding operation on the rearranged frame, wherein the external decoder comprises: Errors can be corrected through actions.

In the present invention, the frame block deinterleaver may have an α×β matrix structure, α may be the number of inputs of the internal decoder, and β may be a value set according to a channel environment.

In the present invention, the frame block deinterleaver may rearrange the order of the frames so that at most one error exists in the frame divided by the block unit.

According to another aspect of the present invention, in an encoding method for frame burst error correction, an external encoder performs a Hamming encoding operation on an input bit sequence on a frame-by-frame basis to generate a parity bit, and adds the parity bit to an encoded frame. generating a parity frame, the frame block interleaver divides the parity frame into blocks of a certain block, arranges the frames divided in units of blocks in a matrix form, and rearranges the order of the frames arranged in the matrix form and performing, by an inner encoder, a turbo encoding operation on the rearranged frame.

개를 묶어

배열의 프레임 블록으로 구성하고, 각 프레임 블록 내에서 N번의 해밍 부호화 과정을 수행하여 P개의 패리티 비트들을 생성하며, 상기 생성된 패리티 비트들을 같은 열에 배열하여 길이가 N인 P개의 패리티 프레임이 생성할 수 있다. In the present invention, in the generating of the parity frame, the outer encoder provides a frame having a length of N.

tie the dog

It consists of an array of frame blocks, performs N Hamming encoding processes in each frame block to generate P parity bits, and arranges the generated parity bits in the same column to generate P parity frames of length N. can

In the present invention, in the step of rearranging the order of the frames, the frame block interleaver may rearrange the order of the frames so that at most one error exists in the frame divided by the block unit.

A decoding method for frame burst error correction according to another aspect of the present invention includes the steps of: an internal decoder performing a turbo decoding operation on a received frame; a frame block interleaver dividing the turbo-decoded frame into a predetermined block unit; , arranging the frames divided into blocks in a matrix form, rearranging the order of the frames arranged in the matrix form, and correcting an error by performing a Hamming decoding operation on the rearranged frame by an external decoder including the steps of

In the present invention, in the step of rearranging the order of the frames, the frame block deinterleaver may rearrange the order of the frames so that at most one error exists in the frame divided by the block unit.

An encoder/decoder and an encoding/decoding method for frame burst error correction according to an embodiment of the present invention, when a channel environment between a transmitter and a receiver has a high correlation, BER and FER performance in a poor channel environment can be improved

Since the encoder/decoder and the encoding/decoding method for frame sequence error correction according to an embodiment of the present invention deal with the sequence error in frame units, the channel environment between the transmitter and the receiver is poor through the Hamming block code. Even if it is placed, it is possible to efficiently correct the frame sequence error. This can effectively deal with malfunctions caused by frame aggregation errors that occur due to very poor channel conditions in communication between E-IoT devices that require high reliability.

On the other hand, the effects of the present invention are not limited to the above-mentioned effects, and various effects may be included within the range apparent to those skilled in the art from the description below.

1 is a block diagram illustrating a communication system for frame burst error correction according to an embodiment of the present invention.
2 is a block diagram illustrating an encoder for frame burst error correction according to an embodiment of the present invention.
3 is an exemplary diagram for explaining Hamming encoding and Hamming decoding according to an embodiment of the present invention.
4 is an exemplary diagram for explaining an operation of a frame block interleaver according to an embodiment of the present invention.
5 is a diagram for explaining an internal encoder according to an embodiment of the present invention.
6 is a block diagram for explaining a decoder for frame burst error correction according to an embodiment of the present invention.
7 is a diagram illustrating BER and FER performance curves of a turbo code in which a frame block interleaver and a Hamming code are combined according to an embodiment of the present invention.

Hereinafter, an encoder/decoder and an encoding/decoding method for frame burst error correction according to an embodiment of the present invention will be described with reference to the accompanying drawings. In this process, the thickness of the lines or the size of the components shown in the drawings may be exaggerated for clarity and convenience of explanation. In addition, the terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to intentions or customs of users and operators. Therefore, definitions of these terms should be made based on the content throughout this specification.

Implementations described herein may be implemented in, for example, a method or process, an apparatus, a software program, a data stream, or a signal. Although discussed only in the context of a single form of implementation (eg, discussed only as a method), implementations of the discussed features may also be implemented in other forms (eg, as an apparatus or program). The apparatus may be implemented in suitable hardware, software and firmware, and the like. A method may be implemented in an apparatus such as, for example, a processor, which generally refers to a computer, a microprocessor, a processing device, including an integrated circuit or programmable logic device, or the like. Processors also include communication devices such as computers, cell phones, portable/personal digital assistants ("PDA") and other devices that facilitate communication of information between end-users.

1 is a block diagram illustrating a communication system for frame burst error correction according to an embodiment of the present invention.

Referring to FIG. 1 , a communication system for frame aggregation error correction according to an embodiment of the present invention may include a transmitter 10 and a receiver 20 .

The transmitter 10 may include an encoder 100 and a modulator 200 .

The encoder 100 may encode the input bit sequence in units of frames, and transmit the encoded frame to the modulator 200 . In this case, the encoder 100 may perform encoding using a frame Hamming code. A detailed description of the encoder 100 will be referred to FIG. 2 .

The modulator 200 modulates the frame encoded by the encoder 100 using a preset modulation method to generate a transmission signal, and transmits the generated transmission signal to the receiver 20 through a channel.

The receiver 20 may include a demodulator 300 and a decoder 400 .

The demodulator 300 may demodulate the transmission signal received from the transmitter 10 in a preset demodulation method and transmit it to the decoder 400 .

The decoder 400 may decode the demodulated frame. In this case, the decoder 400 may perform decoding using frame Hamming decoding. A detailed description of the decoder 400 will be described with reference to FIG. 6 .

On the other hand, the frame sequence error means that frame errors continuously occur within a threshold length in consecutive frames during data transmission. Accordingly, a frame error sequence may be constructed by comparing the input signal transmitted from the transmitter 10 and the signal decoded from the receiver 20 , and then the frame sequence error may be investigated.

In the present invention, the frame burst error is defined and described as the longest sequence among the error sequences that do not include consecutive correct bits that are not greater than the threshold length in the error sequence.

Such a frame burst error can be investigated by constructing a frame error sequence. Each bit constituting the frame error sequence indicates whether an error in the frame has occurred. By comparing the message frame X transmitted from the transmitter 10 and the frame Y decoded by the receiver 20, as shown in Equation 1 below, if there is no error in the frame, it is expressed as '0' and if there is an error, it is expressed as '1'. can

[Equation 1]

는 프레임 오류 시퀀스 내 i번째 비트를 의미하며,

와

는 각각 i번째 메시지 프레임과 복호된 프레임을 의미한다. 프레임 연집 오류는 임의의 두 프레임 오류 비트 '1' 사이에 올바른 프레임 비트 '0'이 연속하여 임계 길이 이상으로 포함되지 않는 오류 시퀀스 중 길이가 가장 긴 것을 의미할 수 있다. here,

means the i-th bit in the frame error sequence,

Wow

denotes an i-th message frame and a decoded frame, respectively. The frame burst error may mean that the length of the error sequence in which correct frame bit '0' is not included by more than a threshold length consecutively between any two frame error bit '1' has the longest length.

)를 설정할 수 있다.The transmitter 10 may transmit the pilot signal to the receiver 20 using the [15 13] turbo code to which the frame Hamming code is not combined. After estimating the channel environment using the decoded pilot signal, the receiving device 20 determines the depth (

) can be set.

If the channel environment of the receiver 20 is changed, the depth of the frame block interleaver 120 is reset in response thereto so that the wireless communication system can properly respond to the changed channel environment.

2 is a block diagram for explaining an encoder for frame burst error correction according to an embodiment of the present invention, FIG. 3 is an exemplary diagram for explaining Hamming encoding and Hamming decoding according to an embodiment of the present invention, FIG. 4 is an exemplary diagram for explaining an operation of a frame block interleaver according to an embodiment of the present invention, and FIG. 5 is a diagram for explaining an internal encoder according to an embodiment of the present invention.

Referring to FIG. 2 , the encoder 100 for frame burst error correction according to an embodiment of the present invention may include an external encoder 110 , a frame block interleaver 120 , and an internal encoder 130 .

The external encoder 110 may generate a parity frame by encoding the input bit sequence in units of frames. That is, the external encoder 110 may generate a parity bit by performing a Hamming encoding operation on the input frame, and may generate a parity frame by adding the parity bit to the encoded frame.

배열의 프레임 블록으로 구성할 수 있다. 여기서, 프레임 블록은 같은 열에 위치한 (2^P-P-1)개의 비트들이 묶인 N개의 신호 블록으로 구성될 수 있다. 외부 부호기(110)는 도 3에 도시된 바와 같이 각 프레임 블록 내에서 해밍 부호화 과정을 N번 수행할 수 있고, 프레임 블록 내의 해밍 부호화 과정을 통해 P개의 패리티 비트들을 생성하며, 생성된 패리티 비트들을 같은 열에 배열하여 길이가 N인 P개의 패리티 프레임을 생성할 수 있다. Specifically, the external encoder 110 bundles (2 ^P -P-1) frames of length N

It can consist of an array of frame blocks. Here, the frame block may be composed of N signal blocks in which (2 ^P -P-1) bits located in the same column are bundled. As shown in FIG. 3 , the external encoder 110 may perform the Hamming encoding process in each frame block N times, generate P parity bits through the Hamming encoding process in the frame block, and divide the generated parity bits. P parity frames of length N may be generated by arranging them in the same column.

개의 입력 프레임들에 P개의 패리티 프레임을 추가하여

개의 프레임을 생성할 수 있다. 예를 들면, 외부 부호기(110)는 길이가 k인 입력 프레임

을 입력받을 수 있다. 여기서, (i)는 i번째 입력 프레임을 나타낸다. 외부 부호기(110)는 입력된 프레임들을 M×N 행렬 형태로 배열한 후, N개의 프레임 블록으로 구성할 수 있다. 프레임 해밍 부호화를 위한 j번째 프레임 블록은 각각의 (2^P-P-1)개의 입력 프레임 내 j번째 비트들인

로 구성되어 P개의 패리티 프레임을 생성할 수 있다. In the encoding process, the external encoder 110 corrects one frame error in the frame block in the decoding process.

By adding P parity frames to the input frames,

You can create multiple frames. For example, the external encoder 110 provides an input frame of length k.

can be input. Here, (i) represents the i-th input frame. After arranging the input frames in an M×N matrix form, the external encoder 110 may consist of N frame blocks. The j-th frame block for frame Hamming coding is the j-th bit in each (2 ^P -P-1) input frame.

may be configured to generate P parity frames.

On the other hand, in order to correct an error using the frame Hamming code, there should be at most one or less frame errors in the frame block. A frame block may be configured by arranging several frames in an M×N matrix form. Hamming encoding may be performed N times in the external encoder 110 . In this case, N signal blocks may be configured within a frame block for each Hamming coding. An arbitrary i-th signal block may be configured using bits located in the i-th order of frames existing in the frame block. The frame block interleaver 120 may be inserted between the frame Hamming code and the turbo code in order to disperse consecutively occurring frame sequence errors.

The frame block interleaver 120 may rearrange the order of frames between the inner encoder 130 and the outer encoder 110 .

The frame block interleaver 120 divides the frames output from the external encoder 110 in units of blocks, arranges the frames divided in units of blocks in a matrix form, and rearranges the order of the frames arranged in a matrix form. have. For example, the frame block interleaver 120 may rearrange the order of frames output from the external encoder 110 as shown in FIG. 4 .

The frame block interleaver 120 may have an α×β matrix structure, α may be the number of inputs of the internal encoder 130 , and β may be a value set according to a channel environment.

The α×β frame block interleaver 120 receives the order of frames, divides them into blocks, arranges them in a matrix form, changes the rows and columns to shuffle the order of frames, and then according to the order of the newly created frames. Frames can be printed. Here, β may represent the depth of the frame block interleaver 120 . The depth of the frame block interleaver 120 may be set by examining the distribution of frame burst errors according to channel estimation. For example, in the quasi-Static Rayleigh Fading channel environment, from the order of the smallest frame sequence error, the length β _99% of which the cumulative probability is 99% or more and the length β 99.9% of the length β _99.9% or more are investigated, and the codewords of the Hamming code higher than that are When the length β including β is set to the depth of the frame block interleaver 120, there may be at most one frame error or less in the frame block interleaved frame block. When α is sufficiently larger than the depth β of the frame block interleaver 120, the frame block includes only one or less frame errors at most. The presence of at most one frame error means that there is only one error at most in each of the N signal blocks existing in the frame block. Accordingly, all bit errors present in the frame block may be corrected through the N times Hamming decoding performed by the external decoder 430 . Through this, a maximum of one or less frame errors present in the frame block can be corrected, and the frame sequence error can be corrected by correcting errors in all signal blocks existing in the frame block through the frame Hamming code.

The internal encoder 130 may perform a turbo encoding operation on a frame whose order is rearranged in the frame block interleaver 120 .

이며, 전달 함수

는 아래 수학식 2와 같을 수 있다. According to the Part 5 Narrowband Wireless Communication Physical Layer Specification, when the length of the input bit sequence including the CRC is greater than 80, the turbo code can be used as the forward error correction code. Accordingly, in the embodiment of the present invention, the encoder of the [15 13] turbo code shown in FIG. 5 is used as the internal encoder 130. FIG. Referring to FIG. 5 , the turbo code internal encoder 130 may include a recursive systematic convolutional (RSC) encoder 132 connected in parallel and one internal interleaver 134 . In this case, the internal interleaver 134 may be a random interleaver. The generator polynomial of the turbo code used in the present invention is

is the transfer function

may be as in Equation 2 below.

[Equation 2]

,

이다. 내부 부호기(130) 내 RSC 부호기(132)의 초기 상태는 모두 0으로 설정할 수 있다. 모든 입력 비트들이 부호화된 이후 터보 부호는 내부 부호기(130) 내 RSC 부호기(132)의 각 상태를 모두 0으로 만들기 위하여 테일 터미네이션 과정을 수행할 수 있다. 하나의 RSC 부호기(132) 당 테일 터미네이션 과정을 위하여 3개의 테일 입력 비트와 이로 인한 3개의 테일 출력 비트가 생성되며 테일 비트는 RSC 부호기(132) 각각의 피드백 신호와 동일한 값을 갖는다.

의 길이는 K이며

과

의 길이는 테일 터미네이션 과정으로 인하여 각각 6개의 비트가 추가될 수 있다. here,

,

to be. All initial states of the RSC encoder 132 in the internal encoder 130 may be set to 0. After all input bits are encoded, the turbo code may perform a tail termination process to make all states of the RSC encoder 132 in the inner encoder 130 to 0. For the tail termination process per one RSC encoder 132 , three tail input bits and three tail output bits are generated therefrom, and the tail bits have the same value as the feedback signal of each RSC encoder 132 .

is of length K

class

6 bits may be added to the length of each due to the tail termination process.

6 is a block diagram for explaining a decoder for frame burst error correction according to an embodiment of the present invention.

Referring to FIG. 6 , the decoder 400 for frame burst error correction according to an embodiment of the present invention may include an internal decoder 410 , a frame block deinterleaver 420 , and an external decoder 430 .

The internal decoder 410 may perform a decoding operation based on a turbo decoding scheme corresponding to the turbo coding scheme used in the transmitter 10 and output a turbo-decoded frame.

The frame block deinterleaver 420 may rearrange the turbo-decoded frame so that an error can be corrected through the frame Hamming code.

The frame block deinterleaver 420 may divide the turbo-decoded frame in units of blocks, arrange the frames divided in units of blocks in a matrix form, and rearrange the order of the frames arranged in a matrix form. In this case, the frame block deinterleaver 420 may rearrange the order of the frames so that at most one error exists in the frame divided by blocks.

The frame block deinterleaver 420 may have an α×β matrix structure, α may be the number of inputs of the internal decoder 410 , and β may be a value set according to a channel environment. The frame block interleaving process should be performed after all signals are received. In this process, latency may occur between the transmitter 10 and the receiver 20 .

개의 프레임들을

개의 프레임으로 복호할 수 있다. 이때, 외부 복호기(430)는 N번의 해밍 복호를 통해 프레임 블록 내 존재하는 모든 비트 오류를 정정할 수 있다. 이를 통해 프레임 블록 내 존재하는 최대 1개 이하의 프레임 오류를 정정할 수 있다.The external decoder 430 may perform a Hamming decoding operation on the rearranged frame based on a Hamming decoding method corresponding to the Hamming encoding method used in the transmitter 10 . That is, the external decoder 430 decodes the Hamming code N times for each frame block,

frames of dogs

It can be decoded into frames. In this case, the external decoder 430 may correct all bit errors existing in the frame block through Hamming decoding N times. Through this, it is possible to correct at most one or less frame errors existing in the frame block.

Frames rearranged while passing through the frame block deinterleaver 420 may be decoded by the external decoder 430 . At this time, if Hamming decoding is performed N times in the external decoder 430 and there is only one error or less in the N signal blocks constituting the frame block, the external decoder 430 may correct the frame sequence error. can

Meanwhile, the present invention is to improve BER and FER performance in a poor channel environment when the channel environment between the transmitter 10 and the receiver 20 has a high correlation. When a channel environment with high correlation is placed in a poor state, since arbitrary successive frames are transmitted and received through the poor channel environment, frame errors increase. In addition, an error occurs in almost all bits existing in a frame in which a frame error occurs. Therefore, even if the FER performance curve is similar to the case with low correlation, the BER performance is worse than when it has low correlation. To correct this, when bits are rearranged through the conventional bit-unit block interleaving, since the distribution of bit-unit burst errors becomes very long, the depth of the block interleaver becomes very long, making it difficult to achieve efficient performance improvement. In addition, since the codeword length of the block code set through the depth of the block interleaver is also very long, it is difficult to achieve improvement in BER and FER performance through the adjacent code inserting the existing bit-unit interleaver. Therefore, in the present invention, the performance can be improved by handling the frame-sequential error on a frame-by-frame basis rather than on the conventional bit-unit-by-sequence error.

Hereinafter, the BER and FER performance of the turbo code in which the frame block interleaver 120 and the Hamming code are combined according to the present invention will be described through simulation.

에서 임계 길이 3일 때의 프레임 연집 오류의 분포는 4 ~ 14이며, 임계 길이가 길어질수록 프레임 연집 오류의 분포 또한 늘어나 임계 길이가 7일 때는 13 ~ 37까지 늘어났다. 임계 길이가 늘어날수록 프레임 블록 인터리버(120)의 깊이 또한 길어지는 경향이 있기 때문에 프레임 연집 오류의 임계 길이는 3으로 설정하였으며 프레임 연집 오류를 정정하기 위한 프레임 블록 인터리버(120)의 깊이는 15로 설정하여 모의실험을 진행하였다.In order to investigate the distribution of frame burst error according to the critical length of the frame sequence error, a simulation was conducted by changing the critical length. It was confirmed that the length of the frame sequence error also increased as the critical length increased. FER

In , the distribution of frame sequencing errors when the critical length is 3 is 4 to 14, and as the critical length increases, the distribution of frame sequencing errors also increases, increasing to 13 to 37 when the critical length is 7. Since the depth of the frame block interleaver 120 also tends to increase as the threshold length increases, the threshold length of the frame burst error is set to 3, and the depth of the frame block interleaver 120 for correcting the frame burst error is set to 15. Therefore, a simulation experiment was conducted.

(Normalized Doppler Frequency)를 0.001로 설정하여 모의실험을 진행하였다. 도 7은

가 0.001일 때의 통신 시스템의 BER과 FER을 나타낸다. 도 7을 참조하면,

가 0.001일 때, 채널 상태 간 높은 상관관계를 갖기 때문에 성능 열화가 나타난다.

가 13 이하일 때, 프레임 연집 오류의 분포를 살펴보면, 길이가 작은 순으로 누적 확률 99% 또는 99.9%를 포함하는 프레임 연집 오류의 길이가 프레임 연집 오류 사이의 길이보다 충분히 크지 않아 성능 개선이 없는 것을 확인할 수 있다.

가 15이상일 때, 뚜렷하지 않지만 성능이 개선되는 것을 확인할 수 있다.

가 증가함에 따라 결합된 부호의 정정 성능이 개선되는 것을 확인할 수 있다.

가 15 근처에서 FER은 거의 개선되지 않지만

가 28 근처에서는 약 44배 정도 개선되는 것을 확인할 수 있다. In the simulation, the channel environment with high correlation was assumed, and for this, the experiment was conducted in the quasi-static rayleigh fading environment modeled with FSMC (Finite State Markov Chain). To check the operation of the system in a poor channel environment

(Normalized Doppler Frequency) was set to 0.001 and simulation was performed. 7 is

It represents the BER and FER of the communication system when is 0.001. Referring to Figure 7,

When is 0.001, performance degradation occurs because there is a high correlation between channel states.

When is 13 or less, looking at the distribution of frame burst errors, it can be seen that the length of the frame burst error including the cumulative probability of 99% or 99.9% in descending order of length is not sufficiently larger than the length between the frame burst errors, so that there is no performance improvement. can

When is more than 15, it can be seen that the performance is improved although it is not clear.

It can be seen that the correction performance of the combined code is improved as n is increased.

Although the FER hardly improves at around 15

It can be seen that around 28, the improvement is about 44 times.

In E-IoT communication, the characteristics of the channel environment between the transmitter 10 and the receiver arch have a high probability of having a high correlation with the channel environment. Therefore, if the channel environment is placed in a poor state, this poor state is likely to continue, and this The possibility of malfunctions also increases. If the communication system of the present invention deals with the burst error on a frame-by-frame basis, the frame sequence error can be efficiently corrected even if the channel environment between the transmitter 10 and the receiver 20 is in a poor state through the Hamming block code. have. This can effectively deal with malfunctions caused by frame aggregation errors that occur due to very poor channel conditions in communication between E-IoT devices that require high reliability.

As described above, when the channel environment between the encoder/decoder and the encoding/decoding method and the transmitter 10 and the receiver 20 for frame burst error correction according to an embodiment of the present invention has a high correlation , it is possible to improve BER and FER performance in a poor channel environment.

The encoder/decoder and the encoding/decoding method for frame sequence error correction according to an embodiment of the present invention deal with a sequence error on a frame-by-frame basis. Even if the channel environment is in a poor state, it is possible to efficiently correct the frame burst error. This can effectively deal with malfunctions caused by frame aggregation errors that occur due to very poor channel conditions in communication between E-IoT devices that require high reliability.

Although the present invention has been described with reference to the embodiment shown in the drawings, this is merely exemplary, and those of ordinary skill in the art to which various modifications and equivalent other embodiments are possible. will understand

Therefore, the true technical protection scope of the present invention should be defined by the following claims.

10: transmitter
20: receiving device
100 : encoder
110: external encoder
120: frame block interleaver
130: internal encoder
200: modulator
300: demodulator
400 : decoder
410: internal decoder
420: frame block deinterleaver
430: external decoder

Claims (13)

an external encoder for generating a parity bit by performing a Hamming encoding operation on an input bit sequence in units of frames, and adding the parity bit to an coded frame to generate a parity frame;
a frame block interleaver that divides the parity frame into a block unit, arranges the frame divided by block unit in a matrix form, and rearranges the order of the frames arranged in the matrix form; and
An inner encoder that performs a turbo encoding operation on the rearranged frame
An encoder for frame sequence error correction comprising a.
According to claim 1,
The external encoder is
length

in frame

tie the dog

It consists of an array of frame blocks, performs N Hamming encoding processes in each frame block to generate P parity bits, and arranges the generated parity bits in the same column to generate P parity frames of length N An encoder for frame sequence error correction, characterized in that.
According to claim 1,
The frame block interleaver,
α × β matrix structure,
wherein α is the number of inputs of the internal encoder, and β is a value set according to a channel environment.
According to claim 1,
The frame block interleaver,
An encoder for frame sequence error correction, characterized in that the order of the frames is rearranged so that at most one error exists in the frame divided by the block unit.
According to claim 1,
The internal encoder is
a plurality of recursive systematic convolutional (RSC) encoders connected in parallel; and
comprising one internal interleaver;
and the internal interleaver is a random interleaver.
an inner decoder for performing turbo decoding on a received frame;
a frame block deinterleaver that divides the turbo-decoded frame into blocks, arranges the frames divided into blocks in a matrix form, and rearranges the order of the frames arranged in the matrix form; and
An external decoder for performing a Hamming decoding operation on the rearranged frame,
and the external decoder corrects an error through the Hamming decoding operation.
7. The method of claim 6,
The frame block deinterleaver,
α × β matrix structure,
wherein α is the number of inputs of the internal decoder, and β is a value set according to a channel environment.
7. The method of claim 6,
The frame block deinterleaver,
The decoder for frame sequence error correction, characterized in that the order of the frames is rearranged so that at most one error exists in the frame divided by the block unit.
generating a parity bit by performing, by an external encoder, a Hamming encoding operation on an input bit sequence in units of frames, and adding the parity bit to an coded frame to generate a parity frame;
dividing, by a frame block interleaver, the parity frame in units of predetermined blocks, arranging the frames divided in units of blocks in a matrix form, and rearranging the order of the frames arranged in the matrix form; and
performing, by an inner encoder, a turbo encoding operation on the rearranged frame
A coding method for frame sequence error correction comprising a.
10. The method of claim 9,
In the step of generating the parity frame,
The external encoder has a length

in frame

tie the dog

It consists of an array of frame blocks, performs N Hamming encoding processes in each frame block to generate P parity bits, and arranges the generated parity bits in the same column to generate P parity frames of length N An encoding method for frame sequence error correction, characterized in that.
10. The method of claim 9,
In the step of rearranging the order of the frames,
and the frame block interleaver rearranges the order of the frames so that at most one error exists in the frame divided by blocks.
performing, by an inner decoder, a turbo decoding operation on the received frame;
dividing, by a frame block interleaver, the turbo-decoded frames in units of predetermined blocks, arranging the frames divided in units of blocks in a matrix form, and rearranging the order of the frames arranged in the matrix form; and
correcting an error by performing a Hamming decoding operation on the rearranged frame by an external decoder
A decoding method for frame sequence error correction, comprising:
13. The method of claim 12,
In the step of rearranging the order of the frames,
and the frame block deinterleaver rearranges the order of the frames so that at most one error exists in the frame divided by blocks.

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