KR20220113736A - 메모리 액세스 요청 스테이징 - Google Patents

메모리 액세스 요청 스테이징 Download PDF

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Publication number
KR20220113736A
KR20220113736A KR1020227022687A KR20227022687A KR20220113736A KR 20220113736 A KR20220113736 A KR 20220113736A KR 1020227022687 A KR1020227022687 A KR 1020227022687A KR 20227022687 A KR20227022687 A KR 20227022687A KR 20220113736 A KR20220113736 A KR 20220113736A
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South Korea
Prior art keywords
memory access
access request
memory
staging buffer
command queue
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KR1020227022687A
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English (en)
Korean (ko)
Inventor
제임스 알. 마그로
케다나쓰 발라크리쉬난
라빈드라 엔. 바르가바
관하오 센
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20220113736A publication Critical patent/KR20220113736A/ko
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1009Address translation using page tables, e.g. page table structures
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1673Details of memory controller using buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
KR1020227022687A 2019-12-27 2020-12-22 메모리 액세스 요청 스테이징 Pending KR20220113736A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/728,114 US12253961B2 (en) 2019-12-27 2019-12-27 Staging memory access requests
US16/728,114 2019-12-27
PCT/US2020/066618 WO2021133806A1 (en) 2019-12-27 2020-12-22 Staging memory access requests

Publications (1)

Publication Number Publication Date
KR20220113736A true KR20220113736A (ko) 2022-08-16

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KR1020227022687A Pending KR20220113736A (ko) 2019-12-27 2020-12-22 메모리 액세스 요청 스테이징

Country Status (6)

Country Link
US (1) US12253961B2 (https=)
EP (1) EP4081905B1 (https=)
JP (1) JP7708767B2 (https=)
KR (1) KR20220113736A (https=)
CN (1) CN114846454B (https=)
WO (1) WO2021133806A1 (https=)

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US20260099448A1 (en) * 2024-10-07 2026-04-09 Nxp Usa, Inc. System and method of exclusive memory access among multiple processing devices

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Also Published As

Publication number Publication date
JP7708767B2 (ja) 2025-07-15
EP4081905B1 (en) 2025-07-16
CN114846454B (zh) 2026-01-30
EP4081905A1 (en) 2022-11-02
CN114846454A (zh) 2022-08-02
WO2021133806A1 (en) 2021-07-01
JP2023508460A (ja) 2023-03-02
US12253961B2 (en) 2025-03-18
US20210200695A1 (en) 2021-07-01

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