KR20220113736A - 메모리 액세스 요청 스테이징 - Google Patents
메모리 액세스 요청 스테이징 Download PDFInfo
- Publication number
- KR20220113736A KR20220113736A KR1020227022687A KR20227022687A KR20220113736A KR 20220113736 A KR20220113736 A KR 20220113736A KR 1020227022687 A KR1020227022687 A KR 1020227022687A KR 20227022687 A KR20227022687 A KR 20227022687A KR 20220113736 A KR20220113736 A KR 20220113736A
- Authority
- KR
- South Korea
- Prior art keywords
- memory access
- access request
- memory
- staging buffer
- command queue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
- G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Memory System (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/728,114 US12253961B2 (en) | 2019-12-27 | 2019-12-27 | Staging memory access requests |
| US16/728,114 | 2019-12-27 | ||
| PCT/US2020/066618 WO2021133806A1 (en) | 2019-12-27 | 2020-12-22 | Staging memory access requests |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20220113736A true KR20220113736A (ko) | 2022-08-16 |
Family
ID=74181383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020227022687A Pending KR20220113736A (ko) | 2019-12-27 | 2020-12-22 | 메모리 액세스 요청 스테이징 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US12253961B2 (https=) |
| EP (1) | EP4081905B1 (https=) |
| JP (1) | JP7708767B2 (https=) |
| KR (1) | KR20220113736A (https=) |
| CN (1) | CN114846454B (https=) |
| WO (1) | WO2021133806A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11347644B2 (en) * | 2018-10-15 | 2022-05-31 | Texas Instruments Incorporated | Distributed error detection and correction with hamming code handoff |
| US20210200694A1 (en) * | 2019-12-27 | 2021-07-01 | Advanced Micro Devices, Inc. | Staging buffer arbitration |
| US11593024B1 (en) * | 2021-08-30 | 2023-02-28 | Micron Technology, Inc. | Request control for memory sub-systems |
| US20260099448A1 (en) * | 2024-10-07 | 2026-04-09 | Nxp Usa, Inc. | System and method of exclusive memory access among multiple processing devices |
Family Cites Families (51)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4394732A (en) * | 1980-11-14 | 1983-07-19 | Sperry Corporation | Cache/disk subsystem trickle |
| US7181548B2 (en) * | 1998-10-30 | 2007-02-20 | Lsi Logic Corporation | Command queueing engine |
| CA2255418C (en) * | 1998-12-07 | 2003-01-21 | Pmc-Sierra Ltd. | Ring interface and ring network bus flow control system |
| JP3235578B2 (ja) * | 1998-12-24 | 2001-12-04 | 日本電気株式会社 | メモリアクセス制御方式 |
| US6816947B1 (en) * | 2000-07-20 | 2004-11-09 | Silicon Graphics, Inc. | System and method for memory arbitration |
| US7269709B2 (en) * | 2002-05-15 | 2007-09-11 | Broadcom Corporation | Memory controller configurable to allow bandwidth/latency tradeoff |
| US7418540B2 (en) * | 2004-04-28 | 2008-08-26 | Intel Corporation | Memory controller with command queue look-ahead |
| US20060112240A1 (en) * | 2004-11-24 | 2006-05-25 | Walker Robert M | Priority scheme for executing commands in memories |
| JP4843216B2 (ja) | 2004-12-10 | 2011-12-21 | 株式会社リコー | メモリ制御装置 |
| US7587521B2 (en) * | 2005-06-23 | 2009-09-08 | Intel Corporation | Mechanism for assembling memory access requests while speculatively returning data |
| US7716387B2 (en) * | 2005-07-14 | 2010-05-11 | Canon Kabushiki Kaisha | Memory control apparatus and method |
| CN100505676C (zh) * | 2006-12-28 | 2009-06-24 | 复旦大学 | 智能多缓冲区管理的集中调度控制器和动态调度方法 |
| CN101340569A (zh) * | 2007-07-06 | 2009-01-07 | 扬智科技股份有限公司 | 高速缓存及其数据处理方法 |
| JP2010003067A (ja) * | 2008-06-19 | 2010-01-07 | Sony Corp | メモリシステムおよびそのアクセス制御方法、並びにプログラム |
| WO2010013189A2 (en) * | 2008-07-29 | 2010-02-04 | Nxp B.V. | Data processing circuit with arbitration between a plurality of queues |
| CN101621469B (zh) * | 2009-08-13 | 2012-01-04 | 杭州华三通信技术有限公司 | 数据报文存取控制装置和方法 |
| US8312187B2 (en) * | 2009-09-18 | 2012-11-13 | Oracle America, Inc. | Input/output device including a mechanism for transaction layer packet processing in multiple processor systems |
| US8838853B2 (en) * | 2010-01-18 | 2014-09-16 | Marvell International Ltd. | Access buffer |
| US8539129B2 (en) * | 2010-04-14 | 2013-09-17 | Qualcomm Incorporated | Bus arbitration techniques to reduce access latency |
| US9268720B2 (en) * | 2010-08-31 | 2016-02-23 | Qualcomm Incorporated | Load balancing scheme in multiple channel DRAM systems |
| US9164772B2 (en) * | 2011-02-04 | 2015-10-20 | Qualcomm Incorporated | Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available |
| DE112012007037T5 (de) * | 2012-12-19 | 2015-08-06 | Intel Corporation | Verarbeiten von Videoinhalt |
| CN103914412B (zh) * | 2013-01-09 | 2017-11-24 | 国际商业机器公司 | 用于存储设备中的流量优先化的方法,存储设备以及存储系统 |
| KR102034626B1 (ko) * | 2013-06-26 | 2019-10-21 | 삼성전자 주식회사 | 메모리 동작을 제어하는 방법 및 장치 |
| CN104252420B (zh) * | 2013-06-29 | 2017-08-29 | 华为技术有限公司 | 数据写入方法及内存系统 |
| CN105960770B (zh) * | 2013-12-09 | 2019-12-06 | 飞利浦灯具控股公司 | 用于操作网络中节点和节点设备的方法 |
| TWI528379B (zh) * | 2014-02-05 | 2016-04-01 | 廣明光電股份有限公司 | 固態硬碟的讀取方法 |
| US9575890B2 (en) * | 2014-02-27 | 2017-02-21 | International Business Machines Corporation | Supporting atomic accumulation with an addressable accumulator |
| US10318420B2 (en) * | 2014-10-31 | 2019-06-11 | Hewlett Packard Enterprise Development Lp | Draining a write queue based on information from a read queue |
| US9569362B2 (en) * | 2014-11-13 | 2017-02-14 | Cavium, Inc. | Programmable ordering and prefetch |
| JP6711281B2 (ja) * | 2015-01-22 | 2020-06-17 | ソニー株式会社 | メモリコントローラ、記憶装置、情報処理システムおよびメモリの制御方法 |
| US10146434B1 (en) * | 2015-05-15 | 2018-12-04 | Marvell Israel (M.I.S.L) Ltd | FIFO systems and methods for providing access to a memory shared by multiple devices |
| US9639280B2 (en) * | 2015-06-18 | 2017-05-02 | Advanced Micro Devices, Inc. | Ordering memory commands in a computer system |
| US10180803B2 (en) * | 2015-07-28 | 2019-01-15 | Futurewei Technologies, Inc. | Intelligent memory architecture for increased efficiency |
| US9904635B2 (en) * | 2015-08-27 | 2018-02-27 | Samsung Electronics Co., Ltd. | High performance transaction-based memory systems |
| US10642500B2 (en) * | 2015-09-28 | 2020-05-05 | Sandisk Technologies Llc | Methods, systems and computer readable media for intelligent fetching of data storage device commands from submission queues |
| US10198216B2 (en) * | 2016-05-28 | 2019-02-05 | Advanced Micro Devices, Inc. | Low power memory throttling |
| KR101888405B1 (ko) * | 2016-06-01 | 2018-08-14 | 주식회사 맴레이 | 메모리 컨트롤러, 그리고 이를 포함하는 메모리 모듈 및 프로세서 |
| US10037150B2 (en) * | 2016-07-15 | 2018-07-31 | Advanced Micro Devices, Inc. | Memory controller with virtual controller mode |
| EP3270294B1 (en) | 2016-07-15 | 2018-09-26 | Advanced Micro Devices, Inc. | Command arbitration for high-speed memory interfaces |
| US10684969B2 (en) * | 2016-07-15 | 2020-06-16 | Advanced Micro Devices, Inc. | Command arbitration for high speed memory interfaces |
| US10402120B2 (en) * | 2016-07-15 | 2019-09-03 | Advanced Micro Devices, Inc. | Memory controller arbiter with streak and read/write transaction management |
| WO2018175559A1 (en) * | 2017-03-22 | 2018-09-27 | Burlywood, LLC | Drive-level internal quality of service |
| US10452278B2 (en) * | 2017-03-24 | 2019-10-22 | Western Digital Technologies, Inc. | System and method for adaptive early completion posting using controller memory buffer |
| US10310996B2 (en) * | 2017-05-31 | 2019-06-04 | International Business Machines Corporation | Hardware queue manager with water marking |
| US10339067B2 (en) * | 2017-06-19 | 2019-07-02 | Advanced Micro Devices, Inc. | Mechanism for reducing page migration overhead in memory systems |
| US10275352B1 (en) * | 2017-12-28 | 2019-04-30 | Advanced Micro Devices, Inc. | Supporting responses for memory types with non-uniform latencies on same channel |
| US10534565B1 (en) * | 2018-04-11 | 2020-01-14 | Cadence Design Systems, Inc. | Programmable, area-optimized bank group rotation system for memory devices |
| US10901887B2 (en) * | 2018-05-17 | 2021-01-26 | International Business Machines Corporation | Buffered freepointer management memory system |
| US10969996B1 (en) * | 2019-02-06 | 2021-04-06 | Marvell Israel (M.I.S.L) Ltd. | Extendable hardware queue structure and method of operation thereof |
| US10990321B2 (en) * | 2019-02-20 | 2021-04-27 | Micron Technology, Inc. | Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue |
-
2019
- 2019-12-27 US US16/728,114 patent/US12253961B2/en active Active
-
2020
- 2020-12-22 JP JP2022539322A patent/JP7708767B2/ja active Active
- 2020-12-22 KR KR1020227022687A patent/KR20220113736A/ko active Pending
- 2020-12-22 CN CN202080090528.6A patent/CN114846454B/zh active Active
- 2020-12-22 EP EP20839527.7A patent/EP4081905B1/en active Active
- 2020-12-22 WO PCT/US2020/066618 patent/WO2021133806A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| JP7708767B2 (ja) | 2025-07-15 |
| EP4081905B1 (en) | 2025-07-16 |
| CN114846454B (zh) | 2026-01-30 |
| EP4081905A1 (en) | 2022-11-02 |
| CN114846454A (zh) | 2022-08-02 |
| WO2021133806A1 (en) | 2021-07-01 |
| JP2023508460A (ja) | 2023-03-02 |
| US12253961B2 (en) | 2025-03-18 |
| US20210200695A1 (en) | 2021-07-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| D13-X000 | Search requested |
St.27 status event code: A-1-2-D10-D13-srh-X000 |
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| D21 | Rejection of application intended |
Free format text: ST27 STATUS EVENT CODE: A-1-2-D10-D21-EXM-PE0902 (AS PROVIDED BY THE NATIONAL OFFICE) |
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| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
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| E13 | Pre-grant limitation requested |
Free format text: ST27 STATUS EVENT CODE: A-2-3-E10-E13-LIM-X000 (AS PROVIDED BY THE NATIONAL OFFICE) |
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| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
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| P11 | Amendment of application requested |
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| P11-X000 | Amendment of application requested |
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| P13 | Application amended |
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| P13-X000 | Application amended |
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