JP7708767B2 - メモリアクセス要求のステージング - Google Patents

メモリアクセス要求のステージング

Info

Publication number
JP7708767B2
JP7708767B2 JP2022539322A JP2022539322A JP7708767B2 JP 7708767 B2 JP7708767 B2 JP 7708767B2 JP 2022539322 A JP2022539322 A JP 2022539322A JP 2022539322 A JP2022539322 A JP 2022539322A JP 7708767 B2 JP7708767 B2 JP 7708767B2
Authority
JP
Japan
Prior art keywords
memory access
access request
memory
staging buffer
command queue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022539322A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023508460A5 (https=
JP2023508460A (ja
Inventor
アール． マグロ ジェームズ
バラクリシュナン ケダーナシュ
エヌ． バルガバ ラビンドラ
シェン グァンハオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2023508460A publication Critical patent/JP2023508460A/ja
Publication of JP2023508460A5 publication Critical patent/JP2023508460A5/ja
Application granted granted Critical
Publication of JP7708767B2 publication Critical patent/JP7708767B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
JP2022539322A 2019-12-27 2020-12-22 メモリアクセス要求のステージング Active JP7708767B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/728,114 US12253961B2 (en) 2019-12-27 2019-12-27 Staging memory access requests
US16/728,114 2019-12-27
PCT/US2020/066618 WO2021133806A1 (en) 2019-12-27 2020-12-22 Staging memory access requests

Publications (3)

Publication Number Publication Date
JP2023508460A JP2023508460A (ja) 2023-03-02
JP2023508460A5 JP2023508460A5 (https=) 2023-12-22
JP7708767B2 true JP7708767B2 (ja) 2025-07-15

Family

ID=74181383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022539322A Active JP7708767B2 (ja) 2019-12-27 2020-12-22 メモリアクセス要求のステージング

Country Status (6)

Country Link
US (1) US12253961B2 (https=)
EP (1) EP4081905B1 (https=)
JP (1) JP7708767B2 (https=)
KR (1) KR20220113736A (https=)
CN (1) CN114846454B (https=)
WO (1) WO2021133806A1 (https=)

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US20210200694A1 (en) * 2019-12-27 2021-07-01 Advanced Micro Devices, Inc. Staging buffer arbitration
US11593024B1 (en) * 2021-08-30 2023-02-28 Micron Technology, Inc. Request control for memory sub-systems
US20260099448A1 (en) * 2024-10-07 2026-04-09 Nxp Usa, Inc. System and method of exclusive memory access among multiple processing devices

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JP2000194601A (ja) 1998-12-24 2000-07-14 Nec Corp メモリアクセス制御方式
JP2013534348A (ja) 2010-08-31 2013-09-02 クアルコム，インコーポレイテッド マルチチャネルｄｒａｍシステムにおける負荷分散方式
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JP2019521448A (ja) 2016-07-15 2019-07-25 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ ストリーク及び読出し／書込みトランザクション管理を有するメモリコントローラアービタ

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JP2013534348A (ja) 2010-08-31 2013-09-02 クアルコム，インコーポレイテッド マルチチャネルｄｒａｍシステムにおける負荷分散方式
JP2017045452A (ja) 2015-08-27 2017-03-02 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． トランザクション基盤メモリシステム及びメモリモジュール並びにマスターコントローラ及びスレーブコントローラの動作方法
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Also Published As

Publication number Publication date
EP4081905B1 (en) 2025-07-16
KR20220113736A (ko) 2022-08-16
CN114846454B (zh) 2026-01-30
EP4081905A1 (en) 2022-11-02
CN114846454A (zh) 2022-08-02
WO2021133806A1 (en) 2021-07-01
JP2023508460A (ja) 2023-03-02
US12253961B2 (en) 2025-03-18
US20210200695A1 (en) 2021-07-01

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