KR20220061896A - P-type multilevel element including Tellurium layers as active layers - Google Patents

Abstract

Provided is a P-type multilevel element. The P-type multilevel element comprises: a gate electrode; an active structure including a first Te active layer overlapping the gate electrode, a second Te active layer, and a barrier layer separating the first Te active layer and the second Te active layer, wherein the first Te active layer and the second Te active layer are tellurium element layers; and source and drain electrodes electrically connected to both ends of the active structure. A threshold voltage for forming a channel in the first Te active layer and a threshold voltage for forming a channel in the second Te active layer have different values. According to the present invention, the P-type multilevel element is capable of stably providing multi-level conductivity.

Description

P-type multilevel element including Tellurium layers as active layers

The present invention relates to a semiconductor layer and a semiconductor device having the same, and more particularly, to a multi-level device.

In recent years, with the development of smart devices and artificial intelligence computer technology, the demand for higher performance devices such as high performance and multifunctionality is rapidly increasing.

However, it is predicted that the binary device manufacturing technology that has led the existing semiconductor industry is not far from the limit in terms of technology, economy, and principle through continuous miniaturization and high integration. That is, the existing MOSFET development method through miniaturization has difficulties in the miniaturization technology itself, so the approach through down scaling is evaluated to have fundamental limitations.

In order to compensate for this, research on multi-level devices is being made. Single electron transistor (SET) and resonance tunneling transistor (RTT) have been studied as multi-level device technologies previously studied. In the case of a single electron transistor (SET) and a resonance tunneling transistor (RTT), multilevel characteristics are mainly observed only at cryogenic temperatures, require a complex manufacturing process, and integration for circuit implementation is not easy, so it is difficult to realize the technology.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-level device that provides excellent multi-level characteristics.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, an aspect of the present invention provides a P-type multi-level device. The P-type multilevel device has a gate electrode. a first Te active layer, a second Te active layer overlapping the gate electrode, and a barrier layer separating the first Te active layer and the second Te active layer; 2 Te active layer is an active structure that is a tellurium element layer is disposed. Source and drain electrodes electrically connected to both ends of the active structure are disposed. A threshold voltage for forming a channel in the first Te active layer and a threshold voltage for forming a channel in the second Te active layer have different values.

The first Te active layer and the second Te active layer may have a thickness of 3 to 10 nm regardless of each other. Specifically, the first Te active layer and the second Te active layer may have a thickness of 5 to 7 nm regardless of each other.

At least one of the first Te active layer and the second Te active layer may have nanocrystals dispersed in an amorphous matrix. The nanocrystals may have a diameter of 3 to 8 nm. A distance between the nanocrystals may be smaller than a diameter of the nanocrystals. The nanocrystals may be arranged as a single layer in the first Te active layer or the second Te active layer in a thickness direction of the corresponding active layer.

When the gate voltage applied to the gate electrode increases in a negative direction, a current flowing in the first Te active layer after a channel is formed in the first Te active layer and before a channel is formed in the second Te active layer can be saturated. When the gate voltage applied to the gate electrode increases in the negative direction, the ratio of the current flowing through the active structure to the gate voltage is a first gate voltage range having a first slope, a second slope lower than the first slope It may be divided into a second gate voltage range and a third gate voltage range having a third slope higher than the second slope. The second slope may be zero.

The barrier layer is a first barrier layer, the active structure further includes a second barrier layer disposed between the gate electrode and the first Te active layer, the first Te active layer includes the first barrier layer and the second It may be interposed between the barrier layers to form a quantum well. The barrier layer may include at least one organic monolayer. When the barrier layer includes two or more organic monolayers, it may further include a metal atomic layer disposed between the organic monolayers.

As described above, according to an embodiment of the present invention, the P-type multi-level device may have a plurality of turn-on voltages, that is, a threshold voltage, and thus may provide multi-level conductivity.

Furthermore, the multi-level device according to an embodiment of the present invention may have a gate voltage range that does not occur in conventional devices, that is, a range in which there is little or no change in the magnitude of the current even when the gate voltage increases, so that multi-level conductivity is improved. can be provided stably.

However, the effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view showing a multi-level device according to an embodiment of the present invention. It is also
2 is a flowchart illustrating a method of manufacturing an active structure among a method of manufacturing a multi-level device according to an embodiment of the present invention.
3 is an enlarged schematic view of a region A of FIG. 1 corresponding to an active structure according to an embodiment of the present invention.
4 is a graph showing the transfer characteristics of the multi-level device described with reference to FIG. 1 .
5, 6, and 7 are cross-sectional views for explaining the characteristics of each operation step of the multi-level device described with reference to FIG. 1 .
8 is a cross-sectional view showing a multi-level device according to another embodiment of the present invention, and FIG. 9 is a graph showing the transfer characteristics of the multi-level device according to FIG. 8 .
10 is a cross-sectional view showing a multi-level device according to another embodiment of the present invention, and FIG. 11 is a graph showing the transfer characteristics of the multi-level device according to FIG. 10 .
12 is an X-ray diffraction graph of a Te active layer formed to a thickness of 5 nm obtained during the process of Multilevel Device Manufacturing Example 1;
13 is a TEM (Transmission Electron Microscope) image of a cross-section of a Te active layer formed to a thickness of 8 nm obtained during the process of Multilevel Device Manufacturing Example 4;
14 to 17 are ID-VG graphs illustrating transfer characteristics of multi-level devices manufactured according to manufacturing examples 1 to 4 of the multi-level device.

Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to explain the present invention in more detail. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, when it is said that a layer is “on” another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. In the present embodiments, "first", "second", or "third" is not intended to impose any limitation on the components, but should be understood as terms for distinguishing the components.

As used herein, the term “multi-level device” may mean a device having a ternary or higher state that may have 0, 1, or 2 or more states, rather than a binary state having 0, 1 states. That is, if the existing device could have only two states, on and off, the multilevel device according to an embodiment of the present invention may have another third state in addition to on and off.

1 is a cross-sectional view showing a multi-level device according to an embodiment of the present invention. It is also

Referring to FIG. 1 , the multilevel device 100 may be formed on a substrate 110 .

The substrate 110 may be a semiconductor substrate, a metal substrate, a glass substrate, or a flexible substrate. The semiconductor substrate may be a silicon substrate. The flexible substrate may be a polymer substrate, for example, a PET (polyethylene terephthalate) or PI (polyimide) substrate. Devices for operation circuits, etc. are formed on the substrate 110, a protective layer (not shown) such as an insulating film covering the substrate is formed, or a protective layer covering the device and the device may be formed. . The surface of the substrate 110 may be washed and, if necessary, surface treated.

A gate electrode 120 extending in one direction may be formed on the substrate 110 . The gate electrode 120 may be formed using Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy thereof. A gate insulating layer 130 may be formed on the gate electrode 120 . The gate insulating layer 130 may be a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, a hafnium oxide layer, a hafnium oxynitride layer, or a composite layer thereof. The gate insulating layer 130 may be formed using an atomic layer deposition method, and may be, for example, an aluminum oxide layer. The thickness of the gate insulating layer 130 may be within a range such that insulation is not broken in the operating range of the applied gate voltage. For example, when the operating range of the gate voltage is low, the thickness of the gate insulating layer 130 may be thinner than when the operating range of the gate voltage is high.

An active structure 135 patterned to overlap the gate electrode 120 may be formed on the gate insulating layer 130 . A source electrode 180 and a drain electrode 185 may be formed on both ends of the active structure 135 . The source electrode 180 and the drain electrode 185 include aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), nickel (Ni), and molybdenum. (Mo) at least one metal or an alloy containing them, or a metal oxide conductive film as an example, may be formed using ITO (Indium Tin Oxide) or nickel (Ni).

The active structure 135 may include at least one Te active layer and at least one barrier layer. Specifically, the active structure 135 may include two or more Te active layers and a barrier layer disposed between the Te active layers adjacent to each other. As an example, the active structure 135 may include a first Te active layer 150 , a barrier layer 160 , and a second Te active layer 170 sequentially stacked. In this case, a barrier layer may be further provided under the first Te active layer. In this case, the active structure 135 may include a first barrier layer 140 , a first Te active layer 150 , a second barrier layer 160 , and a second Te active layer 170 sequentially stacked. can As another example, the active structure 135 may include a first Te active layer 150 , a barrier layer 160 , a second Te active layer 170 , a barrier layer (not shown), and a third Te active layer sequentially stacked. A layer (not shown) may be provided. In this case, as the distance from the gate electrode 120 increases, the thickness of the Te active layer may increase. Alternatively, the thickness of the Te active layer may be constant regardless of the distance from the gate electrode 120 .

The Te active layers 150 and 170 are tellurium element layers, and each layer has a thickness of 3 to 10 nm, specifically 4 to 8 nm, more specifically 5 to 7 nm, so that quantization in the thickness direction may be possible. In addition, the Te active layers 150 and 170 may have a band gap of about 0.4 to 0.7 eV, and may exhibit p-type semiconductor characteristics.

The barrier layers 140 and 160 are insulating layers, and may have a larger bandgap than the Te active layers 150 and 170 . As an example, the barrier layers 140 and 160 may have a bandgap of 6 to 8 eV. The barrier layers 140 and 160 form an interface adjacent to the Te active layers 150 and 170 , and the Te active layer 150 includes the first barrier layer 140 and the second barrier layer 160 . It may be interposed therebetween to form a quantum well. In another example, even if the first barrier layer 140 positioned under the first Te active layer 150 is omitted, the first Te active layer 150 is interposed between the gate insulating layer 130 and the second barrier layer 160 . can be used to form quantum wells.

At least one of the barrier layers 140 and 160 may be an organic material layer, an inorganic material layer, or an organic-inorganic composite layer. The barrier layer may protect the Te active layer. For example, after forming the first Te active layer 150 , when another layer is formed, the barrier layer 160 may be unintentionally doped with the first Te active layer 150 or may be subjected to deposition of another layer. It is possible to minimize the penetration of the precursor into the first Te active layer 150 . According to an embodiment, the Te active layer and the barrier layer adjacent to the active layer may form a super lattice structure with each other. Stability can be improved by the super lattice structure.

A description of the method of manufacturing the active structure, specifically, the barrier layer and the Te active layer will be described later.

As an example of the thin film transistor in FIG. 1, a bottom gate-top contact type, that is, a bottom gate staggered thin film transistor, is shown, but the present invention is not limited thereto. It is also applicable to thin film transistors of the top gate-bottom contact type (top gate staggered) or top gate-top contact type (top gate coplanar) type. However, the gate electrode 120 is provided on the upper surface or the lower surface of the active structure 135 , and source and drain electrodes are provided on the surface opposite to the surface of the active structure 135 adjacent to the gate electrode 120 . A staggered type thin film transistor having (180, 185) may be preferable.

2 is a flowchart illustrating a method of manufacturing an active structure among a method of manufacturing a multi-level device according to an embodiment of the present invention. 3 is an enlarged schematic view of a region A of FIG. 1 corresponding to an active structure according to an embodiment of the present invention.

1, 2, and 3 , in the method of manufacturing the active structure 135 in the method of manufacturing a multi-level device according to an embodiment of the present invention, a first barrier layer forming step ( S110 ), a first At least one of the Te active layer forming step S120 , the second barrier layer forming step S130 , and the second Te active layer forming step S140 may be included. Hereinafter, each step will be described.

First barrier layer forming step (S110)

1, 2, and 3 , a first barrier layer 140 may be formed on the gate insulating layer 130 . The first barrier layer 140 has a larger bandgap than the Te active layer 150 , so that the Te active layer 150 may have a quantum well structure.

In this embodiment, the first barrier layer 140 may include at least one organic monolayer, and may be formed using a molecular layer deposition method. Specifically, the first barrier layer 140 includes a metal precursor dosing step, a first purge step, an organic precursor dosing step, and a second purge step by placing the substrate on which the gate insulating layer 130 is formed in a reaction chamber. After repeating the unit cycle several to tens of times, the metal precursor dosing step and the purging step may be performed to form it.

In the metal precursor dosing step, the metal precursor is dosed into the reaction chamber, but in the first unit cycle, the metal (M) of the metal precursor is chemically bonded to the surface functional group of the gate insulating layer 130, and in the second or more unit cycles, the following Chemical Formula 1 The metal (M) of the metal precursor may be chemically bonded, specifically, covalently bonded to Y ₁ and/or Y ₂ (Y) of the organic precursor represented by . In the first purge step, a purge gas may be supplied to purge the unreacted metal precursor and the reaction product. In the organic precursor dosing step, one or two or more organic precursors represented by the following Chemical Formula 1 are dosed to chemically bond X ₁ and/or X ₂ (X) of the organic precursor represented by the following Chemical Formula 1 and the metal (M) of the metal precursor. can be covalently linked. In the second purge step, a purge gas may be supplied to purge the unreacted organic precursor and the reaction product. 3 illustrates that the unit cycle is repeated twice, but is not limited thereto. The temperature of the chamber for depositing the barrier layer 140 may be 90 to 120 degrees (°C), specifically, 100 to 115 degrees (°C).

The metal precursor may be selected from the group consisting of alkyl metals, metal alkoxides, metal halides, metal hydroxides, and mixtures thereof, and may be, for example, trimethylaluminium (TMA), or diethylzinc (DEZ). .

In addition, the organic precursor may be represented by the following formula (1).

[Formula 1]

In Formula 1, X ₁ , X ₂ , Y ₁ , and Y ₂ are O, S, Se, NH, or PH independently of each other, and each of a, b, c, and d is 1 or 0, a+b is 1 or more, c+d is 1 or more, and Ar is a functional group including at least one aromatic group. When two or more aromatic groups are provided, the aromatic groups may be connected through a linking group. The aromatic group may be a C5 to C8 aromatic hydrocarbon group or a C3 to C7 heterocyclic aromatic group. As an example, the aromatic group may be a phenyl group. L ₁ and L ₂ are functional groups connecting Ar and X ₁ and X ₂ , respectively, L ₃ and L ₄ are functional groups connecting Ar and Y ₁ and Y ₂ , respectively, L ₁ , L ₂ , L ₃ , and L ₄ may be a bond or a C1 to C3 alkylene group regardless of each other. X ₁ or X ₂ may be more reactive than Y ₁ or Y ₂ . As an example, X ₁ or X ₂ may be O, and Y ₁ or Y ₂ may be S, Se, NH, or PH.

The organic precursor represented by Formula 1 may be any one of the following compounds (18) to (34) or a combination of two or more thereof.

The first barrier layer 140 may have a thickness of several to several tens of nm.

The first barrier layer 140 generated in this way may include at least one organic monolayer (X-R-Y). Also, when the barrier layer includes two or more organic monolayers X-R-Y, a metal atomic layer M disposed between the organic monolayers X-R-Y may be disposed. The metal atomic layer (M) may be, for example, aluminum or zinc, and the organic monolayer (X-R-Y) may be represented by Formula 2 below.

[Formula 2]

In Formula 2, Ar, X ₁ , X ₂ , Y ₁ , Y ₂ , L ₁ , L ₂ , L ₃ , L ₄ , a, b, c, and d are the same as defined in Formula 1 above. * means a bond or hydrogen with an element in the lower layer of the monomolecular layer, wherein the bond with an element in the lower layer of the monomolecular layer is one or more, and # means a bond or hydrogen with an element in the upper layer of the monomolecular layer, wherein There is more than one bond with an element in the upper layer of the monolayer. In addition, R in FIG. 3 may correspond to (L ₁ )(L ₂ )Ar(L ₃ )(L ₄ ) in Formula 2 above.

The material represented by Formula 2 may be any one of the following compounds (1) to (17) or a combination of two or more thereof.

Molecules represented by Chemical Formula 2 disposed adjacent to each other in the barrier layer 140 may be stabilized by π-π bonds between aromatic groups included in the adjacent molecules.

The method of forming the first barrier layer 140 is not limited thereto, and the first barrier layer 140 may be an organic layer, an inorganic layer, or another organic/inorganic composite layer.

First Te active layer forming step (S120)

The first Te active layer 150 may be formed by depositing a Te film of 3 to 10 nm, specifically 4 to 8 nm, more specifically 5 to 7 nm, on the first barrier layer 140 using an evaporation method. . When depositing the Te film, the temperature in the chamber may be 50 to 150 degrees.

Forming a second barrier layer (S130)

A second barrier layer 160 may be deposited on the first Te active layer 150 . The second barrier layer 160 and the first barrier layer 140 have a larger bandgap than the first Te active layer 150 , so that the first Te active layer 150 may have a quantum well structure. Since the second barrier layer 160 can be formed by the same method ( S110 ) as that of the first barrier layer 140 described above, a detailed description thereof will be omitted. However, the present invention is not limited thereto, and as will be described later with reference to FIG. 4 , the second barrier layer 160 includes the first Te active layer 150 and the second Te active layer 170 when a gate voltage is applied to the gate electrode. If it is an insulating layer capable of providing an appropriate voltage drop to have turn-on voltages distinct from each other, it may be an organic/inorganic composite layer different from that of the first barrier layer 140 , or may be an organic layer or an inorganic layer.

Forming a second Te active layer (S140)

A second Te active layer 170 may be deposited on the second barrier layer 160 . Since the second Te active layer can be formed by the same method ( S120 ) as the first Te active layer described above, a detailed description thereof will be omitted.

At least one of the Te active layers 150 and 170 according to an embodiment of the present invention has an amorphous region and a plurality of surrounded by the amorphous region, as confirmed in the TEM photograph of FIG. 13 . may be a film containing grains or crystalline regions of In other words, in the active layer, an amorphous region or a crystalline region in an amorphous matrix may be irregularly dispersed in an island shape. The crystalline region may have an approximately spherical shape. The amorphous region or both the amorphous matrix and the crystalline region may be Te, but only the atomic arrangement state may be different.

Each of the crystalline regions is a nanocrystal having a nano size, and may have a quantum confinement effect. Specifically, the crystalline region may have a size of several nm, for example, a diameter of 10 nm or less, and more specifically, a diameter of 3 to 8 nm, more specifically, 4 to 6 nm. In addition, the average spacing between the crystalline regions may also be several nm, but may be smaller than the diameter of the crystalline regions. Such a crystalline region may provide a quantum confinement effect in the in-plane X-axis direction and Y-axis direction, and in the thickness direction, that is, the Z-axis direction. In other words, the crystalline region and thus the Te active layer can provide a quantum confinement effect in the triaxial direction.

The crystalline regions may be arranged in a single layer (one layer) in the thickness direction of the active layers 150 and 170 or may be stacked in multiple layers.

The amorphous regions in the Te active layers 150 and 170 may have numerous localized states. Alternatively, the crystalline region in the Te active layer may have fewer discrete localized states than the localized states of the amorphous region. In this case, a specific energy state among the localized energy states of the amorphous region and a specific energy state among the localized energy states of the crystalline region may achieve resonant energy matching. Hybridization by the resonance energy matching may provide a quantized conduction state. The quantized conductive state may provide a discontinuous conductive state, and may also provide limited current movement in the quantized conductive state.

4 is a graph showing the transfer characteristics of the multi-level device described with reference to FIG. 1 . 5, 6, and 7 are cross-sectional views for explaining the characteristics of each operation step of the multi-level device described with reference to FIG. 1 . Except for the description below, reference will be made to the aforementioned parts.

4 and 5 , in a state in which the ground voltage V _S is applied to the source electrode 180 , the drain voltage V _D is applied to the drain electrode 185 and the first threshold voltage is applied to the gate electrode 120 . Alternatively, when a voltage less than or equal to the first turn-on voltage (V _th1 ) is applied, holes are sufficiently accumulated to form a channel in the first Te active layer 150 , so that the first Te active layer 150 . ) can be activated, that is, turn-on. Accordingly, a current I _D may flow between the source electrode 180 and the drain electrode 185 .

Specifically, in the source electrode 180 , holes pass through the second Te active layer 170 and tunnel the second barrier layer 160 , and then flow along the first Te active layer 150 . can Holes flowing through the first Te active layer 150 may tunnel through the second barrier layer 160 again and then pass through the second Te active layer 170 and be provided to the drain electrode 185 .

As the voltage applied to the gate electrode 120 gradually increases in a negative direction within the first gate voltage range R1 , the absolute value of the current flowing in the first Te active layer 150 may also increase. That is, a ratio of a current flowing through the active structure 135 to a change amount of the gate voltage within the first gate voltage range R1 , that is, a change amount of a current between the source/drain electrodes may have a first slope.

At this time, the second Te active layer 170 may be in an inactive, that is, a turn-off state, which means that the voltage applied to the gate electrode 120 within the first gate voltage range R1 is the first Te active layer. Shielding effect by the current flowing through 150, and/or reduced by a delay or voltage drop through the barrier layer 160, the actual strength of the voltage applied to the second Te active layer 170 is second This is because 2 Te is not sufficient to activate the active layer 170 . To this end, the barrier layer 160 may have an appropriate thickness and/or dielectric constant. The appropriate thickness of the barrier layer 160 may be affected by various parameters such as the voltage range applied to the gate electrode 120, but as an example, 5 to tens of nm, as an example 6 to 20 nm, 7 to 15 nm, or 8 to 12 nm.

4 and 6 , when the voltage applied to the gate electrode 120 further increases in the negative direction, the current flowing through the active structure 135, that is, the magnitude of the current flowing between the source/drain electrodes is the first The second slope may be changed to be smaller than the first slope in the gate voltage range R1 . This range will be referred to as a second gate voltage range R2, and a gate voltage when entering the second gate voltage range R2 will be referred to as a saturation voltage Vsat.

Specifically, the magnitude of the current flowing between the source/drain electrodes 180 and 185 within the second gate voltage range R2 may be substantially constant. That is, in one example, the second slope may be substantially zero. This means that, within the second gate voltage range R2, only the first Te active layer 150 may be in a turn-on state, and the second Te active layer 170 may be turned on by the shielding effect and/or voltage drop as described above. ) is a turn-off state, and may mean that the amount of current flowing through the first Te active layer 150 is almost saturated. That is, the second gate voltage range R2 may be understood as an intermediate voltage range in that the current remains almost constant even when the absolute value of the gate voltage increases.

4 and 7, when the voltage applied to the gate electrode 120 further increases in the negative direction and a voltage less than the second threshold voltage or the second turn-on voltage (V _th2 ) is applied, the As holes are sufficiently accumulated to form a channel in the second Te active layer 170 , the second Te active layer 170 may also be activated, that is, turn-on. That is, in a voltage range below the second turn-on voltage V _th2 , that is, within the third gate voltage range R3 , unlike the first and second gate voltage ranges R1 and R2 , the first and second Since both the Te active layers 150 and 170 are in an activated state, more current than the first gate voltage range R1 or the second gate voltage range R2 flows between the source and drain electrodes 180 and 185 can As the absolute value of the gate voltage increases within the third gate voltage range R3 , the absolute value of the current flowing between the source and drain electrodes 180 and 185 may increase with a third slope. That is, a ratio of an increase in current according to an increase in the gate voltage within the third gate voltage range R3 may increase with a third slope.

When a gate voltage in the third gate voltage range R3 is applied, as shown in FIG. 7 , the gate voltage reaches the second Te active layer 170 due to field penetration. Accordingly, the second active layer 170 may be turned on.

In summary, when a gate voltage in the first gate voltage range R1 is applied to the gate electrode 120 , only the first Te active layer 150 may be activated and the second Te active layer 170 may not be activated. there is. Subsequently, when a gate voltage of a second gate voltage range R2 larger than the first gate voltage range R2 is applied in a negative direction, the activation state of the first Te active layer 150 is maintained, but the current movement is saturated. state can be reached. Also, in this state, the second Te active layer 170 may still be in an inactive state. After that, when a gate voltage of a third gate voltage range R3 larger than the second gate voltage range R2 is applied in a negative direction, both the first and second Te active layers 150 and 170 may be activated. .

Accordingly, the multi-level device according to an embodiment of the present invention may have a plurality of turn-on voltages, that is, a threshold voltage, and thus may provide multi-level conductivity. Furthermore, the multi-level device according to an embodiment of the present invention may have a second gate voltage range that does not occur in a conventional device, that is, a range in which the magnitude of the current changes even when the gate voltage is increased. Conductivity can be stably provided. In other words, the first turn-on voltage by the first gate voltage range R1 and the second turn-on voltage by the third gate voltage range R3 can be clearly distinguished. Therefore, even if the operating margin of the gate voltage is widened, an error rate can be reduced.

To summarize the above, in the multilevel device according to an embodiment of the present invention, as shown in FIG. 4 , the second gate voltage range R2 in which the magnitude of the current does not change despite the sweep of the gate voltage. ) has That is, the second gate voltage range R2 may clearly distinguish the first and third gate voltage ranges from the first and third gate voltage ranges. This means that multi-level conductivity characteristics are stably provided by the second gate voltage range R2.

In an embodiment of the present invention, even if the gate voltage increases in the second gate voltage range R2, there may be little change in the magnitude of the current. Specifically, even when the magnitude change of the current is measured on a linear scale when the gate voltage is increased, the slope of the current magnitude with respect to the gate voltage may be zero. In this case, the multilevel conductivity characteristic can be provided very stably. As described above, the active layers 150 and 170 have nanocrystals dispersed in the microcrystalline matrix, and the nanocrystals provide a quantum confinement effect in the three-axis direction, and the amorphous matrix A specific energy state among the localized energy states of the nanocrystal and a specific energy state among the localized energy states of the nanocrystal achieve resonant energy matching with each other to achieve hybridization by the resonance energy matching. It was understood that the current movement in the active layers 150 and 170 is limited because a quantized conduction state is provided.

8 is a cross-sectional view showing a multi-level device according to another embodiment of the present invention, and FIG. 9 is a graph showing the transfer characteristics of the multi-level device according to FIG. 8 . The contents described above may be applied to the device according to the present embodiment, except for those described later.

8 and 9 , the multi-level device may further include a third barrier layer 172 on the second Te active layer 170 described with reference to FIG. 1 . In this case, the source and drain electrodes 180 and 185 may contact the third barrier layer 172 . In other words, the source and drain electrodes 180 and 185 are in contact with the first barrier layer 140 , the first Te active layer 150 , the second barrier layer 160 , and the second Te active layer 170 . may not

Since the source and drain electrodes 180 and 185 are in contact with the third barrier layer 172 , a first gate voltage range to a fourth gate voltage range R1 to R4 may be provided. That is, the second Te active layer 170 may also provide a quantum well having a conductivity state quantized by the second and third barrier layers 160 and 172 . Accordingly, even if the gate voltage increases in the negative direction in the fourth gate voltage range R4 , the current between the source and drain electrodes 180 and 185 may be constantly maintained.

10 is a cross-sectional view showing a multi-level device according to another embodiment of the present invention, and FIG. 11 is a graph showing the transfer characteristics of the multi-level device according to FIG. 10 . The contents described above may be applied to the device according to the present embodiment, except for those described later.

10 and 11 , the multilevel device may further include a third Te active layer 174 on the third barrier layer 172 described with reference to FIG. 8 . Also, the source and drain electrodes 180 and 185 may contact the third Te active layer 174 . That is, the source and drain electrodes 180 and 185 include a first barrier layer 140 , a first Te active layer 150 , a second barrier layer 160 , a second Te active layer 170 , and a third barrier layer. It may not be in contact with layer 172 . The first Te active layer 150 , the second Te active layer 170 , and furthermore the third Te active layer 170 may all be the same as the active layer described with reference to FIGS. 1 , 2 , and 3 .

In the present embodiment, since the third Te active layer 174 is additionally provided, the first gate voltage range to the fifth gate voltage range R1 to R5 may be provided. That is, in the second and fourth gate voltage ranges R2 and R4 , a saturation current due to a quantized conductivity state may occur, and in the fifth gate voltage range R5 , the third Te active layer 174 and The current may increase due to the contact of the source/drain electrodes 180 and 185 .

Hereinafter, a preferred experimental example (example) is presented to help the understanding of the present invention. However, the following experimental examples are only for helping understanding of the present invention, and the present invention is not limited by the following experimental examples.

Multilevel device manufacturing example 1

A 300 nm-thick silicon wafer was prepared as a substrate, and an aluminum gate electrode with a thickness of 70 nm was deposited on the silicon wafer using a hot vapor deposition method using a shadow mask.

As a gate insulating film on the gate electrode, aluminum oxide (Al ₂ O ₃ ) was deposited. Al ₂ O ₃ layer is an aluminum precursor triethylaluminum (trimethylaluminum (TMA), Aldrich, 97%) and a mixed gas providing step of argon as a carrier gas, a step of providing argon as a purge gas, H ₂ O as an oxidizing agent and a carrier gas A unit cycle including a step of providing a mixed gas of argon and a step of providing argon as a purge gas was repeatedly formed.

A first barrier layer was deposited on the Al ₂ O ₃ layer as the gate insulating layer. For this, a mixed gas of TMA source gas and argon is provided at a temperature of 20 degrees for 2 seconds, an argon purge gas is provided for 20 seconds, and a mixed gas of 4MP (4-mercaptophenol), an organic precursor, and argon, a carrier gas, is provided for 75 seconds for 20 seconds. An Al-DMP layer was deposited as a first barrier layer having a thickness of about 10 nm by performing a unit cycle of providing at a temperature of 10°C and providing an argon purge gas for 200 seconds 20 times.

A first Te active layer was formed by depositing a Te film of about 5 nm at about 80 degrees using an evaporation method on the first barrier layer. Thereafter, a second barrier layer is formed on the first Te active layer in the same manner as in the method of forming the first barrier layer, and then a second barrier layer is formed on the second barrier layer in the same manner as in the method of forming the first Te active layer. A Te active layer was formed.

Thereafter, nickel patterns having a thickness of 70 nm were formed by hot vapor deposition using a shadow mask to form source and drain electrodes.

Multilevel device manufacturing examples 2 to 4

The same method as in Multilevel Device Manufacturing Example 1 was followed except that the first Te active layer and the second Te active layer were formed to be 6 nm (Preparation Example 2), 7 nm (Preparation Example 3), or 8 nm (Preparation Example 4). was used to fabricate a multilevel device.

12 is an X-ray diffraction graph of a Te active layer formed to a thickness of 5 nm obtained during the process of Multilevel Device Manufacturing Example 1; The X-ray diffraction experiment was conducted using Smartlab (model name) of Rigaku Corporation, and GI-XRD analysis was used. was 3°/min, and the target was Cu-Kα (wavelength = 1.5405 Å 45 kV/200 mA).

12 , the Te active layer has a ratio of [100] peak intensity to [101] peak intensity, that is, I _[100]/[101] is 0.5 or more and less than 0.7 Specifically, 0.6 or more and less than 0.65 More specifically, 0.625 , and the [102] peak intensity was found to be more than twice the [110] peak intensity.

13 is a TEM (Transmission Electron Microscope) image of a cross-section of a Te active layer formed to a thickness of 8 nm obtained during the process of Multilevel Device Manufacturing Example 4;

Referring to FIG. 13 , it can be seen that the Te active layer has a thickness of about 8 nm, and crystal grains having a diameter of about 0.75 nm are arranged in a single layer in an amorphous Te matrix. At this time, it can be seen that the crystal grains have different crystal directions and do not form grain boundaries in contact with each other, so that an amorphous matrix exists between the crystal grains.

14 to 17 are ID-VG graphs illustrating transfer characteristics of multi-level devices manufactured according to manufacturing examples 1 to 4 of the multi-level device. 14 to 17 (a), the drain current ID is expressed on a linear scale, and in (b), the drain current ID is expressed on a logarithmic scale.

14 to 17 , it was confirmed that the multi-level devices manufactured according to Multi-level Device Manufacturing Examples 1 to 4 exhibited characteristics as shown in Table 1 below.

Te active layer thickness 1st Vth 2nd Vth intermediate
voltage range Preparation Example 1 5 nm -1.8 -8.0 -3.4 to -5.5 Preparation 2 6 nm -2.4 -10.5 -6.2 to -9.1 Preparation 3 7 nm -0.8 -7.8 -3.4 to -5.0 Preparation 4 8 nm - - -

14 to 17 and Table 1, in the case of the multi-level device according to the multi-level device manufacturing examples 1 to 3, when the drain current ID is expressed on a linear scale ( It can be seen that a)) also shows an intermediate voltage range in which there is little or no increase in the drain current between the first Vth and the second Vth.

However, it can be seen that when the thickness of the Te active layer is 8 nm, the drain current continuously increases between the first Vth and the second Vth, and thus a perfect intermediate voltage range is not obtained.

From these results, it can be seen that when the thickness of the Te active layer of the Te multilevel device is 5 to 7 nm, the device exhibits excellent multilevel characteristics in which different current levels are almost completely distinguished.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes are made by those skilled in the art within the technical spirit and scope of the present invention. This is possible.

Claims (13)

gate electrode;
a first Te active layer, a second Te active layer overlapping the gate electrode, and a barrier layer separating the first Te active layer and the second Te active layer; 2 Te active layer is an active structure that is a tellurium element layer; and
including source and drain electrodes electrically connected to both ends of the active structure, respectively;
A threshold voltage for forming a channel in the first Te active layer and a threshold voltage for forming a channel in the second Te active layer have different values. The method according to claim 1,
The first Te active layer and the second Te active layer have a thickness of 3 to 10 nm regardless of each other. 3. The method according to claim 2,
The first Te active layer and the second Te active layer have a thickness of 5 to 7 nm regardless of each other. The method according to claim 1,
At least one of the first Te active layer and the second Te active layer has nanocrystals dispersed in an amorphous matrix. 5. The method according to claim 4,
The nanocrystals are P-type multilevel devices having a diameter of 3 to 8 nm. 5. The method according to claim 4,
The spacing between the nanocrystals is a small P-type multi-level device compared to the diameter of the nanocrystals. 5. The method of claim 4,
The nanocrystals are arranged as a single layer in the first Te active layer or the second Te active layer in the thickness direction of the corresponding active layer. The method according to claim 1,
When the gate voltage applied to the gate electrode increases in a negative direction,
After a channel is formed in the first Te active layer,
Before a channel is formed in the second Te active layer,
A current flowing through the first Te active layer is saturated with a P-type multi-level device. The method according to claim 1,
When the gate voltage applied to the gate electrode increases in a negative direction,
A ratio of a current flowing through the active structure to the gate voltage is a first gate voltage range having a first slope, a second gate voltage range having a second slope lower than the first slope, and a third slope higher than the second slope A P-type multilevel device divided by a third gate voltage range having 10. The method of claim 9,
The second slope is 0 P-type multi-level device. The method according to claim 1,
The barrier layer is a first barrier layer,
The active structure further comprises a second barrier layer disposed between the gate electrode and the first Te active layer,
The first Te active layer is interposed between the first barrier layer and the second barrier layer to form a quantum well. The method according to claim 1,
The barrier layer is a P-type multilevel device having at least one organic monolayer. The method according to claim 1,
When the barrier layer includes two or more organic monolayers, the P-type multilevel device further comprising a metal atomic layer disposed between the organic monolayers.

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