KR20220056546A - Apparatus and method for producing an oxide layer in an oxide semiconductor - Google Patents

Abstract

The present invention relates to an oxide layer manufacturing apparatus. The oxide layer manufacturing apparatus manufactures an oxide layer in an oxide semiconductor including a substrate, an insulating layer on the substrate, an oxide layer on the insulating layer, and an upper electrode on the oxide layer. The oxide layer manufacturing apparatus includes: a gas storage unit which stores inert gas to be injected into a chamber; a holder for fixing the substrate on which the insulating layer is formed in the chamber; a gun which is spaced apart from the substrate in the chamber so as to fix a target made of an oxide; a vacuum pump for vacuuming the chamber; and an RF power generator for applying RF power to the gun, wherein the RF power generator generates plasma in the vacuum state of the chamber where the inert gas has been injected so that a material constituting the target is isolated through glow discharge to form an oxide thin film on the insulating layer. According to the present invention, an oxide semiconductor using indium-gallium-zinc oxide (IGZO) is manufactured on the oxide layer, thereby improving electrical characteristics.

Description

Apparatus and method for producing an oxide layer in an oxide semiconductor

The present invention is a resistive random access memory (resistive random access memory), non-volatile memory (non-volatile memory), next generation memory (next generation memory), memristor (memristor), multi-layer channel structure using a solution process IZO thin film fabrication (fabrication) of multi-layer channel structure IZO thin films using solution process), oxide resistance variable memory with high electrical and environmental stability, and oxide semiconductor.

Recently, research on oxide semiconductors to replace silicon-based semiconductor devices has been widely conducted. In terms of material, indium oxide (In ₂ O ₃ ), zinc oxide (ZnO), gallium oxide (Ga ₂ O ₃ ), indium zinc oxide (InZnO), zinc tin oxide (Zn), and indium gallium zinc oxide (InGaZnO) are based Research results on single, binary, and ternary compounds have been reported. On the other hand, in terms of the process, research on a liquid-phase-based process instead of the conventional vacuum deposition is in progress.

Oxide semiconductors show the same amorphous phase compared to hydrogenated amorphous silicon, but exhibit very good mobility, so they are suitable for high-definition liquid crystal displays (LCDs) and active organic light-emitting diodes (AMOLEDs). In addition, the oxide semiconductor manufacturing technology using the liquid phase-based process has an advantage of low cost compared to the high-cost vacuum deposition method.

In the conventional memory structure, TiO _{2 -x} implements a switching operation using oxygen vacancy serving as a carrier, but generation/recombination between oxygen vacancies in the movement process. There is a problem in that the endurance characteristic of the memory is deteriorated due to the occurrence of a carrier trap, a decrease in an on/off ratio, and a decrease in electron mobility. In addition, in the conventional memory, an oxide layer has a problem that a root-mean square (RMS) value is high and defects on the surface exist.

Republic of Korea Patent Publication 10-2008-0082616

The present invention has been devised to solve the above problems, and electron movement of IGZO (Indium-Gallium-Zinc oxide) occurs through ns-orbital, and fast electron mobility can be obtained even in an amorphous state. As an electronic material for resistive random access memory (ReRAM) that can overcome the disadvantages of TiO _{2 -x} , since excellent resistance switching characteristics of the memory can be implemented, an apparatus and method for manufacturing an oxide layer are provided. but it has a purpose.

In addition, another object of the present invention is to fabricate an oxide semiconductor in which IGZO is deposited through an RF magnetron sputtering system.

Objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

The present invention for achieving the above object relates to an apparatus for manufacturing an oxide layer, comprising a substrate, an insulating layer formed on the substrate, an oxide layer formed on the insulating layer, and an upper electrode formed on the oxide layer In an apparatus for manufacturing an oxide layer in an oxide semiconductor comprising: a gas storage unit storing an inert gas for injection into a chamber; A gun for fixing a target made of oxide by being located in a gun, a vacuum pump for making the chamber into a vacuum state, and a plasma generated in a vacuum state in which an inert gas is injected into the chamber, the target through glow discharge and an RF power generator for applying RF power to the gun so that a constituent material is peeled off to form an oxide thin film on the insulating layer.

The target may be an Indium-Gallium-Zinc oxide (IGZO) target having an In ₂ O ₃ :Ga ₂ O ₃ :ZnO composition ratio of 1:1:1 mol.%.

The holder may have a structure capable of rotating the substrate at a constant speed so that the oxide thin film is uniformly deposited.

In the method for manufacturing an oxide layer of the present invention, a holder for fixing a substrate on which an insulating layer is formed, and a gun positioned at a distance from the substrate to fix a target made of an oxide in a vacuum state Injecting an inert gas into the chamber, applying RF power to the gun through an RF power generator to generate plasma, and materials constituting the target are separated through glow discharge to form an oxide thin film on the insulating layer including the steps of

The target may be an Indium-Gallium-Zinc oxide (IGZO) target having an In ₂ O ₃ :Ga ₂ O ₃ :ZnO composition ratio of 1:1:1 mol.%.

The holder may rotate the substrate at a constant speed so that the oxide thin film is uniformly deposited.

According to the present invention, by producing an oxide semiconductor using IGZO (Indium-Gallium-Zinc oxide) as an oxide layer, there is an effect that can improve electrical properties.

1 is a diagram illustrating symbols and structures of an oxide semiconductor according to an embodiment of the present invention.
2 is a view showing the configuration of an oxide layer manufacturing apparatus according to an embodiment of the present invention.
3 is a flowchart illustrating a method for manufacturing an oxide layer according to an embodiment of the present invention.
4 is a schematic diagram of a TiO _2-x TFT and an IGZO TFT formed in a top contact-bottom gate structure.
FIG. 5 is a graph illustrating transfer curves of the TiO _{2 -x} TFT and the IGZO TFT of FIG. 4 .
6 is a representation of the overall driving mechanism of the IGZO / TiO ₂ based oxide semiconductor.
Figure 7 is a graph showing the results of measuring the electrical performance of the IGZO / TiO ₂ based oxide semiconductor that was subjected to post heat treatment at 200, 300, 400, and 500 ℃ after depositing the IGZO layer, respectively.
8 is a graph showing the results of analyzing the O1s peak in the surface after depositing the IGZO layer at 200, 300, 400, and 500 ° C, respectively, by x-ray photoelectron spectroscopy (XPS). .
9 shows an image measured using a scanning electron microscope (SEM) to analyze the surface area performance of the IGZO layer after the IGZO layer was subsequently subjected to post heat treatment at 200, 300, 400, and 500 ° C., respectively. .
Figure 10 shows a schematic diagram and energy band implementing the electron transfer mechanism in the MIOS structure in order to analyze the effect of heat treatment after proceeding to the IGZO layer.
11 is a graph showing the measurement results of the CV curve (curve) of the IGZO / TiO ₂ based oxide semiconductor that was subjected to post heat treatment at 200, 300, 400, and 500 ℃ after depositing the IGZO layer, respectively.

Advantages and features of the embodiments disclosed herein, and methods for achieving them will become apparent with reference to the embodiments described below in conjunction with the accompanying drawings. However, the embodiments to be proposed in the present disclosure are not limited to the embodiments disclosed below, but may be implemented in various different forms, and only the present embodiments are provided to those of ordinary skill in the art. It is only provided to be a complete indication of the category.

Terms used in this specification will be briefly described, and the disclosed embodiments will be described in detail.

Terms used in this specification have been selected as currently widely used general terms as possible in consideration of the functions of the disclosed embodiments, but may vary according to intentions or precedents of those of ordinary skill in the art, the emergence of new technologies, and the like. In addition, in a specific case, there is a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the detailed description part of the corresponding specification. Therefore, the terms used in the present disclosure should be defined based on the meaning of the term and the contents of the entire specification, rather than the simple name of the term.

References in the singular herein include plural expressions unless the context clearly dictates the singular.

In the entire specification, when a part "includes" a certain element, this means that other elements may be further included, rather than excluding other elements, unless otherwise stated. Also, as used herein, the term “unit” refers to a hardware component such as software, FPGA, or ASIC, and “unit” performs certain roles. However, "part" is not meant to be limited to software or hardware. A “unit” may be configured to reside on an addressable storage medium and may be configured to refresh one or more processors. Thus, by way of example, “part” includes components such as software components, object-oriented software components, class components and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays and variables. The functionality provided within components and “parts” may be combined into a smaller number of components and “parts” or further divided into additional components and “parts”.

In addition, in the description with reference to the accompanying drawings, the same components are given the same reference numerals regardless of the reference numerals, and the overlapping description thereof will be omitted. In describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a diagram illustrating symbols and structures of an oxide semiconductor according to an embodiment of the present invention.

In FIG. 1, (a) is an electrical symbol indicating that it is a nonlinear passive device related to the coupling between electric charge and magnetic flux, and (b) is a schematic diagram of an oxide semiconductor structure based on MoW/IGZO/TiO ₂ /Si(MIOS) .

Referring to FIG. 1 , the oxide semiconductor of the present invention includes a substrate 110 , an oxide layer 120 , an insulating layer 130 , and a top electrode 140 .

In an embodiment of the present invention, the substrate 110 may be implemented as an N-type heavily doped silicon (Si) substrate, and may function as a lower electrode.

The insulating layer 120 is formed on the substrate 110 and may be made of TiO ₂ (Titanium dioxide).

The oxide layer 130 is formed on the insulating layer 120 and may be formed of an amorphous oxide thin film. In an embodiment of the present invention, the oxide layer 130 may be formed of an Indium-Gallium-Zinc oxide (IGZO) thin film.

The upper electrode 140 is formed on the oxide layer 130 and may be made of MoW (Molybdenum tungsten).

2 is a view showing the configuration of an oxide layer manufacturing apparatus according to an embodiment of the present invention.

Referring to FIG. 2 , the oxide layer manufacturing apparatus of the present invention includes a gas storage unit 210 , a holder 220 , a gun 230 , an RF power generator 240 , and a vacuum pump. (vacuum pump) 250 .

The gas storage unit 210 stores an inert gas to be injected into the chamber 10 . In an embodiment of the present invention, the inert gas may be argon (Ar).

The holder 220 serves to fix the substrate 110 on which the insulating layer 120 is formed in the chamber 10 .

The gun 230 is positioned in the chamber 10 at a distance from the substrate 110 to fix the target 20 made of oxide.

The RF power generator 240 generates plasma in a vacuum state in which an inert gas is injected into the chamber 10 , and the material constituting the target 20 is separated off through a glow discharge and on the insulating layer 120 . RF power is applied to the gun 230 to form an oxide thin film on the .

The vacuum pump 250 is a pump for making the chamber 10 into a vacuum state.

The target 20 may be an Indium-Gallium-Zinc oxide (IGZO) target having an In ₂ O ₃ :Ga ₂ O ₃ :ZnO composition ratio of 1:1:1 mol.%.

In an embodiment of the present invention, the holder 220 may be implemented in a structure capable of rotating the substrate 110 at a constant speed so that the oxide thin film is uniformly deposited.

3 is a flowchart illustrating a method for manufacturing an oxide layer according to an embodiment of the present invention.

Referring to FIG. 3 , a holder 220 for fixing the substrate 110 on which the insulating layer 120 is formed, and a gun for fixing the target 20 made of oxide located at a distance from the substrate 110 . An inert gas is injected into the chamber 10 in a vacuum state having a (gun) 230 ( S310 ).

Then, RF power is applied to the gun 230 through the RF power generator 240 to generate plasma (S320).

Then, the material constituting the target 20 is peeled off through the glow discharge to form an oxide thin film on the insulating layer 120 ( S330 ).

The target 20 may be an Indium-Gallium-Zinc oxide (IGZO) target having an In ₂ O ₃ :Ga ₂ O ₃ :ZnO composition ratio of 1:1:1 mol.%.

In an embodiment of the present invention, the holder 220 may be implemented in a structure capable of rotating the substrate 110 at a constant speed so that the oxide thin film is uniformly deposited.

The actual manufacturing process and experimental process of the oxide semiconductor having the amorphous oxide thin film in the present invention are exemplified as follows.

In the embodiment of the present invention, a heavily doped n-type silicon (Si) wafer was used as the substrate 110 of the oxide semiconductor, and a thickness of 600 μm was implemented.

SPM (sulfuric acid hydrogen peroxide mixture solution) cleaning (Sulfuric acid hydrogen peroxide mixture solution) for 20 minutes at a temperature of 60 °C with H ₂ SO ₄ and H ₂ O ₂ in a 3:1 ratio to remove organic and inorganic impurities on the surface of the substrate 110 cleaning) was performed, and the sample was immersed in deionized water and IPA (acetone, isopropyl alcohol) solution for 20 minutes each, and after ultra-sonication was completed, a vacuum oven dried for 1 hour.

To fabricate the insulating layer 120 on the substrate 110 , TiO ₂ (Titanium dioxide) was deposited using an atomic layer deposition (ALD) system of NCD (LUCIA D100). ALD cycle (cycle) starts by injecting titanium tetraisopropoxide as a precursor of Ti, injecting N ₂ purge gas for 10 seconds, injecting H ₂ O for 1 second, and then injecting again for 10 seconds During the N ₂ purge gas injection process was set as 1 cycle, and a total of 1,000 cycles were repeated with 0.2 Å deposition per cycle to form a TiO ₂ thin film with a thickness of 20 nm.

Then, in order to form an IGZO (Indium-Gallium-Zinc oxide) channel layer that is an oxide layer 130 on the TiO ₂ insulating layer after the SPM cleaning, a sputtering process using an RF magnetron sputtering system proceeded. As a target, an IGZO (In ₂ O ₃ :Ga ₂ O ₃ :ZnO) target having a diameter of 3 inches and a ratio of 1:1:1 was used, and the distance between the target and the substrate was set to 8 cm.

And, to remove impurities in the chamber, the initial vacuum degree in the chamber was set to 3 × 10 ^-6 torr or less using a rotary pump and TMP, and then 30 sccm of Ar gas was injected into the chamber. The vacuum degree was maintained at 1.5 × 10 ^-2 torr.

Then, the substrate was rotated at a speed of 7 rpm for uniform deposition of the thin film, and the RF power of the RF power generator was applied to 150 W to generate plasma to form a 20 nm IGZO channel layer. deposited.

Thereafter, the temperature of the furnace was evaluated to confirm the temperature for optimizing the properties of the IGZO-based oxide semiconductor, and heat treatment was performed in the range of about 200, 300, 400, and 500 ° C. for about 1 hour, respectively. was analyzed.

After the heat treatment, in order to form the upper electrode 140, a source/drain electrode of MoW (Molybdenum tungsten) was deposited using a DC magnetron sputtering system. In order to generate a vacuum plasma in the chamber, DC 150 W was applied to a DC power supply to deposit a MoW source/drain electrode of 100 nm for 10 minutes. The horizontal and vertical lengths of the formed MoW upper electrode have a square shape of 100 × 100 μm, respectively, and four oxide semiconductor devices are disposed on one wafer, respectively.

The IV curve was measured to determine the electrical performance of the finally fabricated IGZO/TiO ₂ oxide semiconductor. In addition, in order to confirm the optimum post-heat treatment temperature of IGZO oxide semiconductors applicable to oxide semiconductors, the memory characteristics were confirmed through composition and surface analysis and CV measurement.

4 is a simplified schematic diagram of a TiO _2-x TFT and an IGZO TFT formed in a top contact-bottom gate structure, (a) is a schematic diagram of a TiO _{2 -x} TFT, (b) is It is a schematic diagram of IGZO TFT.

In FIG. 4, a heavily doped n-type Si wafer having a thickness of 600 μm was used as a substrate and a lower gate electrode, and each TFT was made of 100 nm thick SiO ₂ as an insulating film. was used. TiO _{2 -x} has a thickness of 30 nm, and after deposition through ALD, rapid thermal annealing was performed at 700° C. for 5 minutes. The thickness of a-IGZO was 50 nm, and after deposition through an RF magnetron sputtering system, heat treatment was performed in a furnace at 350° C. for 1 hour. Each electrode is identical to 100 nm thick Al, and the length of the channel is 200 μm and the width is 2,000 μm.

FIG. 5 is a graph illustrating transfer curves of the TiO _{2 -x} TFT and the IGZO TFT of FIG. 4 .

In the experiment of FIG. 5 , each source-drain voltage (V _ds ) was fixed to 30 V and a bias voltage was applied, and the gate voltage (V _gs ) was increased to 10 to 30 V. The source-drain current (I _ds ) when the step was set to 0.2 V and applied was investigated.

Referring to FIG. 5 , the electron mobility of the IGZO TFT is 11.02 cm ² /Vs, which is very good compared to the TiO _{2 -x} TFT, which is 0.15 cm ² /Vs.

In addition, it can be seen that the on/off current ratio values are 6.2 × 10 ⁶ and 7.2 × 10 ³ , respectively, showing a large difference. The off current level of a-IGZO TFT is about 1.0 × 10 ^-10 , similar to TiO _{2 -x} TFT, but the on current level is about 1.0 × 10 ^-3 , 7.0 × 10 ^- Compared to the TiO _{2 -x} TFT having ⁷ , it is expected that the high resistance state (HRS) and low resistance state (LRS) characteristics of the oxide semiconductor will be excellent.

6 is a representation of the overall driving mechanism of the IGZO / TiO ₂ based oxide semiconductor.

In FIG. 6, a heavily doped n-type Si wafer substrate was used as a lower electrode as the measurement standard of the oxide semiconductor, and a voltage was applied to the MoW electrode, which is the upper electrode, of the a-IGZO oxide semiconductor. operation was confirmed.

Referring to FIG. 6 , first, when a (+) voltage is applied to the IGZO oxide active layer as a positive bias region, the current maintains a low value and rapidly increases when it becomes a specific threshold voltage, this process It is called SET operation.

Conversely, when a voltage is applied from the positive bias region to the negative bias region, the state of the device reaches the ( ) threshold voltage and the current value rapidly decreases. This process is called a RESET operation.

When the oxide semiconductor performs this process and the state of the IGZO thin film reaches a (+) threshold voltage, a filament is formed and a conducting pathway is created. However, when a voltage ( ) is applied, the oxygen trap of the TiO ₂ insulating layer prevents electron movement, thereby causing rupture of the filament. Through this process, the resistance state changes according to the applied bias and induces a hysteresis phenomenon to drive the IGZO/TiO ₂ oxide semiconductor.

Figure 7 is a graph showing the results of measuring the electrical performance of the IGZO / TiO ₂ based oxide semiconductor that was subjected to post heat treatment at 200, 300, 400, and 500 ℃ after depositing the IGZO layer, respectively.

In FIG. 7 , a KEITHLEY model name SYSTEM 4200 source meter was used as a measuring device, and the I-V curve when 2 to 4 V was applied was confirmed.

In the case of Figure 7 (a), it is an I-V curve of the oxide semiconductor subjected to post heat treatment in the range of 200 ° C. HRS is shown at 0 ~ 4 V, and then about 2.83 × 10 -4 A at 4 V, which is a reverse sweep. Record the current value of , and the state transitions to LRS. In addition, it can be seen that the oxide semiconductor that has reached the write state is applied up to 2 V, then changes to HRS again and is converted to the erase state.

7 (b) is an IV curve of an oxide semiconductor subjected to post-heat treatment at 300° C., and a current value of about 9.82 × 10 ⁻⁴ at 4 V was confirmed.

7 (c) is an IV curve of the oxide semiconductor subjected to post heat treatment at 400 °C, and FIG. 7 (d) is an IV curve of the oxide semiconductor subjected to post heat treatment at 500 ° C. The IV curve is the compliance It reached the set current value of 1.00 × 10 ^-3 .

In addition, it was confirmed that hysteresis characteristics were realized due to an increase in a current level according to an increase in the post-heat treatment temperature of the oxide semiconductor.

In (a), the oxide semiconductor subjected to post-heat treatment at 200 ° C does not show a perfect hysteresis curve in the (+) region, and in (b) at 300 ° C, it shows a small hysteresis form. there is.

On the other hand, when the temperature of the post heat treatment in (c) is 400 °C, the best form of hysteresis can be confirmed. However, in (d), the I-V curve of the oxide semiconductor that was post-annealed at 500 °C reached the compliance current value, but as the off current level increased, the gap between HRS and LRS decreased and the hysteresis characteristics decreased.

That is, in the low post-annealing temperature range, electrons are trapped due to defects and interfacial resistance of the IGZO thin film surface, and as the carrier concentration increases through a decrease in trap density as the temperature increases, the memory characteristics are improved. improvement was confirmed. Therefore, when the post heat treatment temperature of the IGZO oxide active layer deposited at a low temperature by RF magnetron sputtering was performed at 400 °C, the optimum characteristics as an oxide semiconductor were confirmed through reduction of carrier concentration and electron trap density. On the other hand, it seems that the hysteresis characteristic decreased due to the unstable state in which crystals were partially formed in the IGZO thin film when heat treated at 500 °C or higher.

8 is a graph showing the results of analyzing the O1s peak in the surface after depositing the IGZO layer at 200, 300, 400, and 500 ° C, respectively, by x-ray photoelectron spectroscopy (XPS). .

In Fig. 8, (a) is 200 ℃, (b) is 300 ℃, (c) is 400 ℃, (d) is 500 ℃ the O1s peak in the surface after heat treatment at 500 ℃ XPS (x-ray) It is a graph showing the analysis result by photoelectron spectroscopy, and (e) is a bar graph showing the O1s peak in the surface after heat treatment at 200, 300, 400, and 500 °C.

Referring to FIG. 8, as shown in (c) and (e), when post-heat treatment was performed at 400 °C, the temperature condition with the best electrical performance results, the specific gravity of the oxygen vacancy peak (O ₁ ) in the O1s peak was It is the largest at about 78.2%, and the specific gravity of the hydroxide peak (O ₃ ) is the smallest at about 2.6%.

On the other hand, referring to FIGS. 8 (a) and (e), the component of the IGZO thin film subjected to post-heat treatment at 200 ° C. has an O ₁ specific gravity of about 53.0% and an O ³ specific gravity of about 11.6% in the entire O1s peak. there is. Then, looking at Figure 6(b), (e), the component of the IGZO thin film subjected to post-heat treatment at 300 °C has a specific gravity of about 49.0% at the O1s peak, and compared to the condition of 200 °C, the specific gravity _{of O 1 is} about It decreased slightly from 53.0% to 49.0%, and the specific gravity of O ₃ increased from about 11.6% to about 14.5%.

As such, when the O ₁ peak is small and the O ₃ peak is large, oxygen vacancies remain without sufficiently recovering the metal-oxygen bond, and the overall electrical performance of the oxide semiconductor decreases due to an increase in leakage current. will do In addition, when the O ₃ peak increases, hydrogen ions bind to oxygen vacancies and the number of oxygen traps that are relatively strongly bonded to hydrogen increases, and the interfacial trap charge phenomenon that prevents the movement of electrons occurs more. This contributes to the generation of leakage current and causes the electron mobility of the memory device to decrease, and consequently, the electrical performance of the oxide semiconductor is reduced.

On the other hand, as shown in FIGS. 8 (d) and (e), when the post-heat treatment temperature was increased to 500 °C, the specific gravity of O ₁ in the _O1s peak of the component of the IGZO thin film was greatly reduced to about 52.7%, and the The specific gravity increased again to about 11.2%. In this way, when the specific gravity of O ₁ decreases and the specific gravity of O ₃ increases, the oxygen separated from the metal-oxygen bond rapidly diffuses to the outside of the thin film with a relatively low concentration, which causes a decrease in the electrical performance of the oxide semiconductor. do. As a result, this was the same as the electrical test result proving that the post-heat treatment temperature was 400 °C is the optimal condition, and it can be a basis for supporting this.

9 shows an image measured using a scanning electron microscope (SEM) to analyze the surface area performance of the IGZO layer after the IGZO layer was subsequently subjected to post heat treatment at 200, 300, 400, and 500 ° C., respectively. .

9 is an electron high tension (electron high tension) 1.0 kV, I probe using a scanning electron microscope (SEM) to analyze the performance of the IGZO surface area subjected to post heat treatment at 200, 300, 400, and 500 ° C, respectively; (probe) is set to 1.0 nA, working distance (working distance) is set to 2.5 mm shows the image measured.

As shown in Fig. 9 (a)-(c), as the post heat treatment temperature from 200 to 400 ° C. gradually increases, the grain boundary of small elliptical grains takes on an arbitrary curved shape and gradually increases. . However, as shown in (d), in the case of post-heat treatment at 500 °C, it can be confirmed that large-sized grains and small-sized grains coexist within one surface, and secondary recrystallization (secondary recrystallization) ) is confirmed. This refers to a phenomenon in which certain grains are rapidly coarsened during the growth process of grains compared to others, especially when there are many impurities in the surface or crystallization is very large. becomes this

In addition, as the post heat treatment temperature increases, the grain boundary becomes more distinct, and in the case of the a-IGZO thin film subjected to post heat treatment at 500 ° C, many hillocks are observed on the surface of the thin film. This is because the degree of relaxation of the compressive stress received by the IGZO thin film is increased due to the high post-heat treatment at 500 ° C. seems to be Therefore, in the IGZO thin film subjected to post heat treatment at 500 °C, many large and small hillocks were generated, so the surface roughness was also greatly reduced. The greater the roughness of the oxide semiconductor surface, the greater the current leakage due to the interface trap charge that prevents the movement of electrons, which greatly adversely affects the overall electrical characteristics of the device. As a result, after depositing the IGZO oxide semiconductor layer, if the post heat treatment temperature is too high, such as 500 ° C, a deteriorated surface condition can be confirmed. It can be seen that the influence

Figure 10 shows a schematic diagram and energy band implementing the electron transfer mechanism in the MIOS structure in order to analyze the effect of heat treatment after proceeding to the IGZO layer.

Figure 10 (a) is a schematic diagram implementing the electron transfer mechanism in the MIOS structure in order to analyze the effect of the post-heat treatment proceeded to IGZO. The magnitude and direction of the current in the C-V characteristics of the oxide semiconductor subjected to post-IGZO heat treatment greatly depend on the state of the active layer. In general, in a metal-insulator-metal (MIM) device, electrons injected from the upper/lower metal electrode to the interface of the insulating layer flow in both directions, and the direction is determined by the applied bias voltage. However, the MIOS device flows unidirectionally from the metal to which a positive bias voltage is applied toward the IGZO active layer.

First, by a positive voltage applied to the upper MoW metal electrode, the IGZO active layer moves the injected electrons to create an electron movement path, and a-IGZO/TiO ₂ Through the area where electrons are accumulated from the contact interface (accumulation) electrons are injected The injected electrons drive the memory by forming a filament by the conductivity of the lower electrode. Conversely, when a negative bias voltage is applied to the upper electrode, electrons transferred from the lower electrode by the TiO ₂ insulating film move by an electron depletion region acting as a capacitor at the TiO ₂ /SiO ₂ interface. The path is blocked. Therefore, little current flows and is rectified in a negative bias, so that the TiO ₂ /IGZO filament is ruptured.

FIG. 10 (b) is an energy band expressing electron movement due to excited electrons when a positive bias and a negative bias are respectively applied to the upper electrode in the MIOS structure.

In FIG. 10(b) , electrons and holes are changed to an excited state by a voltage applied to the upper electrode, and the electrons or holes changed to an excited state have energy to pass through the TiO ₂ insulating film (tunneling).

11 is a graph showing the measurement results of the CV curve (curve) of the IGZO / TiO ₂ based oxide semiconductor that was subjected to post heat treatment at 200, 300, 400, and 500 ℃ after depositing the IGZO layer, respectively.

11 is after depositing the IGZO oxide semiconductor layer (a) 200, (b) 300, (c) 400, (d) 500 ℃ after depositing the IGZO / TiO ₂ based on the oxide semiconductor subjected to post heat treatment 0.1 seconds This is the result of measuring the CV curve in the range of 2 to 4 V at intervals.

In FIG. 11, the frequency was maintained at 1 kHz, and for the applied voltage, the y-axis represents the C/Cmax value obtained by dividing the capacitance value by the largest value.

As shown in FIG. 11 (a), the oxide semiconductor subjected to post-heat treatment at 200° C. has a C/Cmax value of about 0.91 in the inverted inversion region, but about 0.99 in the accumulation region, which is very fine. You can see the difference.

In addition, in the case of the oxide semiconductor in which the post-heat treatment was performed at 300° C. in FIG. 11 (b) and in the case of the oxide semiconductor in which the post-heat treatment was performed at 500° C. in FIG. 11 (d), the C/C max value in the inversion region is about 0.90, and in the accumulation area, it is about 0.98, which is not significantly different from the case of post-heat treatment at 200 °C.

11 (a), (b), and (d), due to the lack of post-heat treatment, it has characteristics similar to that of an insulating film at low temperatures and conductors at high temperatures, and it can be seen that MIM has similar characteristics.

However, as shown in FIG. 11(c), in the case of the oxide semiconductor subjected to post-heat treatment at 400° C., when 2 to 0 V is applied to the upper MoW electrode, the C/Cmax value is about 0.45, and the current state is inversion. ) can be confirmed. At this time, the electric field passing through the oxide layer becomes large enough to attract minority carriers to the semiconductor surface, and the electron concentration on the semiconductor surface is kept relatively constant because it does not respond to a high-frequency signal.

After that, when 0 to 2 V is applied, since the applied voltage increases from () to (+), the energy of electrons in the MoW electrode is lowered, and (+) charges are collected at the interface between the electrode and the oxide. Accordingly, corresponding () charges gather near the interface between the semiconductor and the oxide to drive out holes or recombine, and the interface becomes a depletion region, a depletion state where there are no carriers.

When 2 to 4 V is applied, the C/Cmax value is about 0.98, and electrons are collected at the interface between the metal and the oxide semiconductor layer, reaching an accumulation region where the capacitance value increases. In conclusion, it can be confirmed that the memory characteristics are optimized through the C-V value when the MoW electrode of the IGZO-based oxide semiconductor subjected to the post heat treatment at 400 °C is applied with a positive bias voltage and a negative bias voltage, respectively.

The present invention has been described above using several preferred embodiments, but these embodiments are illustrative and not restrictive. Those of ordinary skill in the art to which the present invention pertains will understand that various changes and modifications can be made without departing from the spirit of the present invention and the scope of the rights set forth in the appended claims.

110 Substrate 120 Insulation Layer
130 oxide layer 140 top electrode

Claims (6)

An apparatus for manufacturing an oxide layer in an oxide semiconductor comprising a substrate, an insulating layer formed on the substrate, an oxide layer formed on the insulating layer, and an upper electrode formed on the oxide layer,
a gas storage unit storing an inert gas for injection into the chamber;
a holder for fixing a substrate on which an insulating layer is formed in the chamber;
a gun positioned in the chamber at a distance from the substrate to fix a target made of oxide;
a vacuum pump for creating a vacuum state of the chamber; and
RF for applying RF power to the gun so that a plasma is generated in a vacuum state in which an inert gas is injected into the chamber, and a material constituting the target is separated through a glow discharge to form an oxide thin film on the insulating layer power generator
Oxide layer manufacturing apparatus comprising a.
The method according to claim 1,
The target is an Indium-Gallium-Zinc oxide (IGZO) target having a composition ratio of In ₂ O ₃ :Ga ₂ O ₃ :ZnO of 1:1:1 mol.%.
The method according to claim 1,
The holder is an oxide layer manufacturing apparatus, characterized in that it has a structure capable of rotating the substrate at a constant speed so that the oxide thin film is uniformly deposited.
A method for manufacturing an oxide layer in an oxide semiconductor comprising a substrate, an insulating layer formed on the substrate, an oxide layer formed on the insulating layer, and an upper electrode formed on the oxide layer,
injecting an inert gas into a chamber in a vacuum state having a holder for fixing a substrate on which an insulating layer is formed, and a gun positioned at a distance from the substrate to fix a target made of oxide;
generating plasma by applying RF power to the gun through an RF power generator; and
Forming an oxide thin film on the insulating layer by peeling off a material constituting the target through a glow discharge
An oxide layer manufacturing method comprising a.
5. The method according to claim 4,
The target is an In ₂ O ₃ :Ga ₂ O ₃ :ZnO composition ratio of 1:1:1 mol.% of an IGZO (Indium-Gallium-Zinc oxide) target, characterized in that the oxide layer manufacturing method.
5. The method according to claim 4,
The holder is an oxide layer manufacturing method, characterized in that it has a structure capable of rotating the substrate at a constant speed so that the oxide thin film is uniformly deposited.

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