KR20220030683A - Integrated Circuit and Display Device including the same - Google Patents

Abstract

The present invention provides a display device, which includes: a display panel for displaying an image; a shift register which supplies a scan signal to the display panel; and a level shifter which outputs signals necessary for driving the shift register. The level shifter includes: a circuit driver for outputting the signals; and an inspection driver which outputs a test result signal which can determine whether its own output terminals are normally connected to signal pads of the external substrate through a test result terminal based on a test signal. Accordingly, there is an effect of minimizing configuration required for inspection and reducing cost.

Description

Integrated Circuit and Display Device including the same

The present invention relates to an integrated circuit and a display device including the same.

With the development of information technology, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as a light emitting display device (LED), a quantum dot display device (QDD), and a liquid crystal display device (LCD) is increasing.

The display devices described above include a display panel including sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit, and the like.

In the above display devices, when a driving signal, for example, a scan signal and a data signal, is supplied to the sub-pixels formed on the display panel, the selected sub-pixel transmits light or directly emits light to display an image.

The present invention can improve the inspection speed by configuring a device capable of inspecting the connection state between the integrated circuit and the external substrate inside the integrated circuit, as well as reducing the number of test points for inspection on the external substrate to be integrated on the external substrate. It is to reduce the area occupied by the components related to the inspection of the circuit.

The present invention provides a display panel for displaying an image; and a shift register for supplying a scan signal to the display panel and a level shifter for outputting signals necessary for driving the shift register, wherein the level shifter includes a circuit driver outputting the signals; It is possible to provide a display device including a test driver that outputs a test result signal capable of determining whether the output terminals are normally connected to the signal pads of an external substrate through the test result terminal.

When the test signal is applied, the test driver may detect a voltage value through the output terminals of the level shifter, and prepare the test result signal based on a result of comparing the detected voltage value with an internal reference value.

The test result signal may be generated as a logic low or a logic high.

The test driver includes voltage detectors respectively connected to the output terminals of the level shifter, respectively detecting voltage values from the output terminals of the level shifter, comparing the detected voltage values with an internal reference value, and then generating the result values. It may include voltage comparators each outputting, and a result output circuit unit for collecting the result values output from the voltage comparators to prepare the test result signal and outputting the result through the test result terminal.

The test driver may further include a selection signal output unit for generating a selection signal for selecting at least one of the voltage detection units.

The voltage detectors include a test transistor having a first electrode connected to an output terminal of the level shifter and a gate electrode connected to the selection signal output part, one end connected to a second electrode of the test transistor, and the other end connected to a reference voltage terminal Each of the connected test resistors may be included, and a voltage value may be output through a second electrode of the test transistor and a feedback node that is one end of the test resistor.

The result output circuit unit may perform an AND operation on the result values output from the voltage comparators to output only one test result signal.

In another aspect, the present invention provides a circuit driver for generating and outputting signals necessary for driving a device; and a test driver for outputting a test result signal capable of determining whether its output terminals are normally connected to the signal pads of the external board through the test result terminal based on the test signal. there is.

The test driver includes voltage detectors respectively connected to the output terminals of the integrated circuit and respectively detecting voltage values from the output terminals of the integrated circuit, and compares the detected voltage values with an internal reference value and outputs the result values It may include voltage comparators each outputting, and a result output circuit unit for collecting the result values output from the voltage comparators to prepare the test result signal and outputting the result through the test result terminal.

The voltage detection units include a test transistor having a first electrode connected to an output terminal of the integrated circuit and a gate electrode connected to the selection signal output unit, and one end connected to a second electrode of the test transistor and the other end connected to a reference voltage terminal. Each of the connected test resistors may be included, and the detected voltage value may be output through the output terminal of the integrated circuit through the second electrode of the test transistor and a feedback node that is one end of the test resistor.

The present invention can improve the inspection speed by configuring a device capable of inspecting the connection state between the integrated circuit and the external substrate inside the integrated circuit, as well as reducing the number of test points for inspection on the external substrate to be integrated on the external substrate. There is an effect of reducing the area occupied by the components related to the inspection of the circuit. In addition, the present invention can test the connection state between the integrated circuit and the external substrate with only one test point, so that the configuration required for the test can be minimized and the cost can be reduced.

FIG. 1 is a block diagram schematically illustrating a light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel shown in FIG. 1 .
3 is a diagram illustrating an arrangement example of a gate-in-panel type scan driver, and FIGS. 4 and 5 are diagrams illustrating the configuration of a device related to the gate-in-panel type scan driver.
6 is a block diagram schematically illustrating a configuration of a level shifter according to a first embodiment of the present invention, and FIG. 7 is a diagram schematically illustrating a function of the level shifter illustrated in FIG. 6 .
8 is a block diagram for explaining in detail the configuration of the level shifter according to the second embodiment of the present invention, and FIGS. 9 and 10 are diagrams for explaining the inspection operation of the level shifter shown in FIG. 8 .
11 is a block diagram for explaining in detail the configuration of the level shifter according to the third embodiment of the present invention, and FIGS. 12 to 14 are diagrams for explaining the inspection operation of the level shifter shown in FIG. 11 .
15 to 17 are exemplary views for explaining the normal operation of the level shifter according to the present invention.
18 is a view for explaining a method for checking a connection state of a level shifter according to a third embodiment of the present invention.

The display device according to the present invention may be implemented as a television, an image player, a personal computer (PC), a home theater, an electric vehicle, a smart phone, and the like, but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), or the like. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode will be exemplified.

In addition, although the light emitting display device described below includes an n-type or p-type thin film transistor as an example, it may be implemented in a form in which both n-type and p-type transistors exist. The thin film transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In a thin film transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the thin film transistor. That is, in the thin film transistor, the flow of carriers flows from the source to the drain.

In the case of the p-type thin film transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, since holes flow from the source to the drain, current flows from the source to the drain. On the other hand, in the case of the n-type thin film transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type thin film transistor, since electrons flow from the source to the drain, the current flows from the drain to the source. However, the source and drain of the thin film transistor may be changed according to an applied voltage. Reflecting this, in the following description, any one of the source and the drain will be described as the first electrode, and the other one of the source and the drain will be described as the second electrode.

FIG. 1 is a block diagram schematically illustrating a light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel shown in FIG. 1 .

1 and 2 , the light emitting display device according to the first embodiment of the present invention includes an image supply unit 110 , a timing controller 120 , a scan driver 130 , a data driver 140 , and a display panel. 150 and the power supply unit 180 may be included.

The image supply unit 110 (or the host system) may output various driving signals together with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image supply unit 110 may supply a data signal and various driving signals to the timing control unit 120 .

The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 130 , a data timing control signal DDC for controlling the operation timing of the data driver 140 , and various synchronization signals ( Vsync, which is a vertical sync signal, and Hsync, which is a horizontal sync signal) can be output. The timing controller 120 may supply the data signal DATA supplied from the image supplier 110 together with the data timing control signal DDC to the data driver 140 . The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

The scan driver 130 may output a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 130 may supply a scan signal to the sub-pixels included in the display panel 150 through the scan lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or may be formed directly on the display panel 150 in a gate-in-panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 , and converts the digital data signal to analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply a data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and may be mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

The power supply unit 180 may generate and output a high potential first panel power EVDD and a low potential second panel power EVSS based on an external input voltage supplied from the outside. The power supply unit 180 provides a voltage (eg, a gate voltage including a gate high voltage and a gate low voltage) or data required for driving the scan driver 130 as well as the first and second panel power sources EVDD and EVSS. A voltage (a drain voltage including a drain voltage and a half-drain voltage) required for driving the driver 140 may be generated and output.

The display panel 150 may display an image in response to a driving signal including a scan signal and a data voltage, and the first panel power and the second panel power EVDD and EVSS. The sub-pixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, polyimide, or the like. In addition, the sub-pixels that emit light may include pixels including red, green, and blue or pixels including red, green, blue, and white.

For example, one sub-pixel SP may include a pixel circuit including a switching transistor, a driving transistor, a storage capacitor, an organic light emitting diode, and the like. Since the sub-pixel SP used in the light emitting display device directly emits light, the circuit configuration is complicated. Also, there are various compensating circuits for compensating for deterioration of the organic light emitting diode that emits light as well as the driving transistor that supplies the driving current to the organic light emitting diode. Accordingly, reference is made to the simple illustration of the sub-pixel SP in the form of a block.

Meanwhile, in the above description, the timing control unit 120 , the scan driving unit 130 , the data driving unit 140 , etc. have been described as individual components. However, depending on the implementation method of the light emitting display device, one or more of the timing controller 120 , the scan driver 130 , and the data driver 140 may be integrated into one IC.

3 is a diagram illustrating an arrangement example of a gate-in-panel type scan driver, and FIGS. 4 and 5 are diagrams illustrating configuration of a device related to a gate-in-panel type scan driver.

3 , the gate-in-panel type scan drivers 130a and 130b are disposed in the non-display area NA of the display panel 150 . The scan drivers 130a and 130b may be disposed in the left and right non-display areas NA of the display panel 150 as shown in FIG. 3A . Also, the scan drivers 130a and 130b may be disposed in the upper and lower non-display areas NA of the display panel 150 as shown in FIG. 3B .

Although the scan drivers 130a and 130b are illustrated and described as being disposed in the non-display area NA positioned on the left or right or upper and lower sides of the display area AA as an example, only one of the scan drivers 130a and 130b may be disposed on the left, right, upper or lower side. .

4 , the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135 . The level shifter 135 may generate and output one or more clock signals Clk and start signals Vst based on signals output from the timing controller 120 . The clock signal Clk may be generated and output in the form of K (K is an integer greater than or equal to 2) phases having different phases, such as two-phase, four-phase, eight-phase, and the like.

The shift register 131 operates based on the signals Clk and Vst output from the level shifter 135 and scan signals Scan[1] to Scan that can turn on or off a transistor formed in the display panel. [m]) can be printed. The shift register 131 is formed in the form of a thin film on the display panel by a gate-in-panel method. Accordingly, the portion formed on the display panel in the scan driver 130 may be the shift register 131 . And in FIG. 3 , 130a and 130b may correspond to 131 .

As shown in FIGS. 4 and 5 , the level shifter 135 may be formed in the form of an IC unlike the shift register 131 , and the power supply unit 180 may be configured according to the size, resolution, or implementation method of the display panel. may be included within the However, this is only an example and is not limited thereto.

On the other hand, after the IC such as the level shifter 135 is mounted on a printed circuit board, a process for checking whether the device is normally connected (SMT test; Surface Mounting Technology) is required. Conventionally, in order to test all the output terminals of the level shifter 135, separate test points on the printed circuit board are configured with the number corresponding to the output terminals. However, since this method requires as many test points as the number of output terminals of the level shifter 135, the required area of the printed circuit board increases as well as the inspection speed, so improvement is required.

6 is a block diagram schematically illustrating a configuration of a level shifter according to a first embodiment of the present invention, and FIG. 7 is a diagram schematically illustrating a function of the level shifter illustrated in FIG. 6 .

As shown in FIG. 6 , the level shifter 135 according to the first embodiment includes a circuit driver 135a that generates and outputs signals necessary for driving a shift register, and a test that performs tests on the circuit driver 135a. It may include a driving unit 135b and the like.

The circuit driver 135a operates based on the control signals Conts applied through the input terminals IN1 and IN2, generates signals necessary for driving the shift register, and then operates the output terminals OUT1 to OUTn. can be printed through The circuit driver 135a may output the clock signals Clks and the start signal Vst as well as the gate high voltage Vgh and the gate low voltage Vgl required for driving the shift register.

The test driver 135b operates based on the test signal Test applied through the test input terminal INT, and the output terminals OUT1 to OUTn of the level shifter 135 are normally connected to the signal pads on the external substrate. It is possible to detect whether a connection is made or not. The test driver 135b uses its own test result terminal TRES to determine from the outside whether the output terminals OUT1 to OUTn of the level shifter 135 are normally connected to the signal pads on the external board. A test result signal Tres can be output.

The test driver 135b may have a circuit connected to the output terminals OUT1 to OUTn corresponding to all channels of the circuit driver 135a. The test driver 135b may stop the operation of the circuit driver 135a based on a circuit included therein to perform a test operation.

The test driver 135b connects the output terminals OUT1 to OUTn of the level shifter 135 normally with the signal pads on the external board based on the voltage value delivered (feeded back) through the output terminals OUT1 to OUTn. Test result signals Tres capable of determining whether or not they are connected may be provided. The test driver 135b may output test results for all the output terminals OUT1 to OUTn (all channels) of the level shifter 135 through one test result terminal TRES.

7 , the level shifter 135 may be mounted on an external board (PCB) (printed circuit board). Only one test point TP may be formed on the external substrate PCB to correspond to the test result terminal TRES of the level shifter 135 .

When the test signal Test is applied through the test input terminal INT, the test result signal Tres for determining the connection state to the output terminals OUT1 to OUTn of the level shifter 135 is the test result terminal It can be transmitted to the test point (TP) through (TRES).

Accordingly, when the probe 210 connected to the test apparatus 200 comes into contact with the test point TP, the test result signal Tres may be transmitted to the test apparatus 200 . In addition, it may be determined whether the output terminals OUT1 to OUTn are normally connected to the signal pads on the external board based on the test result signal Tres transmitted to the test apparatus 200 .

However, this is only an example, and the output terminals OUT1 to OUTn of the level shifter 135 are all the output terminals OUT1 to OUTn on the external board PCB based on whether the light is emitted or not after the LED is mounted on the test point TP. It may be determined whether the signal pads are normally connected.

8 is a block diagram for explaining in detail the configuration of the level shifter according to the second embodiment of the present invention, and FIGS. 9 and 10 are diagrams for explaining the inspection operation of the level shifter shown in FIG. 8 .

As shown in FIG. 8 , the level shifter 135 according to the second embodiment includes a selection signal output unit DCIR, first to Nth connection state detection units CIR1 to CIRn, and a result output circuit unit RCIR. can do.

The selection signal output unit DCIR generates and outputs first to Nth selection signals Tc#1 to Tc#n for selectively driving the plurality of first to Nth connection state detection units CIR1 to CIRn. can play a role

The first to Nth connection state detection units CIR1 to CIRn detect a voltage value for determining whether all of the output terminals OUT1 to OUTn of the level shifter 135 are normally connected to the signal pads on the external substrate. can play a role

The result output circuit unit RCIR may serve to collect the first to Nth voltage values output from the first to Nth connection state detection units CIR1 to CIRn into one and then output the inspection result.

The first to Nth connection state detection units CIR1 to CIRn operate based on the first to Nth selection signals Tc#1 to Tc#n output from the selection signal output unit DCIR, respectively, and the level shifters ( The first to Nth voltage values may be respectively acquired through the first to Nth output terminals OUT1 to OUTn of 135 , and then may be transmitted to the result output circuit unit RCIR.

The first to Nth connection state detection units CIR1 to CIRn may include circuits such as the first voltage detection unit TCIR1 and the first voltage comparison unit CMP1, respectively. The first voltage detection unit TCIR1 may acquire a first voltage value through the first output terminal OUT1 of the level shifter 135 and transmit it to the first input terminal of the first voltage comparison unit CMP1 .

The first voltage comparator CMP1 may compare the first voltage value transmitted to the first input terminal with the first reference value applied to the second input terminal, and then output a result value (0 or 1). The first voltage comparator CMP1 may receive the first reference value from the first reference voltage terminal REF connected to the second input terminal. The first voltage comparison unit CMP1 may be defined as a determination circuit that determines the connection state of the first output terminal OUT1 of the level shifter 135 based on the first voltage value transmitted to both terminals and the first reference value. .

9 and 10 , the selection signal output unit DCIR provides a first result value Tre#1 for determining the connection state of the first output terminal OUT1 of the level shifter 135 . The first selection signal Tc#1 may be applied to the first connection state detection unit CIR1. Next, the selection signal output unit DCIR is a second connection state detection unit to prepare a second result value Tre#2 for determining the connection state of the second output terminal OUT2 of the level shifter 135 . A second selection signal Tc#2 may be applied to (CIR2). In this sequential manner, while outputting from the first selection signal Tc#1 to the N-th selection signal Tc#n, all output terminals OUT1 to OUTn of the level shifter 135 can be tested. there is.

The result output circuit unit RCIR prepares a test result signal Tres based on the result values output from the first to Nth connection state detection units CIR1 to CIRn, respectively, and uses it through one test result terminal TRES. It can serve as an output. The result output circuit unit RCIR may perform an AND operation on the result values output from the first to Nth connection state detection units CIR1 to CIRn, respectively, and output the test result signal Tres in the form of a logic high or a logic low.

As such, the selection signal output unit DCIR may detect the connection state of the output terminals OUT1 to OUTn of the level shifter 135 while sequentially driving the first to Nth connection state detection units CIR1 to CIRn. Reverse-sequential or random detection may be performed. The reason is that the first to Nth result values are combined into one and then the test result is output in a specific logic state.

11 is a block diagram for explaining in detail the configuration of the level shifter according to the third embodiment of the present invention, and FIGS. 12 to 14 are diagrams for explaining the inspection operation of the level shifter shown in FIG. 11 . Since the third embodiment includes more specific features compared to the second embodiment, the related parts will be mainly described. In addition, hereinafter, for convenience of description, a circuit related to the first connection state detection unit CIR1 will be described as a reference.

11 , according to the third embodiment, the first connection state detection unit CIR1 may include a first voltage detection unit TCIR1 and a first voltage comparison unit CMP1. The first voltage detector TCIR1 may include a first test transistor VT and a first test resistor Rtest. Although the first test transistor VT1 is illustrated as having a P-type as an example, it may also be formed of an N-type.

The first test transistor VT1 has a first electrode connected to a first output terminal OUT1 of the level shifter 135, a second electrode connected to one end of the first test resistor Rtest, and a selection signal output unit A gate electrode may be connected to the first control terminal of (DCIR). The first test resistor Rtest may have one end connected to the second electrode of the first test transistor VT1 and the other end connected to the second reference voltage terminal VREF.

The first inspection transistor VT1 may be turned on/off in response to the selection signal output from the first output terminal of the selection signal output unit DCIR. When the first test transistor VT1 is turned on, a connection state test for the first output terminal OUT1 of the level shifter 135 may be performed.

Also, according to the third embodiment, the selection signal output unit DCIR may be connected to the first signal output circuit units TU1 and TD1 for generating a first signal required for driving the shift register.

The first signal output circuit units TU1 and TD1 may include driving transistors such as the first pull-up transistor TU1 and the first pull-down transistor TD1 . The first pull-up transistor TU1 has a first electrode connected to the gate high voltage line VGH, a second electrode connected to the first output terminal OUT1 of the level shifter 135, and the selection signal output unit DCIR. A gate electrode may be connected to the second control terminal. The first pull-down transistor TD1 has a first electrode connected to the gate low voltage line VGL, a second electrode connected to the first output terminal OUT1 of the level shifter 135, and the selection signal output unit DCIR. A gate electrode may be connected to the third control terminal.

The first signal output circuit units TU1 and TD1 may be turned on/off in response to a control signal output from the selection signal output unit DCIR. The first signal output circuit units TU1 and TD1 may maintain an inactive state (eg, a turn-off state/floating state) in response to a control signal output from the selection signal output unit DCIR. For example, the first signal output circuit units TU1 and TD1 may maintain an inactive state (eg, a turned-off state/floating state) while the connection state check is performed.

Meanwhile, in FIG. 11 , the first pull-up transistor TU1 and the first pull-down transistor TD1 are configured as N-type as an example. However, this is only an example, and the first pull-up transistor TU1 and the first pull-down transistor TD1 may be configured as P-type. Also, one of the first pull-up transistor TU1 and the first pull-down transistor TD1 may be configured as a different type according to a control method.

In addition, in FIG. 11 , in order to functionally classify and explain circuits included in the first connection state detection unit CIR1, only a portion of the first voltage detection unit TCIR1 is blocked, and the first voltage detection unit TCIR1 and the first voltage comparison unit CMP1 are blocked. ) was physically divided. However, since the first test transistor VT1, the first test resistor Rtest, and the first voltage comparator CMP1 have one configuration, the TCIR1 block that physically separates them will be deleted below.

As shown in FIG. 12 , when the test signal Test is applied through the test input terminal INT, the connection state of the first output terminal OUT1 of the level shifter 135 may be checked.

When the test signal Test is applied through the test input terminal INT, the first test transistor VT1 may be turned on in response to the control signal VTon output from the selection signal output unit DCIR. At this time, the first signal output circuit units TU1 and TD1 may be turned off to proceed with the inspection.

Even when the first signal output circuit units TU1 and TD1 are turned off, the first output terminal OUT1 of the level shifter 135 is connected to the first signal line LN1 on the external substrate PCB. The first signal line LN1 may be affected by a resistance component of the external resistor Rpcb existing on the external substrate PCB. Also, the first signal line LN1 may be affected by an external capacitance component by the external capacitor Cpcb formed between the first signal line GND and the ground line GND. Since the first signal line LN1 is affected by the external resistor Rpcb and the external capacitor Cpcb present on the external substrate PCB, it may be in a state having a specific voltage level rather than an electrically floating state. .

As such, since the first signal line LN1 has a specific voltage level, when the first inspection transistor VT1 is turned on, the second reference voltage applied to the second reference voltage terminal VREF, the first inspection The first voltage value Vtest1 may be determined based on the resistance value of the resistor Rtest, the resistance value of the external resistor Rpcb, and the capacitance value of the external capacitor Cpcb. In addition, the first voltage value Vtest1 may be transmitted (feedback) to the first input terminal of the first voltage comparator CMP1 .

The first voltage comparator CMP1 has a first input terminal connected to the feedback node FN to which the second electrode of the first test transistor VT1 and one end of the first test resistor Rtest are connected, and a first reference A second input terminal may be connected to the voltage terminal REF. The first voltage comparator CMP1 may compare the first voltage value Vtest1 transmitted through the first input terminal with the first reference value applied through the second input terminal, and then output a result value (0 or 1). For example, when the first voltage value Vtest1 satisfies the first reference value, the first voltage comparator CMP1 outputs a logic high corresponding to 1, but the first voltage value Vtest1 does not satisfy the first reference value. In this case, a logic low corresponding to 0 may be output.

When the first output terminal OUT1 of the level shifter 135 is normally connected to the first signal pad on the external board PCB, as shown in FIG. 13 , the first result value Tre#1 made of logic high (H) can be printed out. In addition, when the second output terminal OUT2 to the N-th output terminal OUTn are also normally connected to the second to N-th signal pads on the external substrate PCB, the second to N-th signal pads formed of logic high (H) as shown in FIG. 13 . The Nth result value (Tre#2 ~ Tre#n) can be output.

Then, the result output circuit unit RCIR performs an AND operation to collect all of the first to Nth result values Tre#1 to Tre#n to generate a test result signal Tres of logic high (H) and tests the resultant signal Tres. It can be output through the result terminal (TRES).

As such, that the test result signal Tres of logic high (H) is output through the test result terminal TRES means that all output terminals OUT1 to OUTn of the level shifter 135 are all signals on the external board PCB. It means that it is normally connected to the pads.

However, if only the third output terminal OUT3 among all the output terminals OUT1 to OUTn of the level shifter 135 is not normally connected to the third signal pad on the external board PCB, the logic low ( A third result value Tre#3 consisting of L) may be output. In this case, since the result output circuit unit RCIR performs an AND operation on the first to Nth result values Tre#1 to Tre#n, it generates the test result signal Tres of the logic low L, and then converts it to the test result terminal It can be output through (TRES).

As such, that the test result signal Tres of the logic low L is output through the test result terminal TRES means that one of the output terminals of the level shifter 135 is normally connected to the signal pads on the external board PCB It means that it is not in a non-connected state (bad connection).

The test result terminal TRES is connected to the test point TP through the test result line LNTP on the external board PCB. Accordingly, after the test result signal Tres is transmitted to the test device, it is possible to check whether the test result signal Tres is a logic high (H) or a logic low (L). However, it is also possible to check whether the connection state of the output terminals of the level shifter 135 is normal or abnormal based on whether the LED or the like is mounted on the test point TP and whether light is emitted or not.

15 to 17 are exemplary views for explaining the normal operation of the level shifter according to the present invention.

15 to 17 , when the level shifter 135 is normally connected (mounted) on the external substrate PCB, the first pull-up transistor TU1 and the first pull-down transistor TD1 are connected at regular intervals You can alternate turn on and turn off. And this may occur in common in circuits that generate clock signals necessary for driving the shift register, such as the first output terminal OUT1 to the fourth output terminal OUT4 .

As a result, the level shifter 135 stably outputs the first to fourth clock signals Clk1 to Clk4 through its first output terminal OUT1 to the fourth output terminal OUT4 as shown in FIG. 17 . and pass it to the shift register.

18 is a view for explaining a method of checking a connection state of a level shifter according to a third embodiment of the present invention.

As shown in FIG. 18 , a test signal may be applied to the level shifter in order to execute the test mode (test mode On) ( S110 ). When the test signal is applied, all driving transistors that generate signals (VGH, VGL, etc.) necessary for driving the shift register in the level shifter may be turned off (S120).

Thereafter, the test transistor may be turned on to execute the test mode (S130). When the test transistor is turned on, a voltage value may be detected through each output terminal of the level shifter, the detected voltage value and a comparison value are compared, and then the detection result may be output ( S140 ).

The detection result may be transmitted to the test point TP (S150). Then, the signal of the test point TP may be transmitted to the test apparatus and the test result may be determined (S160). If the signal transmitted from the test point TP matches the reference signal, it is possible to determine good quality (S170), and if it does not match the reference signal, it is defective (S180) and then the inspection can be terminated (S190).

As described above, according to the present invention, a device capable of inspecting a connection state between an integrated circuit and an external substrate can be configured inside the integrated circuit to improve the inspection speed and reduce the number of test points for inspection on the external substrate on the external substrate. There is an effect of reducing the area occupied by the components related to the inspection of the integrated circuit. In addition, the present invention can test the connection state between the integrated circuit and the external board with only one test point, thereby minimizing the configuration required for the test and reducing the cost.

135: level shifter INT: test input terminal
Test: Test signal DCIR: Select signal output section
RCIR: result output circuit unit TCIR1: first voltage detection unit
CMP1: first voltage comparison unit CIR1 to CIRn: first to Nth connection state detection unit

Claims (10)

a display panel for displaying an image; and
a shift register for supplying a scan signal to the display panel and a level shifter for outputting signals necessary for driving the shift register;
The level shifter includes a circuit driver for outputting the signals;
A display device comprising: a test driver configured to output a test result signal capable of determining whether its output terminals are normally connected to signal pads of an external board through the test result terminal based on the test signal. According to claim 1,
The inspection driving unit
When the test signal is applied, a voltage value is detected through the output terminals of the level shifter, and the test result signal is provided based on a result of comparing the detected voltage value with an internal reference value. 3. The method of claim 2,
The test result signal is
A display device that generates logic low or logic high. According to claim 1,
The inspection driving unit
voltage detection units respectively connected to the output terminals of the level shifter and respectively detecting voltage values from the output terminals of the level shifter;
Voltage comparison units that compare the detected voltage values with an internal reference value and output the result values, respectively;
and a result output circuit unit for collecting the result values output from the voltage comparators to prepare the test result signal and outputting the result through the test result terminal. 5. The method of claim 4,
The inspection driving unit
and a selection signal output unit configured to generate a selection signal for selecting at least one of the voltage detection units. 6. The method of claim 5,
The voltage detectors are
a test transistor having a first electrode connected to an output terminal of the level shifter and a gate electrode connected to the selection signal output portion;
Each of the test resistors having one end connected to the second electrode of the test transistor and the other end connected to the reference voltage terminal,
The display device outputs the detected voltage value through an output terminal of the level shifter through a second electrode of the test transistor and a feedback node that is one end of the test resistor. 5. The method of claim 4,
The result output circuit unit
A display device for outputting only one test result signal by performing an AND operation on the result values output from the voltage comparators. a circuit driver generating and outputting signals necessary for driving the device; and
An integrated circuit comprising a test driver for outputting a test result signal capable of determining whether its output terminals are normally connected to signal pads of an external board through the test result terminal based on the test signal. 9. The method of claim 8,
The inspection driving unit
voltage detection units respectively connected to the output terminals of the integrated circuit and respectively detecting voltage values from the output terminals of the integrated circuit;
voltage comparators for comparing the detected voltage values with an internal reference value and outputting the result values, respectively;
and a result output circuit unit for collecting the result values output from the voltage comparators to prepare the test result signal and outputting the result through the test result terminal. 10. The method of claim 9,
The voltage detectors are
a test transistor having a first electrode connected to an output terminal of the integrated circuit and a gate electrode connected to the selection signal output portion;
Each of the test resistors having one end connected to the second electrode of the test transistor and the other end connected to the reference voltage terminal,
An integrated circuit for outputting the detected voltage value through an output terminal of the integrated circuit through a second electrode of the test transistor and a feedback node that is one end of the test resistor.

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