KR20220075577A - Display Device and Driving Method of the same - Google Patents

Abstract

The present invention provides a display panel for displaying an image; a power supply providing a voltage for driving the display panel; and an OCP level controller for setting an OCP (Over Current Protection) level for protecting the display panel and the power supply unit from overcurrent or ESD, wherein the OCP level controller varies the OCP level for each operation mode. can do.

Description

Display Device and Driving Method of the Same

The present invention relates to a display device and a driving method thereof.

With the development of information technology, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as a light emitting display device (LED), a quantum dot display device (QDD), and a liquid crystal display device (LCD) is increasing.

The display devices described above include a display panel including sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit, and the like.

In the above display devices, when a driving signal, for example, a scan signal and a data signal, is supplied to the sub-pixels formed on the display panel, the selected sub-pixel transmits light or directly emits light to display an image.

The present invention varies the level at which overcurrent or static electricity can be detected for each operation mode of the display device, and in particular, when ESD occurs in the compensation mode, the compensation operation is stopped to prevent and solve problems such as a sensing error or compensation error of the device. To improve driving stability and reliability.

The present invention provides a display panel for displaying an image; a power supply providing a voltage for driving the display panel; and an OCP level controller for setting an OCP (Over Current Protection) level for protecting the display panel and the power supply unit from overcurrent or ESD, wherein the OCP level controller varies the OCP level for each operation mode. can do.

The OCP level controller may control to have a lower OCP level in a compensation mode for performing a compensation operation of the display panel than a driving mode for displaying an image on the display panel.

The OCP level controller may select a resistance value to have an OCP level higher than that in the compensation mode in the driving mode and an OCP level lower than that in the driving mode in the compensation mode.

The OCP level control unit may include at least two resistors, at least two switches, and a circuit outputting a signal for controlling the at least two switches.

The OCP level controller may use one of the at least two resistors by controlling the at least two switches so that a lower resistance value is set in the driving mode than in the compensation mode.

The OCP level controller may use the at least two resistors by controlling the at least two switches so that a higher resistance value is set in the compensation mode than in the driving mode.

The OCP level control unit includes a first resistor having one end connected to an OCP level input terminal of a level shifter interworking with the power supply unit, a second resistor having one end connected to the other end of the first resistor, the other end of the first resistor and the a first switch having a first electrode connected to one end of a second resistor, a second electrode connected to a ground line, and a gate electrode connected to a first switch signal line through which a first switch control signal is transmitted, and the other end of the second resistor and a second switch connected to a first electrode, a second electrode connected to the ground line, and a gate electrode connected to a second switch signal line to which a second switch control signal is transmitted.

The first switch and the second switch may be configured as N-type and P-type, or may be configured as the same type.

In addition, the present invention provides a display panel that displays an image, a power supply that provides a voltage for driving the display panel, and an OCP (Over Current Protection) level for protecting the display panel and the power supply from overcurrent or ESD. In the driving method of a display device including an OCP level controller, when a power cut-off signal is generated, the operation mode is changed to a compensation mode for performing a compensation operation, and the OCP level is set lower than the driving mode for displaying an image step; and stopping execution of the compensation mode when ESD is applied.

In order to set the OCP level to be lower, a higher resistance value may be selected in the compensation mode than in the driving mode.

The present invention varies the level at which overcurrent or static electricity can be detected for each operation mode of the display device, and in particular, when ESD occurs in the compensation mode, the compensation operation is stopped to prevent and solve problems such as a sensing error or compensation error of the device. There is an effect of improving driving stability and reliability. In addition, the present invention has the effect of minimizing the occurrence of errors due to ESD by providing a method for immediately detecting low ESD, stopping execution of the compensation mode, and then restarting the operation.

FIG. 1 is a block diagram schematically illustrating a light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel shown in FIG. 1 .
3 is a diagram illustrating an arrangement example of a gate-in-panel type scan driver, FIGS. 4 and 5 are diagrams illustrating a configuration of a device related to a gate-in-panel type scan driver, and FIG. 6 is an exemplary diagram of a stage configuration of a shift register.
7 is an exemplary view illustrating a sub-pixel having a compensation circuit and a data driver for driving the sub-pixel, FIG. 8 is an exemplary view of the sensing circuit unit of FIG. 7, and FIG. 9 is an example showing a sensing method using the sensing circuit unit of FIG. FIG. 10 is an exemplary diagram illustrating a power selector for switching the second power of FIG. 9 .
11 is a diagram illustrating a configuration of a light emitting display device according to a first embodiment of the present invention, FIG. 12 is a diagram illustrating an operation state in a driving mode, and FIG. 13 is a diagram illustrating an operation state in a compensation mode.
14 is a diagram illustrating the configuration of a light emitting display device according to a second embodiment of the present invention, FIG. 15 is a diagram showing a change in a switch control signal for each operation mode of the display device and a change in an OCP level according thereto, and FIG. 16 is It is a view showing an operating state in the driving mode, and FIG. 17 is a view showing the operating state in the compensation mode.
18 is a diagram illustrating the configuration of a light emitting display device according to a third embodiment of the present invention, and FIG. 19 is a diagram showing a change in a switch control signal for each operation mode of the display device and a change in the OCP level accordingly.
20 is a configuration diagram of a light emitting display device according to a fourth embodiment of the present invention, FIG. 21 is a configuration diagram of a light emitting display device according to a fifth embodiment of the present invention, and FIG. 22 is a sixth embodiment of the present invention It is an exemplary configuration diagram of a light emitting display device according to an embodiment.
23 and 24 are flowcharts for explaining a method of driving a light emitting display device according to a seventh embodiment of the present invention.

The display device according to the present invention may be implemented as a television, an image player, a personal computer (PC), a home theater, an electric vehicle, a smart phone, and the like, but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), or the like. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode will be exemplified.

In addition, although the light emitting display device described below includes an n-type or p-type thin film transistor as an example, it may be implemented in a form in which both n-type and p-type transistors exist. The thin film transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In a thin film transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the thin film transistor. That is, in the thin film transistor, the flow of carriers flows from the source to the drain.

In the case of the p-type thin film transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, since holes flow from the source to the drain, current flows from the source to the drain. On the other hand, in the case of the n-type thin film transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type thin film transistor, since electrons flow from the source to the drain, the current flows from the drain to the source. However, the source and drain of the thin film transistor may be changed according to an applied voltage. Reflecting this, in the following description, any one of the source and the drain will be described as the first electrode, and the other one of the source and the drain will be described as the second electrode.

FIG. 1 is a block diagram schematically illustrating a light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel shown in FIG. 1 .

1 and 2 , the light emitting display device according to the first embodiment of the present invention includes an image supply unit 110 , a timing controller 120 , a scan driver 130 , a data driver 140 , and a display panel. 150 and the power supply unit 180 may be included.

The image supply unit 110 (set or host system) may output various driving signals together with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image supply unit 110 may supply a data signal and various driving signals to the timing control unit 120 .

The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 130 , a data timing control signal DDC for controlling the operation timing of the data driver 140 , and various synchronization signals ( Vsync, which is a vertical sync signal, and Hsync, which is a horizontal sync signal) can be output. The timing controller 120 may supply the data signal DATA supplied from the image supplier 110 together with the data timing control signal DDC to the data driver 140 . The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

The scan driver 130 may output a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 130 may supply a scan signal to the sub-pixels included in the display panel 150 through the scan lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or may be formed directly on the display panel 150 in a gate-in-panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 , and converts the digital data signal to analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply a data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and may be mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates high potential first power and low potential second power based on an external input voltage supplied from the outside, and through the first power line EVDD and the second power line EVSS can be printed out. The power supply unit 180 is used to drive the first power and the second power as well as a voltage required for driving the scan driver 130 (eg, a gate voltage including a gate high voltage and a gate low voltage) or a data driver 140 . A necessary voltage (a drain voltage including a drain voltage and a half-drain voltage) may be generated and output.

The display panel 150 may display an image in response to a driving signal including a scan signal and a data voltage, and a first power and a second power. The sub-pixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, polyimide, or the like. In addition, the sub-pixels that emit light may include pixels including red, green, and blue or pixels including red, green, blue, and white.

For example, one sub-pixel SP may be connected to the first data line DL1 , the first scan line GL1 , the first power line EVDD, and the second power line EVSS, and a switching transistor, driving It may include a pixel circuit including a transistor, a capacitor, an organic light emitting diode, and the like. Since the sub-pixel SP used in the light emitting display device directly emits light, the circuit configuration is complicated. Also, there are various compensating circuits for compensating for deterioration of the organic light emitting diode that emits light as well as the driving transistor that supplies the driving current to the organic light emitting diode. Accordingly, reference is made to the simple illustration of the sub-pixel SP in the form of a block.

Meanwhile, in the above description, the timing control unit 120 , the scan driving unit 130 , the data driving unit 140 , etc. have been described as individual components. However, depending on the implementation method of the light emitting display device, one or more of the timing controller 120 , the scan driver 130 , and the data driver 140 may be integrated into one IC.

3 is a diagram illustrating an arrangement example of a gate-in-panel type scan driver, FIGS. 4 and 5 are diagrams illustrating a configuration of a device related to a gate-in-panel type scan driver, and FIG. 6 is an exemplary diagram of a stage configuration of a shift register.

3 , the gate-in-panel type scan drivers 130a and 130b are disposed in the non-display area NA of the display panel 150 . The scan drivers 130a and 130b may be disposed in the left and right non-display areas NA of the display panel 150 as shown in FIG. 3A . Also, the scan drivers 130a and 130b may be disposed in the upper and lower non-display areas NA of the display panel 150 as shown in FIG. 3B .

Although the scan drivers 130a and 130b are illustrated and described as being disposed in the non-display area NA positioned on the left or right or upper and lower sides of the display area AA as an example, only one of the scan drivers 130a and 130b may be disposed on the left, right, upper or lower side. .

4 , the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135 . The level shifter 135 may generate clock signals Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply unit 180 . The clock signals Clks may be generated in the form of K (K is an integer greater than or equal to 2) phases having different phases, such as two-phase, four-phase, eight-phase, and the like.

The shift register 131 operates based on the signals Clks and Vst output from the level shifter 135 and scan signals Scan[1] to Scan [m]) can be printed. The shift register 131 may be formed in the form of a thin film on the display panel by a gate-in-panel method. Accordingly, the portion formed on the display panel in the scan driver 130 may be the shift register 131 . And in FIG. 3 , 130a and 130b may correspond to 131 .

4 and 5 , unlike the shift register 131 , the level shifter 135 may be formed independently in the form of an IC or may be included in the power supply unit 180 . However, this is only an example and is not limited thereto.

As shown in FIG. 6 , the shift register 131 may include a plurality of stages STG[1] to STG[m] that output scan signals Scan[1] to Scan[m]. have. The plurality of stages STG[1] to STG[m] may be connected to the clock signal lines CLKs and the voltage lines VOLs. The plurality of stages STG[1] to STG[m] may have a dependent connection relationship to sequentially output the scan signals Scan[1] to Scan[m].

Since a plurality of stages (STG[1] ~ STG[m]) are dependently connected, only the first stage (STG[1]) at the front is based on the start signal applied through the start signal line (VST). operation and the remaining stages STG[2] to STG[m] may operate based on the scan signal or carry signal output from the previous stage.

In addition, to the clock signal lines CLKs, a scan clock signal line SCCLK for transmitting a scan clock signal for outputting a scan signal and a carry clock signal line CRCLK for transferring a carry clock signal for outputting a carry signal Although illustrated as being included, the present invention is not limited thereto. In addition, although it is illustrated that only the gate high voltage line VGH transmitting the gate high voltage and the gate low voltage line VGL transmitting the gate low voltage are included in the voltage lines VOLs, the present invention is not limited thereto.

7 is an exemplary diagram illustrating a sub-pixel having a compensation circuit and a data driver for driving the sub-pixel, FIG. 8 is an exemplary diagram of the sensing circuit of FIG. 7, and FIG. 9 is an example showing a sensing method using the sensing circuit of FIG. 8 FIG. 10 is an exemplary diagram illustrating a power selector for switching the second power of FIG. 9 .

7 , the sub-pixel SP having the compensation circuit may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light emitting diode (OLED). can

The driving transistor DT may have a gate electrode connected to a first electrode of the capacitor CST, a first electrode connected to a first power line EVDD, and a second electrode connected to an anode electrode of the organic light emitting diode OLED. have. The capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode electrode of the organic light emitting diode OLED. The organic light emitting diode OLED may have an anode electrode connected to the second electrode of the driving transistor DT and a cathode electrode connected to the second power line EVSS.

The switching transistor SW has a gate electrode connected to the first A scan line GL1a included in the first scan line GL1 , a first electrode connected to the first data line DL1 , and a gate of the driving transistor DT. A second electrode may be connected to the electrode. The sensing transistor ST has a gate electrode connected to the 1B scan line GL1b included in the first scan line GL1, a first electrode connected to the first reference line REF1, and the A second electrode may be connected to the anode electrode.

The sensing transistor ST is a kind of compensation circuit added to compensate for deterioration (such as a threshold voltage) of the driving transistor DT or the organic light emitting diode OLED. The sensing transistor ST may enable sensing of a physical threshold voltage based on a source follower operation of the driving transistor DT. The sensing transistor ST may operate to acquire a sensing voltage through a sensing node defined between the driving transistor DT and the organic light emitting diode OLED.

Meanwhile, although the first scan line GL1 is divided into the first A scan line GL1a and the first B scan line GL1b as an example, they may be integrated into one. That is, the switching transistor SW and the sensing transistor ST are commonly connected to the first scan line GL1 and may be turned on or off at the same time.

In addition, the configuration of the sub-pixel SP having the compensation circuit is only an example, and the present invention is not limited thereto. However, for better understanding of the present invention, the structure shown in FIG. 7 is taken as an example.

The sub-pixel SP having the compensation circuit may operate based on the data driver 140 including the driving circuit unit 141 for driving the sub-pixels and the sensing circuit unit 145 for sensing the sub-pixels. The driving circuit unit 141 may output a data voltage for driving the sub-pixels through the first data channel DCH1 . The sensing circuit unit 145 may acquire a sensing voltage sensed from the sub-pixels through the first sensing channel SCH1 .

As shown in FIG. 8 , the sensing circuit unit 145 may include a first voltage circuit unit SPRE, a second voltage circuit unit RPRE, a sampling circuit unit SAM, an analog-to-digital converter ADC, and the like.

The first voltage circuit unit SPRE and the second voltage circuit unit RPRE receive the first reference voltage and the second voltage from the first reference voltage source VPRES and the second reference voltage source VPRER to initialize the node or circuit included in the sub-pixel. Two reference voltages can be output separately. The first reference voltage may be a voltage used in the sensing mode (compensation mode), and the second reference voltage may be defined as a voltage used in the driving mode (normal mode). In addition, the first reference voltage may be set to a lower voltage than the second reference voltage.

The sampling circuit unit SAM may perform a sampling operation for acquiring a sensing voltage through the first sensing channel SCH1 . The analog-to-digital converter ADC may convert the sensing voltage in the analog form acquired by the sampling circuit unit SAM into the sensing voltage in the digital form and output the converted voltage.

The sensing circuit unit 145 acquires the first sensing voltage Vsen1 for compensating for deterioration of the driving transistor DT or the organic light emitting diode OLED included in the sub-pixel SP through the first reference line REF1 . and can be printed.

The first sensing voltage Vsen1 output from the sensing circuit unit 145 may be transmitted to the timing controller. In addition, the timing controller may determine whether the driving transistor DT or the organic light emitting diode OLED included in the sub-pixel SP has deteriorated based on the first sensing voltage Vsen1, and may perform a compensation operation to compensate for this. have.

As shown in FIGS. 8 and 9 , the method for obtaining the first sensing voltage Vsen1 from the sub-pixel SP includes a first step ( S1 ), a second step ( S2 ), and a third step ( S3 ). and the fourth step (S4).

The first sensing data voltage Sdata may be applied to the first data line DL1 to acquire the first sensing voltage Vsen1 from the sub-pixel SP. The first sensing data voltage Sdata may be applied over the entire section including the first step S1 to the fourth step S4, but is not limited thereto.

The first A scan signal G11a may be applied at a logic high level from the first step S1 to the fourth step S4. The switching transistor SW may maintain a turned-on state from the first step S1 to the fourth step S4 in response to the first A scan signal G11a.

The first B scan signal G11b may be applied at a logic high level from the second step S2 to the fourth step S4. The sensing transistor ST may maintain a turned-on state from the second step S2 to the fourth step S4 in response to the first B scan signal G11b.

The first voltage control signal Spre may be applied at a logic high level from the first step S1 to the second step S2. The first voltage circuit unit SPRE may output a first reference voltage from the first step S1 to the second step S2 in response to the first voltage control signal Spre. The first reference voltage output from the first voltage circuit unit SPRE may be transmitted through the first reference line REF1 and may be applied to the sensing node through the sensing transistor ST turned on during the sensing mode.

When the first reference voltage is applied together with the first sensing data voltage Sdata, the driving transistor DT may operate as a source follower. In addition, the first sensing voltage Vsen1 applied to the sensing node by the source follower operation of the driving transistor DT may drop to the first reference voltage level and then be saturated.

The sampling signal Sam may be applied at a logic high level during the fourth step S4 . The sampling circuit unit SAM may have a turned-on state during the fourth step S4 in response to the sampling signal Sam. The sampling circuit unit SAM is illustrated as having a temporarily turned-on state at the beginning of the fourth step S4 as an example, but the present invention is not limited thereto.

The sampling circuit unit SAM may acquire the first sensing voltage Vsen1 saturated to a specific level during the fourth step S4 . The difference value between the first sensing data voltage Sdata and the saturated first sensing voltage Vsen1 can determine the degree of deterioration (variability of the threshold voltage) of the driving transistor DT or the organic light emitting diode OLED. can be judged.

The analog-type first sensing voltage Vsen1 sensed by the sampling circuit unit SAM may be converted into a digital form by the analog-to-digital converter ADC and output, and then transmitted to the timing controller. The timing controller may determine the degree of deterioration (variability of the threshold voltage) of the driving transistor DT or the organic light emitting diode OLED based on the first sensing voltage Vsen1 , and compensate the data signal and the like to output it. In addition, the data driver may output a compensated data voltage based on the compensated data signal.

Meanwhile, during the sensing operation performed from the first step S1 to the fourth step S4, the second power Evss applied through the second power line EVSS is at the first level Evss1 (eg, the ground level). Alternatively, it may be changed (switched) from a negative level lower than this to the second level Evss2 (eg, a level higher than the ground level and lower than the threshold voltage of the organic light emitting diode).

As such, when the level of the second power Evss applied through the second power line EVSS during the sensing operation is changed from the first level Evss1 to the second level Evss2, the sensing voltage Vsen1 is Discharge through the second power line EVSS connected to the cathode electrode of the organic light emitting diode OLED can be prevented.

As shown in FIG. 10 , the level of the second power Evss applied through the second power line EVSS during the sensing operation is changed from the first level Evss1 to the second level Evss2. In order to do this, a power selection unit SEL may be provided.

When the period for performing the sensing operation of the power selector SEL comes, the cathode electrode of the organic light emitting diode OLED is connected from the second power line EVSS1 of the first level to the second power line EVSS2 of the second level. A switching operation may be performed to be connected. The power selection unit SEL may be located in a non-display area of the display panel (eg, a pad unit of the display panel), a printed circuit board connected to the display panel, or inside a power supply unit.

The period during which the above-described sensing operation is performed may be defined as a period in which a signal to cut off power to the display panel is generated. In the power selector SEL, the cathode electrode of the organic light emitting diode OLED is connected to the first level of the second power line EVSS1 in response to the compensation start signal OFFRS accompanying when the power cutoff signal of the display panel is generated. A switching operation may be performed to be connected to the second power line EVSS2 of the second level.

Meanwhile, the light emitting display device described above may switch an operation mode into a driving mode for displaying an image, a compensation mode for performing a compensation operation, and the like. Among the compensation modes, sensing and compensating for deterioration of elements included in sub-pixels during the period in which the device power-off signal is generated affects the lifespan, reliability, and display quality of the device, and thus can be classified as an important compensation operation. Therefore, it is necessary to prepare for static electricity so that the safe compensation mode can be performed even during the period in which the power cut-off signal of the device is generated, the following embodiments are proposed.

11 is a diagram illustrating a configuration of a light emitting display device according to a first embodiment of the present invention, FIG. 12 is a diagram showing an operation state in a driving mode, and FIG. 13 is a diagram illustrating an operation state in a compensation mode.

11 , the light emitting display device according to the first embodiment includes a timing controller 120 , a level shifter 135 , an OCP (Over Current Protection) level controller 170 and 175, and a power supply unit. (180) and the like.

The level shifter 135 may include an OCP level input terminal OCP for setting an OCP level to protect the light emitting display device from overcurrent or electrostatic discharge (ESD). In addition, the level shifter 135 may include an output terminal OU for outputting an alarm signal INBDP for indirectly controlling whether a burnt detection protection (BDP) signal is generated.

The power supply unit 180 may receive the notification signal INBDP output from the level shifter 135 through the input terminal IN. The power supply unit 180 may generate a BDP signal BDP based on the notification signal INBDP and output it through the output terminal OU.

The timing controller 120 may receive the BDP signal BDP output from the power supply unit 180 through the input terminal IN. When the BDP signal BDP is input, the timing controller 120 may stop or block some or all operations included in the display device to prevent damage to the device.

The timing controller 120 may output an OCP control signal OCPCON for controlling the OCP level controllers 170 and 175 in response to the operation mode of the display device. The OCP control signal OCPCON may be output through the output terminal OU of the timing controller 120 .

The OCP level control units 170 and 175 may include a first circuit unit 170 and a second circuit unit 175 . The first circuit unit 170 may receive the OCP control signal OCPCON output through the output terminal OU of the timing controller 120 through the input terminal IN. The first circuit unit 170 may generate and output the switch control signal CON in response to the OCP control signal OCPCON. The second circuit unit 175 may change the resistance value of the internal resistor Rs in response to the switch control signal CON. The changed resistance value of the internal resistor Rs may be applied to the OCP level input terminal OCP of the level shifter 135 .

As such, the light emitting display device may perform a protection operation to protect the device from overcurrent or ESD. In addition, the light emitting display device may stop or block some or all operations included in the display device to prevent damage to the device based on the notification signal INBDP and the BDP signal BDP. As a basic condition for devices included in the light emitting display device to perform the above operation, the voltage or current level set through the OCP level input terminal (OCP) will be described.

As shown in FIG. 12 , when the display device operates in the driving mode (normal mode), the second circuit unit 175 changes the resistance of the internal resistor to the first resistor R1 in response to the switch control signal CON. It may operate to have the first resistance value set in . As a result, the level shifter 135 may set the OCP level based on the first resistance value.

As shown in FIG. 13 , when the display device operates in the compensation mode, the second circuit unit 175 sets the resistance value of the internal resistor to the first resistor R1 and the second resistor in response to the switch control signal CON. It may operate to have the first resistance value and the second resistance value set in (R2). As a result, the level shifter 135 may set the OCP level based on the first resistance value and the second resistance value.

Meanwhile, the first resistor R1 and the second resistor R2 may have a structure connected in series between the OCP level input terminal OCP and the ground line GND. In addition, the second resistance value of the second resistor R2 may be the same as or different from the first resistance value of the first resistor R1 . Accordingly, the resistance value of the internal resistor Rs may be higher than before in response to the resistance ratio of the two resistors connected in series.

12 and 13 , the OCP level of the level shifter 135 may be set based on the first resistance value when the display device operates in the driving mode, and when the display device operates in the compensation mode, the OCP level It may be set based on the first resistance value and the second resistance value.

The OCP level of the level shifter 135 may be lower than the first resistance value based on the first resistance value and the second resistance value. That is, the OCP level of the level shifter 135 may be set lower when the display device operates in the compensation mode than when the display device operates in the driving mode.

According to the first embodiment of the present invention, the OCP level of the level shifter 135 may be changed by changing the internal resistance value Rs of the second circuit unit 175 according to the driving mode of the display device. In addition, the OCP level of the level shifter 135 may be set lower when the display device operates in the compensation mode than when the display device operates in the driving mode.

As such, when the display device operates in the compensation mode, if the OCP level of the level shifter 135 is set lower than before, the ability to detect ESD applied to the display device may be increased. The reason is that, when the display device operates in the compensation mode, the OCP level of the level shifter 135 is lowered due to a higher resistance than before. Accordingly, when the OCP level of the level shifter 135 is lowered when the display device operates in the compensation mode, even when ESD is weakly generated, it can be detected.

Hereinafter, a light emitting display device according to a second embodiment of the present invention will be described, but parts different or changed from the first embodiment will be mainly dealt with.

14 is a diagram illustrating a configuration of a light emitting display device according to a second embodiment of the present invention, FIG. 15 is a diagram showing a change in a switch control signal for each operation mode of the display device and a change in an OCP level according thereto, and FIG. 16 is It is a view showing an operating state in the driving mode, and FIG. 17 is a view showing the operating state in the compensation mode.

14 , the OCP level control units 170 and 175 may include a first circuit unit 170 and a second circuit unit 175 . The first circuit unit 170 may receive the OCP control signal OCPCON output through the output terminal OU of the timing controller 120 through the input terminal IN. The first circuit unit 170 may generate and output the first switch control signal CON1 and the second switch control signal CON2 in response to the OCP control signal OCPCON.

The second circuit unit 175 may change the resistance value of the internal resistor in response to the first switch control signal CON1 and the second switch control signal CON2 . The changed resistance value of the internal resistor may be applied to the OCP level input terminal OCP of the level shifter 135 . The second circuit unit 175 is configured to change the resistance value of the internal resistor, and may include a first resistor R1, a second resistor R2, a first switch M1, and a second switch M2. have. The first switch M1 and the second switch M2 may be selected as N-type transistors that are turned on in response to a logic high signal.

One end of the first resistor R1 may be connected to the OCP level input terminal OCP, and the other end may be connected to one end of the second resistor R2 and the first electrode of the first switch M1. One end of the second resistor R2 may be connected to the other end of the first resistor R1 and the first electrode of the first switch M1 , and the other end may be connected to the first electrode of the second switch M2 . The first switch M1 has a gate electrode connected to the first output terminal OU1 (or the first switch signal line) of the first circuit unit 170 from which the first switch control signal CON1 is output, and a first resistor ( The first electrode may be connected to the other end of R1 and one end of the second resistor R2, and the second electrode may be connected to the ground line GND. The second switch M2 has a gate electrode connected to the second output terminal OU2 (or the second switch signal line) of the first circuit unit 170 from which the second switch control signal CON2 is output, and a second resistor ( The first electrode may be connected to the other end of R2) and the second electrode may be connected to the ground line GND.

15 and 16 , when the display device operates in the NORMAL mode, the first switch control signal CON1 is output at a logic high level and the second switch control signal CON2 is at a logic low level. can be output as The first switch M1 is turned on (M1_On) by the first switch control signal CON1 of logic high, and the second switch M2 is turned off (M1_Off) by the second switch control signal CON2 of the logic low. ) can be

When the first switch M1 is turned on (M1_On) and the second switch M2 is turned off (M1_Off), the resistance value of the internal resistor of the second circuit unit 175 is the first resistor set in the first resistor R1 can have a value. As a result, the level shifter 135 may set the OCP level based on the first resistance value.

15 and 17 , when the display device operates in the compensation mode (OFFRS Mode), the first switch control signal CON1 is output at a logic low level and the second switch control signal CON2 is at a logic high level. can be output as The first switch M1 is turned off (M1_Off) by the first switch control signal CON1 of logic low, and the second switch M2 is turned on (M1_On) by the second switch control signal CON2 of logic high. ) can be

When the first switch M1 is turned off (M1_Off) and the second switch M2 is turned on (M1_On), the resistance value of the internal resistor of the second circuit unit 175 is the first resistor R1 and the second resistor ( It may have a first resistance value and a second resistance value set in R2). As a result, the level shifter 135 may set the OCP level based on the first resistance value and the second resistance value.

Meanwhile, the first resistor R1 and the second resistor R2 may have a structure connected in series between the OCP level input terminal OCP and the ground line GND. Accordingly, the resistance value of the internal resistor may be higher than before. For this reason, when the display device operates in the NORMAL mode, a high level such as 150 mA may be applied to the OCP level input terminal OCP. However, when the display device operates in the compensation mode (OFFRS Mode), a low level such as 100mA may be applied to the OCP level input terminal OCP.

Accordingly, when the display device operates in the compensation mode, the OCP level of the level shifter 135 is lowered due to a higher resistance than before, so that even when ESD is weakly generated, it can be detected.

Hereinafter, a light emitting display device according to a third embodiment of the present invention will be described, but parts different or changed from the first or second embodiments will be mainly dealt with.

18 is a diagram illustrating a configuration of a light emitting display device according to a third embodiment of the present invention, and FIG. 19 is a diagram showing a change in a switch control signal for each operation mode of the display device and a change in the OCP level accordingly.

As shown in FIG. 18 , the OCP level control units 170 and 175 may include a first circuit unit 170 and a second circuit unit 175 . The first circuit unit 170 may receive the OCP control signal OCPCON output through the output terminal OU of the timing controller 120 through the input terminal IN. The first circuit unit 170 may generate and output the switch control signal CON in response to the OCP control signal OCPCON.

The second circuit unit 175 may change the resistance value of the internal resistor in response to the switch control signal CON. The changed resistance value of the internal resistor may be applied to the OCP level input terminal OCP of the level shifter 135 . The second circuit unit 175 is configured to change the resistance value of the internal resistor, and may include a first resistor R1, a second resistor R2, a first switch M1, and a second switch M2. have. The first switch M1 may be selected as an N-type transistor that is turned on in response to a logic high signal, and the second switch M2 may be selected as a P-type transistor that is turned on in response to a logic low signal. have.

One end of the first resistor R1 may be connected to the OCP level input terminal OCP, and the other end may be connected to one end of the second resistor R2 and the first electrode of the first switch M1. One end of the second resistor R2 may be connected to the other end of the first resistor R1 and the first electrode of the first switch M1 , and the other end may be connected to the first electrode of the second switch M2 . The first switch M1 has a gate electrode connected to an output terminal OU (or a switch signal line) of the first circuit unit 170, and is connected to the other end of the first resistor R1 and one end of the second resistor R2. The first electrode may be connected and the second electrode may be connected to the ground line GND. The second switch M2 has a gate electrode connected to the output terminal OU (or switch signal line) of the first circuit unit 170 from which the switch control signal CON is output, and the second switch M2 is connected to the other end of the second resistor R2. The first electrode may be connected and the second electrode may be connected to the ground line GND.

18 and 19 , when the display device operates in the NORMAL mode, the switch control signal CON is output as a logic low and when the display device operates in the OFFRS Mode , the switch control signal CON may be output as logic high.

The first switch M1 may be turned on (M1_On) by the logic high switch control signal CON, but the second switch M2 may be turned off (M1_Off). When the first switch M1 is turned on (M1_On) and the second switch M2 is turned off (M1_Off), the resistance value of the internal resistor of the second circuit unit 175 is the first resistor set in the first resistor R1 can have a value. As a result, the level shifter 135 may set the OCP level based on the first resistance value.

The first switch M1 may be turned off (M1_Off) and the second switch M2 may be turned on (M1_On) by the logic low switch control signal CON. When the first switch M1 is turned off (M1_Off) and the second switch M2 is turned on (M1_On), the resistance value of the internal resistor of the second circuit unit 175 is the first resistor R1 and the second resistor ( It may have a first resistance value and a second resistance value set in R2). As a result, the level shifter 135 may set the OCP level based on the first resistance value and the second resistance value.

Meanwhile, the first resistor R1 and the second resistor R2 may have a structure connected in series between the OCP level input terminal OCP and the ground line GND. Accordingly, the resistance value of the internal resistor may be higher than before. For this reason, when the display device operates in the NORMAL mode, a high level such as 150 mA may be applied to the OCP level input terminal OCP. However, when the display device operates in the compensation mode (OFFRS Mode), a low level such as 100mA may be applied to the OCP level input terminal OCP.

Accordingly, when the display device operates in the compensation mode, the OCP level of the level shifter 135 is lowered due to a higher resistance than before, so that even when ESD is weakly generated, it can be detected.

Hereinafter, the light emitting display device according to the fourth to sixth embodiments of the present invention will be described, but mainly different or changed parts from the first to third embodiments will be described.

20 is a configuration diagram of a light emitting display device according to a fourth embodiment of the present invention, FIG. 21 is a configuration diagram illustrating a configuration of a light emitting display device according to a fifth embodiment of the present invention, and FIG. 22 is a sixth embodiment of the present invention It is an exemplary configuration diagram of a light emitting display device according to an embodiment.

As shown in FIG. 20, the first circuit unit 170 that generates and outputs the switch control signal from the OCP level control units 170 and 175 can be implemented based on a logic circuit, so it does not exist as an independent device and does not exist as a timing control unit ( 120) may be included.

In addition, the timing controller 120 is a first output for outputting the first switch control signal (CON1) and the second switch control signal (CON2) to independently control the first switch (M1) and the second switch (M2), respectively It may have a terminal OU1 and a second output terminal OU2. In this case, the BDP signal BDP output from the output terminal OU of the power supply unit 180 may be input through the input terminal IN of the timing control unit 120 .

As shown in FIG. 21, the first circuit unit 170 that generates and outputs the switch control signal in the OCP level control units 170 and 175 can be implemented based on a logic circuit, so it does not exist as an independent device and does not exist as a timing control unit ( 120) may be included.

In addition, the BDP signal BDP output from the output terminal OU of the power supply unit 180 may be input through the input terminal IN of the image supply unit 110 (set or host system). In addition, the OCP control signal OCPCON output from the output terminal OU of the image supply unit 110 may be input through the input terminal IN of the timing controller 120 .

As shown in FIG. 22 , the first circuit unit 170 for generating and outputting a switch control signal from the OCP level control units 170 and 175 may exist as an independent device. In addition, the BDP signal BDP output from the output terminal OU of the power supply unit 180 may be input through the input terminal IN of the image supply unit 110 (set or host system). In addition, the OCP control signal OCPCON output from the output terminal OU of the image supply unit 110 may be input through the input terminal IN of the first circuit unit 170 .

20 to 22 , it is exemplified that an N-type first switch M1 and a P-type second switch M2 are included in the second circuit unit 175 . However, unlike the drawings, (1) P-type first switch (M1) and N-type second switch (M2), (2) P-type first switch (M1) and P-type second switch (M2), (3) An N-type first switch M1 and an N-type second switch M2 may be selected. Also, only one switch control signal may exist depending on the type of the switches M1 and M2 or the circuit and control method included in the second circuit unit 175 .

23 and 24 are flowcharts for explaining a method of driving a light emitting display device according to a seventh exemplary embodiment of the present invention.

As shown in FIG. 23 , in the method of driving a light emitting display device according to the seventh embodiment of the present invention, OCP between a driving mode for displaying an image (Normal Mode) and a compensation mode for performing a compensation operation (OFFRS Mode) The difference in level and how the device operates after ESD is applied will be mainly explained.

After the device is driven (S110), it may be determined whether a power cut-off signal is generated (S115). When the power cut-off signal does not occur (N), since it can operate in the driving mode (Normal Mode) (S120) for displaying an image, the OCP level is the first resistor set by the first resistor (R1) It may be determined as a value (S125).

However, when the power cut-off signal is generated (Y), since it can operate in the compensation mode (OFFRS Mode) (S130) for performing the compensation operation, the OCP level is applied to the first and second resistors (R1 & R2). It may be determined as the first and second resistance values set by the ? ( S140 ).

As described above in the device-related embodiments, the first and second resistance values set by the first and second resistors R1 & R2 are higher than the first resistance values set by the first resistor R1. . As a result, the OCP level of the compensation mode (OFFRS mode) may be lower than the OCP level of the driving mode (Normal mode), and the ESD detection capability of the display device may be increased. Accordingly, depending on whether ESD is applied, the device may operate as follows.

It may be determined whether ESD is authorized (S150). When ESD is not applied (N), the compensation mode (OFFRS Mode) for performing the compensation operation may be continuously performed (S155). However, when ESD is applied (Y), a BDP signal may be generated from the power supply unit (PMIC) (S160), and in response to this, the execution of the compensation mode (OFFRS Mode) may be stopped (S170).

Even if low ESD is applied during the OFFRS mode, it is not a normal voltage, so it may affect the sensed value or compensation value (sensing error, compensation error, etc.). Therefore, if the ESD detection capability is increased, even if low ESD occurs, it is immediately detected, the OFFRS mode is stopped, and the error occurrence can be minimized in a way that it can be restarted in the future.

Furthermore, as shown in FIG. 24 , if the operation of the device cannot be controlled according to whether ESD is applied, the state in which the light emitting display device 100 cannot perform the compensation mode (OFFRS Mode) may continue. However, as in the embodiment, if the operation of the device is controlled depending on whether ESD is applied, the light emitting display device 100 can be restored to a state in which the compensation mode (OFFRS Mode) can be performed thereafter.

As described above, according to the present invention, the level at which overcurrent or static electricity can be detected is different for each operation mode of the display device, and in particular, when ESD occurs in the compensation mode, the compensation operation is stopped to prevent and solve problems such as a sensing error or a compensation error. It has the effect of improving the driving stability and reliability of the In addition, the present invention has the effect of minimizing the occurrence of errors due to ESD by providing a method for immediately detecting low ESD, stopping execution of the compensation mode, and then restarting the operation.

120: timing control 135: level shifter
170, 175: OCP level control unit 180: power supply unit
CON: switch control signal R1: first resistor
R2: second resistor M1: first switch
M2: second switch

Claims (10)

a display panel for displaying an image;
a power supply providing a voltage for driving the display panel; and
and an OCP level control unit for setting an OCP (Over Current Protection) level for protecting the display panel and the power supply unit from overcurrent or ESD,
The OCP level controller varies the OCP level for each operation mode. According to claim 1,
The OCP level control unit
A display device for controlling to have a lower OCP level in a compensation mode for performing a compensation operation of the display panel than a driving mode for displaying an image on the display panel. 3. The method of claim 2,
The OCP level control unit
and selecting a resistance value to have an OCP level higher than that in the compensation mode in the driving mode and an OCP level lower than that in the driving mode in the compensation mode. 4. The method of claim 3,
The OCP level control unit
A display device comprising: at least two resistors; at least two switches; and a circuit for outputting a signal for controlling the at least two switches. 5. The method of claim 4,
The OCP level control unit
A display device using one of the at least two resistors by controlling the at least two switches so that a lower resistance value is set in the driving mode than in the compensation mode. 5. The method of claim 4,
The OCP level control unit
A display device using the at least two resistors by controlling the at least two switches so that a higher resistance value is set in the compensation mode than in the driving mode. 4. The method of claim 3,
The OCP level control unit
a first resistor having one end connected to the OCP level input terminal of the level shifter interlocking with the power supply;
a second resistor having one end connected to the other end of the first resistor;
A first switch having a first electrode connected to the other end of the first resistor and one end of the second resistor, a second electrode connected to a ground line, and a gate electrode connected to a first switch signal line through which a first switch control signal is transmitted. Wow,
and a second switch having a first electrode connected to the other end of the second resistor, a second electrode connected to the ground line, and a gate electrode connected to a second switch signal line through which a second switch control signal is transmitted. 8. The method of claim 7,
The first switch and the second switch are
A display device composed of N-type and P-type or the same type. A display panel for displaying an image, a power supply for providing a voltage for driving the display panel, and an OCP level controller for setting an OCP (Over Current Protection) level for protecting the display panel and the power supply from overcurrent or ESD In the method of driving a display device,
when a power-off signal is generated, changing the operation mode to a compensation mode for performing a compensation operation and setting an OCP level lower than a driving mode for displaying an image; and
and stopping execution of the compensation mode when ESD is applied. 10. The method of claim 9,
To set the OCP level lower
A method of driving a display device for selecting a higher resistance value in the compensation mode than in the driving mode.

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