KR20220023196A - Digital phase locked-loop circuit, system-on chip including the same and method of operating the same - Google Patents

Abstract

The present invention is to provide a digital phase-locked loop circuit capable of reducing dynamic range and reducing jitter at high frequencies. The digital phase-locked loop circuit according to an embodiment of the present invention includes an optimal interval time-to-digital converter, a digitally controlled oscillator, a first sub-circuit, a second sub-circuit, a first hybrid switched capacitor circuit, a second hybrid switched capacitor circuit, and a sequence calibration circuit. The optimal interval time-to-digital converter compares a reference clock signal having a first frequency and a divided clock signal obtained by dividing an output clock signal having a second frequency, to output a first digital value including a sign which indicates quantized timing errors between the reference clock signal and the divided clock signal.

Description

Digital phase locked-loop circuit, system-on chip including the same and method of operating the same

The present invention relates to a digital phase-locked loop, and more particularly, to a digital phase-locked loop with improved signal characteristics, a system-on-chip including the same, and a method of operating the digital phase-locked loop.

A phase-locked loop (PLL) is a control circuit that generates an output clock signal having a phase related to a phase of an input clock signal. A phase-locked loop can generate a system clock used in a variety of digital products. As an example of the phase-locked loop, a digital phase-locked loop (DPLL) based on digital control may be used. In a digital phase-locked loop (DPLL), performance degradation may occur due to jitter or signal noise.

Accordingly, one object of the present invention is to provide a digital phase-locked loop circuit capable of reducing a dynamic range and reducing jitter at a high frequency.

It is an object of the present invention to provide a system-on-chip including the digital phase-locked loop circuit.

SUMMARY OF THE INVENTION One object of the present invention is to provide a method of operating a digital phase-locked loop circuit capable of reducing a dynamic range and reducing jitter at a high frequency.

A digital phase-locked loop circuit according to an embodiment of the present invention for achieving the above object is an optimal interval time-digital converter, a digitally controlled oscillator, a first sub-circuit, a second sub-circuit, a first hybrid switched capacitor circuit, a first 2 It contains a hybrid switched capacitor circuit and a sequence calibration circuit. The optimal interval time-to-digital converter compares a divided clock signal obtained by dividing a reference clock signal having a first frequency and an output clock signal having a second frequency to eliminate quantized timing errors between the reference clock signal and the divided clock signal. Outputs a first digital value including a sign indicating The digitally controlled oscillator generates the output clock signal. The first sub-circuit generates a first switching signal and a first control voltage based on the first digital value. The second sub-circuit generates a second switching signal and a second control voltage based on the first digital value. The first hybrid switched capacitor circuit stores the first control voltage and provides the first control voltage to the digitally controlled oscillator in response to the first switching signal. The second hybrid switched capacitor circuit stores the second control voltage and provides the second control voltage to the digitally controlled oscillator in response to the second switching signal. The sequence calibration circuit adjusts the time thresholds based on the divided clock signal and the first digital value so that time thresholds related to the quantized timing errors converge to target thresholds, and the adjusted time threshold Delay weight values based on the values are provided to the optimal interval time-to-digital converter. The digitally controlled oscillator adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage.

A system-on-chip according to embodiments of the present invention for achieving the above object includes a buffer, a digital phase-locked loop circuit, and a plurality of subsystems. The buffer generates a reference clock signal having a first frequency. The digital phase-locked loop circuit generates an output clock signal having a second frequency based on the reference clock signal. The plurality of subsystems operate based on the output clock signal. The digital phase-locked loop circuit includes an optimal interval time-to-digital converter, a digitally controlled oscillator, a first sub-circuit, a second sub-circuit, a first hybrid switched capacitor circuit, a second hybrid switched capacitor circuit, and a sequence calibration circuit. The optimal interval time-to-digital converter compares the reference clock signal and the divided clock signal by which the output clock signal is divided to indicate quantized timing errors between the reference clock signal and the divided clock signal. Outputs a digital value. The digitally controlled oscillator generates the output clock signal. The first sub-circuit generates a first switching signal and a first control voltage based on the first digital value. The second sub-circuit generates a second switching signal and a second control voltage based on the first digital value. The first hybrid switched capacitor circuit stores the first control voltage and provides the first control voltage to the digitally controlled oscillator in response to the first switching signal. The second hybrid switched capacitor circuit stores the second control voltage and provides the second control voltage to the digitally controlled oscillator in response to the second switching signal. The sequence calibration circuit adjusts the time thresholds based on the divided clock signal and the first digital value so that time thresholds related to the quantized timing errors converge to target thresholds, and the adjusted time threshold Delay weight values based on the values are provided to the optimal interval time-to-digital converter. The digitally controlled oscillator adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage.

In the method of operating a digital phase-locked loop circuit according to embodiments of the present invention for achieving the above object, in the optimal interval time-digital converter, a reference clock signal having a first frequency and an output clock signal having a second frequency are Comparing the divided clock signal to generate a first digital value including a sign indicating quantized timing errors between the reference clock signal and the divided clock signal, and based on the first digital value, a first control voltage generate a second control voltage based on the first digital value, generate the output clock signal based on the first control voltage and the second control voltage in a digitally controlled oscillator, and in a sequence calibration circuit , rearranges the time thresholds associated with the timing errors based on the divided clock signal and the first digital value, and in the optimal interval time-to-digital converter, the quantization based on the rearranged time thresholds Adjust the timing errors.

In a digital phase-locked loop and an operating method thereof according to embodiments of the present invention, the digital phase-locked loop circuit includes an optimum interval time-digital converter and a sequence control circuit, and the optimum interval time in the sequence control circuit is included in the digital converter. An output clock signal may be generated while a dynamic range and jitter are reduced by adjusting time thresholds of the plurality of time-digital converters.

1 is a block diagram illustrating a digital phase-locked loop circuit according to embodiments of the present invention.
2 illustrates an optimal interval time-to-digital converter and a sequence calibration circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.
3 is a circuit diagram illustrating a configuration of one of the time-digital converters of FIG. 2 according to embodiments of the present invention.
FIG. 4 shows a pair of a corresponding time-to-digital converter and a bang-bang phase detector in the optimal interval time-to-digital converter of FIG. 2 according to embodiments of the present invention.
5 illustrates a phase difference between the reference clock signal and the divided clock signal in FIG. 4 .
6 shows individual digital values according to the phase difference between the reference clock signal and the divided clock signal in FIG. 4 .
7 is a graph illustrating a relationship between a timing error and a first digital value.
8 illustrates a sequence adjustment circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.
9 is a block diagram illustrating a configuration of a sequence rearrangement logic in the sequence control circuit of FIG. 8 according to embodiments of the present invention.
10 is an example of adjusting time thresholds without using a sequence rearrangement scheme.
11 is an example of adjusting time thresholds without using a sequence rearrangement scheme.
12 is an example of adjusting time thresholds without using a sequence rearrangement scheme.
13 is an example illustrating a case in which a sequence rearrangement scheme is applied according to embodiments of the present invention.
14 illustrates the probability that time thresholds are all matched to target thresholds in a given dynamic range when the sequence rearrangement scheme according to embodiments of the present invention is not applied.
15 illustrates the probability that time thresholds are all matched to target thresholds in a given dynamic range when a sequence rearrangement scheme according to embodiments of the present invention is applied.
16 is a block diagram illustrating a system-on-chip to which a digital phase-locked loop according to embodiments of the present invention can be applied.
17 is a flowchart illustrating a method of operating a digital phase-locked loop circuit according to embodiments of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms and the text It should not be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each drawing, similar reference numerals are used for components.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

When an element is referred to as being “connected” or “connected” to another element, it is understood that it may be directly connected or connected to the other element, but other elements may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or a combination thereof exists, but one or more other features or numbers , it is to be understood that it does not preclude the possibility of the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 is a block diagram illustrating a digital phase-locked loop circuit according to embodiments of the present invention.

1 , the digital phase locked loop circuit 10 includes an optimal interval time-to-digital converter (OS TDC, 100), a sequence calibration circuit 200, a coarse phase detector 300, an interlocking control logic 310, and a phase error correction logic 320 , first sub-circuit 330 , second sub-circuit 340 , third sub-circuit 350 , first hybrid switched capacitor circuit 420 , second hybrid switched capacitor circuit 430 , It may include a divider 360 and a ring-type digitally controlled oscillator (RDCO 500, hereinafter 'digital controlled oscillator').

The optimal interval time-to-digital converter 100 compares the reference clock signal SREF having the first frequency and the divided clock signal SDIV obtained by dividing the output clock signal SOUT having the second frequency to obtain the reference clock signal ( SREF) and the first digital value DTDC including a sign indicating quantized timing errors between the divided clock signal SIIV may be output.

The digitally controlled oscillator 500 may generate an output clock signal SOUT. The divider 360 may generate a divided clock signal SDIV by dividing the frequency of the output clock signal SOUT.

The first sub-circuit 330 may generate the first switching signal DP and the first control voltage VKP based on the first digital value DTDC. The second sub-circuit 340 may generate the second switching signal DI and the second control voltage VKI based on the first digital value DTDC. The first sub-circuit 330 may correspond to a proportional path.

The first hybrid switched capacitor circuit 420 stores the first control voltage VKP and selectively provides the first control voltage VKP to the digitally controlled oscillator 500 in response to the first switching signal DP. can The first hybrid switched capacitor circuit 420 may include a variable capacitor 421 connected to a ground voltage and a switch 423 connected between the variable capacitor 421 and the digitally controlled oscillator 500 . The variable capacitor 421 may store the first control voltage VKP, and the switch 423 may switch the first control voltage VKP to the digitally controlled oscillator 500 in response to the first switching signal DP. there is.

The second hybrid switched capacitor circuit 430 stores the second control voltage VKI and selectively provides the second control voltage VKI to the digitally controlled oscillator 500 in response to the second switching signal DI. can The second hybrid switched capacitor circuit 430 may include a variable capacitor 431 connected to a ground voltage and a switch 433 connected between the variable capacitor 431 and the digitally controlled oscillator 500 . The variable capacitor 431 may store the second control voltage VKI, and the switch 433 may switch the second control voltage VKI to the digitally controlled oscillator 500 in response to the second switching signal DI. there is. The digitally controlled oscillator 500 may adjust the frequency of the output clock signal SOUT based on the first control voltage VKP and the second control voltage VKI.

The first hybrid switched capacitor circuit 420 and the second hybrid switched capacitor circuit 430 store and provide the first control voltage VKP and the second control voltage VKI to the digitally controlled oscillator 500, thereby digitally controlling The oscillator 500 may immediately respond to the first control voltage VKP and the second control voltage VKI.

The sequence calibration circuit 200 rearranges time thresholds for controlling the quantized timing errors based on the divided clock signal SDIV and the first digital value DTDC based on target thresholds, and rearranges the time thresholds. Delay weight values DCW based on the calculated time thresholds may be provided to the optimal interval time-to-digital converter 100 .

The linkage control logic 310 may generate a first linkage control signal DKP and a second linkage control signal DKI based on the first digital value DTDC. The phase error correction logic 320 may detect a phase error of the output clock signal SOUT and correct the detected phase error to generate the detection signal SFPEC. The detection signal SFPEC may have digital values of '0' and '1'.

The first sub-circuit 330 may include a multiplier 331 , a first binary-to-thermometer code converter (B2T, 332 ), a first delta-sigma digital-to-analog converter 333 , and a first low pass filter 334 . can

The multiplier 331 may perform a multiplication operation on the detection signal SFPEC and the first digital value DTDC. The first binary-thermometer code converter 330 may convert the output of the multiplier 331 into a binary-thermometer code to output the first switching signal DP. The first delta-sigma digital-analog converter 333 may perform delta-sigma digital-analog conversion on the first interlocking control signal DKP. The first low-pass filter 334 may provide the first control voltage VKP by low-pass filtering the output of the first delta-sigma digital-to-analog converter 333 .

The second sub-circuit 340 may include an accumulator 341 , a second binary-thermometer code converter 342 , a second delta-sigma digital-to-analog converter 343 , and a second low-pass filter 344 . . The second sub-circuit 340 may correspond to an integration path.

The accumulator 341 may accumulate the first digital value DTDC. The second binary-thermometer code converter 342 may convert the output of the accumulator 341 into a binary-thermometer code to output the second switching signal DI. The second delta-sigma digital-analog converter 343 may perform delta-sigma digital-analog conversion on the second interlocking control signal DKI. The second low-pass filter 344 may provide the second control voltage VKI by low-pass filtering the output of the second delta-sigma digital-to-analog converter 353 .

The coarse phase detector 300 detects a phase difference between the reference clock signal SREF and the divided clock signal SDIV.

The third sub-circuit 350 includes a limiter 351 , an operator 352 , an summer 353 , an accumulator 354 , a third delta-sigma digital-to-analog converter 355 , and a third low-pass filter 356 . , a register 357 and a summer 358 . The third sub-circuit 350 may correspond to a frequency acquisition path.

The limiter 351 limits the output of the accumulator 341 and provides it to the adder 353 . The operator 352 multiplies the output of the coarse phase detector 300 by a power of 2 (2 ¹⁷ ) and provides it to the adder 353 . The adder 353 sums the output of the limiter 351 and the output of the operator 352 . Accumulator 354 accumulates the output of summer 354 . The output of the accumulator 354 may be provided as control codes for controlling the capacitor banks included in the digitally controlled oscillator 500 .

The third delta-sigma digital-analog converter 355 may perform delta-sigma digital-analog conversion on the output of the accumulator 354 . The low-pass filter 356 may low-pass filter the output of the third delta-sigma digital-to-analog converter 355 . An output of the low-pass filter 356 may be provided as control codes for controlling varactors included in the digitally controlled oscillator 500 .

The register 357 may store high-level data. The summer 358 may sum the output of the coarse phase detector 300 and high-level data. The output of summer 358 may be provided as control codes for controlling capacitor banks included in digitally controlled oscillator 500 .

The sequence calibration circuit 200 is configured to converge time thresholds related to the quantized timing errors to target thresholds based on the divided clock signal SDIV and individual digital values included in the first digital value. The values may be adjusted, and delay weight values DCW based on the adjusted time thresholds may be provided to the optimal interval time-to-digital converter 100 .

2 illustrates an optimal interval time-to-digital converter and a sequence calibration circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.

2, the optimal interval time-to-digital converter 100 is a plurality of time-digital converters (110a to 110g, g is a natural number greater than or equal to 3), a plurality of bang bang phase detectors (BBPD) (130a to 130g) and A summer 150 may be included.

The plurality of time-to-digital converters 110a to 110g respectively perform time-digital conversion on the divided clock signal SDIV, and convert the clock signal SDIV divided by the corresponding time threshold among the time thresholds. can be delayed

Each of the bang-bang phase detectors 130a to 130g compares the phase of the reference clock signal SREF with the phase of the output of each of the time-digital converters 110a to 110g, and compares the respective digital values DSGN_0 to representing the corresponding phase difference. DSGN_6) can be output. Each of the individual digital values DSGN_0 to DSGN_6 may have a value of (-1) or (+1) according to a phase difference.

The summer 150 may output the first digital value DTDC by summing the individual digital values DSGN_0 to DSGN_6 .

The sequence calibration circuit 200 receives the individual digital values DSGN_0 to DSGN_6 provided from the bang-bang phase detectors 130a to 130g, and based on the individual digital values DSGN_0 to DSGN_6, time threshold values are set as target thresholds. The time thresholds are adjusted to converge on 110a ~ 110g) can be provided to each. The sequence calibration circuit 200 quantizes individual digital values DSGN_0 to DSGN_6, and based on an average delay digital value and target delay digital values generated by sampling the quantized individual digital values, the delay weight values DCW_0 to DCW_6) can be created.

Each of the time-digital converters 110a to 110g may adjust time thresholds based on a corresponding delay weight value among the delay weight values DCW_0 to DCW_6.

3 is a circuit diagram illustrating a configuration of one of the time-digital converters of FIG. 2 according to embodiments of the present invention.

3 shows the configuration of the time-to-digital converter 110a, the configuration of each of the time-to-digital converters 110b to 110g may be the same as that of the time-to-digital converter 110a.

Referring to FIG. 3 , the time-digital converter 110a includes a first inverter 111 , a second inverter 112 connected to the first inverter 112 , and a first inverter 111 and a second inverter 112 . It may include a plurality of MOS capacitors 121 to 12p, where p is a natural number equal to or greater than 3) connected in parallel therebetween.

The plurality of MOS capacitors 121 to 12p may store the delay weight value DCW_0 in a binary weighted form (DCW_0[0] to DCW_0[7]).

The inverter 111 inverts the input IN corresponding to the divided clock signal SDIV, and the inverter 112 inverts the output of the inverter 111 to provide the inverted output OUT. That is, the time-to-digital converter 110a may delay and output the divided clock signal SDIV by the delay weight value DCW_0.

FIG. 4 shows a pair of a corresponding time-to-digital converter and a bang-bang phase detector in the optimal interval time-to-digital converter of FIG. 2 according to embodiments of the present invention.

Referring to FIG. 4 , the time-to-digital converter DTCk has a variable time threshold value TTH_k and converts the divided clock signal SDIV into a digital signal. The bang-bang phase detector BBPD compares the phase of the reference clock signal SREF with the phase of the divided clock signal SDIV based on the output of the time-digital converter DTCk, and the phase of the reference clock signal SREF and the divided clock An individual digital value DSGN_k representing the phase difference of the signal SDIV as a sign may be output. The individual digital value DSGN_k may have a (+1) or (-1) value according to a phase difference between the phase of the reference clock signal SREF and the divided clock signal SDIV.

5 illustrates a phase difference between the reference clock signal and the divided clock signal in FIG. 4 .

5, when the phase of the reference clock signal SREF is earlier than the phase of the divided clock signal SDIV, the timing error corresponding to the phase difference between the phase of the reference clock signal SREF and the divided clock signal SDIV ( TERR) has a positive value.

6 shows individual digital values according to the phase difference between the reference clock signal and the divided clock signal in FIG. 4 .

Referring to FIG. 6 , when the timing error TERR is greater than the time threshold value TTH_k, the individual digital value DSGN_k has a value of (+1), and the timing error TERR is smaller than the time threshold value TTH_k. When the individual digital value (DSGN_k) has a value of (-1).

7 is a graph illustrating a relationship between a timing error and a first digital value.

In FIG. 7 , TTH_0 to TTH_6 represent time thresholds of each of the time-digital converters 110b to 110g, and TTRG_0 to TTRG_6 represent target thresholds of each of the time-digital converters 110b to 110g. The target thresholds TTRG_0 to TTRG_6 may be found by the Lloyd-Max algorithm.

In addition, □ indicates a value corresponding to 0.5 of the variance of the timing error TERR, and Δ indicates a value corresponding to 0.5 of the variance of the timing error TERR.

Referring to FIG. 7 , it can be seen that as the timing error TERR increases, the first digital digital value DTDC increases.

8 illustrates a sequence adjustment circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 8 , the sequence adjustment circuit 200 may include a plurality of delay weight generators 210a to 210g , a divider 220 , and a sequence rearrangement logic 230 .

The delay weight generators 210a to 210g quantize the individual digital values DSGN_0 to DSGN_6, respectively, and based on the average delay digital value and target delay digital values generated by sampling the quantized individual digital values, delay weight values ( DCW_0 to DCW_6) can be generated respectively.

The divider 220 divides the divided clock signal SDIV and provides the first divided clock signal SDIV1 to each of the delay weight generators 210a to 210g.

The sequence rearrangement logic 230 may generate target delay weight values DTRG_0 to DTRG_6 based on the average delay digital values DAVG_0 to DAVG_6.

The delay weight generator 210a may include a quantizer 211 , a sample/hold circuit 212 , an operator 213 , and an accumulator 214 .

The quantizer 211 quantizes the individual digital values DSGN_1, and the sample/hold circuit 212 samples and maintains the output of the quantizer 211 in synchronization with (based on) the first divided clock signal SDIV1. to (average) to generate an average delay digital value (DAVG_0).

The operator 213 may subtract the target delay weight value DTRG_0 from the average delay digital value DAVG_0, and the accumulator 214 may accumulate the output of the operator 213 to generate the delay weight value DCW_0.

Although the configuration of the delay weight generator 210a is illustrated in FIG. 8 , the configuration of each of the delay weight generators 210b to 210g may be the same as that of the delay weight generator 210a.

9 is a block diagram illustrating a configuration of a sequence rearrangement logic in the sequence control circuit of FIG. 8 according to embodiments of the present invention.

Referring to FIG. 9 , the sequence rearrangement logic 230 includes a plurality of unit circuits ( 240a-240g) may be included.

The unit circuit 240a includes a modulo operation result (DAVG_mod[k, 7]) of an average delay digital value related to the unit circuit 240a among average delay digital values and an average digital value related to other unit circuits 240b to 240g. A plurality of comparators 251 to 257 outputting comparison signals CS1 to CS7 by comparing the modulo operation results of the values (DAVG_mod[k+1, 7] to DAVG_mod[k+6, 7]), respectively. , a summer 260 for summing the comparison signals CS1 to CS7 to output a summed digital value DSUM_0, and a decoder 270 for decoding the summed digital value DSUM_0 into a corresponding target delay digital value DTRG_0. may include

The decoder 270 may store the summed digital value DSUM_k and the corresponding target delay digital value DTRG_k in the form of a mapping table.

10 is an example of adjusting time thresholds without using a sequence rearrangement scheme.

In FIG. 10 , reference number 611 denotes that time thresholds TTH_0 to TTH_6 have the same timing error TERR, and reference number 612 denotes delays in which target thresholds TTRG_0 to TTRG_6 are different from each other. indicates that it has

That is, when the time thresholds TTH_0 to TTH_6 have the same timing error TERR, the time-to-digital converters 110a to 110g of FIG. 2 can generate the same delay with respect to the divided clock signal SDIV. there is.

11 is an example of adjusting time thresholds without using a sequence rearrangement scheme.

In FIG. 11 , reference number 621 indicates that the time thresholds TTH_0 to TTH_6 have a timing error TERR that is equal at the time of design, and reference number 622 denotes time-to-digital converters 110a to 110g. ) is actually manufactured, indicating that the timing error TERR of the time thresholds TTH_0 to TTH_6 is randomly distributed, and reference number 623 indicates that the target thresholds TTRG_0 to TTRG_6 have different delays. indicates that there is

That is, in the case of FIG. 11 , even if the time thresholds TTH_0 to TTH_6 have the same timing error TERR, the time-to-digital converters 110a to 110g of FIG. 2 are each other with respect to the divided clock signal SDIV. You can create other delays.

12 is an example of adjusting time thresholds without using a sequence rearrangement scheme.

12 is an example of adjusting time thresholds without using a sequence rearrangement scheme.

In FIG. 12 , reference number 631 indicates that the time threshold values TTH_0 to TTH_6 have a timing error TERR that is equal at the time of design, and reference number 632 denotes time-digital converters 110a to 110g. ) is actually manufactured, indicating that the timing error TERR of the time thresholds TTH_0 to TTH_6 is randomly distributed, and reference number 633 indicates that the time thresholds TTH_0 to TTH_6 are arranged in a predetermined order. This indicates matching with the target thresholds TTRG_0 to TTRG_6 in the order of the time thresholds TTH_0 to TTH_6. In this case, the target threshold value TTH_0 has the largest timing error TERR and the target threshold value TTH_6 has the smallest timing error TERR. In order to cover this, the time-digital converters 110a ~110g) should increase the dynamic range very much.

13 is an example illustrating a case in which a sequence rearrangement scheme is applied according to embodiments of the present invention.

In FIG. 13 , reference numeral 641 denotes that the time thresholds TTH_0 to TTH_6 have the same timing error TERR at the time of design, and reference numeral 642 denotes the time-to-digital converters 110a to 110g. ) is actually manufactured, indicating that the timing error TERR of the time thresholds TTH_0 to TTH_6 is randomly distributed, and reference number 633 indicates that the time thresholds TTH_0 to TTH_6 are the timing error TERR. This indicates matching with the target thresholds TTRG_0 to TTRG_6 irrespective of the order of the time thresholds TTH_0 to TTH_6 according to the size of . In this case, the target threshold value TTH_0 has the largest timing error TERR and the target threshold value TTH_6 has the smallest timing error TERR, in the order of increasing the timing error TERR. Since the target thresholds are matched to the target thresholds TTRG_0 to TTRG_6, the dynamic range of the time-digital converters 110a to 110g can be reduced.

14 illustrates the probability that time thresholds are all matched to target thresholds in a given dynamic range when the sequence rearrangement scheme according to embodiments of the present invention is not applied.

Referring to FIG. 14 , a dynamic range of about 6.31 ps is required to properly operate in a dynamic lane corresponding to three times the standard deviation. In Fig. 14, P denotes a matching probability.

15 illustrates the probability that time thresholds are all matched to target thresholds in a given dynamic range when a sequence rearrangement scheme according to embodiments of the present invention is applied.

Referring to FIG. 15 , a dynamic range of about 2.66 ps is required to properly operate in a dynamic lane corresponding to three times the standard deviation. Accordingly, in the case of adjusting the time thresholds of the time-to-digital converters 110a to 110g by rearranging the time thresholds according to embodiments of the present invention, the dynamic range of the time-to-digital converters 110a to 110g is reduced. know that it can be done. In Fig. 15, P denotes a matching probability.

16 is a block diagram illustrating a system-on-chip to which a digital phase-locked loop according to embodiments of the present invention can be applied.

Referring to FIG. 16 , the system-on-chip (SoC) may include a buffer 710 , a digital phase locked loop 720 ( ADPLL), a plurality of subsystems 741 to 743 , and a divider 730 . .

The buffer 710 generates a reference clock signal SREF by buffering an output signal of the crystal-oscillator 701 that may be provided outside the SoC 700 . The digital phase-locked loop 720 may employ the digital phase-locked loop 10 of FIG. 1 . Accordingly, the digital phase locked loop circuit 720 includes an optimal interval time-to-digital converter and a sequence adjustment circuit, and the sequence adjustment circuit adjusts time thresholds of a plurality of time-digital converters included in the optimal interval time-to-digital converter in the sequence adjustment circuit. Thus, the output clock signal SOUT can be generated while reducing the dynamic range and jitter.

Each of the plurality of subsystems 741 to 7443 may operate in response to the output clock signal SOUT, and the divider 730 divides the output clock signal SOUT according to a predetermined division ratio, The clock signal DSOUT may be provided to at least one subsystem 743 . Each of the plurality of subsystems 741 to 743 may represent hardware or a circuit operating using the output clock signal SOUT or a signal related to the output clock signal SOUT.

For example, the subsystem 741 may be a central processing unit (CPU), a processor, or an application processor (AP), and the subsystem 742 may be a graphic processing unit (GPU), and the subsystem 743 may be a graphics processing unit (GPU). may be a memory device or a memory controller.

Meanwhile, each of the plurality of subsystems 741 to 743 may be an intellectual property (IP). IP is a function block used in the SoC 700 , and includes a CPU, a processor, each core of a multi-core processor, a memory device, a universal serial bus (USB), and a peripheral component interconnect (PCI). ), digital signal processor, wired interface, wireless interface, controller, embedded software, codec, video module (eg, camera interface, JPEG processor, video processor or mixer, etc.), a 3D graphic core, an audio system, or a driver. Also, SoC 700 may represent part of an AP or part of a mobile AP.

17 is a flowchart illustrating a method of operating a digital phase-locked loop circuit according to embodiments of the present invention.

1 to 15 and 17 , an optimal interval time-to-digital converter 100 , a sequence calibration circuit 200 , a first sub-circuit 330 , a second sub-circuit 340 , and a first hybrid switched capacitor In the method of operation of the digital phase-locked loop circuit 10 including the circuit 420 , the second hybrid switched capacitor circuit 430 , and the digitally controlled oscillator 500 , the optimal interval time-to-digital converter 100 in the first The reference clock signal SREF having a frequency and the divided clock signal SDIV obtained by dividing the output clock signal SOUT having a second frequency are compared to obtain a difference between the reference clock signal SREF and the divided clock signal SIIV. A first digital value DTDC including a sign indicating quantized timing errors is generated ( S110 ).

The first sub-circuit 330 generates a first control voltage VKP based on the first digital value DTDC ( S120 ), and applies the first control voltage VKP to the first hybrid switched capacitor circuit 420 . Save.

The second sub-circuit 340 generates a second control voltage VKI based on the first digital value DTDC ( S130 ), and applies the second control voltage VKI to the second hybrid switched capacitor circuit 430 . Save.

The digitally controlled oscillator 500 generates the output clock signal SOUT based on the first control voltage VKP and the second control voltage VKI ( S140 ), and adjusts the frequency of the output clock signal SOUT.

The sequence calibration circuit 200 rearranges time thresholds for controlling the quantized timing errors based on the divided clock signal SDIV and the first digital value DTDC based on target thresholds (S150) .

The quantized timing errors are adjusted based on the rearranged time thresholds in the optimal interval time-to-digital converter 100 ( S160 ).

Therefore, in the digital phase-locked loop and its operating method according to the embodiments of the present invention, the digital phase-locked loop circuit includes an optimal interval time-digital converter and a sequence control circuit, and the optimal interval time in the sequence control circuit includes the digital converter The output clock signal may be generated while reducing the dynamic range and jitter by adjusting the time thresholds of the plurality of time-to-digital converters.

Embodiments of the present invention are employed in various wireless communication devices, so that frequency disturbance correction and noise correction of an output clock signal can be performed separately, and the falling edge of a non-uniform clock signal with respect to an arbitrary multiplication factor can align to the zero crossing point of the output clock signal, and reduce the loss of frequency resolution in a wide lock-in range while reducing power consumption.

Although the above has been described with reference to the embodiments of the present invention, those of ordinary skill in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that you can

Claims (16)

A first signal including a sign, indicating quantized timing errors between the reference clock signal and the divided clock signal obtained by comparing the divided clock signal obtained by dividing the reference clock signal having a first frequency and an output clock signal having a second frequency an optimal interval time-to-digital converter that outputs a digital value;
a digitally controlled oscillator for generating the output clock signal;
a first sub-circuit for generating a first switching signal and a first control voltage based on the first digital value;
a second sub-circuit for generating a second switching signal and a second control voltage based on the first digital value;
a first hybrid switched capacitor circuit that stores the first control voltage and provides the first control voltage to the digitally controlled oscillator in response to the first switching signal;
a second hybrid switched capacitor circuit that stores the second control voltage and provides the second control voltage to the digitally controlled oscillator in response to the second switching signal; and
Adjust the time thresholds so that time thresholds related to the quantized timing errors converge to target thresholds based on the divided clock signal and the first digital value, and a delay based on the adjusted time thresholds a sequence calibration circuit that provides weight values to the optimal interval time-to-digital converter;
The digitally controlled oscillator is a digital phase locked loop circuit that adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage. The method of claim 1, wherein the optimal interval time-to-digital converter is
a plurality of time-to-digital converters delaying the divided clock signal by a corresponding one of the time thresholds;
a plurality of bang-bang phase detectors comparing a phase of the reference clock signal with a phase of each of the outputs of the plurality of time-digital converters and outputting individual digital values representing the phase difference; and
and a summer for summing the individual digital values and outputting the first digital value. The method of claim 2, wherein each of the plurality of time-to-digital converters comprises:
a first inverter for inverting the divided clock signal;
a second inverter outputting one of the delayed divided clock signals by inverting the output of the first inverter;
connected between the first inverter and the output terminal and the input terminal of the second inverter,
and a plurality of MOS capacitors for storing a corresponding delay weight value among the delay weight values in a binary weighted form. 3. The method of claim 2, wherein each of the bang-bang phase detectors is
A digital phase locked loop for outputting the individual digital value as one of (-1) and (+1) based on a comparison of the phase of the reference clock signal and a phase of a corresponding delayed divided clock signal among the delayed divided clock signals. 3. The method of claim 2, wherein the sequence control circuit is
a plurality of delay weight generators that quantize each of the individual digital values and generate the delay weight values, respectively, based on an average delay digital value and target delay digital values generated by sampling the quantized individual digital values; and
and sequence reordering logic to generate the target delay weight values based on the average delay digital values. 6. The method of claim 5,
Each of the plurality of delay weight generators is
a quantizer that quantizes a corresponding individual digital value among the individual digital values and outputs a quantized individual digital value;
a sample/hold circuit for averaging the individual quantized digital values based on a first divided clock signal by which the divided clock signal is divided and outputting the average delayed digital value;
an operator for subtracting a corresponding target delay digital value among the target delay digital values from the average delay digital value; and
and an accumulator for accumulating outputs of the calculator and outputting a corresponding delay weight value among the delay weight values. 6. The method of claim 5, wherein the sequence rearrangement logic is
and a plurality of unit circuits each generating the target delay digital values based on the average delay digital values. The method according to claim 7, wherein each of the plurality of unit circuits comprises:
a plurality of comparators outputting comparison signals by comparing a result of a modulo operation of a corresponding average delay digital value among the average delay digital values with a result of a modulo operation of average delay digital values related to other unit circuits;
a summer for summing the comparison signals and outputting a summed digital value; and
and a decoder for decoding the summed digital value into a corresponding target delayed digital value. The method of claim 1,
wherein the sequence adjustment circuit rearranges the time thresholds in a sequence in which a timing error of the time thresholds increases to match the target thresholds. The method of claim 1, wherein the first sub-circuit
a multiplier for performing a multiplication operation on a detection signal based on a phase error of the output clock signal and the first digital value;
a first binary-thermometer code converter for outputting the first switching signal by converting the output of the multiplier into a binary-thermometer code;
a first delta-sigma digital-analog converter for performing delta-sigma digital-analog conversion on a first interlocking control signal based on the first digital value; and
and a first low-pass filter that low-pass filters the output of the first delta-sigma digital-to-analog converter and provides the first control voltage as the first control voltage. 11. The method of claim 10, wherein the second sub-circuit
an accumulator for accumulating the first digital value;
a second binary-thermometer code converter for converting the output of the accumulator into a binary-thermometer code and outputting the second switching signal;
a second delta-sigma digital-analog converter for performing delta-sigma digital-analog conversion on a second interlocking control signal based on the first digital value; and
and a second low-pass filter configured to low-pass filter an output of the second delta-sigma digital-to-analog converter to provide the second control voltage. 12. The method of claim 11,
interlocking control logic for generating the first interlocking control signal and the second interlocking control signal based on the first digital value; and
and a phase error correction logic detecting a phase error of the output clock signal and correcting the detected phase error to generate the detection signal. The method of claim 1,
and a third sub-circuit for generating control codes for controlling capacitor banks and varactors included in the digitally controlled oscillator based on a phase difference between the reference clock signal and the divided clock signal. a buffer for generating a reference clock signal having a first frequency;
a digital phase locked loop circuit for generating an output clock signal having a second frequency based on the reference clock signal; and
a plurality of subsystems operating based on the output clock signal;
The digital phase locked loop circuit is
Optimal interval time for outputting a first digital value including a sign indicating quantized timing errors between the reference clock signal and the divided clock signal by comparing the reference clock signal and the divided clock signal by which the output clock signal is divided - digital converter;
a digitally-controlled oscillator for generating the output clock signal;
a first sub-circuit for generating a first switching signal and a first control voltage based on the first digital value;
a second sub-circuit for generating a second switching signal and a second control voltage based on the first digital value;
a first hybrid switched capacitor circuit that stores the first control voltage and provides the first control voltage to the digital-controlled oscillator in response to the first switching signal;
a second hybrid switched capacitor circuit that stores the second control voltage and provides the second control voltage to the digital-controlled oscillator in response to the second switching signal; and
Based on the divided clock signal and the first digital value, time thresholds for controlling the quantized timing errors are rearranged based on target thresholds, and delay weights based on the rearranged time thresholds are calculated. a sequence control circuit provided to the optimal interval time-to-digital converter;
wherein the digital-controlled oscillator adjusts a frequency of the output clock signal based on the first control voltage and the second control voltage. 15. The method of claim 14,
The optimal interval time-to-digital converter is
a plurality of time-to-digital converters delaying the divided clock signal by a corresponding one of the time thresholds;
a plurality of bang-bang phase detectors comparing a phase of the reference clock signal with a phase of each of the outputs of the plurality of time-digital converters and outputting individual digital values representing the phase difference; and
a summer for summing the individual digital values and outputting the first digital value;
The sequence control circuit is
a plurality of delay weight generators that quantize each of the individual digital values and generate the delay weight values, respectively, based on an average delay digital value and target delay support values generated by sampling the quantized individual digital values; and
and sequence reordering logic to generate the target delay weight values based on the average delay digital values. A method of operating a digital phase locked loop circuit, comprising:
In the optimal interval time-to-digital converter, a divided clock signal obtained by dividing a reference clock signal having a first frequency and an output clock signal having a second frequency is compared to eliminate quantized timing errors between the reference clock signal and the divided clock signal. generating a first digital value comprising a sign representing;
generating a first control voltage based on the first digital value;
generating a second control voltage based on the first digital value;
generating the output clock signal based on the first control voltage and the second control voltage in a digitally controlled oscillator;
rearranging, in a sequence calibration circuit, time thresholds associated with the timing errors based on the divided clock signal and the first digital value; and
and adjusting, in the optimal interval time-to-digital converter, the quantized timing errors based on the rearranged time thresholds.

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