KR102481711B1 - Digital phase locked-loop circuit, system-on chip including the same and method of operating the same - Google Patents

Abstract

A digital phase-locked loop circuit according to an embodiment of the present invention includes an optimal interval time-to-digital converter, a digitally controlled oscillator, a first sub-circuit, a second sub-circuit, a first hybrid switched capacitor circuit, and a second hybrid switched capacitor circuit and sequence. It includes a calibration circuit. The optimum interval time-to-digital converter compares a divided clock signal obtained by dividing a reference clock signal having a first frequency and an output clock signal having a second frequency, and detects quantized timing errors between the reference clock signal and the divided clock signal. and outputs a first digital value including a sign. The digitally controlled oscillator generates the output clock signal. The first sub-circuit generates a first switching signal and a first control voltage based on the first digital value. The second sub-circuit generates a second switching signal and a second control voltage based on the first digital value. The first hybrid switched capacitor circuit stores the first control voltage and provides the first control voltage to the digitally controlled oscillator in response to the first switching signal. The second hybrid switched capacitor circuit stores the second control voltage and provides the second control voltage to the digital control oscillator in response to the second switching signal. The sequence calibration circuit adjusts the time threshold values so that the time threshold values related to the quantized timing errors converge to target threshold values based on the divided clock signal and the first digital value, and the adjusted time threshold values delay weight values based on the values are provided to the optimal interval time-to-digital converter. The digitally controlled oscillator adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage.

Description

Digital phase locked-loop circuit, system-on-chip including the same and method of operating the same

The present invention relates to a digital phase-locked loop, and more particularly, to a digital phase-locked loop with improved signal characteristics, a system-on-chip including the same, and a method of operating the digital phase-locked loop.

A phase-locked loop (PLL) is a control circuit that generates an output clock signal having a phase related to the phase of an input clock signal. Phase-locked loops can generate system clocks used in a variety of digital products. As an example of the phase-locked loop, a digital phase-locked loop (DPLL) based on digital control may be used. In a digital phase locked loop (DPLL), performance degradation may occur due to jitter or signal noise.

Accordingly, one object of the present invention is to provide a digital phase-locked loop circuit capable of reducing dynamic range and reducing jitter at high frequencies.

One object of the present invention is to provide a system-on-chip including the digital phase-locked loop circuit.

One object of the present invention is to provide a method of operating a digital phase-locked loop circuit capable of reducing dynamic range and reducing jitter at high frequencies.

A digital phase-locked loop circuit according to an embodiment of the present invention for achieving the above object is an optimal interval time-to-digital converter, a digitally controlled oscillator, a first sub-circuit, a second sub-circuit, a first hybrid switched capacitor circuit, a 2 hybrid switched capacitor circuit and sequence calibration circuit. The optimum interval time-to-digital converter compares a divided clock signal obtained by dividing a reference clock signal having a first frequency and an output clock signal having a second frequency, and detects quantized timing errors between the reference clock signal and the divided clock signal. and outputs a first digital value including a sign. The digitally controlled oscillator generates the output clock signal. The first sub-circuit generates a first switching signal and a first control voltage based on the first digital value. The second sub-circuit generates a second switching signal and a second control voltage based on the first digital value. The first hybrid switched capacitor circuit stores the first control voltage and provides the first control voltage to the digitally controlled oscillator in response to the first switching signal. The second hybrid switched capacitor circuit stores the second control voltage and provides the second control voltage to the digital control oscillator in response to the second switching signal. The sequence calibration circuit adjusts the time threshold values so that the time threshold values related to the quantized timing errors converge to target threshold values based on the divided clock signal and the first digital value, and the adjusted time threshold values delay weight values based on the values are provided to the optimal interval time-to-digital converter. The digitally controlled oscillator adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage.

A system-on-chip according to embodiments of the present invention for achieving the above object includes a buffer, a digital phase-locked loop circuit, and a plurality of subsystems. The buffer generates a reference clock signal having a first frequency. The digital phase-locked loop circuit generates an output clock signal having a second frequency based on the reference clock signal. The plurality of subsystems operate based on the output clock signal. The digital phase-locked loop circuit includes an optimal interval time-to-digital converter, a digitally controlled oscillator, a first sub-circuit, a second sub-circuit, a first hybrid switched capacitor circuit, a second hybrid switched capacitor circuit and a sequence calibration circuit. The optimal interval time-to-digital converter compares the reference clock signal and a divided clock signal obtained by dividing the output clock signal, and indicates quantized timing errors between the reference clock signal and the divided clock signal. output a digital value. The digitally controlled oscillator generates the output clock signal. The first sub-circuit generates a first switching signal and a first control voltage based on the first digital value. The second sub-circuit generates a second switching signal and a second control voltage based on the first digital value. The first hybrid switched capacitor circuit stores the first control voltage and provides the first control voltage to the digitally controlled oscillator in response to the first switching signal. The second hybrid switched capacitor circuit stores the second control voltage and provides the second control voltage to the digital control oscillator in response to the second switching signal. The sequence calibration circuit adjusts the time threshold values so that the time threshold values related to the quantized timing errors converge to target threshold values based on the divided clock signal and the first digital value, and the adjusted time threshold values delay weight values based on the values are provided to the optimal interval time-to-digital converter. The digitally controlled oscillator adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage.

In an optimal interval time-to-digital converter, a reference clock signal having a first frequency and an output clock signal having a second frequency are provided in an operating method of a digital phase-locked loop circuit according to embodiments of the present invention for achieving the above object. comparing the divided divided clock signals to generate a first digital value including a sign indicating quantized timing errors between the reference clock signal and the divided clock signal; and a first control voltage based on the first digital value generate a second control voltage based on the first digital value, generate the output clock signal based on the first control voltage and the second control voltage in a digital control oscillator, and in a sequence calibration circuit , Rearranging time thresholds related to the timing errors based on the divided clock signal and the first digital value, and performing the quantization based on the rearranged time thresholds in the optimum interval time-to-digital converter. correct timing errors.

In the digital phase-locked loop and its operating method according to embodiments of the present invention, the digital phase-locked loop circuit includes an optimal interval time-to-digital converter and a sequence control circuit, and in the sequence control circuit, the optimal interval time-to-digital converter is included An output clock signal may be generated while reducing a dynamic range and jitter by adjusting time threshold values of a plurality of time-to-digital converters.

1 is a block diagram illustrating a digital phase-locked loop circuit according to embodiments of the present invention.
FIG. 2 shows an optimal interval time-to-digital converter and a sequence calibration circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.
3 is a circuit diagram showing a configuration of one of the time-to-digital converters of FIG. 2 according to embodiments of the present invention.
FIG. 4 shows a pair of corresponding time-to-digital converters and bang-bang phase detectors in the optimum interval time-to-digital converter of FIG. 2 according to embodiments of the present invention.
FIG. 5 shows a phase difference between a reference clock signal and a divided clock signal in FIG. 4 .
FIG. 6 shows individual digital values according to the phase difference between the reference clock signal and the divided clock signal in FIG. 4 .
7 is a graph showing a relationship between a timing error and a first digital value.
8 shows a sequence adjusting circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.
9 is a block diagram illustrating the configuration of sequence rearrangement logic in the sequence control circuit of FIG. 8 according to embodiments of the present invention.
10 is an example of adjusting time threshold values without using a sequence rearrangement scheme.
11 is an example of adjusting time threshold values without using a sequence rearrangement scheme.
12 is an example of adjusting time threshold values without using a sequence rearrangement scheme.
13 is an example illustrating a case in which a sequence rearrangement scheme is applied according to embodiments of the present invention.
14 shows the probability that time thresholds are all matched to target thresholds in a given dynamic range when the sequence rearrangement scheme according to embodiments of the present invention is not applied.
15 shows the probability that time thresholds are all matched to target thresholds in a given dynamic range when a sequence rearrangement scheme according to embodiments of the present invention is applied.
16 is a block diagram illustrating a system-on-a-chip to which a digital phase-locked loop according to embodiments of the present invention can be applied.
17 is a flowchart illustrating an operating method of a digital phase-locked loop circuit according to embodiments of the present invention.

For the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of explaining the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms and the text It should not be construed as being limited to the embodiments described above.

Since the present invention may have various changes and various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Similar reference numerals have been used for components while describing each figure.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as "comprise" or "having" are intended to indicate that the described feature, number, step, operation, component, part, or combination thereof exists, but that one or more other features or numbers are present. However, it should be understood that it does not preclude the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, they should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a block diagram illustrating a digital phase-locked loop circuit according to embodiments of the present invention.

Referring to FIG. 1, the digital phase locked loop circuit 10) includes an optimal interval time-to-digital converter (OS TDC, 100), a sequence calibration circuit 200, a coarse phase detector 300, an interlocking control logic 310, and a phase error Correction logic 320, first sub-circuit 330, second sub-circuit 340, third sub-circuit 350, first hybrid switched capacitor circuit 420, second hybrid switched capacitor circuit 430, It may include a divider 360 and a ring-type digitally controlled oscillator (RDCO 500, hereinafter 'digitally controlled oscillator').

The optimal interval time-to-digital converter 100 compares a reference clock signal SREF having a first frequency and a divided clock signal SDIV obtained by dividing an output clock signal SOUT having a second frequency, and compares the reference clock signal ( SREF) and the divided clock signal SIIV, the first digital value DTDC representing quantized timing errors including a sign may be output.

The digitally controlled oscillator 500 may generate an output clock signal SOUT. The divider 360 may divide the frequency of the output clock signal SOUT to generate the divided clock signal SDIV.

The first sub-circuit 330 may generate a first switching signal DP and a first control voltage VKP based on the first digital value DTDC. The second sub-circuit 340 may generate a second switching signal DI and a second control voltage VKI based on the first digital value DTDC. The first sub-circuit 330 may correspond to a proportional path.

The first hybrid switched capacitor circuit 420 stores the first control voltage VKP and selectively provides the first control voltage VKP to the digital control oscillator 500 in response to the first switching signal DP. can The first hybrid switched capacitor circuit 420 may include a variable capacitor 421 connected to a ground voltage and a switch 423 connected between the variable capacitor 421 and the digitally controlled oscillator 500 . The variable capacitor 421 may store the first control voltage VKP, and the switch 423 may switch the first control voltage VKP to the digital control oscillator 500 in response to the first switching signal DP. there is.

The second hybrid switched capacitor circuit 430 stores the second control voltage VKI and selectively provides the second control voltage VKI to the digital control oscillator 500 in response to the second switching signal DI. can The second hybrid switched capacitor circuit 430 may include a variable capacitor 431 connected to a ground voltage and a switch 433 connected between the variable capacitor 431 and the digitally controlled oscillator 500 . The variable capacitor 431 may store the second control voltage VKI, and the switch 433 may switch the second control voltage VKI to the digital control oscillator 500 in response to the second switching signal DI. there is. The digital control oscillator 500 may adjust the frequency of the output clock signal SOUT based on the first control voltage VKP and the second control voltage VKI.

The first hybrid switched capacitor circuit 420 and the second hybrid switched capacitor circuit 430 store the first control voltage VKP and the second control voltage VKI and provide them to the digital control oscillator 500, thereby providing digital control. The oscillator 500 can immediately respond to the first control voltage VKP and the second control voltage VKI.

The sequence calibration circuit 200 rearranges the time threshold values for controlling the quantized timing errors based on the divided clock signal SDIV and the first digital value DTDC based on target threshold values and rearranges the Delay weight values DCW based on the determined time threshold values may be provided to the optimal interval time-to-digital converter 100 .

The interlocking control logic 310 may generate a first interlocking control signal DKP and a second interlocking control signal DKI based on the first digital value DTDC. The phase error correction logic 320 may detect a phase error of the output clock signal SOUT and correct the detected phase error to generate the detection signal SFPEC. The detection signal SFPEC may have digital values of '0' and '1'.

The first sub-circuit 330 may include a multiplier 331, a first binary-thermometer code converter (B2T, 332), a first delta-sigma digital-to-analog converter 333, and a first low pass filter 334. can

The multiplier 331 may perform a multiplication operation on the detection signal SFPEC and the first digital value DTDC. The first binary-thermometer code converter 330 may convert the output of the multiplier 331 to a binary-thermometer code and output the first switching signal DP. The first delta-sigma digital-analog converter 333 may perform delta-sigma digital-analog conversion on the first interlocking control signal DKP. The first low pass filter 334 may provide a first control voltage VKP by low pass filtering the output of the first delta-sigma digital-to-analog converter 333 .

The second sub-circuit 340 may include an accumulator 341, a second binary-thermometer code converter 342, a second delta-sigma digital-to-analog converter 343, and a second low pass filter 344. . The second sub-circuit 340 may correspond to an integration path.

The accumulator 341 may accumulate the first digital value DTDC. The second binary-thermometer code converter 342 may convert the output of the accumulator 341 to a binary-thermometer code and output the second switching signal DI. The second delta-sigma digital-analog converter 343 may perform delta-sigma digital-analog conversion on the second interlocking control signal DKI. The second low pass filter 344 may provide a second control voltage VKI by low pass filtering the output of the second delta-sigma digital-to-analog converter 353 .

The coarse phase detector 300 detects a phase difference between the reference clock signal SREF and the divided clock signal SDIV.

The third sub-circuit 350 includes a limiter 351, an operator 352, a summer 353, an accumulator 354, a third delta-sigma digital-to-analog converter 355, and a third low pass filter 356. , a register 357 and a summer 358. The third sub-circuit 350 may correspond to a frequency acquisition path.

The limiter 351 limits the output of the accumulator 341 and provides it to the adder 353. The operator 352 multiplies the output of the coarse phase detector 300 by a power of 2 (2 ¹⁷ ) and provides the result to the adder 353. The adder 353 sums the output of the limiter 351 and the output of the operator 352. Accumulator 354 accumulates the output of summer 354. The output of the accumulator 354 may be provided as control codes for controlling the capacitor banks included in the digitally controlled oscillator 500 .

The third delta-sigma digital-to-analog converter 355 may perform delta-sigma digital-to-analog conversion on the output of the accumulator 354 . The low pass filter 356 may low pass filter the output of the third delta-sigma digital-to-analog converter 355 . An output of the low pass filter 356 may be provided as control codes for controlling varactors included in the digital control oscillator 500 .

Register 357 can store high level data. The summer 358 may sum the output of the coarse phase detector 300 and the high level data. The output of the summer 358 may be provided as control codes for controlling the capacitor banks included in the digitally controlled oscillator 500 .

The sequence calibration circuit 200 controls the time threshold so that the time threshold values related to the quantized timing errors converge to target threshold values based on the divided clock signal SDIV and individual digital values included in the first digital value. Values may be adjusted, and delay weight values DCW based on the adjusted time threshold values may be provided to the optimal interval time-to-digital converter 100 .

FIG. 2 shows an optimal interval time-to-digital converter and a sequence calibration circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 2, the optimal interval time-to-digital converter 100 includes a plurality of time-to-digital converters 110a to 110g, where g is a natural number of 3 or greater, a plurality of bang-bang phase detectors (BBPD) 130a to 130g, and A summer 150 may be included.

The plurality of time-to-digital converters 110a to 110g perform time-to-digital conversion on the divided clock signal SDIV, respectively, and convert the clock signal SDIV divided by the corresponding time threshold value among the time threshold values. can delay

Each of the bang bang phase detectors 130a to 130g compares the phase of the reference clock signal SREF with the phase of the output of each of the time-to-digital converters 110a to 110g, and generates individual digital values DSGN_0 to indicate a corresponding phase difference. DSGN_6) can be output. Each of the individual digital values DSGN_0 to DSGN_6 may have a value of (-1) or (+1) according to a phase difference.

The summer 150 may sum the individual digital values DSGN_0 to DSGN_6 and output the first digital value DTDC.

The sequence calibration circuit 200 receives individual digital values DSGN_0 to DSGN_6 provided from the bang-bang phase detectors 130a to 130g, and based on the individual digital values DSGN_0 to DSGN_6, time threshold values are determined as target threshold values. The time threshold values are adjusted to converge to , delay weight values DCW_0 to DCW_6 are generated based on the adjusted time threshold values, and the delay weight values DCW_0 to DCW_6 are converted to time-to-digital converters ( 110a to 110g) can be provided to each. The sequence calibration circuit 200 quantizes the individual digital values DSGN_0 to DSGN_6, and calculates the delay weight values DCW_0 to DCW_0 to target delay digital values based on an average delay digital value generated by sampling the quantized individual digital values. DCW_6) can be created.

The time-to-digital converters 110a to 110g may adjust time threshold values based on a corresponding delay weight value among the delay weight values DCW_0 to DCW_6, respectively.

3 is a circuit diagram showing a configuration of one of the time-to-digital converters of FIG. 2 according to embodiments of the present invention.

3 shows the configuration of the time-to-digital converter 110a, the configuration of each of the time-to-digital converters 110b to 110g may be the same as that of the time-to-digital converter 110a.

Referring to FIG. 3, the time-to-digital converter 110a includes a first inverter 111, a second inverter 112 connected to the first inverter 112, and the first inverter 111 and the second inverter 112. It may include a plurality of MOS capacitors (121 to 12p, where p is a natural number of 3 or more) connected in parallel therebetween.

The plurality of MOS capacitors 121 to 12p may store the delay weight value DCW_0 in a binary weighted form (DCW_0[0] to DCW_0[7]).

The inverter 111 inverts the input (IN) corresponding to the divided clock signal (SDIV), and the inverter 112 inverts the output of the inverter 111 and provides it as an output (OUT). That is, the time-to-digital converter 110a may delay and output the divided clock signal SDIV by the delay weight value DCW_0.

FIG. 4 shows a pair of corresponding time-to-digital converters and bang-bang phase detectors in the optimum interval time-to-digital converter of FIG. 2 according to embodiments of the present invention.

Referring to FIG. 4, the time-to-digital converter (DTCk) has a variable time threshold (TTH_k) and converts the divided clock signal (SDIV) into a digital signal. The bang-bang phase detector BBPD compares the phase of the reference clock signal SREF with the phase of the divided clock signal SDIV based on the output of the time-to-digital converter DTCk, and calculates the phase of the reference clock signal SREF and the divided clock An individual digital value DSGN_k representing the phase difference of the signal SDIV as a code may be output. The individual digital value DSGN_k may have a value of (+1) or (−1) according to a phase difference between the phase of the reference clock signal SREF and the phase of the divided clock signal SDIV.

FIG. 5 shows a phase difference between a reference clock signal and a divided clock signal in FIG. 4 .

Referring to FIG. 5, when the phase of the reference clock signal SREF is faster than the phase of the divided clock signal SDIV, a timing error corresponding to a difference between the phase of the reference clock signal SREF and the divided clock signal SDIV TERR) has a positive value.

FIG. 6 shows individual digital values according to the phase difference between the reference clock signal and the divided clock signal in FIG. 4 .

Referring to FIG. 6 , when the timing error TERR is greater than the time threshold value TTH_k, the individual digital value DSGN_k has a value of (+1), and the timing error TERR is less than the time threshold value TTH_k. At this time, the individual digital value (DSGN_k) has a (-1) value.

7 is a graph showing a relationship between a timing error and a first digital value.

In FIG. 7, TTH_0 to TTH_6 represent time threshold values of each of the time-to-digital converters 110b to 110g, and TTRG_0 to TTRG_6 represent target threshold values of each of the time-to-digital converters 110b to 110g. Target threshold values (TTRG_0 to TTRG_6) can be found by the Lloyd-Max algorithm.

Also, □ represents a value corresponding to 0.5 of the variance of the timing error TERR, and Δ represents a value corresponding to 0.5 of the variance of the timing error TERR.

Referring to FIG. 7 , it can be seen that the first digital value DTDC increases as the timing error TERR increases.

8 shows a sequence adjusting circuit in the digital phase-locked loop circuit of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 8 , the sequence adjusting circuit 200 may include a plurality of delay weight generators 210a to 210g, a divider 220, and a sequence rearrangement logic 230.

The delay weight generators 210a to 210g quantize individual digital values DSGN_0 to DSGN_6, respectively, and generate delay weight values (based on an average delay digital value generated by sampling the quantized individual digital values and target delay digital values). DCW_0 to DCW_6) can be created respectively.

The divider 220 divides the divided clock signal SDIV and provides a first divided clock signal SDIV1 to each of the delay weight generators 210a to 210g.

The sequence rearrangement logic 230 may generate target delay weight values DTRG_0 to DTRG_6 based on the average delay digital values DAVG_0 to DAVG_6.

The delay weight generator 210a may include a quantizer 211 , a sample/hold circuit 212 , an operator 213 and an accumulator 214 .

The quantizer 211 quantizes the individual digital value DSGN_1, and the sample/hold circuit 212 samples and holds the output of the quantizer 211 in synchronization with (based on) the first divided clock signal SDIV1. (averaged) to generate the average delay digital value (DAVG_0).

The calculator 213 may subtract the target delay weight value DTRG_0 from the average delay digital value DAVG_0, and the accumulator 214 may generate the delay weight value DCW_0 by accumulating outputs of the calculator 213.

Although the configuration of the delay weight generator 210a is shown in FIG. 8, the configuration of each of the delay weight generators 210b to 210g may be the same as that of the delay weight generator 210a.

9 is a block diagram illustrating the configuration of sequence rearrangement logic in the sequence control circuit of FIG. 8 according to embodiments of the present invention.

Referring to FIG. 9, the sequence rearrangement logic 230 includes a plurality of unit circuits (DTRG_k, where k is 0 to 6), respectively, based on the average delay digital values DAVG_0 to DAVG_6. 240a ~ 240g) may be included.

The unit circuit 240a calculates the modulo operation result (DAVG_mod[k, 7]) of the average delay digital value associated with the unit circuit 240a among the average delay digital values and the average digital value associated with the other unit circuits 240b to 240g. A plurality of comparators 251 to 257 outputting comparison signals CS1 to CS7 by comparing modulo operation results of values (DAVG_mod[k+1, 7] to DAVG_mod[k+6, 7]), respectively , A summer 260 summing the comparison signals CS1 to CS7 and outputting a sum digital value DSUM_0, and a decoder 270 decoding the sum digital value DSUM_0 into a corresponding target delay digital value DTRG_0. can include

The sum digital value DSUM_k and the corresponding target delay digital value DTRG_k may be stored in the decoder 270 in the form of a mapping table.

10 is an example of adjusting time threshold values without using a sequence rearrangement scheme.

In FIG. 10, reference numeral 611 indicates that the time threshold values TTH_0 to TTH_6 have the same timing error TERR, and reference numeral 612 indicates that the target threshold values TTRG_0 to TTRG_6 have different delays. indicates that you have

That is, when the time threshold values TTH_0 to TTH_6 have the same timing error TERR, the time-to-digital converters 110a to 110g of FIG. 2 may generate the same delay with respect to the divided clock signal SDIV. there is.

11 is an example of adjusting time threshold values without using a sequence rearrangement scheme.

In FIG. 11, reference numeral 621 indicates that time threshold values TTH_0 to TTH_6 have the same timing error TERR at the time of design, and reference numeral 622 indicates that time-to-digital converters 110a to 110g ) indicates that the timing errors (TERR) of the time threshold values (TTH_0 to TTH_6) are randomly distributed when actually manufactured, and reference numeral 623 indicates that the target threshold values (TTRG_0 to TTRG_6) have different delays. indicates that there is

That is, in the case of FIG. 11 , even if the time thresholds TTH_0 to TTH_6 have the same timing error TERR, the time-to-digital converters 110a to 110g of FIG. 2 are mutually dependent on the divided clock signal SDIV. You can create other delays.

12 is an example of adjusting time threshold values without using a sequence rearrangement scheme.

12 is an example of adjusting time threshold values without using a sequence rearrangement scheme.

In FIG. 12, reference numeral 631 indicates that the time thresholds TTH_0 to TTH_6 have the same timing error TERR at the time of design, and reference numeral 632 indicates that time-to-digital converters 110a to 110g ) indicates that the timing errors (TERR) of the time thresholds (TTH_0 to TTH_6) are randomly distributed when actually manufactured, and reference numeral 633 indicates that the time thresholds (TTH_0 to TTH_6) are in a predetermined order. It indicates matching with the target threshold values (TTRG_0 to TTRG_6) in the order of the time threshold values (TTH_0 to TTH_6). In this case, the target threshold value (TTH_0) has the largest timing error (TERR) and the target threshold value (TTH_6) has the smallest timing error (TERR). To cover this, the time-to-digital converters 110a ~110g) should increase very much.

13 is an example illustrating a case in which a sequence rearrangement scheme is applied according to embodiments of the present invention.

In FIG. 13, reference numeral 641 indicates that time threshold values TTH_0 to TTH_6 have the same timing error TERR at the time of design, and reference numeral 642 indicates that time-to-digital converters 110a to 110g ) indicates that the timing errors (TERR) of the time threshold values (TTH_0 to TTH_6) are randomly distributed, and reference numeral 633 indicates that the time threshold values (TTH_0 to TTH_6) are the timing error (TERR) It indicates matching with the target threshold values (TTRG_0 to TTRG_6) regardless of the order of the time threshold values (TTH_0 to TTH_6) according to the size of . In this case, the target threshold value (TTH_0) has the largest timing error (TERR), and the target threshold value (TTH_6) has the smallest timing error (TERR), in order of increasing timing error (TERR). Since the target threshold values TTRG_0 to TTRG_6 are matched, the dynamic range of the time-to-digital converters 110a to 110g can be reduced.

14 shows the probability that time thresholds are all matched to target thresholds in a given dynamic range when the sequence rearrangement scheme according to embodiments of the present invention is not applied.

Referring to FIG. 14, a dynamic range of about 6.31 ps is required to properly operate in a dynamic lane corresponding to three times the standard deviation. In FIG. 14, P represents a matching probability.

15 shows the probability that time thresholds are all matched to target thresholds in a given dynamic range when a sequence rearrangement scheme according to embodiments of the present invention is applied.

Referring to FIG. 15, a dynamic range of about 2.66 ps is required to properly operate in a dynamic lane corresponding to three times the standard deviation. Therefore, when the time thresholds of the time-to-digital converters 110a to 110g are adjusted by rearranging the time thresholds according to embodiments of the present invention, the dynamic range of the time-to-digital converters 110a to 110g is reduced. know you can do it. In FIG. 15, P represents a matching probability.

16 is a block diagram illustrating a system-on-a-chip to which a digital phase-locked loop according to embodiments of the present invention can be applied.

Referring to FIG. 16 , a system-on-a-chip (SoC) may include a buffer 710, a digital phase locked loop 720 (ADPLL), a plurality of subsystems 741 to 743, and a divider 730. .

The buffer 710 buffers an output signal of the crystal-oscillator 701 that may be provided outside the SoC 700 to generate a reference clock signal SREF. Digital phase-locked loop 720 may employ digital phase-locked loop 10 of FIG. Accordingly, the digital phase-locked loop circuit 720 includes an optimum interval time-to-digital converter and a sequence control circuit, and the sequence control circuit adjusts time thresholds of a plurality of time-to-digital converters included in the optimum interval time-to-digital converter. Thus, the output clock signal SOUT can be generated while reducing the dynamic range and jitter.

Each of the plurality of subsystems 741 to 7443 may operate in response to the output clock signal SOUT, and the divider 730 divides the output clock signal SOUT according to a predetermined division ratio and divides the divided The clock signal DSOUT may be provided to at least one subsystem 743 . Each of the plurality of subsystems 741 to 743 may represent hardware or circuitry that operates using the output clock signal SOUT or a signal related to the output clock signal SOUT.

For example, the subsystem 741 may be a Central Processing Unit (CPU), a processor, or an Application Processor (AP), the subsystem 742 may be a Graphic Processing Unit (GPU), and the subsystem 743 may be may be a memory device or a memory controller.

Meanwhile, each of the plurality of subsystems 741 to 743 may be an IP (Intellectual Property). IP is a function block used in the SoC 700, and includes a CPU, a processor, each core of a multi-core processor, a memory device, a universal serial bus (USB), and a peripheral component interconnect (PCI). ), digital signal processor, wired interface, wireless interface, controller, embedded software, codec, video module (eg, camera interface, JPEG processor, video processor or Mixer, etc.), 3D graphic core, audio system or driver. Also, the SoC 700 may represent part of an AP or part of a mobile AP.

17 is a flowchart illustrating an operating method of a digital phase-locked loop circuit according to embodiments of the present invention.

1 to 15 and 17, an optimal interval time-to-digital converter 100, a sequence calibration circuit 200, a first sub-circuit 330, a second sub-circuit 340, a first hybrid switched capacitor In the operating method of the digital phase-locked loop circuit 10 including the circuit 420, the second hybrid switched capacitor circuit 430 and the digitally controlled oscillator 500, the first in the optimal interval time-to-digital converter 100 The reference clock signal SREF having a frequency and the divided clock signal SDIV obtained by dividing the output clock signal SOUT having a second frequency are compared to determine the difference between the reference clock signal SREF and the divided clock signal SIIV. A first digital value DTDC representing quantized timing errors and including a sign is generated (S110).

The first sub-circuit 330 generates a first control voltage VKP based on the first digital value DTDC (S120) and applies the first control voltage VKP to the first hybrid switched capacitor circuit 420. Save.

The second control voltage VKI is generated based on the first digital value DTDC in the second sub-circuit 340 (S130), and the second control voltage VKI is applied to the second hybrid switched capacitor circuit 430. Save.

The digital control oscillator 500 generates an output clock signal SOUT based on the first control voltage VKP and the second control voltage VKI (S140) and adjusts the frequency of the output clock signal SOUT.

The sequence calibration circuit 200 rearranges time threshold values for controlling the quantized timing errors based on the divided clock signal SDIV and the first digital value DTDC based on target threshold values (S150). .

The quantized timing errors are adjusted based on the rearranged time threshold values in the optimal interval time-to-digital converter 100 (S160).

Therefore, in the digital phase-locked loop and its operating method according to embodiments of the present invention, the digital phase-locked loop circuit includes an optimal interval time-to-digital converter and a sequence control circuit, and is included in the optimal interval time-to-digital converter in the sequence control circuit. An output clock signal may be generated while reducing a dynamic range and jitter by adjusting time threshold values of a plurality of time-to-digital converters.

Embodiments of the present invention are employed in various wireless communication devices, can perform frequency disturbance correction and noise correction of an output clock signal separately, and can perform a falling edge of a non-uniform clock signal for an arbitrary multiplication factor can align to the zero crossing of the output clock signal, reducing the loss of frequency resolution in a wide lock-in range while reducing power consumption.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the claims below. You will understand that it can be done.

Claims (16)

A first reference clock signal having a first frequency and a divided clock signal obtained by dividing an output clock signal having a second frequency and comparing the divided clock signal to indicate quantized timing errors between the reference clock signal and the divided clock signal. an optimal interval time-to-digital converter that outputs a digital value;
a digitally controlled oscillator generating the output clock signal;
a first sub-circuit generating a first switching signal and a first control voltage based on the first digital value;
a second sub-circuit generating a second switching signal and a second control voltage based on the first digital value;
a first hybrid switched capacitor circuit for storing the first control voltage and providing the first control voltage to the digital control oscillator in response to the first switching signal;
a second hybrid switched capacitor circuit for storing the second control voltage and providing the second control voltage to the digital control oscillator in response to the second switching signal; and
The time threshold values are adjusted so that the time threshold values related to the quantized timing errors converge to target threshold values based on the divided clock signal and the first digital value, and a delay based on the adjusted time threshold values a sequence calibration circuit providing weight values to the optimal interval time-to-digital converter;
The digital controlled oscillator adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage. The method of claim 1, wherein the optimal interval time-to-digital converter
a plurality of time-to-digital converters delaying the divided clock signal by a corresponding one of the time threshold values;
a plurality of bang bang phase detectors comparing the phase of the reference clock signal with the phase of each output of the plurality of time-to-digital converters and outputting individual digital values representing the phase difference; and
and an adder configured to sum the individual digital values and output the first digital value. The method of claim 2, wherein each of the plurality of time-to-digital converters
a first inverter inverting the divided clock signal;
a second inverter inverting an output of the first inverter and outputting one of the delayed divided clock signals;
It is connected between the first inverter and the output terminal and the input terminal of the second inverter,
A digital phase locked loop circuit comprising a plurality of MOS capacitors for storing a corresponding delay weight value among the delay weight values in a binary weighted form. 3. The method of claim 2, wherein each of the bang bang phase detectors
A digital phase locked loop circuit outputting the individual digital value as one of (-1) and (+1) based on a comparison between the phase of the reference clock signal and the phase of a corresponding delayed divided clock signal among the delayed divided clock signals. . 3. The method of claim 2, wherein the sequence calibration circuit
a plurality of delay weight generators that quantize each of the individual digital values and generate the delay weight values based on an average delay digital value and target delay digital values generated by sampling the quantized individual digital values; and
and sequence rearrangement logic to generate the target delay weight values based on the average delay digital values. According to claim 5,
Each of the plurality of delay weight generators
a quantizer outputting a quantized individual digital value by quantizing a corresponding individual digital value among the individual digital values;
a sample/hold circuit averaging the quantized individual digital values based on a first divided clock signal obtained by dividing the divided clock signal and outputting the average delayed digital value;
an operator subtracting a corresponding target delay digital value from among the target delay digital values from the average delay digital value; and
and an accumulator configured to accumulate outputs of the calculator and output a corresponding delay weight value among the delay weight values. 6. The method of claim 5, wherein the sequence rearrangement logic
and a plurality of unit circuits each generating the target delay digital values based on the average delay digital values. The method of claim 7, wherein each of the plurality of unit circuits
a plurality of comparators for outputting comparison signals by comparing a result of a modulo operation of a corresponding average delay digital value among the average delay digital values with a result of a modulo operation of average delay digital values related to other unit circuits;
an adder summing the comparison signals and outputting a summed digital value; and
and a decoder for decoding the sum digital value into a corresponding target delay digital value. According to claim 1,
The sequence calibration circuit rearranges the time threshold values in a sequence in which timing errors of the time threshold values increase to match the target threshold values. The method of claim 1, wherein the first sub-circuit
a multiplier performing a multiplication operation on the detection signal based on the phase error of the output clock signal and the first digital value;
a first binary-thermometer code converter converting an output of the multiplier to a binary-thermometer code and outputting the first switching signal;
a first delta-sigma digital-analog converter performing delta-sigma digital-analog conversion on a first interlocking control signal based on the first digital value; and
and a first low-pass filter for low-pass filtering an output of the first delta-sigma digital-to-analog converter and providing the first control voltage. 11. The method of claim 10, wherein the second sub-circuit
an accumulator accumulating the first digital value;
a second binary-thermometer code converter converting the output of the accumulator into a binary-thermometer code and outputting the second switching signal;
a second delta-sigma digital-analog converter performing delta-sigma digital-analog conversion on a second interlocking control signal based on the first digital value; and
and a second low-pass filter for low-pass filtering an output of the second delta-sigma digital-to-analog converter and providing the second control voltage. According to claim 11,
an interlocking control logic for generating the first interlocking control signal and the second interlocking control signal based on the first digital value; and
and a phase error correction logic for detecting a phase error of the output clock signal and correcting the detected phase error to generate the detection signal. According to claim 1,
and a third sub-circuit generating control codes for controlling capacitor banks and varactors included in the digital control oscillator based on a phase difference between the reference clock signal and the divided clock signal. a buffer generating a reference clock signal having a first frequency;
a digital phase locked loop circuit generating an output clock signal having a second frequency based on the reference clock signal; and
a plurality of subsystems operating based on the output clock signal;
The digital phase locked loop circuit
An optimum interval time for comparing the reference clock signal and the divided clock signal obtained by dividing the output clock signal to output a first digital value including a sign indicating quantized timing errors between the reference clock signal and the divided clock signal. - digital converter;
a digitally-controlled oscillator generating the output clock signal;
a first sub-circuit generating a first switching signal and a first control voltage based on the first digital value;
a second sub-circuit generating a second switching signal and a second control voltage based on the first digital value;
a first hybrid switched capacitor circuit for storing the first control voltage and providing the first control voltage to the digitally-controlled oscillator in response to the first switching signal;
a second hybrid switched capacitor circuit for storing the second control voltage and providing the second control voltage to the digitally-controlled oscillator in response to the second switching signal; and
Time threshold values for controlling the quantized timing errors based on the divided clock signal and the first digital value are rearranged based on target threshold values, and delay weight values based on the rearranged time threshold values are rearranged. A sequence calibration circuit provided to the optimal interval time-to-digital converter;
wherein the digitally-controlled oscillator adjusts the frequency of the output clock signal based on the first control voltage and the second control voltage. According to claim 14,
The optimal interval time-to-digital converter is
a plurality of time-to-digital converters delaying the divided clock signal by a corresponding one of the time threshold values;
a plurality of bang bang phase detectors comparing the phase of the reference clock signal with the phase of each output of the plurality of time-to-digital converters and outputting individual digital values representing the phase difference; and
An adder summing the individual digital values and outputting the first digital value;
The sequence calibration circuit
a plurality of delay weight generators that quantize each of the individual digital values and generate the delay weight values based on an average delay digital value and target delay digital values generated by sampling the quantized individual digital values; and
and sequence rearrangement logic to generate the target delay weight values based on the average delay digital values. As a method of operating a digital phase-locked loop circuit,
In the optimal interval time-to-digital converter, a divided clock signal obtained by dividing a reference clock signal having a first frequency and an output clock signal having a second frequency is compared to determine quantized timing errors between the reference clock signal and the divided clock signal. generating a first digital value comprising a sign;
generating a first control voltage based on the first digital value;
generating a second control voltage based on the first digital value;
generating the output clock signal based on the first control voltage and the second control voltage in a digitally controlled oscillator;
rearranging, in a sequence calibration circuit, time threshold values related to the timing errors based on the divided clock signal and the first digital value; and
and adjusting the quantized timing errors based on the rearranged time thresholds in the optimum interval time-to-digital converter.

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