KR20220021839A - Vertical channel field effect transistor device, ternary CMOS using same, and manufacturing method thereof - Google Patents

Abstract

A vertical channel field effect transistor device according to an embodiment of the present invention comprises: a semiconductor substrate; a drain region formed on a top surface of the semiconductor substrate; a channel region formed on an upper surface of the drain region; a source region formed on an upper surface of the channel region; a gate insulating layer formed on a side surface of the channel; and a gate formed on a side surface of the gate insulating layer, wherein the drain region is highly doped as the distance from the channel region increases.

Description

Vertical channel field effect transistor device, ternary CMOS using same, and manufacturing method thereof

The present invention relates to a vertical channel field effect transistor device, a ternary CMOS using the same, and a manufacturing method thereof.

For high-performance portable electronic products, semiconductor devices are becoming smaller and the degree of integration for implementing complex circuits is increasing. Accordingly, many limitations have been reached in terms of power density problems and process miniaturization of semiconductor devices.

CMOS is an abbreviation of Complementary Metal Oxide Semiconductor, and consists of a circuit in which a P-channel transistor (pMOS) and an N-channel transistor (nMOS) of a general metal oxide semiconductor field effect transistor (MOSFET) are joined. CMOS is a type of integrated circuit used to construct digital circuits such as microprocessors and S-RAM. It has advantages of high integration and very low power consumption, and is used in products such as portable calculators, electronic watches, and small computers.

Conventional CMOS devices have states of 0 and 1 as binary CMOS, and in order to perform complex calculations in binary CMOS, and for miniaturization, the size of a semiconductor chip must be reduced by reducing the size of one device. There is a problem of subtlety.

In order to solve this problem, a ternary CMOS (T-CMOS device or TCMOS) having three states (eg 0, 1, 2) has been introduced as an alternative. The T-CMOS device increases the amount of information that one device can process to three, so that a larger amount of information can be processed with a small number of devices. In fact, compared to the binary system, the number of elements required in the ternary system is reduced to about 63.1%.

1A is a conceptual diagram of a conventional T-CMOS device 10 using a planar MOSFET. 1B is a graph illustrating a drain current according to a gate voltage.

As shown in FIG. 1A, the conventional T-CMOS device 10 using a planar MOSFET is composed of a body and a complementary combination of pMOS and nMOS on the body. In the conventional T-CMOS device 10, a thin, heavily doped delta layer is put between the source and drain of each pMOS and nMOS to induce a tunneling phenomenon between the drain and the body.

In the case of pMOS, the delta layer is heavily doped with n-type, and in the case of nMOS, the delta layer is heavily doped with p-type. In nMOS, holes tunnel from the drain to the body to generate a drain-body tunneling current (I _DB+ ), and in pMOS, electrons tunnel from the drain to the body to generate a tunneling current (I _DB +) of the drain-body junction. _- ) is created.

As shown in FIG. 1B, the conventional T-CMOS device 10 using a planar MOSFET generates a tunneling current of the drain-body junction independent of the gate voltage, thereby creating an intermediate state more unlike the conventional binary CMOS. and implemented the ternary system using this.

However, when designing a T-CMOS device with a conventional planar MOSFET or FinFET, tunneling may occur at the drain-channel junction, and as the device is made smaller to improve integration, this tunneling current becomes more prominent, preventing tunneling independent of the gate voltage. It has a problem that it is difficult to induce.

In addition, in order to reduce standby power (or off current), it is necessary to lower the tunneling current generated in the drain- _body junction in the off state. Tunneling is dominant over tunneling of the drain-body junction, so it is difficult to make a tunneling current independent of the gate voltage.

In addition, the tunneling current of the drain-channel changes according to the gate voltage. If the tunneling current of the drain-channel junction becomes larger than the tunneling current of the drain-body junction independent of the gate voltage, the third state cannot be realized. There is a problem in that it becomes difficult to implement the operation.

In addition, in order not to affect the operation of the T-CMOS device by the tunneling current of the drain-channel, a tunneling current of the drain-body junction that is relatively large enough to ignore the tunneling current of the drain-channel is required. In this case, standby power Due to this increase, there is a problem in that it is difficult to implement a low-power T-CMOS device.

Republic of Korea Patent Publication No. 10-2020-0051508

The present invention can provide a VC-FET device that provides a constant drain-body junction tunneling current regardless of a change in gate voltage.

The present invention can provide a ternary-CMOS in which a new one state is additionally implemented using a VC-FET device.

The present invention can provide a T-CMOS device capable of reducing standby power by reducing the size of an off current while increasing device integration.

The present invention can provide a device that can operate as a ternary inverter even when the tunneling current of the drain-body junction independent of the gate voltage decreases by minimizing the tunneling occurring in the drain-channel junction to a negligible level.

The present invention can provide a VC-FET device and a T-CMOS device in which the tunneling current of the drain-channel junction is smaller than the tunneling current of the drain-body junction.

The present invention can provide a VC-FET device that spatially separates the drain-body junction from the gate and the channel.

The present invention is to provide a T-CMOS device with reduced standby power and no short channel phenomenon even when the cross-sectional area is reduced due to improved integration by applying a structure of an FET device that can minimize the tunneling current of the drain-channel junction. can

The present invention increases the amount of information that can be processed by the device to three, so that even with a small number of devices, it is possible to provide a device capable of processing more information compared to a binary device compared to a binary device.

The present invention can provide a device applicable to a micro-miniature bio-information collecting bioprocessor, a micro-miniature wearable device, etc., which are micro electronic devices with a small battery capacity, because the size of the semiconductor chip is reduced and can be used with low power.

A vertical channel field effect transistor device according to an embodiment of the present invention comprises: a semiconductor substrate; a drain region formed on a top surface of the semiconductor substrate; a channel region formed on an upper surface of the drain region; a source region formed on an upper surface of the channel region; a gate insulating layer formed on a side surface of the channel; and a gate formed on a side surface of the gate insulating layer, wherein the drain region is highly doped as the distance from the channel region increases.

In the vertical channel field effect transistor device according to the embodiment of the present invention, it is possible to provide a vertical channel field effect transistor device, wherein the semiconductor substrate is doped with a dopant of a different type than that of the drain region.

In the vertical channel field effect transistor device according to the embodiment of the present invention, it is possible to provide a vertical channel field effect transistor device, wherein the semiconductor substrate is doped with the same type of dopant as the channel region.

On the other hand, the T-CMOS device according to an embodiment of the present invention is a T-CMOS device including at least two vertical channel field effect transistor devices, wherein the vertical channel field effect transistor device, a semiconductor substrate; a drain region formed on a top surface of the semiconductor substrate; a channel region formed on an upper surface of the drain region; a source region formed on an upper surface of the channel region; a gate insulating layer formed on a side surface of the channel; and a gate formed on a side surface of the gate insulating layer, wherein the drain region is highly doped as it moves away from the channel region.

In the T-CMOS device according to the embodiment of the present invention, the semiconductor substrate may be doped with a dopant of a different type than that of the drain region.

In the T-CMOS device according to the embodiment of the present invention, the semiconductor substrate may be doped with a dopant of the same type as the channel region.

The present invention has the effect of providing a VC-FET device that provides a constant drain-body junction tunneling current regardless of a change in gate voltage.

The present invention has an effect of providing a ternary-CMOS in which a new one state is additionally implemented using a VC-FET device.

The present invention has the effect of providing a T-CMOS device capable of reducing standby power by reducing the size of an off current while increasing device integration.

The present invention has the effect of providing a device that can operate as a ternary inverter even if the tunneling current of the drain-body junction independent of the gate voltage decreases by minimizing tunneling occurring in the drain-channel junction to a negligible level.

The present invention has the effect of providing a VC-FET device and a T-CMOS device in which the tunneling current of the drain-channel junction is smaller than the tunneling current of the drain-body junction.

The present invention has the effect of providing a VC-FET device that spatially separates a drain-body junction from a gate and a channel.

The present invention provides a T-CMOS device with reduced standby power and no short channel phenomenon even when the cross-sectional area is reduced due to improved integration by applying a structure of a FET device capable of reducing the tunneling current of the drain-channel junction to a minimum have an effect

The present invention has the effect of providing a device capable of processing more information compared to a binary device with the same number of devices even with a small number of devices by increasing the amount of information that can be processed by the device to three.

The present invention has the effect of providing a device applicable to a micro-miniature bio-information collection bioprocessor, a micro-miniature wearable device, etc., which are micro electronic devices with a small battery capacity, because the size of the semiconductor chip is reduced and can be used with low power.

1A is a conceptual diagram of a conventional T-CMOS device 10 using a planar MOSFET.
1B is a graph illustrating a drain current according to a gate voltage.
2 is a perspective view of a vertical channel field effect transistor device according to an embodiment of the present invention.
3A and 3B are perspective and cross-sectional views of a vertical channel field effect transistor device according to another embodiment of the present invention.
4A to 4N illustrate a method of manufacturing a VC-FET device according to an embodiment of the present invention.
5 is a graph illustrating a drain current for a body having different doping concentrations according to a gate voltage applied to a VC-FET device according to an embodiment of the present invention.
6, 7, and 8 are a perspective view, a top view, and a horizontal cross-sectional view of a VC-FET device 100' according to another embodiment of the present invention.
9, 10, and 11 are a perspective view, a top view, and a horizontal cross-sectional view of a VC-FET device according to another embodiment of the present invention.
12 is a perspective view of a T-CMOS device using a VC-FET device according to an embodiment of the present invention.
13 is a conceptual diagram illustrating an operation state of a T-CMOS device using a VC-FET device according to an embodiment of the present invention.
14 is a graph showing three states of a T-CMOS device using a VC-FET device according to an embodiment of the present invention.
15A to 15A show a method of manufacturing a T-CMOS device in which a two-sided gate is applied to a VC-FET device according to an embodiment of the present invention.
16 is a diagram illustrating a FinFET constituting a T-CMOS device.
17 is a graph showing calculation results obtained using a T-CMOS device using a planar MOSFET and a FinFET.
18(a) to 18(d) are diagrams illustrating a potential change according to a change in a channel width and a gate voltage of a FinFET.
19(a) and 19(b) are energy band diagrams according to the gate voltage application of a FinFET having a channel width W _ch of 30 nm and 10 nm, respectively.
20(a) is a graph of V _G -I _D according to body doping concentration in the case of having a FinFET structure. 20(b) is a graph of V _G -I _D according to body doping concentration in the case of having a VC-FET structure.
21( a ) is a graph showing a characteristic change of V _G -I _D according to a channel width (W _ch ) in the case of having a FinFET structure. FIG. 21(b) is a graph showing a change in characteristics of V _G -ID according to a channel width ( _{W ch} ) in the case of having a VC-FET structure.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are only exemplified for the purpose of explaining the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention may have various changes and may have various forms, the embodiments will be illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all modifications, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one element from another, for example, without departing from the scope of the inventive concept, a first element may be termed a second element and similarly a second element A component may also be referred to as a first component.

The technical terms used herein are used only to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to designate that a feature, number, step, operation, component, part, or combination thereof described herein exists, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, with reference to the accompanying drawings, a vertical channel field effect transistor (VC-FET, VC-FET) device according to an embodiment of the present invention, a T-CMOS device using the VC-FET, and manufacturing thereof A method will be described.

2 is a perspective view of a vertical channel field effect transistor device according to an embodiment of the present invention. 3A and 3B are perspective and cross-sectional views of a vertical channel field effect transistor device according to another embodiment of the present invention.

The vertical channel field effect transistor (VC-FET) device 100 may be an nMOS device 100n or a pMOS device 100p. 2, 3A, and 3B show the case of an nMOS device. Hereinafter, an nMOS device will be described as a reference, but the description may also be applied to a pMOS device by changing the type of dopant. Therefore, the vertical channel field effect transistor device of the present invention is not limited to either the nMOS device 100n or the pMOS device 100p.

2, 3A and 3B , the VC-FET device 100 according to an embodiment of the present invention has a body 110 and a drain 120 and a drain 120 provided on the upper side of the body 110. On the side of the channel 130 provided on the upper side of the channel 130 , the source 140 provided on the upper side of the channel 130 , the gate insulating layer 150 provided on the side surface of the channel 130 , and the gate insulating layer 150 . It may include a gate 160 provided in the .

In the case of a conventional planar MOSFET, when a threshold voltage or more is applied to the gate, a channel is created in a horizontal direction between the drain and the source, whereas in the VC-FET device 100 according to the embodiment of the present invention, the first and second When a threshold voltage or more is applied to the gates 160a and 160b, the channel in a vertical direction between the drain 120 and the source 140 by the drain 120 and the source 140 disposed on the upper and lower surfaces of the channel 130. this is created

Body 110 is a semiconductor substrate doped with a specific type of dopant to induce drain-body tunneling. In particular, in the present invention, the body 110 may be doped with the same type of dopant as the channel 130 .

The doping concentration of the body 110 may be determined according to the level of the tunneling current between the drain 120 and the channel 130 and the tunneling current between the drain 120 and the body 110 . The doping concentration of the body 110 may be higher than the concentration of the channel 130 or may be the same as the concentration of the channel 130 . For example, when the difference in concentration between the top and bottom in the doping profile of the drain region is small, the doping concentration of the body 110 may be set higher than that of the channel 130 .

Alternatively, the doping concentration of the body 110 may be smaller than the concentration of the channel 130 by a preset value. In other words, the doping concentration of the body 110 may be smaller than the concentration of the channel 130 . The preset value may be determined by a doping profile of the drain region. For example, as the difference between the upper and lower concentrations in the doping profile of the drain region increases, the preset value may increase. This means that if the difference in concentration between the top and bottom in the doping profile of the drain region is large enough, the tunneling current in the drain-body junction is the same in the drain-channel junction even if the doping concentration of the body 110 is smaller than the doping concentration of the channel 130 . It may be greater than the tunneling current.

The body 110 may be doped with a non-uniform or uniform concentration in the entire region, but is preferably doped uniformly.

When the VC-FET device 100 is an nMOS, the body 110 is heavily doped with a p-type. When the VC-FET device 100 is a pMOS, the body 110 is heavily doped with an n-type. The tunneling current of the drain-body junction is smoothly induced by the heavily doped body 110 .

In addition, in the case of the conventional planar MOSFET, the channel and the body are junctioned, whereas the body 110 of the present invention is installed physically and spatially separated from the channel 130, so that the tunneling current of the drain-body junction is the gate voltage. is not affected, and has the effect of minimizing the size of the off current of the T-COMS using the VC-FET 100 .

Referring to FIG. 2 , the body 110 according to an example may be formed to have a longer length in the left and right direction than the drain 120 . In other words, the drain 120 may be formed to cover a portion of the upper surface of the body 110 . In this case, a gate insulating layer 150 , which will be described later, is formed on the left and right side surfaces of the drain 120 and the upper surface of the body 110 .

Alternatively, referring to FIG. 3A , the body 110 according to another example has an n-body region 110a formed to have the same length as the drain 120 in the left-right direction and an n-body region connected to the lower end of the n-body region 110a. (110b) may be included. In this case, the gate insulating layer 150 to be described later is formed on the left and right sides of the drain 120 , the left and right sides of the n-body region 110a , and the top surface of the n-body region 110b .

The drain 120 is provided above the body 110 . The drain 120 is provided in direct contact with the upper surface of the body 110 . The drain 120 may be provided with a smaller area than the upper surface of the body 110 , or may be formed on the upper side of the body 110 with the same area as the upper surface of the body 110 .

The drain 120 may be doped with a dopant of a different type from that of the body 110 or the channel 130 . For example, when the VC-FET device 100 is an nMOS, the drain 120 is doped with an n-type. When the VC-FET device 100 is a pMOS, the drain 120 is doped with a p-type.

The drain 120 may be non-uniformly doped over the entire region. For example, the drain 120 may be doped with a Gaussian distribution in a vertical direction. The drain 120 may be formed such that the doping concentration decreases as it goes upward in the vertical direction.

The doping concentration of the drain 120 may be lightly doped as it approaches the channel 130 and highly doped as it moves away from the channel 130 . The drain 120 may be doped with a high concentration at a lower end that is a junction with the body 110 , and a lower end that is a junction with the channel at a low concentration.

The drain 120 may include a drain upper surface 120a exposed upward to connect a connection electrode (not shown) and a via (not shown). A connection electrode (not shown) is formed on the drain upper surface 120a, and an external voltage is applied through a via (not shown) connected to the connection electrode (not shown).

The lower surface of the drain 120 is surrounded by the body 110 , at least a partial surface of the upper surface is surrounded by the channel 130 , and left and right side surfaces of the drain 120 are surrounded by the gate insulating layer 150 . Accordingly, the drain 120 is formed to be electrically isolated from the gate 160 .

The drain 120 may be formed so as not to overlap the projected area of the gate 160 in a vertical direction. This is to minimize the effect of the electric field generated in the gate 160 on the drain 120 .

The channel 130 is provided above the drain 120 . The channel 130 may be provided to directly contact the upper surface of the drain 120 . The channel 130 may be formed above the drain 120 to have the same length in the left and right directions as the drain 120 . The channel 130 may be formed to have a shorter length in the front-rear direction than the drain 120 , so that the drain upper surface 120a is exposed.

The lower surface of the channel 130 may be surrounded by the drain 120 , the upper surface may be surrounded by the source 140 , and left and right sides of the channel 130 may be surrounded by the gate insulating layer 150 . Accordingly, the channel 130 is spatially separated from the body 110 so as not to be in direct electrical contact with the body 110 .

Channel 130 may be doped with a different type of dopant than drain 120 and source 140 . The channel 130 may be doped with the same type of dopant as the body 110 . The channel 130 may be lightly doped to suppress tunneling of the drain-channel, and may have a lower doping concentration than the body 110 . The channel 130 may be uniformly doped over the entire region.

The channel 130 is lightly doped and the body 110 is heavily doped, so that the tunneling current of the drain-channel junction is minimized, and the tunneling current in the drain-body junction is induced relatively higher than that of the drain-channel junction. can do.

The source 140 is provided above the channel 130 . The source 140 is provided in direct contact with the upper surface of the channel 130 . The source 140 may be formed on the upper surface of the channel 130 with the same area as that of the upper surface of the channel 130 .

Source 140 may be doped with a different type of dopant than body 110 or channel 130 . For example, when the VC-FET device 100 is an nMOS, the source 140 is doped with an n-type. When the VC-FET device 100 is a pMOS, the source 140 is doped with a p-type.

The source 140 may be uniformly doped or non-uniformly doped over the entire region.

For example, the source 140 may be uniformly doped in the vertical or horizontal direction. Alternatively, the source 140 may be doped with a Gaussian distribution in the vertical direction. The source 140 may be formed such that the doping concentration increases toward the upper side in the vertical direction. The doping concentration of the source 140 may be lightly doped as it approaches the channel 130 and highly doped as it moves away from the channel 130 . The source 140 may be doped with a low concentration at a lower end, which is a junction with the channel 130 , and with a high concentration, doping between a connection electrode (not shown) and an upper end, which is a junction.

The source 140 may include a source upper surface 140a exposed upward to connect a connection electrode (not shown) and a via (not shown). A connection electrode (not shown) is formed on the upper surface of the source 140a, and an external voltage is applied through a via (not shown) connected to the connection electrode (not shown).

The lower side of the source 140 is surrounded by the channel 130 , the upper side is exposed, and left and right side surfaces of the source 140 are surrounded by the gate insulating layer 150 . Accordingly, the source 140 is formed to be electrically isolated from the gate 160 .

As described above, the drain 120 and the source 140 are heavily doped with the same type of dopant. For example, the drain 120 may be highly doped as it moves away from the channel 130 , and the source 140 does not need to have a specific doping concentration profile. Alternatively, both the drain 120 and the source 140 may be heavily doped as the distance from the channel 130 increases.

Tunneling current at the drain-channel junction can be minimized through the non-uniform doping of the drain 120, and the tunneling of the drain-body junction becomes dominant enough to ignore the tunneling of the drain-channel through the non-uniform doping of the drain 120 can make

As another example, one of them may have a non-uniform doping concentration, and the other may have a uniform doping concentration. Preferably, the source 140 is uniformly doped, and the doping concentration of the drain 120 increases as the doping concentration of the drain 120 increases further from the channel 130. By increasing the tunneling current of the drain-body junction, it can be used as a ternary device. can make it

The reason that the doping concentration of the drain 120 is designed to be higher as it moves away from the channel 130 is that the drain-channel tunneling is reduced and the ratio of the drain-body tunneling is increased, so that the drain independent of the voltage of the gate 160 is - This is to ensure that the size of the tunneling current of the body always prevails over the tunneling current of the drain-channel.

The gate insulating layer 150 is provided on the side surface of the channel 130 . The gate insulating layer 150 is formed between the gate 160 , the body 110 , the drain 120 , the channel 130 , and the source 140 , and the gate 160 , the body 110 , and the drain 120 . , electrically insulates between the channel 130 and the source 140 .

The gate insulating layer 150 is formed on the left and right sides of the drain 120 , the first gate insulating layer 150a formed between the gate 160 and the body 110 , and the left and right side surfaces of the channel 130 , , a second gate insulating layer 150b formed between the channel 130 and the gate 160 , and a third gate insulating layer 150c formed on left and right sides of the source 140 .

The gate 160 is provided on the side surface of the gate insulating layer 150 . The gate 160 may include a first gate 160a disposed on the left side of the channel 130 and a second gate 160b disposed on the right side of the channel 130 . An electric field generated when a voltage is applied to the first gate 160a and the n-gate 370n acts on the channel 130, thereby creating a vertical channel 130 through which electrons or holes can move.

The gate 160 may be formed at the same height as the channel 130 and the same length. By forming the gate 160 so that there is no overlapping portion with the drain 120 in the left and right directions, the influence of the tunneling of the drain-body junction to the voltage of the gate 160 can be minimized.

In the VC-FET 100 according to the embodiment of the present invention, the tunneling phenomenon at the drain-body junction separated from the gate 160 by the unbalanced doping of the drain 120 and the isolation structure by the gate insulating layer 150 . This is induced and the tunneling phenomenon in the drain-channel junction that is affected by the voltage of the gate 160 can be suppressed as much as possible.

By maximally suppressing tunneling in the drain-channel junction, only the tunneling current of the drain-body junction that is not affected by the voltage of the gate 160 can be left. In other words, it can be formed so that the tunneling current of the drain-body junction always dominates the tunneling current of the drain-channel junction.

Even if the level of the tunneling current of the drain-body junction is reduced, a constant tunneling current of the drain-body junction can be maintained regardless of the voltage of the gate 160 , and an intermediate state can be output even with a very low off-state current.

In addition, the VC-FET device 100 according to the embodiment of the present invention forms a vertical channel 130 between the source 140 and the drain 120, so that the VC-FET device is adjacent to each other in the left-right or front-rear direction. Since (100) can be disposed, the integration is improved, and even if the cross-sectional area is reduced, the effect that the short channel phenomenon does not occur can be obtained.

4A to 4N illustrate a method of manufacturing a VC-FET device according to an embodiment of the present invention. 4A to 4N illustrate a method of manufacturing an nMOS device, the same manufacturing method may be applied to a method of manufacturing a pMOS device by doping other types of dopants.

Referring to FIG. 4A , a method of manufacturing a VC-FET device includes preparing a semiconductor substrate 210 . The semiconductor substrate 210 may be a substrate already doped with p-type. If the semiconductor substrate 210 is not doped, a step of doping the semiconductor substrate 210 with a p-type may be added. The semiconductor substrate 210 may be a silicon substrate. The doped semiconductor substrate 210 is doped with a high concentration uniformly over the entire region as a p-type. The semiconductor substrate 210 heavily doped with the p-type implements the function of the body 110 of the VC-FET device.

Referring to FIG. 4B , the method of manufacturing a VC-FET device may include depositing a first semiconductor layer 220 on an upper side of a semiconductor substrate 210 and doping with an n-type. The first semiconductor layer 220 may be formed of a silicon material deposited in an epitaxial manner. A lower end of the first semiconductor layer 220 may be heavily doped with n-type doping, and an upper end of the first semiconductor layer 220 may be lightly doped with n-type. The first semiconductor layer 220 may be non-uniformly doped in a vertical direction. The first semiconductor layer 220 may be doped with an n-type dopant at a higher concentration from an upper end to a lower end.

The doping method may non-uniformly dope the first semiconductor layer 220 using a retrograde doping technique. The n-type doped first semiconductor layer 220 implements the function of the drain 120 of the VC-FET device.

Referring to FIG. 4C , the method of manufacturing a VC-FET device may include depositing a second semiconductor layer 230 on an upper side of the first semiconductor layer 220 and doping with p-type. The second semiconductor layer 230 may be formed of a silicon material deposited in an epitaxial manner. The entire region of the second semiconductor layer 230 may be uniformly doped with a low concentration of the p-type.

The p-type doping concentration doped in the second semiconductor layer 230 may be smaller than the p-type doping concentration doped in the semiconductor substrate 210 . The second semiconductor layer 230 doped with the p-type implements the function of the channel 130 of the VC-FET device.

Referring to FIG. 4D , the method of manufacturing a VC-FET device may include depositing a third semiconductor layer 240 on an upper side of the second semiconductor layer 230 and doping with an n-type. The third semiconductor layer 240 may be formed of a silicon material deposited in an epitaxial manner. The doping profile of the third semiconductor layer 240 may be doped so as not to have gradually different concentrations. Alternatively, the lower end of the third semiconductor layer 240 may be lightly doped with n-type doping, and the upper end may be heavily doped with n-type doping. The third semiconductor layer 240 may be non-uniformly doped in a vertical direction. In other words, the third semiconductor layer 240 may be doped with an n-type dopant at a lower concentration from the upper end to the lower end.

The n-type doped third semiconductor layer 240 implements the function of the source 140 of the VC-FET device.

The first semiconductor layer 220 and the third semiconductor layer 240 may be highly doped as the distance from the second semiconductor layer 230 increases. The first semiconductor layer 220 and the third semiconductor layer 240 may be doped with the same type of dopant. The second semiconductor layer 230 and the semiconductor substrate 210 may be doped with the same type of dopant, and may be doped with a dopant of a different type from that of the first semiconductor layer 220 and the third semiconductor layer 240 .

Referring to FIG. 4E , the method of manufacturing a VC-FET device may include etching portions of the stacked semiconductor layers 210 , 220 , 230 , and 240 to form a dielectric bobbin 250a. . The etched semiconductor layers may have a shape of a pillar P in which the third semiconductor layer 240 , the second semiconductor layer 230 , and the first semiconductor layer 220 are stacked from above, and When partially etched, the third semiconductor layer 240 , the second semiconductor layer 230 , the first semiconductor layer 220 , and the semiconductor substrate 210 may have the shape of a pillar P stacked from above.

The dielectric mounting portion 250a is formed on the semiconductor substrate 210 by etching the first to third semiconductor layers 220 and 230 240 or by additionally etching a portion of the semiconductor substrate 210 . The dielectric mounting part 250a may be formed on both sides of the pillar P of the stacked semiconductor layer. The pillar P of the stacked semiconductor layer includes semiconductors serving as the drain 120 , the channel 130 , and the source 140 .

Referring to FIG. 4F , a method of manufacturing a VC-FET device may include forming a dielectric 250 . The dielectric 250 may be formed on the dielectric mounting portion 250a using a deposition process. The dielectric 250 may be stacked on the top surfaces of the semiconductor substrate 210 and the third semiconductor layer 240 , the top surfaces of which are exposed because the first to third semiconductor layers 240 are not stacked. The dielectric 250 stacked on the semiconductor substrate 210 and the stacked first to third semiconductor layers 240 implements the function of the gate insulating layer 150 of the VC-FET device.

Referring to FIG. 4G , a method of manufacturing a VC-FET device may include etching the dielectric 250 . The dielectric 250 is selectively etched and the etched dielectric 250 forms conductive layer seating portions 260a and 260b on which the conductive layer 260 is to be seated. The etched dielectric 250 is a gate insulating layer 150 that insulates and isolates the gate 160 from electrical contact between the stacked semiconductors. The dielectric 250 remaining unetched may be present on left and right side surfaces of the second semiconductor layer 230 and the third semiconductor layer 240 , and on the top surface of the third semiconductor layer 240 .

The conductive layer seating portions 260a and 260b may include a first conductive layer seating portion 260a formed on the left side of the second semiconductor layer 230 and a second conductive layer seating portion 260b formed on the right side of the second semiconductor layer 230 .

The bottom surfaces of the conductive layer seating portions 260a and 260b are formed to coincide with or below the extension surface of the interface between the first semiconductor layer 220 and the second semiconductor layer 230 . The dielectric 250 is etched so that the bottom surface of the conductive layer mounting portion 260a is positioned above the first semiconductor layer 220 . This is to minimize the effect of the electric field by the gate 160 on the drain 120 by preventing the generated gate 160 from overlapping the drain 120 in a horizontal direction.

Referring to FIG. 4H , the method of manufacturing a VC-FET device may include depositing a conductive layer 260 . The conductive layer 260 may be deposited on the conductive layer seating portions 260a and 260b on the top surface of the third semiconductor layer 240 and the top surface of the dielectric 250 . The conductive layer 260 may be made of a metal material having electrical conductivity or poly-silicon.

Referring to FIG. 4I , a method of manufacturing a VC-FET device may include etching the deposited conductive layer 260 .

All portions of the deposited conductive layer 260 except for a portion placed on the dielectric 250 on the upper surface of the third semiconductor layer 240 and a predetermined height on the upper surface of the conductive layer seating portions 260a and 260b are etched.

The remaining conductive layer 260 is all etched away to the same height as the second semiconductor layer 230 . The upper surface of the conductive layer 260 left after etching is formed on or on the same as the interface between the second semiconductor layer 230 and the third semiconductor layer 240 .

Referring to FIG. 4J , the thickness of the remaining conductive layer 260 may be reduced by performing additional etching in the front-rear direction. The remaining conductive layer 260 may include a first gate 160a formed on the first conductive layer seating portion 260a and a second gate 160b formed on the second conductive layer seating portion 260b. The remaining conductive layer 260 implements the function of the gate 160 of the VC-FET device.

Referring to FIG. 4K , the method of manufacturing a VC-FET device may include etching the dielectric 250 disposed above the third semiconductor layer 240 . Through this, the upper surface of the third semiconductor layer 240 corresponding to the source 140 is exposed, and the exposed source 140 is electrically connected to a connection electrode (not shown) and a via (not shown) to apply an external voltage. can be

Referring to FIG. 4L , the method of manufacturing a VC-FET device may include an etching step for reducing the thickness of the dielectric 250 placed above the first semiconductor layer 220 in the front-rear direction. As such, the etched dielectric 250 has a thickness equal to the thickness of the remaining conductive layer 260 .

Referring to FIG. 4M , the method of manufacturing a VC-FET device may include etching to reduce the thickness of the second semiconductor layer 230 and the third semiconductor layer 240 . By reducing the thicknesses of the second semiconductor layer 230 and the third semiconductor layer 240 in the front-rear direction, the upper surface of the first semiconductor layer 220 corresponding to the drain 120 is exposed, and the exposed drain 120 is exposed. The silver may be electrically connected to a connection electrode (not shown) and a via (not shown) to apply an external voltage.

The VC-FET device according to FIG. 4N is the same as all configurations of the VC-FET device according to FIG. 4M , but has a difference in that the doping profile of the third semiconductor layer 240 is gradient doped.

5 is a graph illustrating a drain current for a body having different doping concentrations according to a gate voltage applied to a VC-FET device according to an embodiment of the present invention.

The VC-FET device 100 according to the embodiment of the present invention shows a section in which the drain current (or the tunneling current of the drain-body junction) is constant regardless of the magnitude of the gate voltage. Meanwhile, as the doping concentration of the body 110 decreases, the magnitude of the drain current decreases, but the period of the gate voltage having a constant drain current value tends to be shortened.

When implementing the T-CMOS device 300 using the VC-FET device 100 according to the embodiment of the present invention, it is preferable to implement a low-power device in a standby state by minimizing the off current. Here, the off current includes the tunneling current of the drain-channel and the tunneling current of the drain-body. In order to realize a low-power device, the tunneling current of the drain-body is minimized, and in order to implement a stable ternary system, the drain-body tunneling current is the gate It is important to have a section having a constant value regardless of the voltage.

When the doping concentration (N _body ) of the body 110 is lowered, the tunneling of the drain-body junction is reduced. If the tunneling of the drain-channel junction is not small, the drain current by the drain-channel junction affected by the gate is not constant. will not In other words, if tunneling of the drain-channel junction can be minimized, a constant drain current can be formed even when the tunneling current of the drain-body is reduced by reducing the body concentration.

That is, it shows a section having a constant drain current regardless of the gate voltage. It can operate as the T-CMOS device 300 even with a small off-state current, and can implement the low-power T-CMOS device 300 .

6, 7, and 8 are a perspective view, a top view, and a horizontal cross-sectional view of a VC-FET device 100' according to another embodiment of the present invention. The VC-FET device 100' according to another embodiment of the present invention can be viewed as a vertical channel 3-gate FET device, and the VC-FET device 100 according to the embodiment of the present invention described above is a vertical channel 2-gate FET device. It can be viewed as a FET device.

6 to 8 , the VC-FET device 100 ′ according to another embodiment of the present invention includes a body 110 , a drain 120 provided on the upper side of the body 110 , and a drain 120 . On the side of the channel 130 provided on the upper side, the source 140 provided on the upper side of the channel 130 , the gate insulating layer 150 provided on the side surface of the channel 130 , and the gate insulating layer 150 . It may include a provided gate 160 .

When describing the VC-FET device 100 ′ according to another embodiment of the present invention, the description of the VC-FET device 100 according to the embodiment of the present invention with respect to FIGS. 2, 3A and 3B is given. If there is no structural contradiction, it can be applied as it is, and the differences will be mainly described below.

6 to 8 , in the VC-FET device 100 ′ according to another embodiment of the present invention, the gate 160 may have a structure surrounding three surfaces of the channel 130 . The gate 160 includes a first gate 160a formed on the left side of the channel 130 , a second gate 160b formed on the right side of the channel 130 , and a third gate 160c formed on the rear side of the channel 130 . may include By increasing the area of the gate 160 surrounding the channel 130 , the effect of the electric field on the channel 130 when a voltage is applied to the gate 130 may be further increased.

In addition, the gate insulating layer 150 may be further formed between the third gate 160c and the channel 130 , and may be further further formed between the third gate 160c and the body 110 .

Also, the drain 120 may be formed so as not to overlap the projected area of the gate 160 in a vertical direction. The drain 120 may be formed only on the front side where the gate 160 is not formed so that the drain 120 does not overlap.

9, 10, and 11 are a perspective view, a top view, and a horizontal cross-sectional view of a VC-FET device according to another embodiment of the present invention. The VC-FET device 100 ″ according to another embodiment of the present invention can be viewed as a vertical channel front gate FET device, and the VC-FET device 100 according to the embodiment of the present invention described above is a vertical channel 2 It can be viewed as a gate FET device.

9 to 10 , a VC-FET device 100 ″ according to another embodiment of the present invention includes a body 110 , a drain 120 provided on the upper side of the body 110 , and a drain 120 . On the side of the channel 130 provided on the upper side of the channel 130 , the source 140 provided on the upper side of the channel 130 , the gate insulating layer 150 provided on the side surface of the channel 130 , and the gate insulating layer 150 . It may include a gate 160 provided in the .

When describing the VC-FET device 100 ″ according to another embodiment of the present invention, the description of the VC-FET device 100 according to the embodiment of the present invention with respect to FIGS. 2 , 3A and 3B is applicable as long as there is no structural contradiction, and the differences will be mainly explained below.

9 to 10 , in the VC-FET device 100 ″ according to another embodiment of the present invention, the gate 160 may have a structure surrounding the entire surface of the channel 130 . The gate 160 includes a first gate 160a formed on the left side of the channel 130 , a second gate 160b formed on the right side of the channel 130 , a third gate 160c formed on the rear side of the channel 130 , A fourth gate 160d formed on the front side of the channel 130 may be included. By increasing the area of the gate 160 surrounding the channel 130 , the effect of the electric field on the channel 130 when a voltage is applied to the gate 130 may be further increased.

In addition, the gate insulating layer 150 is additionally formed between the third gate 160c and the fourth gate 160d and the channel 130 , and the third gate 160c and the fourth gate 160d and the body ( 110) may be further formed in between. In addition, the gate insulating layer 150 may be additionally formed between the drain 120 and the third gate 160c and the fourth gate 160d.

In the VC-FET device 100 ″ according to another embodiment of the present invention, the entire side of the channel 130 provided between the source 140 and the drain 120 is surrounded by the gate 150 so that the drain- Channel 130 between the sources can be used to the maximum.

12 is a perspective view of a T-CMOS device using a VC-FET device according to an embodiment of the present invention. 13 is a conceptual diagram illustrating an operation state of a T-CMOS device using a VC-FET device according to an embodiment of the present invention.

The T (ternary)-CMOS 300 is a device having three states, whereas the binary-CMOS has two states, and can implement a ternary system, and is called a ternary inverter.

Referring to FIG. 12 , a T-CMOS device 300 using a VC-FET device according to an embodiment of the present invention may include a pMOS device 100p and an nMOS device 100n that are complementary to each other. The pMOS device 100p and the nMOS device 100n may have the above-described VC-FET 100 structure. Details regarding the complementary coupling of the pMOS device 100p and the nMOS device 100n are well known, and detailed descriptions thereof will be omitted.

An operation state of a T-CMOS device using a VC-FET device according to an embodiment of the present invention will be described with reference to FIG. 13 . A current flows from the upper end of the drain 120 to the source 140 in the pMOS device 100p and the nMOS device 100n of the T-CMOS device 300 according to the embodiment of the present invention through the channel 130, and the drain A tunneling current flows from the lower end of the 120 to the body 110 .

The channel 130 and the body 110 of the pMOS device 100p and the nMOS device 100n are spatially separated with the drain 120 interposed therebetween. The current flowing through and the tunneling current of the drain-body junction, which should have a constant value regardless of the voltage of the gate 160, are spatially separated so that they do not affect each other.

In addition, tunneling is induced at the drain-body junction by doping the body 110 and the lower end of the drain 120 of the pMOS device 100p and the nMOS device 100n at a high concentration, and the upper end of the drain 120 and the channel 130 are doped. ) to suppress tunneling in the drain-channel junction by doping at a low concentration.

Since the T-CMOS device 300 using the VC-FET device according to the embodiment of the present invention shows a clear third state even when the tunneling current of the drain-body junction is small compared to the conventional T-CMOS device, 3 It can be operated as a binary device, and since the tunneling current of the drain-body junction is small, standby power can be reduced, and thus the off current can be minimized to enable operation with low power.

14 is a graph showing three states of a T-CMOS device using a VC-FET device according to an embodiment of the present invention.

The drain current of the T-CMOS device 300 using the VC-FET device according to the embodiment of the present invention is divided into a tunneling current flowing to the body 110 and a current flowing to the source 140 through the channel 130 . 14, in the T-CMOS device 300 according to the embodiment of the present invention, a high state in which current flowing through the channel of the pMOS device 100p flows, and the channel of the nMOS device 100n. It operates to have a low state in which a current flowing through it flows, and an intermediate state in which a tunneling current of the drain-body junction independent of the gate voltage simultaneously flows through the pMOS device 100p and the nMOS device 100n.

15A to 15A show a method of manufacturing a T-CMOS device in which a two-sided gate is applied to a VC-FET device according to an embodiment of the present invention. Hereinafter, a method of manufacturing the T-CMOS device 300 according to an embodiment of the present invention will be described.

Referring to FIG. 15A , a method of manufacturing a T-CMOS device includes preparing a semiconductor substrate 310 . The semiconductor substrate 310 may be a silicon wafer. An nMOS device 100n and a pMOS device 100p are implemented using semiconductors to be subsequently stacked on the semiconductor substrate 310 .

Referring to FIG. 15B , in the method of manufacturing the T-CMOS device, the first insulating layer 311 may be deposited on the semiconductor substrate 310 . The first insulating layer 311 may be made of silicon oxide (SiO2). The first insulating layer 311 may function as an isolation wall between the nMOS device 100n and the nMOS device 100n to be formed through a subsequent process, and is also referred to as shallow trench isolation (STI). The first insulating layer 311 may function as a buffer of the p-body 320p of the pMOS device 100p or the n-body 320n of the nMOS device 100n.

Referring to FIG. 15C , in the manufacturing method of the T-CMOS device, the n-body seat 321n or the pMOS device 100p of the nMOS device 100n is etched by etching a part of the first insulating layer 311 . ), a p-body bobbin 321p is formed, a 1p semiconductor 320p is formed in the p-body bobbin 321p, and ions can be implanted.

Furthermore, the method of manufacturing the T-CMOS device includes planarizing the top surface of the 1p semiconductor 320p after ion implantation, or after forming the 1n-th semiconductor 320n to be described later, the 1p semiconductor 320p ) and planarizing the 1n-th semiconductor 320n together.

Hereinafter, description will be made on the basis that the p-body seating portion 321p of the pMOS device 100p is etched first. Depending on the manufacturing method, the n-body seating part 321n may be etched before the p-body seating part 321p. The p-body mounting portion 321p is etched to expose the semiconductor substrate 310 .

The 1p semiconductor 320p may be formed by depositing inside the p-body mounting portion 321p. The 1p semiconductor 320p may be deposited by epitaxially growing silicon (Si) in the p-body mounting portion 321p. The deposited 1p semiconductor 320p may be formed into silicon doped with a high concentration of n-type doping (ion implantation) by uniformly high-concentration doping (ion implantation) of the n-type dopant.

The n-type heavily doped 1p semiconductor 320p may planarize the top surface of the silicon oxide and the n-type heavily doped 1p semiconductor 320p by using chemical-mechanical polishing (CMP). Alternatively, the n-type heavily doped first p-semiconductor 320p may be planarized together using CMP after a p-type heavily doped 1n-th semiconductor 320n, which will be described later, is generated.

After planarization, the n-type heavily doped 1p semiconductor 320p filled in the p-body mounting portion 321p serves as the p-body 320p of the pMOS device 100p.

Referring to FIG. 15D , the method of manufacturing a T-CMOS device may include depositing a second insulating layer 312 on the first insulating layer 311 and the top surface of the p-body 320p. The height of the second insulating layer 312 may be deposited to be smaller than the height of the first insulating layer 311 . The second insulating layer 312 may be made of silicon oxide (SiO2).

Referring to FIG. 15E , in the manufacturing method of the T-CMOS device, the n-body seating portion 321n of the nMOS device 100n is formed by etching a portion of the first insulating layer 311 and the second insulating layer 312 . and forming the 1n-th semiconductor 320n in the n-body seating part 321n and implanting ions.

The n-body seating part 321n is formed to be spaced apart from the p-body seating part 321p by a predetermined distance in the left and right directions, and a first insulating layer 311 is formed between the n-body seating part 321n and the p-body seating part 321p. ) are separated from each other. In addition, the n-body mounting portion 321n is etched to expose the semiconductor substrate 310 .

The 1n-th semiconductor 320n may be deposited by epitaxially growing silicon inside the n-body mounting portion 321n. The deposited 1n-th semiconductor 320n may be made into highly-concentrated p-type doped silicon by uniformly high-concentration doping (ion implantation) of the entire p-type dopant. The 1n-th semiconductor 320n may be formed to have the same height as the p-body 320p.

Referring to FIG. 15F , the method of manufacturing the T-CMOS device may include removing the second insulating layer 312 . The second insulating layer 312 may be removed by etching. In addition, top surfaces of the second insulating layer 312 and the 1n-th semiconductor 320n may be planarized using CMP. Alternatively, a CMP planarization process may be sequentially performed after etching of the second insulating layer 312 . The planarized p-type heavily doped 1n-th semiconductor 320n serves as the n-body 320n of the nMOS device 100n. Alternatively, when the planarization process of the 1p-th semiconductor 320p is not performed in FIG. 15C , the 1n-th semiconductor 320n and the 1p-th semiconductor 320p may be planarized together using CMP.

Referring to FIG. 15G , the manufacturing method of the T-CMOS device includes depositing the first insulating layer 311, the p-body 320p, and the n-body 320n on the upper surfaces, and etching the third insulating layer 313. may include steps. The third insulating layer 313 may be made of silicon oxide (SiO2). The third insulating layer 313 is etched to expose the top surface of the p-body 320p, so that the p-drain seating portion 331p of the pMOS device 100p may be formed.

Referring to FIG. 15H , in the method of manufacturing the T-CMOS device, the second p semiconductor 330p may be formed in the p-drain seating portion 331p.

Furthermore, the method of manufacturing the T-CMOS device includes planarizing the top surface of the 2p semiconductor 330p after forming the 2p semiconductor 330p, or after forming the 2n-th semiconductor 330n, the 2p semiconductor ( 330p) and planarizing the 2n-th semiconductor 330n together. When the top surface of the 2p semiconductor 330p is planarized by CMP, the third insulating layer 313 may also be planarized.

The 2p semiconductor 330p may be formed by epitaxial growth of silicon in the p-drain seating portion 331p.

The 2p semiconductor 330p may be ion-implanted during epitaxial growth.

The 2p semiconductor 330p may be non-uniformly doped in a vertical direction. The 2p semiconductor 330p may be doped with a low concentration p-type dopant from bottom to top. The doping concentration of the 2p semiconductor 330p may have a Gaussian distribution in which the lower end is high and the upper end is low. In order to non-uniformly dope the 2p semiconductor 330p in a vertical direction, a retrograde doping method may be applied. The non-uniformly p-type 2p semiconductor 330p serves as a p-drain 330p of the pMOS device 100p.

Referring to FIG. 15I , in the method of manufacturing the T-CMOS device, a fourth insulating layer 314 is deposited on the third insulating layer 313 and the top surface of the p-drain 330p, and the third insulating layer 313 and The method may include forming the n-drain seating portion 331n by etching a portion of the fourth insulating layer 314 .

The fourth insulating layer 314 may be made of silicon oxide (SiO2). The fourth insulating layer 314 is etched to expose the top surface of the n-body 320n, thereby forming the n-drain seating portion 331n of the nMOS device 100n.

Referring to FIG. 15J , the method of manufacturing a T-CMOS device may include forming and planarizing a 2n-th semiconductor 330n. The 2n-th semiconductor 330n is formed by epitaxial growth of silicon in the n-drain seating portion 331n.

The fourth insulating layer 314 may be selectively etched and removed, and top surfaces of the fourth insulating layer 314 and the 2n-th semiconductor 330n may be planarized by CMP. The planarized 2n-th semiconductor 330n has the same vertical length as the p-drain 330p.

The 2n-th semiconductor 330n may be ion-implanted while epitaxially growing. The 2n-th semiconductor 330n may be non-uniformly doped in a vertical direction. The 2n-th semiconductor 330n may be doped with a low concentration n-type dopant from bottom to top. The doping concentration of the 2n-th semiconductor 330n may have a Gaussian distribution in which the lower end is high and the upper end is lower. In order to non-uniformly dope the 2n-th semiconductor 330n in a vertical direction, a retrograde doping method may be applied. The non-uniformly n-type doped 2n-th semiconductor 330n serves as the n-drain 330n of the nMOS device 100n.

Referring to FIG. 15K , in the manufacturing method of the T-CMOS device, a fifth insulating layer 315 is deposited on the top surfaces of the p-drain 330p, the n-drain 330n, and the third insulating layer 313, and a fifth It may include etching the insulating layer 315 . The fifth insulating layer 315 may be made of silicon oxide (SiO2). The fifth insulating layer 315 may be etched to expose the top surface of the p-drain 330p, thereby forming the p-channel seating portion 341p of the pMOS.

Referring to FIG. 15L , in the method of manufacturing a T-CMOS device, a 3p semiconductor 340p may be formed and ion implanted.

Furthermore, the manufacturing method of the T-CMOS device includes planarizing the top surface of the 3p semiconductor 340p after ion implantation, or after forming the 3n semiconductor 340n, which will be described later, the 3p semiconductor 340p and It may include planarizing the 3n-th semiconductor 340n together.

The 3p semiconductor 340p may be deposited by epitaxially growing silicon inside the p-channel bobbin portion 341p. The deposited third p semiconductor 340p may be uniformly doped with an n-type dopant.

The 3p semiconductor 340p may be doped at a lower concentration than the 1p semiconductor 320p. It may be doped in the same type as that of the 1p semiconductor 320p. When the top surface of the 3p semiconductor 340p is planarized by a CMP process, the fifth insulating layer 315 may also be planarized. The 3p semiconductor 340p lightly doped with n-type serves as a p-channel 340p of the pMOS device 100p.

Referring to FIG. 15M , in the method of manufacturing the T-CMOS device, the n-channel seating portion 341n is formed by forming the sixth insulating layer 316 and etching the fifth insulating layer 315 and the sixth insulating layer 316 . ) may include the step of forming

The sixth insulating layer 316 is deposited on the p-channel 340p and the fifth insulating layer 315 . The sixth insulating layer 316 may be made of silicon oxide (SiO2). The sixth insulating layer 316 may be etched to expose the top surface of the n-drain 330n, thereby forming the n-channel seating portion 341n of the nMOS device 100n.

Referring to FIG. 15N , the method of manufacturing a T-CMOS device may include forming a 3n-th semiconductor 340n, implanting ions, and planarizing the semiconductor 340n.

The 3n-th semiconductor 340n is deposited by epitaxially growing silicon inside the n-channel bobbin portion 341n. The 3n-th semiconductor 340n may be uniformly doped with a p-type dopant.

The 3n-th semiconductor 340n may be doped at a lower concentration than the 1n-th semiconductor 320n. It may be doped in the same type as the 1n-th semiconductor 320n.

The 3n-th semiconductor 340n may be formed to have the same vertical length as the 3p-th semiconductor 340p. The sixth insulating layer 316 may be selectively etched, and the remaining top surfaces of the sixth insulating layer 316 and the 3n-th semiconductor 340n may be planarized by CMP. The 3n-th semiconductor 340n lightly doped with the p-type serves as the n-channel 340n of the nMOS device 100n. Alternatively, when the planarization process of the 3p semiconductor 340p is not performed in FIG. 15L , the 3n-th semiconductor 340n and the 3p-semiconductor 340p may be planarized together using CMP.

Referring to FIG. 15O , the method of manufacturing a T-CMOS device may include forming a seventh insulating layer 317 and etching the seventh insulating layer 317 . The seventh insulating layer 317 may be deposited on the fifth insulating layer 315 , the p-channel 340p, and the n-channel 340n. The seventh insulating layer 317 may be made of silicon oxide (SiO2). The seventh insulating layer 317 may be etched to expose the top surface of the p-channel 340p, thereby forming the p-source seating portion 351p.

Referring to FIG. 15P , in the method of manufacturing a T-CMOS device, a 4p semiconductor 350p may be formed.

Furthermore, the method of manufacturing the T-CMOS device includes planarizing the 4p semiconductor 350p after forming the 4p semiconductor 350p, or after forming the 4n semiconductor 350n to be described later, the 4p semiconductor ( 350p) and planarizing the 4n-th semiconductor 350n together.

The 4p semiconductor 350p may be deposited by epitaxially growing silicon into the p-source seating portion 351p. When the top surface of the 4p semiconductor 350p is planarized by CMP, the seventh insulating layer 317 may also be planarized.

The 4p semiconductor 350p may be ion-implanted during epitaxial growth.

The 4p semiconductor 350p may be heavily doped with a p-type dopant. The 4p semiconductor 350p may have a uniform doping concentration over the entire region. The doping concentration of the 4p semiconductor 350p may be similar to that of the heavily doped region of the 2p semiconductor 330p.

Alternatively, the 4p semiconductor 350p may be non-uniformly doped in a vertical direction. The 4p semiconductor 350p may be doped with a high-concentration p-type dopant from bottom to top. The doping concentration of the 4p semiconductor 350p may have a Gaussian distribution in which the lower end is low and the upper end is high.

Referring to FIG. 15Q , in the method of manufacturing the T-CMOS device, the eighth insulating layer 318 may be formed and the eighth insulating layer 318 may be etched. The eighth insulating layer 318 is deposited on the seventh insulating layer 317 and the top surface of the p-source 350p. The eighth insulating layer 318 may be made of silicon oxide (SiO2). The eighth insulating layer 318 may be etched to expose the top surface of the n-channel 340n, thereby forming the n-source seating portion 351n.

Referring to FIG. 15R , the method of manufacturing a T-CMOS device may include generating and planarizing a 4n-th semiconductor 350n. The 4n-th semiconductor 350n may be deposited by epitaxially growing silicon inside the n-source seating portion 351n. The eighth insulating layer 318 may be selectively etched and removed, and upper surfaces of the eighth insulating layer 318 and the 4n-th semiconductor 350n may be planarized by CMP.

The 4n-th semiconductor 350n may be ion-implanted while epitaxially growing.

The 4n-th semiconductor 350n may be heavily doped with an n-type dopant. The 4n-th semiconductor 350n may have a uniform doping concentration over the entire region. The doping concentration of the 4n-th semiconductor 350n may be similar to that of the heavily doped region of the 2n-th semiconductor 330n.

Alternatively, the 4n-th semiconductor 350n may be non-uniformly doped in a vertical direction. The 4n-th semiconductor 350n may be doped with a high concentration of n-type dopant from bottom to top. The doping concentration of the 4n-th semiconductor 350n may have a Gaussian distribution in which the lower end is lower and the upper end is higher.

Referring to FIG. 15S , the method of manufacturing a T-CMOS device may include generating a ninth insulating layer 319 . The ninth insulating layer 319 is deposited on the seventh insulating layer 317 , the p-source 350p, and the n-source 350n. The ninth insulating layer 319 may be made of silicon oxide (SiO2).

Referring to FIG. 15T , the method of manufacturing a T-CMOS device may include etching insulating layers. The insulating layers may include a fifth insulating layer 315 , a seventh insulating layer 317 , and a ninth insulating layer 319 . The top and both sides of the 3p and 4p semiconductors 340p and 350p are etched so as not to be exposed to the outside. The top and both sides of the 3n and 4n semiconductors 340n and 350n are etched so as not to be exposed to the outside.

When the insulating layers are etched, the separation wall 360 may be left between the 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n. Based on the partition wall 360 , the pMOS device 100p and the nMOS device 100n are partitioned from each other. The partition wall 360 may have the same vertical length as the 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n.

The insulating layers may be etched up to a surface extending from the lower surface of the 3p semiconductor 340p or the 3n semiconductor 340n.

The insulating layers are etched so that left and right side surfaces and top surfaces of the 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n, respectively, are not exposed. Non-etched insulating layers around the 3p and 4p semiconductors 340p and 350p may include unetched p-gate insulating layers 362p on left and right sides of the 3p and 4p semiconductors 340p and 350p. . Non-etched insulating layers around the 3n and 4n semiconductors 340n and 350n may include unetched n-gate insulating layers 362n on left and right sides of the 3n and 4n semiconductors 340n and 350n. .

The insulating layers are etched to form a p-gate seating portion 371p of the pMOS device 100p and an n-gate seating portion 371n of the nMOS device 100n. The p-gate bobbin part 371p may include a 1p gate bobbin part 371p-1 and a 2p gate bobbin part 371p-2 formed on the left and right sides of the 3p and 4p semiconductors 340p and 350p. there is. The n-gate seating part 371n may include a 1n-th gate seating part 371n-1 and a 2n-th gate seating part 371n-2 formed on the left and right sides of the 3n and 4n-th semiconductors 340n and 350n. there is. The partition wall 360 partitions the 2p-th gate seating part 371p-2 and the 1n-th gate seating part 371n-1 to be spatially separated.

Referring to FIG. 15U , in the method of manufacturing the T-CMOS device, a conductive material 370 may be deposited on the p-gate bobbin portion 371p and the n-gate bobbin portion 371n. The conductive material 370 may be made of poly-silicon (Poly-Si) or a metal material having electrical conductivity. The conductive material 370 may be deposited on the p-gate bobbin portion 371p and the n-gate bobbin portion 371n as well as the upper portion of the ninth insulating layer 319 .

Referring to FIG. 15V , the method of manufacturing the T-CMOS device may include removing a portion of the conductive material 370 . The conductive material 370 may be selectively etched to the same height as the top surface of the 3p semiconductor 340p or the 3n semiconductor 340n.

The conductive material 370 remaining on both sides of the 3p semiconductor 340p serves as a p-gate 370p of the pMOS device 100p. The p-gate 370p includes a 1p gate 370p-1 seated on the 1p gate bobbin part 371p-1 and a 2p gate 370p-2 seated on the 2p gate bobbin part 371p-2. may include

The conductive material 370 remaining on both sides of the 3n-th semiconductor 340n serves as the n-gate 370n of the nMOS device 100p. The n-gate 370n includes the 1n-th gate 370n-1 seated on the 1n-th gate bobbin part 371n-1 and the 2n-th gate 370n-2 seated on the 2n-th gate bobbin part 371p-2. may include

Each of the p-gate 370p and the n-gate 370n may be formed to have the same vertical length as the third p semiconductor 340p and the third n semiconductor 340n. Each of the p-gate 370p and the n-gate 370n may be formed to have the same height as the 3p semiconductor 340p and the 3n-th semiconductor 340n.

The 2p-th gate 370p - 2 and the 1n-th gate 370n - 1 are partitioned by the partition wall 360 and are partitioned so as not to electrically contact each other. The partition wall 360 is formed to be higher than the 2p-th gate 370p-2 and the 1n-th gate 370n-1. However, the p-gate 370p and the n-gate 370n may be formed by depositing materials having different work functions to adjust the threshold voltages of the nMOS and the pMOS.

Referring to FIG. 15W, the method of manufacturing a T-CMOS device includes implanting ions into the p-gate 370p and the n-gate 370n when the p-gate 370p and the n-gate 370n are made of poly-silicon. may include The doped p-gate 370p and the n-gate 370n may be doped with different types. The doped p-gate 370p and the n-gate 370n may be doped with the same type. The doped p-gate 370p and the n-gate 370n may be heavily doped with different concentrations.

When the p-gate 370p and the n-gate 370n are formed of a metal material, the p-gate 370p and the n-gate 370n may be formed of a metal material having different work functions.

Referring to FIG. 15X , the method of manufacturing the T-CMOS device may include removing the ninth insulating layer 319 . The ninth insulating layer 319 may be etched to expose top surfaces of the p-source 350p and the n-source 350n. A voltage may be applied to the top surfaces of the p-source 350p and the n-source 350n by connecting an electrode metal (not shown) and a via (not shown).

Referring to FIG. 15Y , the method of manufacturing the T-CMOS device may include removing the conductive material 370 . The p-gate 370p and the n-gate 370n may selectively etch the p-gate 370p and the n-gate 370n in order to reduce the thickness of the p-gate 370p and the n-gate 370n in the front-rear direction. .

Referring to FIG. 15Z , the method of manufacturing a T-CMOS device may include removing a portion of the p-gate insulating layer 362p and the n-gate insulating layer 362n. The p-gate insulating layer 362p and the n-gate insulating layer 362n may be selectively etched to reduce the thickness of the p-gate insulating layer 362p and the n-gate insulating layer 362n in the front-rear direction. In addition, the partition wall 360 may be selectively etched to reduce the thickness of the partition wall 360 in the front-rear direction.

The etched p-gate insulating layer 362p and the n-gate insulating layer 362n may have the same thickness in the front-back direction as the p-gate 370p and the n-gate 370n, or may be formed to be thicker. The thickness of the partition wall 360 in the front-rear direction may be equal to or thicker than the thickness of the p-gate 370p and the n-gate 370n.

Referring to FIG. 15A , the method of manufacturing a T-CMOS device may include removing portions of the 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n. The 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n are in the forward and backward directions of the 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n. It can be selectively etched to reduce the thickness. The etched 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n may be formed to have the same thickness as the p-gate 370p and the n-gate 370n.

As the 3p and 4p semiconductors 340p and 350p and the 3n and 4n semiconductors 340n and 350n are etched back and forth, top surfaces of the 2p semiconductor 330p and the 2n semiconductor 330n may be exposed. An electrode metal (not shown) and a via (not shown) may be connected to the exposed top surfaces of the 2p semiconductor 330p and the 2n semiconductor 330n so that a voltage may be applied thereto.

The T-CMOS device according to FIG. 15A is the same as all configurations of the T-CMOS device according to FIG. 15A , but has a difference in that doping profiles of the 4p semiconductor 350p and the 4n semiconductor 350n are gradient doped.

Experimental data of T-CMOS and conventional T-CMOS using VC-FET according to an embodiment of the present invention

Hereinafter, a result of analyzing the performance of a T-CMOS device using a VC-FET device according to an embodiment of the present invention will be described.

The performance of the T-CMOS device using the VC-FET device according to the embodiment of the present invention and the T-CMOS device using the conventional Planar MOSFET and FinFET were compared and analyzed. For performance analysis, mixed-mode circuit simulation using Synopsys TCAD was performed.

Referring to Figure 1a, for Planar MOSFET, channel length (L _ch ) = 1 μm, thickness (EOT) of oxide (SiO2) = 20 nm, drain doping concentration (N _p ) = 10 ¹⁹ cm ³ , to induce tunneling Calculation was performed under the condition of high-concentration channel doping (N _ch ) = 2 × 10 ¹⁹ cm ³ for

16 is a diagram illustrating a FinFET constituting a T-CMOS device.

Referring to FIG. 16 , a T-CMOS device using a FinFET is not doped with a delta layer, unlike a planar MOSFET, but the entire body is highly doped to cause tunneling. For FinFET, channel length (L _ch ) = 60 nm, channel height (H _ch ) = 60 nm, channel width (W _ch ) = 22 nm, doping concentration in body (N _body ) = 1 × 10 ¹⁹ cm ³ , tunneling Calculation was performed under conditions of high-concentration channel doping (N _ch ) = 2 × 10 ¹⁹ cm ³ , and thickness (EOT) of oxide (SiO2) = 3 nm to induce .

17 is a graph showing calculation results obtained using a T-CMOS device using a planar MOSFET and a FinFET.

Referring to FIG. 17 , since the subthreshold swing (SS) value of the planar MOSFET device is large, in the case of a T-CMOS device implemented as a planar MOSFET, the boundary between states is somewhat unclear, so the reliability of the intermediate state is lowered. there is. This is because transitions between states require a lot of voltage.

Referring to FIG. 17 , in a T-CMOS device using a FinFET, unintentional tunneling occurs at the drain-body junction, and when the tunneling current of the drain-body junction is large, there is no problem in operating as a ternary device. In addition, a T-CMOS device implemented as a FinFET having a small SS value has relatively clear boundaries between states than a planar MOSFET, so that the reliability of the intermediate state is high. As shown in FIG. 17 , in the case of the T-CMOS device of the planar MOSFET, it does not have an intermediate state in the section in which Vout has a constant value regardless of Vin, and Vout changes according to Vin, making the ternary operation difficult.

However, when the off current (tunneling current of the drain-body junction) is lowered by lowering the doping concentration (N _body ) of the body in order to make a T-CMOS device using a FinFET into a low-power device, the off current (tunneling of the drain-body junction) current) is affected by a change in the gate voltage, so there is a problem in operating as a ternary device (refer to Fig. 20(a)). In addition, if the channel width of the FinFET is reduced to improve the degree of integration or the body doping concentration is reduced to reduce power consumption, the operating performance of the T-CMOS device implemented as the FinFET may be deteriorated, so that the intermediate state may not be implemented. As shown in FIG. 17 , in the case of a T-CMOS device using a FinFET, the T-CMOS device has an intermediate state in the section in which Vout has a constant value regardless of Vin. However, in order to sufficiently increase the tunneling current of the drain-body junction, the size of the off current There is a problem in that the energy loss due to standby power increases because the

18(a) to 18(d) are diagrams illustrating a potential change according to a change in a channel width and a gate voltage of a FinFET. 19(a) and 19(b) are energy band diagrams according to the gate voltage application of a FinFET having a channel width W _ch of 30 nm and 10 nm, respectively.

18(a) and 18(b), when a gate voltage is applied at 0V (V _G = 1.5V) in the case of a channel width (W _ch ) of 30 nm, a semiconductor near the dielectric boundary Although the potential increases, the potential at the center of the channel hardly changes. In this case, as shown in FIG. 19( a ), since the energy band of the channel does not change significantly before and after the application of the gate voltage, the magnitude of the tunneling current between the channel and the drain hardly changes.

On the other hand, as shown in FIGS. 18(c) and 18(d), in the case of a channel width (W _ch ) of 10 nm, when a gate voltage is applied at 0V (V _G = 1.5V), the potential will change. In this case, as shown in FIG. 19(b), the energy band of the entire channel is lowered before and after the application of the gate voltage.

Since the energy band of the channel is lowered, the magnitude of the tunneling current between the channel and the drain is changed. Specifically, since the channel has a higher energy section than the drain before the gate voltage is applied, there is a lot of tunneling between the channel and the drain, whereas when the total energy band of the channel is lowered, the channel has a lower energy section than the drain, so the channel and the drain There is almost no tunneling between them.

Due to this phenomenon, in the case of a FinFET having a small channel width such as 10 nm, the off current changes according to a change in the gate voltage. Since the T-CMOS device operates only when the off current is constant, stable T-CMOS device performance cannot be implemented with a FinFET having a channel width of 10 nm. Also, in the case of FinFET, when the level of the tunneling current of the drain-body junction is larger than the level of the tunneling current of the drain-channel junction, the off current is kept constant regardless of the change in the gate voltage, and it can operate as a T-CMOS device. can A T-CMOS device implemented as a FinFET, which has a narrow channel width and is greatly affected by the gate, must have a high off-state current, thus increasing standby power.

20(a) is a graph of V _G -I _D according to body doping concentration in the case of having a FinFET structure. 20(b) is a graph of V _G -I _D according to body doping concentration in the case of having a VC-FET structure.

In the T-CMOS device using the VC-FET device according to the embodiment of the present invention, the off current is divided into a tunneling current of a drain-channel junction and a tunneling current of a drain-body junction.

When the body is lightly doped (10 ¹⁸ cm ^-3 to 10 ¹⁹ cm ^-3 ), the amount of tunneling of the drain-body junction is reduced, thereby reducing the off current and lowering the standby power of the ternary inverter.

However, referring to FIG. 20A , in the FinFET, the drain current decreases as the doping concentration of the body decreases, but it can be seen that the drain current changes according to the change in the gate voltage. This means that as the doping concentration of the FinFET body decreases, the magnitude of the off current decreases at a gate voltage lower than the threshold voltage, but the tunneling current of the drain-channel becomes larger than the tunneling current of the drain-body. Therefore, the off current varies depending on the gate voltage, so it cannot operate as a T-CMOS device.

On the other hand, referring to FIG. 20(b), in the VC-FET of the present invention, even if the concentration of the body is lowered, a constant drain current can be seen regardless of the gate voltage, and it can be seen that the drain current rapidly decreases. This is because the VC-FET can have a constant off current regardless of a change in the gate voltage because the tunneling current of the channel is small even if the doping concentration of the body is lowered, so that the VC-FET can be operated as a T-CMOS device. In addition, it can operate as a low-power T-CMOS device due to the low off-state current.

21( a ) is a graph showing a characteristic change of V _G -I _D according to a channel width (W _ch ) in the case of having a FinFET structure. FIG. 21(b) is a graph showing a change in characteristics of V _G -ID according to a channel width ( _{W ch} ) in the case of having a VC-FET structure.

As shown in Fig. 21(a), when the channel width is reduced in the FinFET, since the tunneling size of the drain-channel is changed by a change in the gate voltage (refer to Figs. 18(b) and 18(d)), the off current change can also be seen.

Referring to FIG. 21(a), when the channel width of the FinFET is 20 nm, the tunneling current of the drain-body junction dominates regardless of the change in the gate voltage when the gate voltage is 1 V or less, showing a constant level of drain current.

On the other hand, when the channel width is 10 nm, since the tunneling current of the drain-channel becomes dominant over the tunneling current of the drain-body junction when the gate voltage is 0.5 V or less, the magnitude of the drain current changes according to the change of the gate voltage. In addition, when the channel width is 5 nm, it can be seen that the change in the magnitude of the drain current according to the change in the gate voltage is further increased.

As shown in FIG. 21(b), in the case of the VC-FET, when the channel width is reduced, the drain current decreases while maintaining a constant drain current below the threshold voltage. It can be seen that, when the channel width of the VC-FET is 20 nm, 10 nm, or 5 nm, a constant off current is maintained regardless of the change in the gate voltage. In the case of a VC-FET, the tunneling current of the drain-body junction prevails over the tunneling current of the drain-channel even when the channel width is reduced, so that a constant drain current is generated regardless of the change in the gate voltage at a voltage below the threshold voltage.

A simulation data value for the T-CMOS 300 using a VC-FET according to an embodiment of the present invention will be described with reference to FIGS. 13 and 14 .

Referring to FIG. 13 , the doping concentration of the body 110 is 6×10 ¹⁸ cm ⁻³ , and the doping concentration of the channel 130 is 10 ¹⁸ cm ⁻³ . The doping concentration of the drain 120 is doped with a Gaussian distribution that increases as the distance from the channel 130 increases. The doping concentration of the drain 120 at the channel 130 and the junction is 1×10 ¹⁸ cm ⁻³ , and the doping concentration of the drain 120 at the body 110 and the junction is 6×10 ¹⁸ cm ⁻³ . The thickness (EOT) of the oxide (SiO2) as the gate insulating layer 150 is 3 nm, the channel width ( _ch ) = 10 nm, the channel length ( _ch ) = 60 nm, the channel height ( _ch ) = 150 nm, is 1.3 set to V.

Referring to FIG. 14 , it can be seen that the SS value of the VC-FET is slightly larger than the SS value of the FinFET, but it is almost similar. can

V _DD [V] Off current [A]
(at V _DS =V _DD /2) static power
[pW] SS
(mV/dec) Binary
CMOS 1.3 3.1e-12 4.03 76.94 Planar
T-CMOS 1.3 2.5e-12 3.25 169.6 FinFETT-CMOS 1.3 9.5e-12 12.35 63.05 VC-FET
T-CMOS 1.3 1.5e-12 1.95 67.02

Table 1 summarizes the off current, static power, and SS (Subthreshold Swing) when VDD, VDS=VDD/2 according to the device structure. Binary CMOS, planar MOSFET T-CMOS device (ch = 1 μm), FinFET T-CMOS device (ch = 60 nm, h = 22 nm), VC-FET T-CMOS device (ch = 60 nm, h = 10 nm) ), when VDD, VDS=VDD/2, off current, standby current (static power), and SS (Subthreshold Swing) values are summarized.

A VC-FET can have a smaller SS value than a planar-MOSFET along with a FinFET. The VC-FET has a larger SS value than the FinFET, but has a lower off-state current, so the standby power of the VC-FET is lower. VC-FET has similar standby power to Planar-MOSFET, but can have a shorter channel length, so VC-FET shows the best characteristics when considering integration and standby power at the same time.

The T-CMOS 300 using the VC-FET device according to the embodiment of the present invention removes the tunneling current of the drain-channel depending on the change in the gate voltage in the OFF state, and the drain-channel regardless of the change in the gate voltage. Only the tunneling current component of the body junction can be left behind. In the VC-FET device 100 according to the embodiment of the present invention, the doping concentration of the body 110 is lowered, the channel width is reduced to reduce the size of the off current, and the voltage of the gate is changed even when the size of the off current is reduced. It shows a constant off current regardless of the voltage and can realize low standby power. Therefore, the T-CMOS 300 using the VC-FET device according to the embodiment of the present invention creates two states using the current flowing through the channel, and adds one state using the tunneling current of the drain-body junction. By making it, a ternary element was implemented.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Transistor Device 100 Substrate 110
drain 120 channel 130
source 140 gate insulating layer 150
Gate 160 T-CMOS Device 300

Claims (6)

semiconductor substrate;
a drain region formed on a top surface of the semiconductor substrate;
a channel region formed on an upper surface of the drain region;
a source region formed on an upper surface of the channel region;
a gate insulating layer formed on a side surface of the channel; and
a gate formed on a side surface of the gate insulating layer;
The vertical channel field effect transistor device, characterized in that the drain region is doped with a high concentration as the distance from the channel region. According to claim 1,
The semiconductor substrate is doped with a dopant of a different type than that of the drain region. According to claim 1,
The semiconductor substrate is a vertical channel field effect transistor device, characterized in that doped with a dopant of the same type as the channel region. A T-CMOS device comprising at least two vertical channel field effect transistor devices, wherein the vertical channel field effect transistor device comprises:
semiconductor substrate;
a drain region formed on a top surface of the semiconductor substrate;
a channel region formed on an upper surface of the drain region;
a source region formed on an upper surface of the channel region;
a gate insulating layer formed on a side surface of the channel; and
a gate formed on a side surface of the gate insulating layer;
The T-CMOS device, characterized in that the drain region is doped with a high concentration as the distance from the channel region. 4. The method of claim 3,
The semiconductor substrate is doped with a dopant of a different type than that of the drain region. 4. The method of claim 3,
The semiconductor substrate is doped with a dopant of the same type as the channel region.

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