JPH11204658A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, having an insulating gate type field-effect transistor of an embedded channel structure that is capable of forming an inverted layer of a conductivity type which is reverse to that of the substrate, including a well in a required small area without having to cause laminate defects. SOLUTION: Through selective epitaxial growth method, a first silicon semiconductor layer 11 of the first conductivity type on a semiconductor substrate 10. Subsequently, the second silicon semiconductor layer 12 of a second conductivity type is formed on the first silicon semiconductor layer to form an embedded channel region. Then, a gate insulating film 22 is formed on top of the second silicon semiconductor layer 12, and a gate electrode 30 is formed on the upper surface of the gate insulating film 22. The source and drain regions 17b of the second conductivity type connected with the embedded channel region is formed, at least in the second silicon semiconductor layer 21 on both sides of the gate electrode 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an insulated gate field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Transistors used in semiconductor devices include bipolar transistors and insulated gate field effect transistors (e.g., MOSFETs (metal-oxide-semiconductor FETs having a metal-oxide-semiconductor stack).
ield Effect Transistor)). MOSFE
T is further classified into an N-channel type and a P-channel type. N-channel type MOSFET (hereinafter referred to as NMO
SFET) and P-channel MOSFET
(Hereinafter abbreviated as PMOSFET)
OS (CMOS: Complementary MOS) integrated circuits are widely used as typical LSIs today and consume a large amount of power because they consume negligible power at rest.

[0003] At present, higher performance, higher performance, and higher capacity are required for the performance of semiconductor devices, and accordingly, the manufacturing process of semiconductor devices is accompanied by fine processing for higher integration. Technology is being developed and researched. If the gate length of the MOSFET is reduced for the above purpose, the short channel effect becomes remarkable, for example, punch-through between the source and the drain tends to occur. In order to suppress the short channel effect, it is effective to increase the impurity concentration in a silicon semiconductor layer such as a well where a MOSFET is formed. However, this increases the threshold voltage of the MOSFET and increases the transconductance. And the operation speed is reduced. Therefore, the impurity concentration in the silicon semiconductor layer such as the well is increased, and the impurity concentration in the surface layer region of the silicon semiconductor layer is reduced, thereby suppressing the short channel effect and adjusting the threshold voltage (suppressing the decrease in operation speed). Was realized. In order to reduce the impurity concentration in the surface region of the silicon semiconductor layer, an impurity having a conductivity type opposite to that of the silicon semiconductor layer is introduced into a region at a predetermined depth from the surface of the silicon semiconductor layer.

A CMO in which the gate electrodes of an NMOSFET and a PMOSFET are both formed by an N-type polysilicon gate
In the case of the SFET, since the Fermi level of the silicon semiconductor layer such as the N-type well in the PMOSFET and the N-type polysilicon gate becomes almost equal, the PMOSF is used to make the threshold voltages of the NMOSFET and the PMOSFET uniform.
It is necessary to lower the threshold voltage of ET. In order to further reduce the N-type impurity concentration in a region at a predetermined depth from the surface of the N-type silicon semiconductor layer such as an N-type well for forming the PMOSFET for the purpose of lowering the threshold voltage of the PMOSFET, the P-type introduced into the region is It is effective to further increase the impurity concentration, and finally to a so-called buried channel structure in which the region is inverted to a P-type.

The above-mentioned MOSFE having a buried channel structure
In the method of manufacturing T, in the step of forming an inversion region in a semiconductor layer such as a well, for example, a PMOSFET will be described. As shown in FIG. 10 keV, 3 × 10 ¹⁵ atoms /
Ion implantation was performed at a high concentration at a dose of about cm ² to form the inversion layer 12.

However, when boron B is ion-implanted at a high concentration as described above, even if the implantation energy is selected so that the range Rp of boron B becomes a predetermined depth, FIG.
As shown in (b), the profile of boron B concentration is N
The shape is distributed widely from the mold well or the surface of the N-type silicon substrate 10. If the depth of the inversion layer is too large, the channel formed in the inversion layer is likely to be affected by the drain electric field, causing a problem that the short channel effect becomes remarkable. Must be formed to be an extremely narrow region.

As described above, there is known a method of solid-phase diffusion of boron, which is a P-type impurity, into an N-type well or an N-type silicon substrate, for example, so as to extremely reduce the depth of the inversion layer. According to this method, a high-concentration inversion layer is formed in a region near the surface of the N-type well or the N-type silicon substrate, which causes another problem that carrier scattering is reduced due to carrier scattering by boron as an impurity. I do.

According to the method disclosed in Japanese Unexamined Patent Publication No. 5-41492, as shown in FIG. 8A, for example, a P-type well is formed on an N-type well or an upper layer of an N-type silicon substrate 10 by a selective epitaxial growth method. An inversion layer 12 containing boron as an impurity is formed. In this method, the depth of the inversion layer 12 is controlled by the thickness of the film formed by the selective epitaxial growth method. As shown in FIG. 8B, the profile of the boron B concentration is determined by the N-type well or the N-type silicon. It can be formed to have a desired depth from the surface of the substrate.

[0009]

However, in the method of forming an inversion layer by the selective epitaxial growth method described above, when a thin inversion layer having a thickness of, for example, 50 nm or less is formed, as shown in FIG. There arises a problem that stacking faults D easily occur therein. In order to suppress the generation of the stacking faults D, it is important how to keep the state of the surface of the substrate 10 such as the N-type well at a stage before the selective epitaxial growth is performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device having an insulated gate field effect transistor having a buried channel structure. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can form an inversion layer containing an impurity of the opposite conductivity type at a high concentration without forming a stacking fault in a desired extremely narrow region.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an insulated gate field effect transistor. Forming a first silicon semiconductor layer of the first conductivity type thereon;
Forming a second conductivity-type second silicon semiconductor layer to be a buried channel region above the first silicon semiconductor layer, continuously with the step of forming the first silicon semiconductor layer by selective epitaxial growth; Forming a gate insulating film above the second silicon semiconductor layer;
Forming a gate electrode on the gate insulating film, and forming a second conductivity type source / drain region connected to the buried channel region at least in the second silicon semiconductor layer on both sides of the gate electrode. And a process.

The method of manufacturing a semiconductor device according to the present invention is
Forming a first silicon semiconductor layer of the first conductivity type on the semiconductor substrate by the selective epitaxial growth method, and forming a buried channel in the upper layer of the first silicon semiconductor layer following the step of forming the first silicon semiconductor layer by the selective epitaxial growth method A second conductivity type second silicon semiconductor layer serving as a region is formed. Next, a gate insulating film is formed above the second silicon semiconductor layer, a gate electrode is formed above the gate insulating film, and connected to the buried channel region in at least the second silicon semiconductor layer on both sides of the gate electrode. A source / drain region of the second conductivity type is formed.

According to the method of manufacturing a semiconductor device of the present invention described above, the second conductive type second semiconductor layer, which is an inversion layer to be a buried channel region above the first conductive type first silicon semiconductor layer.
By forming a silicon semiconductor layer, a buried channel type insulated gate field effect transistor can be formed. The formation of the second silicon semiconductor layer is performed continuously with the step of forming the first silicon semiconductor layer by the selective epitaxial growth method, and the surface of the first silicon semiconductor layer on which the second silicon semiconductor layer is laminated is very clean. Therefore, the second silicon semiconductor layer can be formed as a film in which stacking faults are suppressed. Further, since the second silicon semiconductor layer is formed by the selective epitaxial growth method, the inversion layer can be formed in a desired extremely narrow region by controlling the thickness of the second silicon semiconductor layer.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, after the step of forming the second silicon semiconductor layer and before the step of forming the gate insulating film, the step of forming the second silicon semiconductor layer by a selective epitaxial growth method is performed, The method further includes the step of forming a third silicon semiconductor layer with no impurity added on the upper layer of the second silicon semiconductor layer, and in the step of forming the gate insulating film, the step of forming the gate insulating film on the third silicon semiconductor layer. Form. Thereby, the inversion layer (second silicon semiconductor layer) can be formed from the region near the surface of the silicon semiconductor layer by the separation of the thickness of the third silicon semiconductor layer, and the carrier mobility due to carrier scattering due to impurities is reduced. It can be prevented from lowering.

The method for manufacturing a semiconductor device according to the present invention described above includes:
Preferably, the first conductivity type is N-type and the second conductivity type is P-type, forming a P-channel insulated gate field effect transistor. For example, in the case of forming both gate electrodes of an NMOSFET and a PMOSFET with an N-type polysilicon gate in a CMOSFET, a PMO
It is necessary to lower the threshold voltage of the SFET, and by using a P-channel insulated gate field-effect transistor having a buried channel structure as described above,
The threshold voltage of T can be lowered.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, the gate electrode is formed of N-type polysilicon. For example, PMOSFET in CMOSFET
Even if the gate electrode is formed of an N-type polysilicon gate, a PMOSFET capable of lowering the threshold voltage as a buried channel structure can be obtained.

The method of manufacturing a semiconductor device according to the present invention described above includes:
Preferably, the step of forming the first conductivity-type first silicon semiconductor layer includes the step of forming an undoped silicon semiconductor layer to be the first silicon semiconductor layer, and the step of forming the undoped silicon semiconductor layer. Introducing a first conductivity type impurity. The first conductive type first silicon semiconductor layer can be formed by ion implantation of the first conductive type impurity into the impurity-free silicon semiconductor layer.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the gate electrode and before the step of forming the source / drain regions, an impurity of a second conductivity type is implanted using the gate electrode as a mask, and at least both sides of the gate electrode. Forming a low-concentration diffusion layer region in the portion of the second silicon semiconductor layer that contains a second conductivity type impurity at a lower concentration than the source / drain region and is connected to the buried channel region; Forming a side wall at a position facing both side surfaces of the gate electrode, wherein the step of forming the source / drain region has a higher concentration than the low concentration diffusion layer region using the side wall as a mask. Is implanted with a second conductivity type impurity. As a result, LDD (Lightl
y DopedDrain) An insulated gate field effect transistor having a structure can be formed, and the short channel effect can be further suppressed.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an N-channel transistor and a P-channel transistor, wherein an insulating film is formed on a semiconductor substrate. Forming a first opening reaching the semiconductor substrate in the insulating film in the first transistor formation region; and exposing the semiconductor exposed to the first opening by selective epitaxial growth in the first transistor formation region. Forming a first silicon semiconductor layer of a first conductivity type on a substrate and forming the first silicon semiconductor layer by a selective epitaxial growth method; Forming a second silicon semiconductor layer of the second conductivity type to be a channel region, and forming a second transistor Forming a second opening reaching said semiconductor substrate to said insulating film in the range, the second
Forming a third silicon semiconductor layer of the second conductivity type on the semiconductor substrate exposed in the second opening by selective epitaxial growth in a transistor formation region;
Forming a fourth silicon semiconductor layer of the first conductivity type to be a second buried channel region above the third silicon semiconductor layer, continuously with the step of forming the third silicon semiconductor layer by selective epitaxial growth; , The first
Forming a first gate insulating film above the second silicon semiconductor layer in the transistor forming region, and forming a second gate insulating film above the fourth silicon semiconductor layer in the second transistor forming region Forming a first gate electrode above the first gate insulating film in the first transistor formation region;
Forming a second gate electrode on the second gate insulating film in the transistor formation region; and forming the second gate electrode in the second silicon semiconductor layer at least on both sides of the first gate electrode in the first transistor formation region. Forming a first source / drain region of a second conductivity type connected to the one buried channel region; and forming the first source / drain region of the second conductivity type in the fourth silicon semiconductor layer at least on both sides of the second gate electrode in the second transistor formation region. Forming a second source / drain region of the first conductivity type connected to the second buried channel region.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
An insulating film is formed on a semiconductor substrate, a first opening reaching the semiconductor substrate is formed in the insulating film in the first transistor forming region, and the semiconductor substrate is exposed to the first opening in the first transistor forming region by selective epitaxial growth. Forming a first silicon semiconductor layer of the first conductivity type thereon and forming the first silicon semiconductor layer by the selective epitaxial growth method; and forming a first buried channel region in the upper layer of the first silicon semiconductor layer. A two-conductivity-type second silicon semiconductor layer is formed. Next, a second opening reaching the semiconductor substrate is formed in the insulating film in the second transistor formation region, and the second conductivity type is formed on the semiconductor substrate exposed to the second opening by the selective epitaxial growth method in the second transistor formation region. Continuing with the step of forming the third silicon semiconductor layer and forming the third silicon semiconductor layer by the selective epitaxial growth method, the fourth silicon of the first conductivity type which becomes the second buried channel region above the third silicon semiconductor layer A semiconductor layer is formed. Next, a first gate insulating film is formed above the second silicon semiconductor layer in the first transistor formation region, and a second gate insulating film is formed above the fourth silicon semiconductor layer in the second transistor formation region. Next, a first gate electrode is formed on the first gate insulating film in the first transistor formation region, and a second gate electrode is formed on the second gate insulating film in the second transistor formation region.
A gate electrode is formed. Next, a first source / drain region of a second conductivity type connected to the first buried channel region is formed in at least the second silicon semiconductor layer on both sides of the first gate electrode in the first transistor formation region, A first conductivity type second source / drain region connected to the second buried channel region is formed at least in the fourth silicon semiconductor layer on both sides of the second gate electrode in the transistor formation region.

According to the method of manufacturing a semiconductor device of the present invention, an insulated gate field effect transistor having an N-channel transistor and a P-channel transistor, each having an inversion layer serving as a buried channel region is formed. be able to. The formation of the second and fourth silicon semiconductor layers is performed continuously with the step of forming the first and third silicon semiconductor layers by selective epitaxial growth, respectively, and the first and second silicon semiconductor layers are stacked. Since the surfaces of the third and third silicon semiconductor layers are very clean, the second and fourth silicon semiconductor layers can be formed as films in which stacking faults are suppressed. In addition, since the second and fourth silicon semiconductor layers are formed by the selective epitaxial growth method, the inversion layer can be formed in a desired extremely narrow region by controlling the thickness of the second and fourth silicon semiconductor layers.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, the method further includes, after the step of forming the second silicon semiconductor layer and before the step of forming the second opening, covering the surface of the second silicon semiconductor layer with a protective film. This can prevent selective epitaxial growth on the surface of the second silicon semiconductor layer.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, the method further includes a step of removing the protective film after the step of forming the fourth silicon semiconductor layer and before the step of forming the first gate insulating film. Thus, the surface of the second silicon semiconductor layer is exposed again, and the first gate insulating film can be formed thereover.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, after the step of forming the second silicon semiconductor layer, and before the step of forming the second opening, the step of forming the second silicon semiconductor layer by a selective epitaxial growth method is continued. Forming a first impurity-free silicon semiconductor layer above the second silicon semiconductor layer; and after the forming the fourth silicon semiconductor layer and before the forming the first gate insulating film. A step of forming a second impurity-free silicon semiconductor layer above the fourth silicon semiconductor layer, following the step of forming the fourth silicon semiconductor layer by selective epitaxial growth. In the step of forming a gate insulating film, the first gate insulating film is formed on the first undoped silicon semiconductor layer, and the second gate insulating film is formed. In that process, to form the second gate insulating film on the upper layer of the second undoped silicon semiconductor layer. Thereby, the inversion layers (second and fourth silicon semiconductor layers) can be formed from the vicinity of the surface of the silicon semiconductor layer by the separation of the thicknesses of the first and second impurity-free silicon semiconductor layers. It is possible to prevent the carrier mobility from lowering due to carrier scattering due to.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the first undoped silicon semiconductor layer and before the step of forming the second opening, the surface of the first undoped silicon semiconductor layer is covered with a protective film. It further has a step. Thereby, the first
It is possible to prevent selective epitaxial growth on the surface of the silicon semiconductor layer with no impurity added.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the method further includes a step of removing the protective film after the step of forming the second impurity-free silicon semiconductor layer and before the step of forming the first gate insulating film. Thus, the surface of the first impurity-free silicon semiconductor layer is exposed again, and the first gate insulating film can be formed thereover.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the first gate insulating film and the second gate insulating film are formed in the same step. Thus, the first gate insulating film and the second gate insulating film can be formed in a simplified process.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, the first gate electrode and the second gate electrode are formed in the same step. Thus, the first gate electrode and the second gate electrode can be formed in a simplified process. Also, for example, in a CMOSFET, an NMOSFE
Even when both the T and PMOSFET gate electrodes are formed of N-type polysilicon gates, a P-channel insulated gate field-effect transistor having a buried channel structure capable of lowering the threshold voltage of the PMOSFET can be obtained.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the second gate electrode and before the step of forming the first source / drain region, a second conductive type is formed in the first transistor formation region using the first gate electrode as a mask. A second conductivity type impurity at a lower concentration than the first source / drain region in at least the second silicon semiconductor layer on both sides of the first gate electrode; Forming a first low-concentration diffusion layer region connected to the one buried channel region; and implanting a first conductivity type impurity in the second transistor formation region using the second gate electrode as a mask to form at least the second conductive impurity. The fourth silicon semiconductor layer on both sides of the gate electrode contains a first conductivity type impurity at a lower concentration than the second source / drain region, and the second buried channel Forming a second low-concentration diffusion layer region connected to the first gate electrode; and forming a first sidewall at a position facing both side surfaces of the first gate electrode, at a position facing both side surfaces of the second gate electrode. The second sidewall,
And forming the first source / drain region. In the step of forming the first source / drain region, the second conductive type is formed at a higher concentration than the first low concentration diffusion layer region using the first sidewall as a mask. Implanting impurities,
In the step of forming the source / drain regions, a first conductivity type impurity is implanted at a higher concentration than the second low concentration diffusion layer region using the second sidewall as a mask.
Thereby, an insulated gate field effect transistor having an LDD structure can be formed, and the short channel effect can be further suppressed.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a sectional view of a semiconductor device according to this embodiment. For example, the silicon semiconductor substrate 10 is formed on the silicon oxide insulating film 20 formed on the silicon semiconductor substrate 10.
Is formed, and in the opening on the right side of the drawing, a P-channel MOSF is used as a first transistor.
ET (PTr) is formed, and a second opening is formed in the left opening.
N-channel MOSFET (NT
r) is formed to constitute a CMOSFET. Both transistors are separated by an insulating film 20.

In a P-channel MOSFET (PTr), an N ⁻ -type first silicon semiconductor layer 11 containing an N-type impurity such as phosphorus at a low concentration, for example, and a P-type P-type second buried channel region containing high-type impurities
A silicon semiconductor layer (inversion layer) 12 and a first impurity-free silicon semiconductor layer 13 are formed by continuous selective epitaxial growth. On the upper layer, a gate electrode 30 made of N-type polysilicon is formed via a gate insulating film 22 of silicon oxide, for example, and sidewall insulating films 23 of silicon oxide are formed on both sides of the gate electrode 30. . Further, the first silicon semiconductor layer 11, over the second silicon semiconductor layer 12 and the first undoped silicon semiconductor layer 13, P ^- first low concentration diffusion layer of the type (first 1LDD diffusion layer) 17a and, the P ⁺ -type First
Source / drain diffusion layers 17b are formed.

In an N-channel MOSFET (NTr), a P ⁻ -type third silicon semiconductor layer 14 containing a P-type impurity such as boron at a low concentration, for example, and an N-type N-type fourth which becomes a buried channel region containing high-concentration impurities
The silicon semiconductor layer (inversion layer) 15 and the second impurity-free silicon semiconductor layer 16 are formed by continuous selective epitaxial growth. On the upper layer, a gate electrode 30 made of N-type polysilicon is formed via a gate insulating film 22 of silicon oxide, for example, and sidewall insulating films 23 of silicon oxide are formed on both sides of the gate electrode 30. . Further, an N ⁻ -type second low-concentration diffusion layer (second LDD diffusion layer) 18a and an N ⁺ -type second low-concentration diffusion layer 18a are formed over the third silicon semiconductor layer 14, the fourth silicon semiconductor layer 15, and the second impurity-free silicon semiconductor layer 16. Second
A source / drain diffusion layer 18b is formed.

The above P-channel MOSFET (PT
FIG. 2A is an enlarged view of the vicinity of the buried channel region of FIG.
Shown in In the drawings, the gate insulating film and the gate electrode are omitted. An N ⁻ -type first silicon semiconductor layer 11 as an upper layer of the silicon semiconductor substrate 10, a P-type second silicon semiconductor layer (inversion layer) 12 serving as a buried channel region, and a first
Since the impurity-free silicon semiconductor layers 13 are stacked and formed by a continuous selective epitaxial growth method, a stacking fault D occurs near the interface of the first silicon semiconductor layer 11 with the silicon semiconductor substrate 10. However, no stacking faults occur in the second silicon semiconductor layer (inversion layer) 12, which greatly affects the transistor characteristics.

FIG. 2B shows a profile of the concentration of the P-type impurity (for example, boron B concentration) near the buried channel region shown in FIG. 2A. The second region is separated from the region near the surface of the first undoped silicon semiconductor layer 13 by the thickness of the first undoped silicon semiconductor layer 13.
The B concentration is high in the silicon semiconductor layer (inversion layer) 12, and the B concentration is reduced again in the first silicon semiconductor layer 11. Thus, the inversion layer is formed in an extremely narrow region.

A method of manufacturing a semiconductor device having such a structure will be described with reference to the drawings. First, as shown in FIG. 3A, an insulating film 20 made of a silicon oxide layer having a thickness of 0.5 μm is formed on the surface of the silicon semiconductor substrate 10 by, for example, a thermal oxidation method.

Next, as shown in FIG. 3B, a P-channel MOSFET (P
Tr) is formed by patterning a resist film which opens a formation region, and is subjected to etching such as RIE (reactive ion etching) to form a silicon semiconductor substrate 1 in the PTr formation region.
A first opening W _PTr that reaches 0 is formed.

Next, as shown in FIG. 3C, an N ^-- type first silicon semiconductor layer containing an N-type impurity such as phosphorus at a low concentration in the first opening W _PTr by a selective epitaxial growth method. 11 is grown to a thickness of, for example, 0.4 μm,
By switching the material gas, the P-type second silicon semiconductor layer (inversion layer) 12 serving as a buried channel region containing a P-type impurity such as boron at a high concentration is, for example, 50 nm in thickness.
The first impurity-free silicon semiconductor layer 13 is continuously grown to a thickness of, for example, 15 nm by switching the material gas again. Here, conditions for the selective epitaxial growth method include, for example, (deposition temperature: 850 ° C., material gas and flow rate: SiCl ₂ H ₂ / HCl = 200 /
The doping gas may be, for example, PH ₃ for N-type and B ₂ H ₆ for P-type, for example. Next, the first impurity-free silicon semiconductor layer 1 is formed by, for example, a thermal oxidation method.
The three surfaces are oxidized to form a protective film 21 of, for example, 10 nm made of silicon oxide. At this time, the thickness of the first impurity-free silicon semiconductor layer 13 is about 10 nm.

Next, as shown in FIG. 4D, an N-channel MOSFET (N
Tr) is formed by patterning a resist film that opens the formation region, and is subjected to etching such as RIE to form a second opening W _NTr reaching the silicon semiconductor substrate 10 in the NTr formation region _.
To form

Next, as shown in FIG. 4E, the first silicon semiconductor layer 11, the second silicon semiconductor layer (inversion layer) 1
By the selective epitaxial growth method under the same conditions as the formation method of the second and first impurity-free silicon semiconductor layers 13,
In the second opening W _NTr , a P ⁻ -type third silicon semiconductor layer 14 containing a P-type impurity such as boron at a low concentration is grown to a thickness of, for example, 0.4 μm, and the material gas is switched.
For example, an N-type fourth silicon semiconductor layer (inversion layer) 15 serving as a buried channel region containing a high concentration of N-type impurities such as phosphorus is continuously grown to a thickness of, for example, 50 nm, and the material gas is switched again. Then, the second impurity-free silicon semiconductor layer 16 is continuously grown to a thickness of, for example, 10 nm.

Next, as shown in FIG. 4F, an upper layer of the first impurity-doped silicon semiconductor layer 13 in the PTr formation region and a second impurity-doped silicon semiconductor layer 16 in the NTr formation region by, for example, thermal oxidation. A thin silicon oxide film is formed in the upper layer to form a gate insulating film 22. As a method of forming the gate insulating film 22, CVD (Chemical Va)
por Deposition) method, or a high dielectric film such as Ta ₂ O ₅ may be used in addition to the silicon oxide film. Next, N-type polysilicon containing N-type impurities is deposited on the gate insulating film 22 in both the PTr formation region and the NTr formation region by, for example, a CVD method, and is processed into a gate electrode pattern. An electrode 30 is formed. Next, PTr is used with the gate electrode 30 as a mask.
In the formation region, a P-type impurity such as boron is ion-implanted with low efficiency to form a P ⁻ -type first low concentration diffusion layer (first LD).
D diffusion layer) 17a is formed, and N-type impurities such as phosphorus are ion-implanted with a low efficiency in the NTr formation region to form N ⁻
A second low concentration diffusion layer (second LDD diffusion layer) 18a is formed.

Next, silicon oxide is deposited on the entire surface by, for example, a CVD method, and the entire surface is etched back by etching such as RIE to form a sidewall insulating film 23. Next, using the sidewall insulating film 23 as a mask, a P-type impurity such as boron is ion-implanted with high efficiency in the PTr formation region to form a P ⁺ -type first source / drain diffusion layer 17b. Then, an N-type impurity such as phosphorus is ion-implanted with high efficiency to form an N ⁺ -type source / drain diffusion layer 18b. Thus, the semiconductor device shown in FIG. 1 is obtained. In the subsequent steps, a desired semiconductor device can be manufactured by, for example, forming an interlayer insulating film on the entire surface, opening a contact hole, and forming an upper layer wiring.

According to the method of manufacturing the semiconductor device of the present embodiment, the second conductive type second silicon semiconductor layer which is an inversion layer to be a buried channel region above the first conductive type first silicon semiconductor layer. To form a buried channel type insulated gate field effect transistor. The formation of the second silicon semiconductor layer is performed continuously with the step of forming the first silicon semiconductor layer by the selective epitaxial growth method, and the surface of the first silicon semiconductor layer on which the second silicon semiconductor layer is laminated is very clean. Therefore, the second silicon semiconductor layer can be formed as a film in which stacking faults are suppressed. Further, since the second silicon semiconductor layer is formed by the selective epitaxial growth method, the inversion layer can be formed in a desired extremely narrow region by controlling the thickness of the second silicon semiconductor layer.

Further, from the region near the surface of the first impurity-free silicon semiconductor layer 13 as shown in FIG.
The B concentration becomes high in the second silicon semiconductor layer (inversion layer) 12 where the thickness of the impurity-free silicon semiconductor layer 13 is separated, and the B concentration again becomes a profile in the first silicon semiconductor layer 11. An inversion layer can be formed in a narrow region. Therefore, it is possible to prevent the carrier mobility from being reduced due to the carrier scattering due to the impurities, and to suppress the remarkable short channel effect due to the wide inversion layer.

Second Embodiment FIG. 5 is a sectional view of a semiconductor device according to the second embodiment . For example, an impurity-free silicon semiconductor layer 10a formed on the silicon semiconductor substrate 10 is formed. In a region on the right side in the drawing separated by the trench-type element isolation insulating film 24 of silicon oxide, P is used as a first transistor. Channel type MOSF
An ET (PTr) is formed, and an N-channel MOSFET (NTr) is formed as a second transistor in a left region.
Are formed to constitute a CMOSFET.

In a P-channel type MOSFET (PTr), an N ⁻ -type first silicon semiconductor layer 11 containing an N-type impurity such as phosphorus at a low concentration is formed on a silicon semiconductor substrate 10 without impurities. Silicon semiconductor layer 10a, a P-type second silicon semiconductor layer (inversion layer) 12 serving as a buried channel region containing a P-type impurity such as boron at a high concentration, and an impurity-free silicon semiconductor layer 13 are respectively continuous. It is formed by the selective epitaxial growth method described above. On the upper layer, a gate electrode 30 made of N-type polysilicon is formed via a gate insulating film 22 of, for example, silicon oxide.
On both sides of the silicon oxide sidewall insulating film 23
Are formed. Also, the first silicon semiconductor layer 11,
Over the second silicon semiconductor layer 12 and the undoped silicon semiconductor layer 13, a P ⁻ -type first low concentration diffusion layer (first LDD diffusion layer) 17 a and a P ⁺ -type first source layer
A drain diffusion layer 17b is formed.

In the N-channel MOSFET (NTr), the impurity-free single-crystal silicon semiconductor layer 10a formed on the silicon semiconductor substrate 10 contains a low concentration of a P-type impurity such as boron. A P ^- type third silicon semiconductor layer 14 is formed. On the upper layer, a gate electrode 30 made of N-type polysilicon is formed via a gate insulating film 22 of silicon oxide, for example, and sidewall insulating films 23 of silicon oxide are formed on both sides of the gate electrode 30. . In the third silicon semiconductor layer 14, an N ^-- type second low concentration diffusion layer (second LDD diffusion layer) 18a and an N ⁺ -type second source / drain diffusion layer 18b are formed.

In the semiconductor device according to the present embodiment, as in the first embodiment, no stacking fault occurs in the second silicon semiconductor layer (inversion layer) 12 which greatly affects the transistor characteristics. Also in the present embodiment, the second silicon semiconductor layer (inversion layer) 12 is separated from the region near the surface of the undoped silicon semiconductor layer 13 by the thickness of the undoped silicon semiconductor layer 13 and is higher. B concentration and the first silicon semiconductor layer 11
In this case, the B concentration again becomes a profile in which the inversion layer is formed in an extremely narrow region.

A method for manufacturing a semiconductor device having such a structure will be described with reference to the drawings. First, as shown in FIG. 6A, an impurity-free single-crystal silicon semiconductor layer 10a is grown on the surface of the silicon semiconductor substrate 10 by selective epitaxial growth to a thickness of, for example, about 1.0 μm. To form a buried channel region containing a high concentration of a P-type impurity such as boron.
Second silicon semiconductor layer (inversion layer) 12 of
The impurity-doped silicon semiconductor layer 13 is continuously grown to a thickness of, for example, 10 nm by switching the material gas again. Here, conditions for the selective epitaxial growth method include, for example, (deposition temperature: 850 ° C., material gas and flow rate: SiCl ₂ H ₂ / HCl = 200 /
When the P-type second silicon semiconductor layer 12 is deposited, for example, B ₂ H ₆ can be used as the doping gas.

Next, as shown in FIG. 6B, a resist film is formed on an element isolation pattern excluding a P-channel MOSFET (PTr) formation region and an N-channel MOSFET (NTr) formation region, and RIE or the like is performed. Etching is performed to form a trench-like element isolation groove. next,
For example, silicon oxide is buried in a trench-like element isolation groove by CVD, and is deposited on the entire surface by, for example, CMP.
(Chemical Mechanical Polishing) The silicon oxide outside the trench-shaped isolation trench is removed by polishing or etch-back, and the trench isolation insulating film 2 is formed.
4 is formed.

Next, as shown in FIG. 6 (c), the N-type impurity of the PTr forming region such as phosphorus etc. is ion implanted N ^- -type well, N ^- first silicon semiconductor layer type It is assumed to be 11. On the other hand, a P ⁻ -type well is formed by ion-implanting a P-type impurity such as boron into the NTr formation region to form the P ⁻ -type third silicon semiconductor layer 14. At this time, by forming the P ⁻ -type third silicon semiconductor layer 14, no inversion layer is formed in the NTr formation region. Next, similarly to the first embodiment, a gate insulating film 22 and a gate electrode 30 are sequentially formed, and the gate electrode 3 is formed.
By ion implantation using 0 as a mask, a first P ^- type low-concentration diffusion layer (first LDD diffusion layer) 17a and a second N ^- type low-concentration diffusion layer (second LDD diffusion layer) 18a are formed.

Next, a sidewall insulating film 23 is formed, and the P ⁺ -type first source / drain diffusion layer 17b and the N ⁺ -type source / drain diffusion layer 18b are formed by ion implantation using the sidewall insulating film 23 as a mask. Are formed respectively. This leads to the semiconductor device shown in FIG. In the subsequent steps, a desired semiconductor device can be manufactured by, for example, forming an interlayer insulating film on the entire surface, opening a contact hole, and forming an upper layer wiring.

According to the method of manufacturing a semiconductor device of the present embodiment, as in the first embodiment, the second layer, which is an inversion layer to be a buried channel region above the first silicon semiconductor layer of the first conductivity type. By forming the conductive second silicon semiconductor layer, a buried channel type insulated gate field effect transistor can be formed. The formation of the second silicon semiconductor layer is performed continuously to the step of forming the first silicon semiconductor layer by the selective epitaxial growth method.
Since the surface of the first silicon semiconductor layer on which the silicon semiconductor layer is stacked is very clean, the second silicon semiconductor layer can be formed as a film in which stacking faults are suppressed. In addition, the second epitaxial growth method
Since the silicon semiconductor layer is formed, the inversion layer can be formed in a desired extremely narrow region by controlling the thickness of the second silicon semiconductor layer.

Further, similarly to the first embodiment, the second region is separated from the region near the surface of the undoped silicon semiconductor layer 13 by the thickness of the undoped silicon semiconductor layer 13.
The B concentration becomes high in the silicon semiconductor layer (inversion layer) 12 and the B concentration again becomes a profile in the first silicon semiconductor layer 11, so that the inversion layer can be formed in an extremely narrow region. Therefore, it is possible to prevent the carrier mobility from being reduced due to the carrier scattering due to the impurities, and to suppress the remarkable short channel effect due to the wide inversion layer.

The present invention is applicable to any semiconductor device having a buried channel type insulated gate transistor, such as a semiconductor memory device such as a DRAM, a semiconductor device such as an A / D converter, or a semiconductor device such as a logical operation element. Applicable to

The present invention is not limited to the above embodiment. For example, the gate electrode may have a single-layer structure, a two-layer structure such as polycide, or a three- or more-layer structure.
The gate insulating films of the N-channel transistor and the P-channel transistor may have different thicknesses.
The DD width may be different. Alternatively, P-type polysilicon can be used as a gate electrode of a P-channel transistor. In addition, various changes can be made without departing from the spirit of the present invention.

[0057]

According to the present invention, there is provided a method of manufacturing a semiconductor device having an insulated-gate field-effect transistor having a buried channel structure, which comprises a high concentration of impurities of a conductivity type opposite to that of a substrate such as a well. A method for manufacturing a semiconductor device in which a layer can be formed without forming stacking faults in a desired extremely narrow region can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment;

FIG. 2A is an enlarged view of a buried channel region of the semiconductor device according to the first embodiment, and FIG. 2B is an impurity (boron B) concentration profile in a depth direction of a corresponding region. .

FIGS. 3A and 3B are cross-sectional views illustrating a manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 3A is a diagram illustrating an insulating film forming process, and FIG. 3B is a diagram illustrating a first opening forming process. Until,
(C) shows up to the step of forming the protective film.

FIG. 4 is a sectional view showing a step subsequent to that of FIG. 3;
(D) shows the steps up to the formation of the second opening, (e) shows the steps up to the step of forming the second impurity-free silicon semiconductor layer, and (f) shows the steps up to the step of forming the low concentration diffusion layer.

FIG. 5 is a sectional view of a semiconductor device according to a second embodiment.

FIGS. 6A and 6B are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a second embodiment, in which FIG. 6A is a diagram up to a process of forming an undoped silicon semiconductor layer, and FIG. (C) shows the steps up to the step of forming the insulating film and the steps up to the step of forming the low concentration diffusion layer.

FIG. 7A is an enlarged view of an inversion layer region according to a first conventional example, and FIG. 7B is an impurity (boron B) concentration profile in a depth direction of a corresponding region.

FIG. 8A is an enlarged view of an inversion layer region according to a second conventional example, and FIG. 8B is an impurity (boron B) concentration profile in a depth direction of a corresponding region.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 10a ... Single-crystal silicon semiconductor layer, 11 ... First silicon semiconductor layer, 12 ... Second silicon semiconductor layer (inversion layer), 13 ... First impurity-free silicon semiconductor layer, 14 ... Third silicon Semiconductor layer, 15: fourth silicon semiconductor layer (inversion layer), 16: second impurity-free silicon semiconductor layer, 17a: first low concentration diffusion layer, 17
b: first source / drain diffusion layer, 18a: second low concentration diffusion layer, 18b: second source / drain diffusion layer, 20 ...
Insulating film, 21: protective film, 22: gate insulating film, 23: sidewall insulating film, 30: gate electrode, D: stacking fault, PTr: P-channel MOSFET, NTr: N-channel MOSFET, W _PTr : first Opening, W _NTr …
Second opening, B: impurity (boron).

Claims (15)

[Claims] 1. A method of manufacturing a semiconductor device having an insulated gate field effect transistor, comprising: forming a first silicon semiconductor layer of a first conductivity type on a semiconductor substrate by a selective epitaxial growth method; Forming a second conductivity-type second silicon semiconductor layer serving as a buried channel region above the first silicon semiconductor layer, following the step of forming the first silicon semiconductor layer; Forming a gate insulating film above the layer; forming a gate electrode above the gate insulating film; connecting to the buried channel region in the second silicon semiconductor layer at least on both sides of the gate electrode Second
Forming a conductive type source / drain region. 2. After the step of forming the second silicon semiconductor layer and before the step of forming the gate insulating film, the step of forming the second silicon semiconductor layer by a selective epitaxial growth method is continued. Forming a third silicon semiconductor layer containing no impurities on the second silicon semiconductor layer; and forming the gate insulating film in the third silicon semiconductor layer.
2. The method according to claim 1, wherein the gate insulating film is formed on a silicon semiconductor layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said first conductivity type is N-type and said second conductivity type is P-type, and a P-channel insulated gate field effect transistor is formed. . 4. The method according to claim 3, wherein said gate electrode is formed of N-type polysilicon. 5. The step of forming the first silicon semiconductor layer of the first conductivity type includes the step of forming an undoped silicon semiconductor layer to be a first silicon semiconductor layer; and the step of forming the undoped silicon semiconductor layer. Introducing a first conductivity type impurity into the semiconductor device. 6. After the step of forming the gate electrode and before the step of forming the source / drain regions, implanting a second conductivity type impurity using the gate electrode as a mask,
A low-concentration diffusion layer region containing a second-conductivity-type impurity at a lower concentration than the source / drain region and connected to the buried channel region is provided in at least the second silicon semiconductor layer on both sides of the gate electrode. Forming, further comprising a step of forming a sidewall at a position opposed to both side surfaces of the gate electrode, wherein the step of forming the source / drain region comprises:
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductivity type impurity is implanted at a higher concentration than the low concentration diffusion layer region using the sidewall as a mask. 7. A method for manufacturing a semiconductor device having an N-channel transistor and a P-channel transistor, comprising: forming an insulating film on a semiconductor substrate; and forming the semiconductor substrate on the insulating film in a first transistor forming region. Forming a first opening reaching the first opening, and forming a first conductivity-type first silicon semiconductor layer on the semiconductor substrate exposed to the first opening by selective epitaxial growth in the first transistor formation region. And forming a second silicon semiconductor layer of the second conductivity type to be a first buried channel region above the first silicon semiconductor layer, continuously with the step of forming the first silicon semiconductor layer by selective epitaxial growth. Forming a second opening reaching the semiconductor substrate in the insulating film in a second transistor formation region. Forming a third silicon semiconductor layer of a second conductivity type on the semiconductor substrate exposed in the second opening by selective epitaxial growth in the second transistor formation region; Forming a fourth silicon semiconductor layer of the first conductivity type to be a second buried channel region above the third silicon semiconductor layer, following the step of forming the third silicon semiconductor layer; Forming a first gate insulating film above the second silicon semiconductor layer in a region; forming a second gate insulating film above the fourth silicon semiconductor layer in the second transistor forming region; Forming a first gate electrode above the first gate insulating film in a first transistor formation region; Forming a second gate electrode above the second gate insulating film in the second transistor formation region; and forming a second gate electrode in the second silicon semiconductor layer at least on both sides of the first gate electrode in the first transistor formation region. Forming a first source / drain region of a second conductivity type connected to the first buried channel region in the second transistor forming region; and forming the fourth silicon semiconductor layer at least on both sides of the second gate electrode in the second transistor forming region Forming a second source / drain region of the first conductivity type connected to the second buried channel region therein. 8. The method according to claim 1, wherein after the step of forming the second silicon semiconductor layer and before the step of forming the second opening,
The method of manufacturing a semiconductor device according to claim 7, further comprising a step of covering a surface of the silicon semiconductor layer with a protective film. 9. The semiconductor device according to claim 8, further comprising a step of removing the protective film after the step of forming the fourth silicon semiconductor layer and before the step of forming the first gate insulating film. Production method. 10. After the step of forming the second silicon semiconductor layer and before the step of forming the second opening, the step of forming the second silicon semiconductor layer by a selective epitaxial growth method is continued. Forming a first impurity-free silicon semiconductor layer above the second silicon semiconductor layer; and forming the first gate insulating film after the forming the fourth silicon semiconductor layer. And forming a second impurity-free silicon semiconductor layer on the fourth silicon semiconductor layer continuously with the step of forming the fourth silicon semiconductor layer by selective epitaxial growth. In the step of forming one gate insulating film, the first gate insulating film is formed on the first impurity-free silicon semiconductor layer, and the second gate insulating film is formed. In the step of forming, method for manufacturing a semiconductor device according to claim 7, wherein forming the second gate insulating film on the upper layer of the second undoped silicon semiconductor layer. 11. A step of forming a first impurity-doped silicon semiconductor layer and covering the surface of the first impurity-doped silicon semiconductor layer with a protective film before the step of forming the second opening. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of: 12. The method according to claim 11, further comprising the step of removing the protective film after the step of forming the second impurity-free silicon semiconductor layer and before the step of forming the first gate insulating film. A method for manufacturing a semiconductor device. 13. The method according to claim 7, wherein the first gate insulating film and the second gate insulating film are formed in the same step. 14. The method according to claim 7, wherein the first gate electrode and the second gate electrode are formed in the same step. 15. After the step of forming the second gate electrode and before the step of forming the first source / drain region, a second conductive layer is formed in the first transistor formation region using the first gate electrode as a mask. Of the second gate at least on both sides of the first gate electrode.
A silicon semiconductor layer containing a second conductivity type impurity at a lower concentration than the first source / drain region;
Forming a first low-concentration diffusion layer region connected to the buried channel region; and implanting a first conductivity type impurity in the second transistor formation region using the second gate electrode as a mask to form at least the second gate. In the fourth silicon semiconductor layer on both sides of the electrode, the second source
Forming a second low-concentration diffusion layer region containing a first conductivity type impurity at a lower concentration than the drain region and connecting to the second buried channel region; and opposing both side surfaces of the first gate electrode. Forming a first sidewall at a position, and forming a second sidewall at a position facing both side surfaces of the second gate electrode. The step of forming the first source / drain region further comprises: Implanting impurities of a second conductivity type at a higher concentration than the first low-concentration diffusion layer region using the first sidewall as a mask, and forming the second source / drain region; 8. The method according to claim 7, wherein the first conductivity type impurity is implanted at a higher concentration than the second low concentration diffusion layer region using the wall as a mask.