JP2003051551A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize increase of operating current and reduction of junction capacitance caused by substrate floating without using an expensive SOI substrate, and solve the problems of thermal resistance and crystal defect which are the defects on an SOI substrate. SOLUTION: An N (P) well NWL (PML) is arranged between a P (N) semiconductor region PA (PN) in which an N (P) channel MISFET Qn (Qp) is arranged and a semiconductor substrate IS. As a result, the P (N) semiconductor region PA (PN) is electrically isolated from the semiconductor substrate IS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device technology, and more particularly to a method of manufacturing a semiconductor device having a field effect transistor and a technology effectively applied to the semiconductor device technology.

[0002]

2. Description of the Related Art A technique studied by the present inventors is, for example, a semiconductor device structure in which a field-effect transistor is provided on a partially depleted SOI (Silicon On Insulator) substrate. SO
The I substrate has a structure in which a thin semiconductor layer is provided on a base insulating layer and an element such as a field effect transistor is formed on the main surface of the semiconductor layer. When a voltage is applied to the gate electrode of the field-effect transistor of this structure, the depletion layer spreads from the gate insulating film side, but even if the width of the depletion layer where the inversion layer is formed reaches the maximum, it should not reach the underlying insulating layer. Therefore, a substrate region that is not depleted is left. This structure is most often used, but since the substrate (that is, the semiconductor layer) is electrically insulated, the substrate potential rises when conducting,
As a result of lowering the threshold voltage, there is an effect that a large drive current can be obtained. In addition, the depletion layer of the junction between the source and drain semiconductor regions and the channel layer spreads over the base insulating layer, and the junction capacitance can be significantly reduced.

Regarding the partially depleted SOI substrate, for example, Scalability of SOI Technology into 0.13
μm 1.2V CMOS Generation, E.Leobandung, et.al, Tec
h.Digest of IEDM98, pp403-406, 1998. IBM.

[0004]

However, the above SOI
In the semiconductor device technology using a substrate, the substrate price is expensive, which is usually five times as high as that of the substrate, and because the element region is covered with an insulator, the thermal resistance is large and the junction temperature easily rises. Is more than the normal board structure,
Further, since the element regions are completely separated by the insulator, it is difficult to control the floating of the substrate potential. Therefore, how to realize the advantages of the SOI structure with a normal substrate structure has become an important issue.

An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

Another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the present invention separates the semiconductor substrate and the semiconductor region in which the channel of the field effect transistor is formed in the main surface thereof by a pn junction.

Further, according to the present invention, between the semiconductor substrate and the semiconductor region in which the field effect transistor formed in the main surface thereof is formed, the semiconductor substrate and the semiconductor region are separated from each other. The semiconductor region of the opposite conductivity type is provided.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION In the following embodiments, when there is a need for convenience, description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are unrelated to each other. However, one of them is in a relationship of a modification, details, supplementary explanation, etc. of a part or all of the other.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.) of the elements, the number is explicitly specified and the number is obviously limited to a specific number in principle. The number is not limited to the specific number except the case, and may be a specific number or more or less.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not always essential unless explicitly stated or in principle considered to be essential. Needless to say

Similarly, in the following embodiments, when referring to shapes, positional relationships, etc. of constituent elements, etc., except when explicitly stated or when it is considered that it is apparently not in principle, it is substantially the same. In addition, the shape and the like are included or similar. This also applies to the above numerical values and ranges.

Further, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

Further, in this embodiment, a MIS • FET (Metal Insula) representing a field effect transistor is used.
tor Semiconductor Field Effect Transistor) MI
Abbreviated as S, p-channel type MIS • FET is abbreviated as pMIS, and n-channel type MIS • FET is abbreviated as nMIS.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a cross-sectional view of essential parts in a logic circuit portion of a semiconductor chip 1C constituting a semiconductor device according to an embodiment of the present invention. Further, FIG. 2 shows an impurity concentration distribution of a semiconductor substrate (hereinafter, simply referred to as a substrate) 1S that constitutes the semiconductor chip 1C.

The substrate 1S is made of, for example, p-type silicon (S
i) It consists of a single crystal and its main surface (device formation surface)
Is a groove type isolation part (SGI; Shallow Groove Isolatio)
n) 2 is formed. The groove type separating part 2 is, for example, a base.
After forming a separation groove on the main surface of the plate 1S, fill the inside of the groove.
A silicon oxide film (Si
O₂), Etc., and then
CMP (Chemical Mechani) so that it is left only in the groove
formed by polishing with cal polishing, etc.
Has been. Depth of the groove-shaped separating portion 2 (from the main surface of the substrate 1S
The distance to the bottom surface of the separating portion 2) is, for example, 0.2 to 0.3.
It is about μm. The area surrounded by the groove-shaped separating portion 2 is
It is an active region (device formation region). This board
In 1S, the p-type semiconductor region PA (first
A conductive type semiconductor region) is formed. p-type semiconductor
In the area PA, for example, boron (B) or borofluoride is used.
Elementary (BF ₂) Is contained. Here, the p-type
NMI for logic circuit formed in semiconductor area PA
SQn is illustrated.

The nMISQn has semiconductor regions 3 and 3 for source and drain, a channel region CHn, a gate insulating film 4 and a gate electrode 5. The semiconductor regions 3 and 3 for the source and drain are arranged so as to be paired on both sides of the channel region CHn formed in the p-type semiconductor region PA, and are arranged in the vicinity of the channel region CHn. N-type semiconductor region 3a
And an n ⁺ type semiconductor region 3b arranged at a position separated from the channel region CHn with the n type semiconductor region 3a interposed therebetween. n-type semiconductor regions 3a and n
^{Both the +} type semiconductor regions 3b contain, for example, phosphorus (P) or arsenic (As), but the n type semiconductor regions 3a are also called extension regions,
The impurity concentration is set to be lower than that of the n ⁺ type semiconductor region 3b. That is, LD
It has a D (Lightly Doped Drain) structure.

Further, in the structure of the first embodiment to be described later, the p-type semiconductor region PA is brought into an electrically floating state and the threshold voltage is lowered, so that the threshold voltage is prevented from being lowered too much. Therefore, by increasing the impurity concentration of the channel region CHn, the threshold voltage is set to be 50 mV to 100 mV higher than usual. Here, in order to adjust the threshold voltage, for example, boron is ion-implanted into the channel region CHn from the main surface of the substrate 1S with an ion implantation energy of about 10 keV.

The gate insulating film 4 is made of, for example, silicon oxide (SiO ₂ ), and its thickness is, in terms of silicon dioxide, 2.5 nm or less, for example, 1.5 nm.
It is about nm. However, the material of the gate insulating film is not limited to this, and various changes can be made. For example, the gate insulating film 4 may be a silicon oxynitride film (SiON). That is, a structure may be adopted in which nitrogen is segregated at the interface between the gate insulating film 4 and the substrate 1S. The silicon oxynitride film is more effective than the silicon oxide film in suppressing the generation of interface states in the film and reducing electron traps, so that the hot carrier resistance of the gate insulating film 4 can be improved and the insulating property can be improved. The resistance can be improved. Further, since the silicon oxynitride film is less likely to be penetrated by impurities than the silicon oxide film, by using the silicon oxynitride film,
It is possible to suppress variation in threshold voltage due to diffusion of impurities in the gate electrode material toward the substrate 1S side. To form a silicon oxynitride film, for example, the substrate 1S
May be heat-treated in a nitrogen-containing gas atmosphere such as NO, NO ₂ or NH ₃ . Further, after forming the gate insulating film 4 made of silicon oxide on the surface of the substrate 1S, the substrate 1S is heat-treated in the above-described nitrogen-containing gas atmosphere to segregate nitrogen at the interface between the gate insulating film 4 and the substrate 1S. Also, the same effect as described above can be obtained. Further, the gate insulating film 4 may have a structure in which a silicon nitride film is laminated on a silicon oxide film. Furthermore, the gate insulating film 4 is
For example, HfO ₂ (dielectric constant ε = 20.6), ZrO ₂ (ε =
24.7), Al ₂ O ₃ (ε = 8.4), Y ₂ O ₃ (ε = 1
4), HfSiO ₄ , ZrSiO ₄ (ε = 19.4), or other high dielectric film.

The gate electrode 5 is made of, for example, low resistance polycrystalline silicon. However, the present invention is not limited to this, and various modifications are possible. For example, a so-called polycide gate electrode structure or low resistance in which a silicide layer such as cobalt silicide (CoSi _x ) is provided on a low resistance polycrystalline silicon film. Tungsten nitride (W
A so-called polymetal gate electrode structure in which a metal film such as tungsten is provided via a barrier metal layer such as N) may be used. LD on the side surface of the gate electrode 5
In order to form the D structure, the sidewall 7 made of, for example, a silicon oxide film is formed. Also, the gate length is
0.1 if the thickness of the gate insulating film 4 is about 2.5 nm
The thickness is about 4 μm and about 0.08 μm if the thickness of the gate insulating film 4 is about 1.5 nm. Further, the power supply voltage on the high potential side of the logic circuit region in which the nMISQn is formed is
For example, it is about 1.5 V to 0.7 V, which is relatively lower than the power supply voltage on the high potential side of the peripheral circuit region. In the semiconductor chip 1C, a peripheral circuit area (for example, an input circuit,
The power supply voltage on the high potential side of the output circuit and the input / output bidirectional circuit) is, for example, about 3.0V or 3.3V.

Such nMISQn is covered with the interlayer insulating film 8 deposited on the main surface of the substrate 1S.
The interlayer insulating film 8 is made of, for example, a silicon oxide film, and the first layer wiring 9 is formed on the upper surface thereof. The first layer wiring 9 is made of, for example, aluminum or aluminum alloy, and has a contact hole 10 formed in the interlayer insulating film 8.
Is electrically connected to the semiconductor region 3 for the source and the drain.

By the way, the present inventors have found that partially depleted S
During the development of a semiconductor device using an OI substrate, when a partially depleted SOI substrate is used, most of the advantages over the case of using a normal substrate are that the driving current increases due to the substrate floating and the junction capacitance decreases. And found that Therefore, in order to realize a structure that produces such an advantage on a normal substrate, the following configuration is adopted.

That is, in the first embodiment, n
P-type semiconductor region PA in which MISQn is formed and below
N-well NWL (second conductivity type half
Conductor areas) are provided. This n-well NWL
The pure substance distribution is obtained by comparing the substrate 1S and the p-type semiconductor region PA and
The channel region CHn and the substrate 1S are not electrically connected
In the depth from the main surface of the substrate 1S,
The p-type semiconductor is located at a position slightly shallower than the bottom of the remote part 2.
Groove-shaped separation from a position deeper than the peak position of the body area PA
It will be distributed in a position slightly deeper than the bottom of part 2.
Is formed. That is, in the first embodiment
Of the nMISQn channel region CHn and p-type
The semiconductor region PA and the substrate 1S are the n-well NWL and the substrate.
It is electrically isolated by a pn junction with 1S. This
This is a semiconductor for the source and drain of nMISQn.
With the power supply voltage applied to the body region 3, the channel
Depletion layer between junctions in the region CHn (p-type semiconductor region PA)
Width and channel region CHn (p-type semiconductor region PA)
By the depletion layer extending between the n-well NWL and n ⁺Type
The semiconductor region 3b of n is not connected to the n-well NWL
Need to do so. That is, the distance x1 in FIG.
Must be larger than the sum of the above depletion layer widths. Well
The width x2 of the n-well NWL itself is also the channel region CHn.
A depletion layer between the (p-type semiconductor region PA) and the substrate 1S
Should not be extinguished by the depletion layer between
It That is, the width x2 is larger than the sum of the widths of the depletion layers.
I need to listen. The n-well NWL is formed in the groove
After forming the mold separation part 2, for example, phosphorus is added at 450 keV.
From the main surface of the substrate 1S with a degree of ion implantation energy
It is formed by ion implantation. In addition, n
The impurity concentration at the peak position of LNWL is shown in FIG.
Like, for example, 10¹⁸/ Cm³Or slightly lower
Is.

By providing such an n-well NWL
From the viewpoint of the performance of the semiconductor device, the SOI substrate was used.
The same effect as the case can be obtained. Ie conduction
Sometimes, the gate electrode 5 and the channel region CHn (p-type
Channel region CH due to capacitive coupling with semiconductor region PA)
Increase in potential of n (p-type semiconductor region PA) and drain
An electric current flows and a hole is generated by impact ionization.
Channel region CHn (p-type semiconductor region
NMISQn threshold due to the rise of the potential in the area PA)
Value voltage decreases and current increases. Figure 3 shows the form
The nMISQn of state 1 and the communication that does not have the n-well isolation structure.
Gate of drain current with nMIS formed on ordinary substrate
Voltage dependence. In the first embodiment, the
The channel region CHn (p-type semiconductor region PA) is electrically isolated.
Since the gate voltage is applied, the threshold voltage is
The pressure is reduced and the drain current can be increased.
Also, the semiconductor region 3 for the source and drain and the substrate 1
The junction capacitance with S is n ⁺Type semiconductor region 3b and cha
Junction capacitance with the channel region CHn (p-type semiconductor region PA)
And channel regions CHn (p-type semiconductor region PA) and n
Junction capacitance with well NWL, n well NWL and substrate 1
Since the junction capacitance with S is connected in series, n
Reduction to about 1/3 of the case without well NWL
You can By these, the circuit including this transistor
It is possible to improve the operating speed of.

Further, the channel region CHn (p-type semiconductor region PA) and the substrate 1S are not completely separated by the insulator, but they are separated by the n well NWL, which is more than that of the SOI substrate. Since it has a structure that allows heat to escape easily, the increase in thermal resistance can be greatly reduced,
It is possible to suppress an increase in the joining temperature. Therefore, the operational reliability of the semiconductor device can be improved. Also,
The cooling structure of the package itself or the cooling device or the cooling mechanism for cooling the semiconductor device can be simplified.

Further, crystal defects can be reduced as compared with the SOI substrate. Therefore, the yield and reliability of the semiconductor device can be improved.

Regarding the control of the rise of the substrate potential,
By controlling the leak current of the pn junction under the channel region CHn, the leak current can be controlled relatively easily.
That is, the controllability of the substrate floating can be improved. Therefore, the circuit design can be facilitated.

Further, since the n-well NWL is provided and the substrate structure is basically normal, the cost of the semiconductor device can be reduced as compared with the case of using an expensive SOI substrate.

(Second Embodiment) In the second embodiment, a case where the present invention is applied to a semiconductor device having a CMIS (Complementary MIS) circuit will be described.

FIG. 4 is a cross-sectional view of an essential part of a CMIS circuit section which constitutes a logic circuit section of a semiconductor chip 1C which constitutes a semiconductor device according to another embodiment of the present invention.

Since the vertical structure of the nMISQn forming region is the same as that of the first embodiment, the description thereof will be omitted.
The vertical structure of the MISQp formation region will be described. pM
In the formation region of ISQp, in the active region of the substrate 1S,
An n-type semiconductor region NA (second conductivity type semiconductor region) is formed, and a pMIS is formed in the n-type semiconductor region NA.
Qp is formed. The n-type semiconductor region NA contains, for example, phosphorus (P) or arsenic (As).

The pMISQp has source and drain semiconductor regions 11 and 11, a channel region CHp, a gate insulating film 4, and a gate electrode 5. The source and drain semiconductor regions 11 and 11 are arranged so as to form a pair with the channel region CHp interposed therebetween.
Each has a p-type semiconductor region 11a arranged near the channel region CHp and ap ⁺ -type semiconductor region 11b arranged at a position separated from the channel region CHp with the p-type semiconductor region 11a interposed therebetween. is doing. In the p-type semiconductor region 11a and the p ⁺ -type semiconductor region 11b,
Together, for example, boron (B) or boron difluoride (BF
₂ ) is contained, but the p-type semiconductor region 11a is
It is also called an extension region, and its impurity concentration is set to be lower than that of the p ⁺ type semiconductor region 11b. That is, it has an LDD structure.

Then, in the second embodiment, pM
A p-well PWL (first-conductivity-type semiconductor region) is provided between the n-type semiconductor region NA in which ISQp is formed and the underlying substrate 1S. That is, the second embodiment
In the above, the channel region CHp (n-type semiconductor region NA) of the pMISQp and the substrate 1S are electrically separated by the pn junction between the p-well PWL and the n-type semiconductor region NA. The impurity distribution and formation state of the p-well PWL are the same as those of the n-well NWL, and the description thereof is omitted. Such a p-well PWL has the above-mentioned groove-type isolation portion 2
After the formation of the substrate, for example, boron is ion-implanted from the main surface of the substrate 1S with an ion implantation energy of about 160 keV. In addition, p well PWL
The impurity concentration at the peak position is about the same as that of the n-well NWL. The channel region CHp of pMISQp has a desired threshold value (50 mV to 100 mV as compared with the case of the conventional structure).
For example, phosphorus should be 2
It is formed by performing ion implantation from the main surface side of the substrate 1S at about 0 keV. Except for this, the description is omitted because it is the same as the first embodiment.

As described above, according to the second embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment. That is, even in pMISQp, the above nM
The same effect as ISQn can be obtained. Therefore, the operation speed (performance) of the semiconductor device having the logic circuit including the CMIS circuit can be improved.

(Third Embodiment) In the vertical structure of the MIS according to the first and second embodiments, the operating speed can be improved as described above, but the threshold voltage of the MIS varies within the operating region. And become unstable. Therefore, the third embodiment
In the above, even if the MISs formed on the same substrate 1S are made separately, ones that adopt the vertical structure of the MISs and those that do not. That is, the vertical structure of the MIS described in the first and second embodiments and the vertical structure of the normal MIS are used properly according to the electrical characteristics required for the circuit. Specifically, a vertical structure of the MIS is adopted for the MIS that constitutes a circuit that does not hinder the operation even if the threshold voltage fluctuates to some extent, and a circuit that hinders the operation when the threshold voltage fluctuates. The MIS that constitutes the
Instead of adopting the vertical structure of S, a vertical structure of general MIS was adopted.
For example, the vertical structure of the MIS described in the first and second embodiments is adopted as the MIS forming the digital circuit. In addition, for example, an MIS that constitutes a memory cell of an analog circuit, an input / output circuit or a memory circuit, a sense amplifier circuit, or the like (hereinafter, simply referred to as an analog circuit) that requires high operation accuracy, adopts the vertical structure of the MIS. Normal MI
The vertical structure of S is adopted. Although the memory cell is a digital circuit, it reads and writes a minute signal (charge), so the MIS-FET that constitutes the memory cell
It is preferable to adopt the normal vertical structure of the MIS because fluctuations in the threshold voltage of 1 h hinder data processing. Further, according to the study by the present inventors, in consideration of the operating voltage of the MIS (power supply voltage on the high potential side), if the operating voltage is, for example, 1.5 V or less, the above-described first and second embodiments are performed. It is preferable to adopt the vertical structure of the MIS described in 2. On the other hand, the operating voltage of the MIS is, for example, 1.5 V
If it is higher than the above, it is preferable to adopt the normal MIS vertical structure.

FIG. 5 shows an example of a fragmentary sectional view of the semiconductor device according to the third embodiment. The area A1 is composed of nMISQn and pM which form a logic circuit (digital circuit).
The ISQp (first field effect transistor) arrangement region is shown. In this area A1, the first and second embodiments
The vertical structure of the MIS described above is adopted.

On the other hand, in the area A2, the nMISQn1 and Qp1 (second circuit) which constitute a circuit which is disturbed when the threshold voltage is changed, such as the analog circuit, the input / output circuit, the memory cell of the memory circuit and the sense amplifier circuit, are formed. The field-effect transistor of FIG. In this area A2, the normal vertical structure of the MIS is adopted. That is, the nMISQn1 is formed in the p well PWL, and the pMISQp1 is formed in the n well NWL. P well PWL and n well NWL in area A2
Structure is similar to that of the p well PWL and n well N in the region A1.
It has the same structure as the WL. NMISQn of this area A2
1 and pMISQp1 also have channel regions CH
Channel ion implantation into n1 and CHp1 is performed, and the threshold voltage is adjusted.

As described above, in the third embodiment,
In addition to the effects obtained in the first and second embodiments, the following effects can be obtained.

That is, the vertical structure of the MIS described in the first and second embodiments is adopted as the MIS of the logic circuit, and the normal vertical structure of the MIS is adopted as the MIS of the analog circuit. It is possible to achieve both improvement in operation speed in the logic circuit and improvement in operation reliability in the analog circuit and the like.

(Embodiment 4) CM of Embodiment 2
In the structure of the IS circuit, the rise of the substrate potential when the gate voltage is applied may be too large. In this case, as shown in FIG. 6, by implanting impurity ions such as argon (Ar) or germanium (Ge) around the junction between the p-type semiconductor region PA and the n-well NWL. , Crystal defects 12 are formed. As a result, an appropriate recombination is generated in the depletion layer of the pn junction between the p-type semiconductor region PA and the n-well NWL, and a leak current can be flowed and controlled, so that the p-type semiconductor region PA can be controlled. It is possible to suppress an increase in the potential of. Therefore, nMI
Since the setting controllability of the threshold voltage of SQn can be improved, the operation reliability of the semiconductor device can be improved. The electrons generated by the impact ionization of the n-type semiconductor region of pMISQp are p-source electrons.
^{Even if the} recombination center is formed on the pMISQp side by flowing to the ⁺ type semiconductor region 11b (power supply wiring on the high potential side), the effect of suppressing the floating of the substrate potential does not occur.
No crystal defect is provided on the SQp side.

(Fifth Embodiment) The fifth embodiment will explain a modification for achieving the same object as that described in the fourth embodiment. That is, for the purpose of suppressing the rise of the substrate potential, as shown in FIG.
Lower part of the p-type semiconductor region PA (p-type semiconductor region PA and n
A p ⁺ type semiconductor region 13P having a high impurity concentration is provided between the well NWL). The p ⁺ type semiconductor region 13P is p
It contacts both the semiconductor region PA of the type and the n-well NWL. By providing such a p ⁺ type semiconductor region 13P, impurities in a region corresponding to the base region of the parasitic bipolar transistor formed by the semiconductor region 3 for the source and drain of the nMISQn and the p type semiconductor region PA are provided. Since the concentration can be increased, the current amplification factor of the parasitic bipolar transistor can be reduced. As a result, the rise in substrate potential can be suppressed. Therefore, the setting controllability of the threshold voltage of the nMISQn can be improved, and the operation reliability of the semiconductor device can be improved.

Further, in the fifth embodiment, in order to suppress the rise of the substrate potential, the lower part of the n-type semiconductor region NA (n-type semiconductor region NA and p-well PWL is used).
And (between) and n ⁺ type semiconductor region 13N having a high impurity concentration. The n ⁺ type semiconductor region 13N is in contact with both the n type semiconductor region NA and the p well PWL. By providing such an n ⁺ type semiconductor region 13N,
For the same reason as the above nMISQn, it is possible to improve the setting controllability of the threshold voltage of the pMISQp, so that it is possible to improve the operational reliability of the semiconductor device.

(Sixth Embodiment) The sixth embodiment describes a modification for achieving the same purpose as that described in the fourth and fifth embodiments. That is, for the purpose of suppressing the rise of the substrate potential, as shown in FIG. 8, in the formation region of the nMISQn, the p ⁺ type semiconductor region 13 is formed below the p type semiconductor region PA in contact with the p type semiconductor region PA. And an n ⁺ type semiconductor region 14 is provided in a lower portion of the n well NWL so as to be in contact therewith, and the n well NWL is provided in a lower portion of the n ⁺ type semiconductor region 14 in contact with the same. As a result, a p ⁺ n ⁺ high-concentration junction can be formed, the tunnel current of the diode can be increased, and recombination can be caused, so that the substrate potential of the p-type semiconductor region PA can be increased. It can be further suppressed. Therefore, the setting controllability of the threshold voltage of the nMISQn can be improved, and the operation reliability of the semiconductor device can be improved. In addition, on the pMISQp side,
For the same reason as described in Embodiments 4 and 5, n
The n ⁺ type semiconductor region and the p ⁺ type semiconductor region are not provided below the type semiconductor region NA.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above description, the CMI, which is the field of application of the invention mainly made by the present inventor, was the background.
Although the case where the present invention is applied to a semiconductor device having an S circuit has been mainly described, the present invention is not limited to this.
RAM (Dynamic Random Access Memory), SRAM
(Static Random Access Memory) or flash memory (EEPROM; Electric Erasable Programmable)
A semiconductor device having a memory circuit such as Read Only Memory), a semiconductor device having a logic circuit such as a microprocessor, or a mixed-type semiconductor device in which the memory circuit and the logic circuit are provided on the same semiconductor substrate. Applicable.

[0049]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1). The performance of the semiconductor device can be improved by separating the semiconductor substrate and the semiconductor region in which the channel of the field effect transistor is formed on the main surface thereof by a pn junction. (2). By separating the semiconductor substrate and the semiconductor region, in which the channel of the field effect transistor is formed on the main surface thereof, by a pn junction, an expensive SOI structure having a relatively large number of defects is not used. Since the semiconductor device can be formed by using the substrate structure described in 1 above, the cost of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor chip that constitutes a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a graph showing an impurity concentration distribution in a semiconductor substrate of the semiconductor device of FIG.

FIG. 3 is a graph showing the gate voltage dependence of the drain current of the field effect transistor of the semiconductor device of FIG. 1 and the field effect transistor formed on a normal semiconductor substrate.

FIG. 4 is a cross-sectional view of a main part of a semiconductor chip forming a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor chip constituting a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor chip constituting a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor chip constituting a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor chip constituting a semiconductor device according to still another embodiment of the present invention.

[Explanation of symbols]

1C Semiconductor Chip 1S Semiconductor Substrate 2 Separation Part 3 Semiconductor Region 3a n-Type Semiconductor Region 3b n ⁺ Type Semiconductor Region 4 Gate Insulating Film 5 Gate Electrode 7 Sidewall 8 Interlayer Insulating Film 9 First Layer Wiring 10 Contact Hole 11 Semiconductor Region 11a p type semiconductor region 11b p ⁺ type semiconductor region 12 crystal defect 13P p ⁺ type semiconductor region 13N n ⁺ type semiconductor region 14 n ⁺ type semiconductor region PA p type semiconductor region (first conductivity type semiconductor Region NWL n-well (second conductivity type semiconductor region) NA n-type semiconductor region (second conductivity type semiconductor region) PWL p-well (first conductivity type semiconductor region) Qp p-channel MIS • FET ( First field effect transistor) Qn n-channel type MIS • FET (first field effect transistor) Qp1 p-channel type MIS • FE (Second field-effect transistor) Qn1 n-channel type MIS · FET (second field-effect transistor) CHn, CHN1 channel region CHp, CHP1 channel region

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F032 AA35 AA44 AB01 AB03 CA01                       CA03 CA17 CA20 DA60 DA63                 5F048 AA01 AA03 AA04 AA07 AB01                       AB03 BA01 BA13 BB05 BB08                       BB09 BB11 BB12 BB13 BB14                       BC06 BE02 BE03 BG14 BH01                       BH03 DA25                 5F140 AA00 AB03 BA01 BD09 BD11                       BD13 BF01 BF04 BF11 BF18                       BF20 BF21 BF25 BF27 BG08                       BG12 BH15 BH50 BJ01 BJ05                       BK13 CB04 CB08 CB10 CD02

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of: (a) introducing a first impurity into a semiconductor substrate of a first conductivity type so that a semiconductor substrate opposite to the first conductivity type is formed. Forming a second conductivity type semiconductor region of conductivity type, and (b) introducing a second impurity into the semiconductor substrate so that the impurity peak of the semiconductor substrate is higher than the impurity peak position of the second conductivity type semiconductor region. A step of forming a first-conductivity-type semiconductor region formed such that an impurity peak position is located at a position shallower than the main surface, (c) a second-conductivity-type channel region in the first-conductivity-type semiconductor region Forming a field effect transistor having. 2. A field effect transistor having a channel region of a second conductivity type opposite to the first conductivity type in a semiconductor region of the first conductivity type provided in a semiconductor substrate, the semiconductor substrate And a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type is provided between the semiconductor region and the semiconductor region of the first conductivity type to form a channel region of the second conductivity type of the field effect transistor. A semiconductor device, wherein a region and the semiconductor substrate are electrically separated. 3. A field effect transistor having a channel region of a second conductivity type opposite to the first conductivity type in a semiconductor region of the first conductivity type provided in a semiconductor substrate, the semiconductor substrate And a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type is provided between the semiconductor region and the semiconductor region of the first conductivity type to form a channel region of the second conductivity type of the field effect transistor. A region and the semiconductor substrate are electrically separated, the thickness of the first conductivity type semiconductor region below the semiconductor region for the source and drain of the field effect transistor is A depletion layer width of a junction between the source and drain semiconductor regions and the first conductivity type semiconductor region, and the first conductivity type semiconductor region and the second conductivity type semiconductor region. Wherein a greater than the sum of the depletion layer width of the junction between. 4. A field effect transistor having a channel region of a second conductivity type opposite to the first conductivity type in a semiconductor region of the first conductivity type provided in a semiconductor substrate, the semiconductor substrate And a semiconductor region of the first conductivity type, a semiconductor region of the second conductivity type is provided between the semiconductor region and the semiconductor region of the first conductivity type to form a channel region of the second conductivity type of the field effect transistor. A region and the semiconductor substrate are electrically separated from each other, and the thickness of the second conductivity type semiconductor region is between the first conductivity type semiconductor region and the second conductivity type semiconductor region. A semiconductor device, wherein the width of the depletion layer of the junction is larger than the sum of the width of the depletion layer of the junction between the semiconductor region of the second conductivity type and the semiconductor substrate. 5. A first field effect transistor and a second field effect transistor are provided on a main surface of a semiconductor substrate, and the first field effect transistor is a first conductivity type provided on the semiconductor substrate. Of the semiconductor region of the first conductivity type, the second conductivity type semiconductor region having a conductivity type opposite to the first conductivity type provided between the semiconductor region of the first conductivity type and the semiconductor substrate. Is electrically separated from the semiconductor substrate by a semiconductor region of the second conductivity type, and the second field effect transistor is provided in the semiconductor region of the second conductivity type provided on the semiconductor substrate. Semiconductor device.