KR20220007489A - Memory device improving write operation speed and Operating method thereof - Google Patents

Abstract

Disclosed are a memory device with an improved write operation speed and an operating method thereof. A memory device according to an aspect of the present disclosure includes: a memory cell array that includes a plurality of memory cells; a voltage generator that generates voltages used for a program operation and verification operation for the memory cells; and a control logic that controls a plurality of program loops in relation to a data record, and performs a control operation so that a first to N-th program loops including the program operation and verification operation for the memory cells and at least two program loops in which the verification operation is skipped are performed, wherein according to a result of determining whether or not the program has passed or failed in the N-th program loop, when the program has passed, the at least two program loops are performed.

Description

Memory device improving write operation speed and operating method thereof

The technical idea of the present disclosure relates to a memory device, and more particularly, to a memory device having an improved write operation speed and an operating method thereof.

As a semiconductor memory device, a nonvolatile memory device includes a plurality of memory cells that nonvolatilely store data. As an example of a nonvolatile memory device, a flash memory device may be used in a mobile phone, a digital camera, a portable digital assistant (PDA), a portable computer device, a stationary computer device, and other devices.

In writing data to the nonvolatile memory device, a plurality of program loops may be performed. In this case, a program operation and a verify operation may be performed in a plurality of program loops, and the time required for the recording operation may be increased due to the above-described plurality of program loops. It can have a significant effect on the increase in the time of operation.

SUMMARY OF THE INVENTION It is an object of the technical spirit of the present invention to provide a memory device in which write operation speed is improved by performing optimal program operation and verification operation, and an operating method thereof.

In order to achieve the above object, a memory device according to an aspect of the inventive concept may provide a memory cell array including a plurality of memory cells, and voltages used for a program operation and a verification operation for the memory cells. First to N-th program loops that control a plurality of program loops in connection with a voltage generator to generate and write data, and include a program operation and a verify operation on the memory cells, and at least two programs in which the verify operation is skipped and a control logic for performing a control operation so that the loop is performed, and according to a result of determining whether a program passes/fails in the N-th program loop, when it is determined as a program pass, the at least two program loops are performed characterized.

Meanwhile, in an operating method of a memory device according to an aspect of the inventive concept, performing an N-th program loop including a program operation and a verify operation on memory cells, and a threshold voltage level lower than a predetermined threshold voltage determining whether a program pass/fail is performed by counting the number of memory cells having performing a (N+1) th program loop including a forcing program operation using a forcing program voltage for second memory cells of other portions of the memory cells, and using the forcing program voltage for the first memory cells performing a (N+2)th program loop including a forcing program operation, wherein the verify operation is skipped in each of the (N+1)th program loop and the (N+2)th program loop do.

Meanwhile, in an operating method of a memory device according to an aspect of the inventive concept, performing first to Nth program loops including a program operation and a verify operation on memory cells, and in the Nth program loop determining whether to pass/fail a program based on a program result of performing at least one of a normal program operation using a normal program voltage and a forcing program operation using a forcing program voltage in each of the (N+1)th to (N+A)th program loops; characterized.

According to the memory device and the operating method of the technical concept of the present invention, it is determined whether a program pass/fail is performed during a program loop, and the verification operation is skipped in two or more subsequent program loops based on the determination result. , it is possible to reduce the number of times that the verification operation is performed in a program cycle, and accordingly, there is an effect that the speed of the write operation can be improved.

On the other hand, according to the memory device and the operating method of the technical idea of the present invention, by using a pass/fail determination circuit capable of counting bit values of a plurality of memory cells, pass/fail before the actual write operation is completed. Since it is determined whether the verification operation has been performed and the subsequent verification operation can be skipped, the number of times the verification operation is performed in a program cycle can be reduced.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
FIG. 2 is a block diagram illustrating an example implementation of the memory device of FIG. 1 .
3 is a diagram illustrating an example of a two-step verification operation according to an exemplary embodiment of the present disclosure.
4 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.
5 is a block diagram illustrating an implementation example of a memory device according to an exemplary embodiment of the present disclosure.
6 is a flowchart illustrating a specific implementation example of a write operation according to an exemplary embodiment of the present disclosure.
7 is a graph illustrating an example of a change in threshold voltage distribution according to execution of program loops according to an exemplary embodiment of the present disclosure.
8 and 9A and B are flowcharts illustrating a write operation according to another exemplary embodiment of the present disclosure.
10 is a diagram illustrating an implementation example of a memory device according to an exemplary embodiment of the present disclosure.
11 is a block diagram illustrating an example in which a memory device according to embodiments of the present disclosure is applied to an SSD system.
12 is a perspective view illustrating an implementation example of the memory block of FIG. 2 according to an embodiment of the present disclosure;
13 is a cross-sectional view illustrating a memory device according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a memory system 10 may include a memory controller 100 and a memory device 200 , and the memory device 200 includes a memory cell array 210 , a voltage generator 220 , and control logic. 230 , and the control logic 230 may include a program loop controller 231 . In the example of FIG. 1 , the program loop controller 231 is illustrated as being included in the control logic 230 , but the program loop controller 231 according to an embodiment of the present disclosure is a separate component outside the control logic 230 . It may be implemented. In addition, the program loop controller 231 may perform functions according to embodiments of the present disclosure through various methods, and may be implemented as, for example, a hardware circuit, software executable by a processor, or a combination thereof. There will be.

According to an exemplary embodiment, the memory device 200 may include a nonvolatile memory device. In some embodiments, the memory system 10 may be implemented as an embedded or removable memory in an electronic device. For example, the memory system 10 may include an embedded Universal Flash Storage (UFS) memory device, an embedded Multi Memory (eMMC). -Media Card), SSD (Solid State Drive), UFS memory card, CF (Compact Flash), SD (Secure Digital), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (extreme Digital) ) or may be implemented in various forms such as a memory stick.

The memory controller 100 may control the memory device 200 to read data stored in the memory device 200 or write data to the memory device 200 in response to a write/read request from the host HOST. have. Specifically, the memory controller 100 controls write, read, and erase operations on the memory device 200 by providing the address ADDR, the command CMD, and the control signal CTRL to the memory device 200 . can Also, data DATA to be stored in the memory device 200 and data DATA read from the memory device 200 may be transmitted/received between the memory controller 100 and the memory device 200 .

The memory cell array 210 may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments of the present disclosure will be described with reference to a case in which the plurality of memory cells are NAND flash memory cells as an example. However, the present invention is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

In an embodiment, the memory cell array 210 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings, each of which is a word stacked vertically on a substrate. It may include memory cells respectively connected to the lines. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 disclose that a three-dimensional memory array is a plurality Those detailing suitable configurations for a three-dimensional memory array organized into levels and in which wordlines and/or bitlines are shared between levels, which are incorporated herein by reference. However, the present invention is not limited thereto, and in some embodiments, the memory cell array 210 may include a two-dimensional memory cell array, wherein the two-dimensional memory cell array includes a plurality of NAND flashes arranged along row and column directions. It may contain strings.

As a write command requesting a write is provided from the memory controller 100 to the memory device 200 , a write operation may be performed based on the control of the control logic 230 . The write operation may be performed through a plurality of program loops, and a period in which the plurality of program loops are performed may be referred to as a program cycle. That is, the operation of writing data to the memory cell may include a plurality of program loops within a program cycle, and a program operation using a program voltage and a verification operation using a verification voltage may be performed in any one program loop. have. In an exemplary embodiment of the present disclosure, in some of the plurality of program loops, the above-described program operation and the verify operation may be performed together, whereas in some of the loops, only the above-described program operation is selectively performed. can be performed.

The voltage generator 220 may generate various voltages used in the memory device 200 , and for example, a program voltage provided to a selected word line and a forbidden voltage provided to unselected word lines for a program operation. can create Also, the voltage generator 220 may further generate a verification voltage used for a verification operation for verifying a program operation and an erase voltage provided to word lines during an erase operation. Also, although not shown in FIG. 2 , the voltage generator 220 may further generate a string selection voltage and a ground selection voltage provided to the string selection lines and the ground selection lines.

The control logic 230 may control the overall operation of the memory device 200 , and as an example, based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 100 , Various internal control signals for programming data into the memory cell array 210 or reading data from the memory cell array 210 may be output. Also, the control logic 230 may output a voltage control signal (not shown) for adjusting the levels of various voltages output from the voltage generator 220 in connection with a program operation, a read operation, and an erase operation.

According to an exemplary embodiment, the program loop controller 231 may control program loops performed to write data to the memory cell array 210 . As an example, the program loop controller 231 may control the number of program loops within a program cycle or variously control the program loops, such as adjusting various voltage levels used in a program/verify operation for each program loop. have. As an example of an operation, a determination operation for determining whether a program passes or fails may be performed in the process of performing the program loop, and the verification operation is skipped in subsequent program loops according to the determination result. can be controlled. In addition, according to an embodiment of the present disclosure, when the determination result is a pass, the program loop may be controlled such that the verification operation is skipped in at least two subsequent program loops. That is, in embodiments of the present disclosure, since the number of program loops in which the verify operation is performed within one program cycle can be reduced, the time required for the data write operation can be shortened.

FIG. 2 is a block diagram illustrating an example implementation of the memory device of FIG. 1 .

1 and 2 , the memory device 200 may include a memory cell array 210 , a voltage generator 220 , a control logic 230 , a row decoder 240 , and a page buffer 250 . . Although not shown in FIG. 2 , the memory device 200 may further include various other components related to a memory operation, such as a data input/output circuit or an input/output interface.

The memory cell array 210 includes a plurality of memory blocks BLK1 to BLKz, and includes word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. can be connected to The memory cell array 210 is connected to the row decoder 240 through word lines WL, string select lines SSL, and ground select lines GSL, and a page buffer through bit lines BL. 250 may be connected. Each of the memory cells may store one or more bits. As an example, each memory cell is a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (Quad Level Cell). , QLC).

The control logic 230 may program data in the memory cell array 210 or program data in the memory cell array 210 based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 100 . Various internal control signals for reading data can be output. The control logic 230 may output a voltage control signal CTRL_vol for controlling the levels of various voltages generated by the voltage generator 220 . Also, in FIG. 2 , the program loop controller 231 and the pass/fail determiner 232 are illustrated as being included in the control logic 230 . However, embodiments of the present invention are not limited thereto, and at least some of the elements constituting the program loop controller 231 and the pass/fail determiner 232 may be provided outside the control logic 230 . .

The control logic 230 may provide a row address X-ADDR to the row decoder 240 and a column address Y-ADDR to the page buffer 250 . During the program operation, the row decoder 240 may provide a program voltage to the word lines of the selected memory cells in response to the row address X-ADDR, and may provide the inhibit voltages to the word lines of the unselected memory cells. have.

According to an exemplary embodiment of the present disclosure, the memory device 200 may perform a program operation based on a two-step verification operation. As an example, a plurality of program loops may be performed within a program cycle, and after a program operation is performed in one program loop, a verification operation may be performed using at least two verification voltages. As an example, the two-step verification operation may include a first verification operation using the pre-verification voltage VV_P and a second verification operation using the main verification voltage VV_M. The main verification voltage VV_M may have a larger value than the pre-verification voltage VV_P.

For the plurality of memory cells on which the program is performed, first memory cells having threshold voltages lower than a predetermined first threshold voltage may be determined through the first verification operation, and the first memory cells are coarse-on-cell ( coarse on cell). Also, through the second verification operation, memory cells having threshold voltages lower than a predetermined second threshold voltage (eg, the second threshold voltage is set to be greater than the first threshold voltage) may be determined, and the second threshold voltage may be determined. Memory cells having threshold voltages lower than the voltage may be referred to as fine on cells. Also, in the following embodiments, memory cells having threshold voltages greater than a first threshold voltage and lower than a second threshold voltage based on the first and second verification operations may be defined as second memory cells. .

Meanwhile, although it has been described that the main verification operation and the pre-verification operation are performed using the main verification voltage VV_M and the pre-verification voltage VV_P having different levels, embodiments of the present disclosure need to be limited thereto. there is no For example, in the verification operation, the operation of determining data based on different threshold voltage levels may be performed in various ways. As an example, setting the level of a current used for the verification operation or setting the data sensing timing The verification operation may be performed through various methods.

In the following program loop, a program operation may be performed based on the above-described verification result. In the program operation, different programming operations may be performed on the memory cells determined as the first memory cell and the second memory cell. As an example, a normal program is performed on the first memory cell, while the second memory A forcing program may be performed on the cell. In the forcing program, compared to the normal program, the difference in voltage level applied between the word line and the bit line connected to the memory cell may be smaller than that in the normal program. Accordingly, the level of the threshold voltage that is changed by the execution of the forcing program may be smaller than that of a normal program. As an example, various levels of voltages may be set for the bit line in the program operation, and the level of the voltage set on the bit line as the bit line forcing is applied in the forcing program is the level of the normal program. It may be set larger than the case. Alternatively, the level of the program voltage applied to the word line in the forcing program may be set to be smaller than that of the normal program.

In the following embodiments, the level of the voltage applied to the word line in the forcing program (eg, the forcing program voltage VP_F) is the voltage applied to the word line in the normal program (eg, the normal program voltage VP_N). It will be described as being set relatively small compared to that. However, as described above, the embodiment of the present disclosure is not limited thereto, and as the forcing program is performed through the bit line setup setting, the bit line setup level is set differently in the normal program and the forcing program. , a voltage of substantially the same level may be provided to the word line in the forcing program and the normal program.

The program loop controller 231 may control operation of program loops within a program cycle according to embodiments of the present disclosure. According to an exemplary embodiment, the program loop controller 231 may perform a control operation for various environment settings such as voltage levels related to program and verify operations in each program loop. Also, the program loop controller 231 may determine whether a verification operation is performed in each program loop, and may perform a control operation such that the verification operation is performed or skipped.

Meanwhile, the pass/fail determiner 232 may receive the data DATA through the page buffer 250 and determine whether to pass/fail the program based on a result of determining the state of the data DATA. In an exemplary embodiment, the number of memory cells (eg, coarse-on cells) having a threshold voltage lower than the first threshold voltage or memory cells (eg, fine-on cells) having a threshold voltage lower than the second threshold voltage By determining whether to pass/fail, it may be determined. In an exemplary embodiment of the present disclosure, when a predetermined reference value is set and the number of coarse-on cells or fine-on cells (or the number of failed memory cells) is less than the reference value, it is determined that the program has passed. can be judged.

According to an exemplary embodiment of the present disclosure, after the pass/fail determiner 232 determines the program pass, at least two program loops may be further performed. For example, when the number of failed memory cells is less than the reference value, it may indicate that all memory cells can have threshold voltages corresponding to all passed memory cells by further performing a small number of program loops. In embodiments of the disclosure, a verify operation may be skipped in the program loops. That is, compared to a case in which a program cycle is terminated as a pass is determined after performing a general program loop, in embodiments of the present disclosure, a verification operation may be skipped in additional program loops after determining a pass, Accordingly, since the number of verification operations performed in one program cycle can be reduced, the time required for the entire write operation can be reduced.

Meanwhile, the page buffer 250 may operate as a write driver or a sense amplifier according to an operation mode. The page buffer 250 may include a plurality of buffer units connected to a plurality of bit lines BL. Each of the buffer units may include one or more latches for storing read data through a corresponding bit line. The bit line setup operation described above may be performed through the page buffer 250, and the bit line is set at different levels for the memory cell in which the program is prohibited, the memory cell in which the normal program is performed, and the memory cell in which the forcing program is performed. can be set up. As an example of an operation, data read in the pre-verification operation and data read in the main verification operation may be stored in the page buffer 250 , and based on the data stored in the page buffer 250 , the first memory cell and the second memory cell A memory cell may be determined, and a pass/fail determination operation may be performed.

3 is a diagram illustrating an example of a two-step verification operation according to an exemplary embodiment of the present disclosure. 3 illustrates an example of a threshold voltage distribution of memory cells on which a program is performed.

2 and 3 , in the case of memory cells to which data is written, a plurality of program loops may be performed to have a higher threshold voltage than a second threshold voltage Vth2 according to a data value. In any one program loop, a two-step verification operation may be performed after the program operation is performed, and the verification operation is performed based on the first threshold voltage Vth1 and the second threshold voltage Vth2, A coarse on cell and a fine on cell may be discriminated. The two-step verification operation may perform a read operation based on the first threshold voltage Vth1, which may be referred to as a coarse read operation. Also, the two-step verification operation may perform a read operation based on the second threshold voltage Vth2, which may be referred to as a fine read operation. Due to the characteristics of the memory cells, threshold voltage fluctuation characteristics according to the program execution may be different from each other, and even though the memory cells go through the same program loops, some slow cells have a lower threshold voltage level than other cells, so coarse-on and fine-on Cells may coexist.

After the two-step verification operation as described above is completed, a program operation may be performed in the next program loop. PGM_N) may be performed, and the forcing program PGM_F using the forcing program voltage VP_F may be performed on the second memory cells corresponding to the coarse-off/fine-on cells. In addition, a two-step verification operation may be performed based on the first threshold voltage Vth1 and the second threshold voltage Vth2, and the memory cell MC1 corresponding to the existing coarse-on-cell through the above-described program operation. ) may be changed to a fine-on cell, and the memory cell MC2 corresponding to an existing coarse-off/fine-on cell may be changed to a fine-off cell.

4 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 4 , in a memory system including a memory controller and a memory device, when a write request is provided from a host, the memory controller provides a write command to the memory device, and the memory device responds to the write command in a plurality of program loops It is possible to perform a recording operation including Also, in an exemplary embodiment, after a specific number of program loops are performed, threshold voltages of a plurality of memory cells among the memory cells to be programmed may be increased to be greater than or equal to the target voltage, and thus the program pass/fail The timing of determining whether or not may be performed after the above-described specific number of program loops is executed.

In response to the reception of the write command, first to Nth program loops may be performed ( S11 ), and a program operation and a verify operation may be performed in each of the first to Nth program loops. Also, in an exemplary embodiment, the program loops may be controlled such that only the program operation is initially performed among the first to Nth program loops and the verification operation is performed from a specific time thereafter. Also, in an exemplary embodiment, a normal program operation using a normal program voltage may be initially performed among the first to Nth program loops, and the program loops may be controlled such that the forcing program operation is performed from a specific time thereafter. it might be In addition, according to the above-described embodiments, a two-step verification operation may be applied to the verification operation, and thus verification operations using the pre-verification voltage and the main verification voltage may be performed, and the above-described 2-step verification operation may be performed. Through this, coarse-on-cell and fine-on-cell can be discriminated.

In the process of performing the first to N-th program loops, it may be determined whether pass/fail timing is performed, and as an example, it is determined that pass/fail determination is performed after the N-th program loop is performed. can be (S12). When the pass/fail determination is performed, a coarse-on-cell or a fine-on-cell may be determined according to the execution result of the N-th program loop (S13), and it may be determined that the program is a pass based on the determination result (S14). ). For example, the determination operation may be performed by determining whether the number of coarse-on-cells is less than a predetermined reference value or by determining whether the number of fine-on-cells is less than a predetermined reference value. That is, when the number of coarse-on-cells or fine-on-cells is less than the reference value, the threshold voltage of a relatively large number of memory cells to be programmed increases above the target voltage to indicate a state in which the program is normally completed. have. Meanwhile, in the embodiment of FIG. 4 , it is assumed that the pass/fail determination result is a pass, but if it is determined as a program fail, an additional program loop and the pass/fail determination operation described above may be performed again.

According to an exemplary embodiment of the present disclosure, if it is determined that the program is a pass, the write operation may be completed by executing a program loop in which the verify operation is skipped multiple times. As an example, after it is determined that the program is a pass, (N+1)th program loop to (N+A)th program loops may be sequentially performed (S15, S16), and the (N+1)th program loop described above ) to the (N+A)th program loops, the verify operation may be skipped. Also, in an exemplary embodiment, a program operation using at least one of a normal program voltage and a forcing program voltage may be performed in each of (N+1)th program loop to (N+A)th program loops, After the N+1) program loop to (N+A)th program loops are performed, the write operation may be completed.

According to the exemplary embodiment of the present disclosure as described above, a plurality of program loops in which a verification operation is not included may be performed based on the result of the program path determination, and a program loop in which the verification operation is not performed during the entire write operation. As these are performed multiple times, the number of overall verification operations can be reduced. In addition, in the (N+1)th program loop to (N+A)th program loops in which the verification operation is skipped, the normal program voltage and the forcing program are appropriately applied based on the number of coarse-on-cells and fine-on-cells, Although the threshold voltage distribution of the memory cells increases to be equal to or greater than the target voltage, the program operation may be adjusted so that a problem in which the distribution width is not widened does not occur because the threshold voltage is excessively increased than the target voltage.

Meanwhile, in the following descriptions of embodiments of the present disclosure, terms may be defined in various ways, and as an example, the end of the program operation as the program cycle is completed is a write operation in response to a write command from the memory controller. This may indicate that it is finished.

5 is a block diagram illustrating an implementation example of a memory device according to an exemplary embodiment of the present disclosure. 5 illustrates an implementation example of control logic provided in a memory device.

Referring to FIG. 5 , the control logic 300 may include a program control circuit 310 , a loop counter 320 , a two-step verification circuit 330 , and a pass/fail determination circuit 340 . The program loop controller shown in FIG. 1 may include at least some of the components of the control logic 300 shown in FIG. 5 .

The program control circuit 310 may perform various control operations related to data writing in the memory device and may output control signals for controlling other components. As an example, the program control circuit 310 may output a voltage control signal CTRL_vol for controlling the voltage generator 301 in the memory device, output a row address X-ADDR to a row decoder, and a column decoder (or the page buffer) can output the column address (Y-ADDR). A two-step verification operation and a program operation based thereon may be controlled according to the row address X-ADDR and the column address Y-ADDR. As an example, for some of the memory cells to be programmed, A normal program operation may be performed, a forcing program operation may be performed on some other memory cells, and a program operation may be prohibited on some other memory cells.

At least one reference value is set therein, and the loop counter 320 may count the number of executions of the program loop and provide a result of comparing the counting result with the reference value. In an exemplary embodiment, based on the counting result of the loop counter 320 , a timing to start performing the pass/fail determination may be determined while the program loop is executing. Also, after the program pass is determined, a counting operation may be performed such that a predetermined number of program loops are further performed.

The two-step verification circuit 330 may determine the coarse-on-cell and the fine-on-cell through the verification operation according to the above-described embodiments. As an example, the two-step verification circuit 330 receives data DATA read using the pre-verification voltage VV_P and data DATA read using the main verification voltage VV_M from the page buffer, respectively. and, through this, a coarse-on-cell and a fine-on-cell can be discriminated. Also, through the two-step verification operation, first memory cells corresponding to the coarse-on cells and second memory cells corresponding to the coarse-off/fine-on cells may be determined. In addition, the pass/fail determination circuit 340 may determine whether to pass or fail the program based on the verification result of the two-step verification circuit 330 , and according to the above-described embodiments, the number or fine of coarse-on cells By comparing the number of on-cells with a predetermined reference value, it is possible to determine whether to pass or fail.

The program control circuit 310 may perform various control operations based on the determination result of the pass/fail determination circuit 340 . For example, if the determination result is fail, the program control circuit 310 controls the normal program voltage VP_N, the forcing program voltage VP_F, and the main verification voltage so that both the program operation and the verification operation can be performed in the next program loop. (VV_M) may output the voltage control signal CTRL_vol so that the pre-verification voltage VV_P is output. On the other hand, if the determination result is PASS, the program control circuit 310 skips the verification operation in the next program loop, and accordingly, the voltage control signal ( CTRL_vol) can be printed. In FIG. 5 , the normal program voltage VP_N and the forcing program voltage VP_F are generated in the first to (N+A)th program loops, while the main verification voltage VV_M and the pre-verification voltage VV_P are An example in which the first to Nth program loops are selectively generated is shown.

According to the exemplary embodiment as described above, a counter (not shown) capable of counting bit values of a plurality of memory cells is provided in the pass/fail determination circuit 340, and whether the program passes/fails based on the counting result can be determined in advance, and since the recording operation can be completed by performing only at least two program operations in a state in which the verification operation is skipped in advance based on the determination result, the total time required for the recording operation can be reduced.

6 is a flowchart illustrating a specific implementation example of a write operation according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6 , normal program loops are performed ( S21 ), and the normal program loop may correspond to a program loop including a program operation and a verify operation in the above-described embodiments. In addition, the memory device may be preset to perform pass/fail determination in a (N-2)th program loop, and a normal program for first memory cells corresponding to the coarse-on-cell in the (N-2)th program loop While the operation is performed, a forcing program operation may be performed on the second memory cells corresponding to the coarse-off/fine-on cell ( S22 ). The normal program operation is described as an ISPP program in FIG. 6 as the incremental step pulse program (ISPP) method in which the level of the program pulse is gradually increased as the program loop is performed is applied to the normal program operation. do.

Meanwhile, pass/fail may be determined in the (N-2)th program loop (S23), and as an example, the number of coarse-on-cells or fine-on-cells determined through the existing verification operation is used as a reference value (Ref) By comparing with , pass/fail may be determined. According to an embodiment that can be implemented, whether to pass/fail based on data stored in the page buffer through a verification operation performed in an existing (eg, (N-3)th program loop) in the (N-2)th program loop can be judged. Also, in an exemplary embodiment, the pass/fail determination operation in the (N-2)th program loop may be performed in parallel with the program operation of the next (N-1)th program loop.

If it is determined that the program fails, the program loop including the two-step verification operation S24 and the program operation S22 may be performed again, and pass/fail status based on the result of the performed verification operation may be re-evaluated. On the other hand, when it is determined as a program pass, two or more additional program loops in which the two-step verification operation is skipped may be performed according to exemplary embodiments of the present disclosure.

As it is determined as a program pass, a normal program operation is performed on the first memory cells corresponding to the coarse-on cell in the (N-1)th program loop without performing a verification operation, and the coarse-off/fine-on-cell is performed. A forcing program operation may be performed on the corresponding second memory cells (S25). In addition, the following program loop (eg, an N-th program loop) may be performed, and in the N-th program loop, a program operation may be selectively performed on memory cells determined as coarse-on cells in a previous verification process, , a forcing program may be applied to the program operation (S26).

According to the exemplary embodiment as described above, after the program pass is determined, the recording operation may be completed by performing two more program operations without performing a separate verification operation. For example, in a state in which the program pass is determined, first memory cells corresponding to the coarse-on cells and second memory cells corresponding to the coarse-off/fine-on cells may exist, and a normal program operation and forcing of the first memory cells The write operation may be completed by performing the program and performing the forcing program on the second memory cells.

7 is a graph illustrating an example of a change in threshold voltage distribution according to execution of program loops according to an exemplary embodiment of the present disclosure. 7 illustrates an example of an operation in a memory device including multi-level cells.

Memory cells may be programmed into any one of a plurality of states corresponding to a plurality of threshold voltage distributions according to a data value thereof. As an example, the threshold voltage distributions may have four or more states. In (a) of FIG. 7 , threshold voltage distributions having a first state P1 to a (n+3) state P(n+3) are exemplified, and the first state P1 corresponds to the erased state, and , by performing the program loop, the threshold voltages of the memory cells may be changed from the first state P1 to the second state P2 to the (n+3)th state (P(n+3)). In each program loop, program operations for programming to the plurality of states may be respectively performed. Also, in each program loop, a verify operation may be performed in relation to each state in order to verify the program operation of each of the plurality of states.

7B illustrates an example of a voltage (or voltage pulse) applied to a selected word line in a program loop. In FIG. 7B , for convenience of explanation, a program operation related to the nth state Pn and a verification operation for the nth to (n+3)th states in the Nth to (N+2)th program loops This is exemplified. Also, in FIG. 7C , an example of a change in threshold voltage distribution according to a program operation in relation to the n-th state Pn is illustrated. Also, pass/fail may be determined at a predetermined timing, and in an exemplary embodiment, pass/fail determination may be performed at different timings for each state. For example, pass/fail determination is performed on the nth state Pn in the Nth program loop, and pass/fail determination is performed on the n+1th state Pn+1 in the (N+1)th program loop. It is assumed that pass/fail determination for the n+2th state (Pn+2) is performed in the (N+2)th program loop. In addition, in FIG. 7 , in the program operation to the n-th state (Pn) and the (n+1)-th state, an example of a program operation performed in each program loop is further illustrated.

First, a program voltage for a program operation may be applied in the N-th program loop, and the two-step verification operation in the above-described embodiment may be performed for each of the n-th to (n+3)-th states. . In addition, a coarse-off cell (first memory cell) and a coarse-off/fine-on cell (second memory cell) may be discriminated in relation to the n-th state, and a result of determining whether to pass/fail the program in the n-th state It is assumed that the program path is determined according to

According to the operation in the N-th program loop as described above, the verification operation related to the n-th state may be skipped as shown by a dotted line in the following program loops. Also, in the (N+1)th program loop, a normal program operation may be performed on the first memory cell and a forcing program operation may be performed on the second memory cell. 7C illustrates an example in which the first memory cell is changed to a coarse-off/fine-on cell and the second memory cell is changed to a fine-off cell according to a program operation of the (N+1)th program loop. In addition, pass/fail determination may be performed in relation to the (n+1)th state in the (N+1)th program loop, and when it is determined as the program pass, the next program loop (eg, (N+2)th program loop), the verify operation may be skipped with respect to the (n+1)th state.

In the (N+2)th program loop, a forcing program operation may be selectively performed only on coarse-off/fine-on cells in relation to the n-th state, and memory cells may be changed to fine-off cells according to the program. Also, in the (N+2)th program loop, a normal program operation and a forcing program operation may be performed in relation to the (n+1)th state, and a forcing program operation may be performed in the next program loop. . In addition, in relation to the (n+2)th state, pass/fail determination may be performed in the (N+2)th program loop, and when it is determined that the program pass is the (n+2)th state according to the above-described embodiments, pass/fail determination may be performed. The verify operation may be skipped in at least two program loops in which the program operation to state is performed.

8 and 9A and B are flowcharts illustrating a write operation according to another exemplary embodiment of the present disclosure.

Referring to FIG. 8 , first to Nth program loops may be performed ( S31 ), and the program operation and verification operation according to the above-described embodiments may be performed on the first to Nth program loops. Then, whether the program pass/fail may be determined at a predetermined timing, and it may be determined that the program has been passed ( S32 ).

Memory cells may have various threshold voltages according to the execution of the Nth program loop, and through a two-step verification operation, first memory cells corresponding to coarse-on cells and second memory cells corresponding to coarse-off/fine-on cells can be identified. In addition, it may be determined whether the first memory cells do not exist and only the second memory cells exist ( S33 ). When the first memory cells do not exist and only the second memory cells exist, an additional verification operation is performed By performing one program loop using the forcing program voltage without performing the forcing program, the write operation may be completed after performing the forcing program on the second memory cells (S34).

On the other hand, when the first memory cells and the second memory cells coexist, at least two program loops may be further performed without performing an additional verification operation. For example, in the (N+1)-th program loop, a normal program may be performed on the first memory cells using a normal program voltage, and a forcing program may be performed on the second memory cells using the forcing program voltage ( S35). Also, a forcing program may be performed on the first memory cells by using the forcing voltage in the (N+2)th program loop ( S36 ).

According to the above embodiment, the number of additional program loops in which the verification operation is not performed may be changed based on the threshold voltage distribution of the memory cells in the pass/fail determination step, and accordingly, in the write operation, a plurality of memory cells Their threshold voltage distribution can be effectively controlled.

9A and 9B exemplify a case in which program loops in which a verification operation is skipped are performed three or more times.

Referring to FIG. 9A , first to Nth program loops may be performed ( S41 ), and a program operation and a verification operation according to the above-described embodiments may be performed on the first to Nth program loops. Then, it may be determined whether the program has passed/failed at a predetermined timing, and it may be determined that the program has been passed ( S42 ).

According to the execution of the N-th program loop, the memory cells may have various threshold voltages, and the number of first memory cells corresponding to the coarse-on-cell may be determined ( S43 ). For example, the number of first memory cells may be compared with a predetermined reference value Ref, and when the number of first memory cells is less than the reference value Ref_1, the level of the threshold voltage is equal to the coarse-on-cell reference. This may indicate that the number of memory cells smaller than the first threshold voltage is relatively small. That is, when the number of coarse-on-cells is relatively small, the write operation may be completed by executing two additional program loops, for example, by performing the (N+1)th and (N+2)th program loops. A write operation may be completed by (S44).

On the other hand, when the number of first memory cells is greater than the reference value Ref_1, it may indicate that the number of memory cells whose threshold voltage level is lower than the first threshold voltage that is the reference value of the coarse-on cell is relatively large. . That is, when the number of coarse-on-cells is relatively large, additional program loops in which the verification operation is skipped may be performed more, and as an example, (N+1)th to (N+3)th program loops are performed. The write operation may be completed by (S45).

Meanwhile, in step S45 of performing the (N+1)th to (N+3)th program loop, program operations may be performed through various methods. Referring to FIG. 9B , in the (N+1)th program loop, a normal program using a normal program voltage may be performed on first memory cells, and a forcing program using a forcing program voltage may be performed on second memory cells. There is (S45_1). Also, in the (N+2)th program loop, program execution is prohibited on the second memory cells, and a normal program using a normal program voltage may be selectively performed only on the first memory cells ( S45_2 ). Also, in the (N+3)th program loop, the second memory cells are prohibited from being programmed, and the forcing program using the forcing program voltage may be selectively performed only on the first memory cells ( S45_3 ).

The embodiment shown in FIG. 9B is a description of one possible operation, and the embodiments of the present disclosure are not limited thereto. For example, more additional program loops in which the verify operation is skipped may be performed, and a different type of program operation may be applied to each program loop. For example, the program loops may be controlled such that the forcing program is performed in the (N+2)th program loop and the (N+3)th program loop for the first memory cells. Alternatively, the program loops may be controlled such that the forcing program is performed in the (N+1)th program loop to the (N+3)th program loop for the first memory cells.

10 is a diagram illustrating an implementation example of a memory device according to an exemplary embodiment of the present disclosure. In FIG. 10 , the page buffer 400 provided in the memory device is exemplified, and an example of an operation of the page buffer 400 in a plurality of program loops is disclosed.

The page buffer 400 may include a plurality of buffer units (eg, first to Kth buffer units BU1 to BUK) corresponding to the bit lines BL1 to BLK. Each buffer unit may function as a sense amplifier during a data read operation or a verify operation, and may also perform a function of a write driver during a write operation. Also, although not shown in FIG. 10 , each buffer unit may include one or more latches (not shown) for storing write data and/or read data.

In the N-th program loop in which the program operation and the verify operation are performed, a setup operation may be performed on the bit lines BL1 to BLK to perform the program operation. The bit lines BL1 to BLK may be set up as various voltage levels through a setup operation. For example, in a normal program operation, bit lines corresponding to memory cells for which programming is prohibited may be set to a power supply voltage, and bit lines corresponding to memory cells to be programmed may be set to a ground voltage. In addition, in the forcing program operation based on the bit line forcing, bit lines corresponding to memory cells for which programming is prohibited may be set with a power supply voltage, and bit lines corresponding to memory cells on which programming is performed may have a ground voltage and a power supply voltage. It can be set up to a voltage with a level in between.

Meanwhile, in the N-th program loop, as the two-step verification operation is performed, data may be read based on at least two threshold voltages, and the read data may be read in the page buffer 400 through the bit lines BL1 to BLK. ) can be provided. As an example, data is read based on the first threshold voltage and provided to the page buffer 400 through the bit lines BL1 to BLK, and data is read based on a second threshold voltage greater than the first threshold voltage. It may be read and provided to the page buffer 400 through the bit lines BL1 to BLK. For example, the coarse-on-cell and the coarse-off cell may be determined based on the data DATA_C read based on the first threshold voltage, and the fine-on-cell based on the data DATA_F read based on the second threshold voltage. and a fine off cell may be determined. In addition, the data DATA_C and data DATA_F may be stored in latches (not shown) in the page buffer 400 .

Meanwhile, in the (N+1)th program loop and the (N+2)th program loop in which the verification operation is skipped, setup for the bit lines BL1 to BLK without receiving data through the page buffer 400 . The operation may be selectively performed. For example, in each of the (N+1)th program loop and the (N+2)th program loop, at least one of a bitline setup operation for performing a normal program and a bitline setup operation for performing a forcing program may be performed. There will be.

11 is a block diagram illustrating an example in which a memory device according to embodiments of the present disclosure is applied to an SSD system.

Referring to FIG. 11 , the SSD system 500 may include a host 510 and an SSD 520 . The SSD 520 exchanges a signal SIG with the host 510 through a signal connector, and receives power PWR through a power connector. The SSD 520 may include an SSD controller 521 , an auxiliary power supply 522 , and memory devices 523_1 to 523_n. The memory devices 523_1 to 523_n may be vertically stacked NAND flash memory devices. The SSD controller 521 may be connected to the memory devices 523_1 to 523_n through a plurality of channels Ch1 to Chn. In this case, each of the memory devices 523_1 to 523_n may be implemented using the embodiments described above with reference to FIGS. 1 to 10 . That is, each of the memory devices 523_1 to 523_n may perform a plurality of program loops during a write operation, and in at least two program loops among the plurality of program loops, a program operation is performed without the 2-step verification operation being performed. only it can be done.

The SSD controller 521 may include an error correction code (ECC) circuit 521_1 and an advanced encryption standard (AES) circuit 521_2 . In addition, although not shown in FIG. 11 , the SSD controller 521 may further include components such as a processor, a buffer, a random access memory (RAM), a host interface, and a memory interface for controlling the overall operation of the SSD 520 . will be able

The ECC circuit 521_1 may perform ECC encoding and ECC decoding on data stored in the memory devices 523_1 to 523_n or read from the memory devices 523_1 to 523_n. As an example, the ECC circuit 521_1 may generate parity used for error detection and correction through ECC encoding processing for write data, and based on the data and parity read from the memory devices 523_1 to 523_n Error detection and correction may be performed. In addition, the AES circuit 521_2 may perform at least one of an encryption operation and a decryption operation on data input/output to the SSD controller 521 , and various types of encryption/decryption algorithms (eg, , it is possible to perform encryption/decryption operations using a symmetric-key algorithm.

12 is a perspective view illustrating an implementation example of the memory block of FIG. 2 according to an embodiment of the present disclosure;

Referring to FIG. 12 , the memory block BLK is formed in a vertical direction with respect to the substrate SUB. The substrate SUB has a first conductivity type (eg, p-type), extends along the second horizontal direction HD2 on the substrate SUB, and has a second conductivity type (eg, n-type) A common source line CSL doped with impurities of A plurality of insulating layers IL extending along the second horizontal direction HD2 are sequentially provided along the vertical direction VD on the region of the substrate SUB between two adjacent common source lines CSL, The plurality of insulating layers IL are spaced apart from each other by a specific distance in the vertical direction VD. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

It is sequentially disposed along the first horizontal direction HD1 on the region of the substrate SUB between two adjacent common source lines CSL, and penetrates the plurality of insulating layers IL along the vertical direction VD. A plurality of pillars (pillars) (P) is provided. For example, the plurality of pillars P may pass through the plurality of insulating layers IL to make contact with the substrate SUB. Specifically, a surface layer S of each pillar P may include the first type silicon material and function as a channel region. Meanwhile, the inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

In a region between two adjacent common source lines CSL, a charge storage layer CS is provided along exposed surfaces of the insulating layers IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a 'tunneling insulating layer'), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between two adjacent common source lines CSL, on the exposed surface of the charge storage layer CS, gate electrodes such as the selection lines GSL and SSL and the word lines WL0 to WL7 (GE) is provided.

Drains or drain contacts DR are provided on the plurality of pillars P, respectively. For example, the drains or the drain contacts DR may include a silicon material doped with impurities having the second conductivity type. Bit lines BL1 to BL3 extending in the first horizontal direction HD1 and spaced apart from each other by a specific distance along the second horizontal direction HD2 are provided on the drains DR.

13 is a cross-sectional view illustrating a memory device according to an embodiment of the present disclosure.

Referring to FIG. 13 , the memory device 600 may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a cell region CELL is fabricated on a first wafer, a lower chip including a peripheral circuit region PERI is fabricated on a second wafer different from the first wafer, and then the upper chip It may mean connecting the chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum or tungsten. The embodiments illustrated in FIGS. 1 to 12 may be implemented in the memory device 600 , and for example, the page buffer described above with reference to FIGS. 1 to 12 may be disposed in the peripheral circuit area PERI. .

Each of the peripheral circuit area PERI and the cell area CELL of the memory device 600 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. The peripheral circuit region PERI includes a first substrate 710 , an interlayer insulating layer 715 , a plurality of circuit elements 720a , 720b , and 720c formed on the first substrate 710 , and a plurality of circuit elements 720a . , 720b, 720c) first metal layers 730a, 730b, 730c connected to each, and second metal layers 740a, 740b, 740c formed on the first metal layers 730a, 730b, 730c. can In an embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten having a relatively high resistance, and the second metal layers 740a, 740b, and 740c may be formed of copper having a relatively low resistance. can

In this specification, only the first metal layers 730a, 730b, 730c and the second metal layers 740a, 740b, and 740c are shown and described, but not limited thereto, and the second metal layers 740a, 740b, 740c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 740a, 740b, and 740c are formed of aluminum having a lower resistance than copper forming the second metal layers 740a, 740b, and 740c. can be

The interlayer insulating layer 715 is a first substrate to cover the plurality of circuit elements 720a, 720b, and 720c, the first metal layers 730a, 730b, and 730c, and the second metal layers 740a, 740b, and 740c. It is disposed on the 710 and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 771b and 772b may be formed on the second metal layer 740b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 771b and 772b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 871b and 872b of the cell area CELL by a bonding method. , the lower bonding metals 771b and 772b and the upper bonding metals 871b and 872b may be formed of aluminum, copper, tungsten, or the like. The upper bonding metals 871b and 872b of the cell region CELL may be referred to as first metal pads, and the lower bonding metals 771b and 772b of the peripheral circuit area PERI may be referred to as second metal pads. can

The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 810 and a common source line 820 . A plurality of word lines 831 - 838 ( 830 ) may be stacked on the second substrate 810 in a direction VD perpendicular to the top surface of the second substrate 810 . String select lines and ground select lines may be disposed above and below the word lines 830 , respectively, and a plurality of word lines 830 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the top surface of the second substrate 810 to pass through the word lines 830 , the string selection lines, and the ground selection line. have. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In an embodiment, the bit line may extend in the first horizontal direction HD1 parallel to the top surface of the second substrate 810 .

13 , an area in which the channel structure CH and the bit line are disposed may be defined as the bit line bonding area BLBA. The bit line may be electrically connected to the circuit elements 720c providing the page buffer 893 in the peripheral circuit area PERI in the bit line bonding area BLBA. As an example, the bit line is connected to the upper bonding metals 871c and 872c in the peripheral circuit region PERI, and the upper bonding metals 871c and 872c are connected to the circuit elements 720c of the page buffer 893. It may be connected to the lower bonding metals 771c and 772c. In an exemplary embodiment of the present disclosure, the bit line may be connected to the page buffer 893 , and various setup operations may be performed on the bit line to perform a normal program and a forcing program, and also In an embodiment, data read based on the first threshold voltage and data read based on the second threshold voltage may be provided to the page buffer 893 through a bit line to perform a two-step verification operation. That is, in the program loop in which the verify operation is skipped, data read based on the first and second threshold voltages may not be provided to the page buffer 893 .

In the word line bonding area WLBA, the word lines 830 may extend in the second horizontal direction HD2 parallel to the top surface of the second substrate 810 , and include a plurality of cell contact plugs 841 - 1 847; 840). The word lines 830 and the cell contact plugs 840 may be connected to each other through pads provided by at least some of the word lines 830 extending in different lengths along the second horizontal direction. A first metal layer 850b and a second metal layer 860b may be sequentially connected to the upper portions of the cell contact plugs 840 connected to the word lines 830 . The cell contact plugs 840 are connected to the word line bonding area WLBA through the upper bonding metals 871b and 872b of the cell area CELL and the lower bonding metals 771b and 772b of the peripheral circuit area PERI through the peripheral circuit. It may be connected to the region PERI.

The cell contact plugs 840 may be electrically connected to circuit elements 720b providing the row decoder 894 in the peripheral circuit region PERI. In an embodiment, the operating voltages of the circuit elements 720b providing the row decoder 894 may be different from the operating voltages of the circuit elements 720c providing the page buffer 893 . For example, the operating voltages of the circuit elements 720c providing the page buffer 893 may be greater than the operating voltages of the circuit elements 720b providing the row decoder 894 .

A common source line contact plug 880 may be disposed in the external pad bonding area PA. The common source line contact plug 880 may be formed of a metal, a metal compound, or a conductive material such as polysilicon, and may be electrically connected to the common source line 820 . A first metal layer 850a and a second metal layer 860a may be sequentially stacked on the common source line contact plug 880 . For example, an area in which the common source line contact plug 880 , the first metal layer 850a , and the second metal layer 860a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 705 and 805 may be disposed in the external pad bonding area PA. Referring to FIG. 13 , a lower insulating film 701 covering the lower surface of the first substrate 710 may be formed under the first substrate 710 , and first input/output pads 705 on the lower insulating film 701 . can be formed. The first input/output pad 705 is connected to at least one of the plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through the first input/output contact plug 703 and the lower insulating layer 701 ) may be separated from the first substrate 710 by the In addition, a side insulating layer may be disposed between the first input/output contact plug 703 and the first substrate 710 to electrically separate the first input/output contact plug 703 from the first substrate 710 .

Referring to FIG. 13 , an upper insulating film 801 covering the upper surface of the second substrate 810 may be formed on the second substrate 810 , and second input/output pads 805 on the upper insulating film 801 . can be placed. The second input/output pad 805 may be connected to at least one of the plurality of circuit elements 720a , 720b , and 720c disposed in the peripheral circuit area PERI through the second input/output contact plug 803 .

In some embodiments, the second substrate 810 and the common source line 820 may not be disposed in the region where the second input/output contact plug 803 is disposed. Also, the second input/output pad 805 may not overlap the word lines 830 in the third direction (Z-axis direction). Referring to FIG. 13 , the second input/output contact plug 803 is separated from the second substrate 810 in a direction parallel to the top surface of the second substrate 810 , and an interlayer insulating layer 815 of the cell region CELL. may pass through and be connected to the second input/output pad 805 .

In some embodiments, the first input/output pad 705 and the second input/output pad 805 may be selectively formed. For example, the memory device 600 includes only the first input/output pad 705 disposed on the first substrate 710 , or the second input/output pad 805 disposed on the second substrate 810 . can contain only Alternatively, the memory device 600 may include both the first input/output pad 705 and the second input/output pad 805 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or The uppermost metal layer may be empty.

In the external pad bonding area PA, the memory device 600 corresponds to the upper metal pattern 872a formed on the uppermost metal layer of the cell area CELL in the uppermost metal layer of the peripheral circuit area PERI. ), a lower metal pattern 773a having the same shape as the upper metal pattern 872a may be formed. The lower metal pattern 773a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, the lower metal pattern of the peripheral circuit area PERI corresponds to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area PERI on the upper metal layer of the cell area CELL. An upper metal pattern having the same shape as the above may be formed.

Lower bonding metals 771b and 772b may be formed on the second metal layer 740b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 771b and 772b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 871b and 872b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the lower part of the peripheral circuit area PERI is located on the uppermost metal layer of the cell area CELL corresponding to the lower metal pattern 752 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 892 having the same shape as the metal pattern 752 may be formed. A contact may not be formed on the upper metal pattern 892 formed on the uppermost metal layer of the cell region CELL.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (20)

a memory cell array including a plurality of memory cells;
a voltage generator that generates voltages used for a program operation and a verification operation on the memory cells; and
A plurality of program loops are controlled in relation to data writing, and the first to Nth program loops including a program operation and a verify operation and at least two program loops in which the verify operation is skipped are performed on the memory cells. having control logic to perform an operation,
The memory device of claim 1 , wherein the program loop is performed at least two times when a program pass is determined according to a result of determining whether a program is pass/failed in the Nth program loop. According to claim 1,
the at least two program loops,
(N+) th (N+), including a normal program operation using a normal program voltage for some first memory cells of the memory cells and a forcing program operation using a forcing program voltage for second memory cells of some other of the memory cells 1) a program loop;
and a (N+2)th program loop including a forcing program operation using the forcing program voltage for the first memory cells. 3. The method of claim 2,
The control logic is
in the first to Nth program loops, control the voltage generator to generate voltages used for the program operation and the verify operation;
and controlling the voltage generator to selectively generate voltages used for the program operation in the at least two program loops. 3. The method of claim 2,
The verification operation includes an operation of discriminating a coarse-on-cell and a coarse-off cell based on a first threshold voltage and an operation of discriminating a fine-on-cell and a fine-off cell based on a second threshold voltage,
The second threshold voltage is greater than the first threshold voltage. 5. The method of claim 4,
Memory cells having a threshold voltage level lower than the first threshold voltage correspond to the first memory cells, and memory cells having a threshold voltage level greater than the first threshold voltage and lower than the second threshold voltage are the second memory cells. A memory device, characterized in that it corresponds to the cells. 5. The method of claim 4,
The determination of whether the program pass/fail is performed by counting the number of memory cells having a threshold voltage level lower than the first threshold voltage or memory cells having a threshold voltage level lower than the second threshold voltage memory device. According to claim 1,
a page buffer connected to the memory cell array through a plurality of bit lines;
the page buffer receives data read from the memory cell array through the plurality of bit lines in connection with the verify operation in the first to Nth program loops;
and in the at least two program loops, an operation of providing data to the page buffer through the plurality of bit lines is skipped. performing an N-th program loop including a program operation and a verify operation on memory cells (where N is an integer greater than or equal to 1);
determining whether to pass/fail a program by counting the number of memory cells having a threshold voltage level lower than a predetermined threshold voltage;
When it is determined as a program pass, a normal program operation using normal program voltages for some of the first memory cells of the memory cells and a forcing program operation using a forcing program voltage for second memory cells of some of the memory cells performing an (N+1)th program loop including and
performing a (N+2)th program loop including a forcing program operation using the forcing program voltage on the first memory cells;
The method of operating a memory device, wherein a verify operation is skipped in each of the (N+1)th program loop and the (N+2)th program loop. 9. The method of claim 8,
The verification operation performed in the N-th program loop includes an operation of determining a coarse-on-cell and a coarse-off cell based on a first threshold voltage and an operation of determining a fine-on-cell and a fine-off cell based on a second threshold voltage including,
The method of operating a memory device, wherein the second threshold voltage is greater than the first threshold voltage. 10. The method of claim 9,
Memory cells having a threshold voltage level lower than the first threshold voltage correspond to the first memory cells, and memory cells having a threshold voltage level greater than the first threshold voltage and lower than the second threshold voltage are the second memory cells. An operating method of a memory device, characterized in that corresponding to the cells. 10. The method of claim 9,
The determining of whether to pass/fail the program includes counting the number of memory cells having a threshold voltage level lower than the first threshold voltage or memory cells having a threshold voltage level lower than the second threshold voltage A method of operating a memory device. 9. The method of claim 8,
If it is determined as a program fail in the step of determining whether the program pass/fail,
The method of claim 1, further comprising: performing a program loop including a program operation and a verify operation at least once more before performing the (N+1)th program loop. 9. The method of claim 8,
each of the memory cells is connected to a word line and a bit line;
A voltage level difference between the word line and the bit line of the memory cell on which the normal program operation is performed is greater than a voltage level difference between the word line and the bit line of the memory cell on which the forcing program operation is performed. A method of operating a memory device. 14. The method of claim 13,
In the forcing program operation, a voltage of the same level as the voltage applied to the word line is provided to the word line during the normal program operation, and a voltage of a level greater than the voltage set on the bit line is set up on the bit line during the normal program operation A method of operating a memory device, characterized in that it becomes. 9. The method of claim 8,
The method of operating a memory device, wherein the operation of determining whether the program pass/fail is performed and a normal program operation or a forcing program operation in the (N+1)th program loop are performed in parallel. 9. The method of claim 8,
The memory device includes a page buffer,
As the verify operation is performed in the Nth program loop, data read from the memory cells is provided to the page buffer;
The method of claim 1, wherein data is not provided to the page buffer as the verify operation is skipped in each of the (N+1)th program loop and the (N+2)th program loop. performing first to N-th program loops including a program operation and a verify operation on memory cells (where N is an integer of 2 or more);
determining whether to pass/fail a program based on a program result in the N-th program loop; and
If it is determined as a program pass, performing (N+1)th to (N+A)th program loops that do not include a verification operation on the memory cells (where A is an integer greater than or equal to 2);
The operation of the memory device, wherein at least one of a normal program operation using a normal program voltage and a forcing program operation using the forcing program voltage is performed in each of the (N+1)th to (N+A)th program loops Way. 18. The method of claim 17,
As the memory cells correspond to multilevel cells, each program loop includes a program operation to a plurality of threshold voltage states;
The method of claim 1 , wherein a verification operation related to at least one of the plurality of threshold voltage states is skipped in each of the (N+1)th to (N+A)th program loops. 18. The method of claim 17,
A first memory cell having a threshold voltage level lower than a first threshold voltage and a second memory cell having a threshold voltage level greater than the first threshold voltage and lower than the second threshold voltage through the verify operation in the N-th program loop A method of operating a memory device, characterized in that the memory cells are identified. 20. The method of claim 19,
The (N+1)th to (N+A)th program loops are
a program loop for performing the normal program operation on the first memory cell and the forcing program operation on the second memory cell;
and a program loop for performing the forcing program operation on the first memory cell.

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