KR20230068237A - Method of programming non-volatile memory device - Google Patents

Abstract

A programming method of a non-volatile memory device includes applying a first voltage to a first word line group and a selected word line that are relatively close to a selected word line in a first channel initialization period and on which a program operation has been performed, and relatively to the selected word line. Applying a second voltage lower than the first voltage to a remote second word line group on which a program operation has been performed, applying a first program voltage to a selected word line in a first program execution period for performing a first program on data. applying a first voltage to a selected word line and a first word line group in a second channel initialization period, applying a second voltage to a second word line group, and performing a second program on data. and applying a second program voltage to the selected word line in a second program execution period for

Description

Method of programming non-volatile memory device

The technical idea of the present disclosure relates to a memory device, and more particularly, to a method for programming a non-volatile memory device including first and second programs sequentially executed.

Memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. According to the demand for high capacity and miniaturization of nonvolatile memory devices, a three-dimensional memory device including a plurality of cell strings extending in a vertical direction on a substrate has been developed. In a channel initialization period for executing a program, a channel initialization or precharge operation may be performed on a plurality of cell strings. At this time, if the memory cells positioned above the cell string are in a programmed state, a portion of the channel corresponding to the programmed memory cells is negatively boosted and the channel initialization or precharge operation is not properly performed due to the high threshold voltage of the programmed memory cells. may not be As a result, a program disturb or hot carrier injection (HCI) problem may occur, and reliability of the nonvolatile memory device may deteriorate.

Technical features of the present disclosure provide a programming method of a nonvolatile memory device capable of reducing program disturb by controlling a word line voltage in a channel initialization period.

A programming method of a nonvolatile memory device according to technical features of the present disclosure may apply a first voltage to a first word line group relatively close to a selected word line and subjected to a program operation and the selected word line in a first channel initialization period. and applying a second voltage lower than the first voltage to a second word line group relatively distant from the selected word line and on which a program operation has been performed, executing a first program for performing a first program on data. applying a first program voltage to the selected word line during a period; applying the first voltage to the selected word line and the first word line group during a second channel initialization period; and applying a second program voltage to the selected word line in a second program execution period for performing a second program on the data.

A programming method of a nonvolatile memory device according to technical features of the present disclosure may include applying a first program voltage to a first select word line in a first program execution period for performing a first program on first data, thereby performing a first program operation on first memory cells connected to one selected word line; performing a first program operation on second memory cells connected to a second selected word line adjacent to the first selected word line; In a word line setup period after performing the first program operation on the second memory cells, a first bias voltage is applied to the first selected word line, and the first bias voltage is applied to the second selected word line. applying a second bias voltage having a higher voltage level than the voltage; and performing a second program operation on the first memory cells by applying a second program voltage to the first selected word line in a second program execution period for performing a second program on the first data. includes

A programming method of a nonvolatile memory device according to the technical idea of the present disclosure includes, in a channel initialization period, applying a precharge voltage to a common source line; In a bit line setup period, a program operation is performed and a first voltage is applied to a first word line disposed above a selected word line and a first voltage is applied to the selected word line, and the program operation is completed and disposed above the first word line applying a second voltage lower than the first voltage to a second word line; applying a third voltage lower than the first and second voltages to the selected word line and the first and second word lines in a word line setup period; and executing a program operation on memory cells connected to a selected word line in a program execution period, wherein the channel initialization period and the bit line setup period correspond to substantially the same time period.

According to the technical idea of the present disclosure, in a channel precharge or channel initialization period for a program operation, word lines on which a program operation has been performed are grouped into a plurality of word line groups, and different voltages are applied to the plurality of word lines. Accordingly, a channel potential difference between channel regions corresponding to the selected word line and adjacent word lines may be reduced. Accordingly, program disturb caused by FN stress or HCI can be reduced, and as a result, reliability of the memory device can be improved.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
2 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.
3 is a circuit diagram illustrating a memory block according to an exemplary embodiment of the present disclosure.
4A and 4B are perspective views each illustrating a memory block according to some exemplary embodiments of the present disclosure.
5 schematically illustrates a memory cell array according to an exemplary embodiment of the present disclosure.
6 illustrates a program operation including a first program operation and a second program operation on a selected word line, according to an embodiment of the present disclosure.
7 illustrates first and second program operations according to an embodiment of the present disclosure.
8 illustrates first and second program operations according to an embodiment of the present disclosure.
9 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure.
10 is a timing diagram illustrating a program operation of a memory device according to an exemplary embodiment of the present disclosure.
11 schematically illustrates a memory cell array according to an exemplary embodiment of the present disclosure.
12A and 12B illustratively show a program sequence according to some embodiments of the present disclosure.
13 illustrates a program operation including first and second program operations on a selected word line and a program operation including first and second program operations on an adjacent word line, according to an embodiment of the present disclosure.
14 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure.
15 is a timing diagram illustrating a first program operation of a memory device according to an exemplary embodiment of the present disclosure.
16 is a timing diagram illustrating a second program operation of a memory device according to an exemplary embodiment of the present disclosure.
17 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure.
18 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure.
19A is a timing diagram illustrating a second program operation for a first selected word line according to a comparative example of the present disclosure, and FIG. 19B is a second program for a first selected word line according to an embodiment of the present disclosure. It is a timing diagram showing the operation.
20 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure.
21 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure.
22 is a timing diagram illustrating a program operation of a memory device according to an embodiment of the present disclosure.
23 illustrates a memory device having a COP structure, according to an embodiment of the present disclosure.
24 is a cross-sectional view illustrating a memory device having a B-VNAND structure, according to an exemplary embodiment.
25 is a block diagram illustrating an SSD system to which a memory device according to an embodiment of the present disclosure is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

1 is a block diagram illustrating a memory system 10 according to an exemplary embodiment of the present disclosure. Referring to FIG. 1 , a memory system 10 may include a memory device 100 and a memory controller 200 , and the memory device 100 may include a memory cell array 110 and a control logic circuit 120 . can do. The memory device 100 may be a non-volatile memory device, and in this specification, a “memory device” refers to a “non-volatile memory device”.

The memory controller 200 may control the memory device 100 to read data stored in the memory device 100 or program data into the memory device 100 in response to a read/write request from the host HOST. there is. Specifically, the memory controller 200 controls program, read, and erase operations of the memory device 100 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 100 . can Also, data DATA for programming and read data DATA may be transmitted and received between the memory controller 200 and the memory device 100 .

The memory cell array 110 may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments of the present disclosure will be described in detail taking a case in which the plurality of memory cells are NAND flash memory cells as an example. However, the present invention is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

The control logic circuit 120 receives a command CMD, an address ADDR, and a control signal CTRL from the memory controller 200, and transmits the received command CMD, address ADDR, and control signal CTRL. Based on this, the overall operation of the memory device 100 can be controlled. When receiving a command CMD, an address ADDR, and data DATA corresponding to a program command from the memory controller 200, the control logic circuit 120 selects a word line or a selected memory corresponding to the address ADDR. Received data DATA may be written into the memory cell array 110 by controlling a program operation including a first program operation and a second program operation for a cell. The first and second program operations may be sequentially performed, and programming of the data DATA may be completed through the first and second program operations. Depending on the embodiment, the first program operation may be referred to as a pre-program operation, pre-program operation, or initial program operation, and the second program operation may be referred to as a post-program operation or final program operation. can do.

The control logic circuit 120 may include a program controller (PGM CONTROLLER) 121 . In one embodiment, the program controller 121 sets the word lines on which the program is performed prior to the selected word line corresponding to the address ADDR to at least two word lines in a channel precharge or channel initialization period for the first program operation. You can group them into groups. The program controller 121 differentiates a first voltage applied to a word line group relatively close to the selected word line among at least two word line groups and a second voltage applied to a word line group relatively far from the selected word line from each other. It can be controlled, and the voltage level of the first voltage can be controlled to be higher than the voltage level of the second voltage. In this case, the first voltage may be substantially the same as or similar to the voltage applied to the selected word line, thereby reducing a channel potential difference in the boundary word line and suppressing negative boosting in the channel region.

2 is a block diagram illustrating a memory device 100 according to an exemplary embodiment of the present disclosure. Referring to FIG. 2 , the memory device 100 may include a memory cell array 110 , a control logic circuit 120 , a page buffer circuit 130 , a voltage generator 140 and a row decoder 150 . Although not shown, the memory device 100 may further include an interface circuit, and the interface circuit may include a data input/output circuit, a command/address input/output circuit, and the like. Also, the memory device 100 may further include a temperature sensor.

The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz, where z is a positive integer. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of pages, and each of the plurality of pages may include a plurality of memory cells. For example, a memory block may be a unit of erase, and a page may be a unit of write and read. Each memory cell may store one or more bits, and specifically, each memory cell is a single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quadruple level cell (QLC). can be used

The memory cell array 110 may be connected to a plurality of word lines WL, a plurality of string select lines SSL, a plurality of ground select lines GSL, and a plurality of bit lines BL. The memory cell array 110 is connected to the row decoder 150 through a plurality of word lines WL, a plurality of string select lines SSL, and a plurality of ground select lines GSL, and a plurality of bit lines. It may be connected to the page buffer circuit 130 through BL. In some embodiments, the memory cell array 110 may further be connected to gate induced drain leakage (GIDL) erase control lines.

In one embodiment, the memory cell array 110 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of cell strings or NAND strings. Each cell string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference. are combined

The control logic circuit 120 writes data into the memory cell array 110 or writes data to the memory cell array 110 based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 200 . ), various control signals for reading data can be output. Accordingly, the control logic circuit 120 may generally control various operations within the memory device 100 . Specifically, the control logic circuit 120 may provide the voltage control signal CTRL_vol to the voltage generator 140, may provide the row address X_ADDR to the row decoder 150, and the page buffer circuit 130 ) can be provided with a column address (Y_ADDR). However, the present invention is not limited thereto, and the control logic circuit 120 may further provide other control signals to the voltage generator 140 , the row decoder 150 and the page buffer circuit 130 .

The program controller 121 may group word lines on which a program operation has been performed into a plurality of word line groups, and generate a voltage control signal CTRL_vol to apply different voltages to each word line group in a channel initialization period. Specifically, the program controller 121 determines word lines relatively close to the selected word line, on which a program operation is performed, as a first word line group, and word lines relatively far from the selected word line, on which a program operation is performed, as a second word line group. determined as a word line group, and in a channel initialization period, a voltage control signal ( CTRL_vol) can be created.

The voltage generator 140 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. Specifically, the voltage generator 140 may generate a word line voltage (VWL), a string select line voltage (VSSL), and a ground select line voltage (VGSL), and the generated word line voltage (VWL), the string select line voltage (VSSL) and the ground select line voltage (VGSL) to the row decoder 150. For example, the voltage generator 140 may generate a program voltage, a pass voltage, a read voltage, a program verify voltage, an erase voltage, and the like as the word line voltage VWL. Also, the voltage generator 140 may further generate a bit line voltage and a common source line voltage.

In an embodiment, the voltage generator 140 may perform a first or second channel initialization period for a first or second program operation on a selected word line (eg, FIG. 15 ) based on the voltage control signal CTRL_vol. In USIP1 of or USIP2 of FIG. 16), a first voltage applied to the selected word line and the first word line group and a second voltage applied to the second word line group may be generated. In one embodiment, the voltage generator 140, based on the voltage control signal CTRL_vol, in a second channel initialization period (eg, USIP2 of FIG. 16) for a second program operation on the selected word line, A first voltage applied to a word line in which one program operation is performed and the second program operation is not completed may be generated.

The row decoder 150 may select one of the plurality of word lines WL and select one of the plurality of string selection lines SSL in response to the row address X_ADDR. For example, during a program operation, the row decoder 150 applies a program voltage (eg, VPGM of FIG. 10 ) to a selected word line in a program execution period, and applies a program verification voltage to a selected word line in a program verification period. can be authorized. Also, in the program execution period, the row decoder 150 applies a first voltage (eg, V1 in FIG. 10 ) to the first word line group in the channel initialization period, and applies a second voltage ( For example, V2) of FIG. 10 may be applied. The page buffer circuit 130 may select at least one bit line from among the plurality of bit lines BL in response to the column address Y_ADDR. The page buffer circuit 130 may operate as a write driver or a sense amplifier according to an operation mode.

3 is a circuit diagram illustrating a memory block BLK according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3 , the memory block BLK may correspond to one of the plurality of memory blocks BLK1 to BLKz of FIG. 2 . The memory block BLK may be connected to bit lines BL1 to BL3, string select lines SSL1 to SSL3, word lines WL1 to WL8, and ground select lines GSL1 to GSL3, and may be connected in a vertical direction. NAND strings or cell strings NS11 to NS33 each extending along (VD) may be included. Here, the number of cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be variously changed according to embodiments.

The bit lines BL1 to BL3 may extend along a first direction or a first horizontal direction HD1 , and the word lines WL1 to WL8 may extend along a second direction or a second horizontal direction HD2 . can Cell strings NS11, NS21, and NS31 are positioned between the first bit line BL1 and the common source line CSL, and cell strings NS12 are positioned between the second bit line BL2 and the common source line CSL. , NS22, and NS32) may be positioned, and cell strings NS13, NS23, and NS33 may be positioned between the third bit line BL3 and the common source line CSL.

For example, the cell string NS11 may include a string select transistor SST, a plurality of memory cells MCs, and a ground select transistor GST connected in series. The string select transistor SST may be connected to a corresponding string select line SSL1 , and the memory cells MCs may be connected to corresponding word lines WL1 to WL8 , respectively. The ground select transistor GST may be connected to a corresponding ground select line GSL1.

In some embodiments, the memory block BLK may further include upper GIDL erase control lines between the bit lines BL1 to BL3 and the string select lines SSL1 to SSL3, and each cell string has at least one It may further include at least one upper GIDL erase control transistor connected to the upper GIDL erase control line of the upper GIDL erase control line. In some embodiments, the memory block BLK may further include lower GIDL erase control lines between the ground select lines GSL1 to GSL3 and the common source line CSL, and each cell string has at least one lower It may further include at least one lower GIDL erase control transistor connected to the GIDL erase control line.

4A is a perspective view illustrating a memory block BLKa according to an exemplary embodiment of the present disclosure. Referring to FIG. 4A , a memory block BLKa may correspond to one of the plurality of memory blocks BLK1 to BLKz of FIG. 2 . The memory block BLKa is formed in a direction VD perpendicular to the substrate SUB.

The substrate SUB has a first conductivity type (eg, p-type) and extends on the substrate SUB in a second horizontal direction or in a second direction HD2. In one embodiment, a common source line CLS doped with impurities of the second conductivity type (eg, n-type) may be provided on the substrate SUB. In one embodiment, the substrate SUB may be implemented with polysilicon, and a plate-shaped common source line CSL may be disposed on the substrate SUB. On the substrate SUB, a plurality of insulating layers IL extending along the second direction HD2 are sequentially provided along the vertical direction VD, and the plurality of insulating layers IL extend in the vertical direction VD. are spaced apart by a certain distance along For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

On the substrate SUB, a plurality of pillars are sequentially disposed along the first horizontal direction or the first direction HD1 and penetrate the plurality of insulating layers IL along the vertical direction VD ( P) is provided. For example, the plurality of pillars P penetrate the plurality of insulating layers IL and contact the substrate SUB. Specifically, a surface layer (S) of each pillar (P) may include a first type silicon material and may function as a channel region. Accordingly, in some embodiments, the pillar P may be referred to as a channel structure or a vertical channel structure. Meanwhile, the inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

A charge storage layer (CS) is provided along the exposed surface of the insulating layers IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (or referred to as 'tunneling insulating layer'), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Also, gate electrodes GE such as a ground select line GSL, word lines WL1 to WL8, and string select lines SSL are provided on the exposed surface of the charge storage layer CS. The number of ground select lines GSL, word lines WL1 to WL8, and string select lines SSL may be variously changed according to embodiments.

Drain contacts or drains DR are respectively provided on the plurality of pillars P. For example, the drains DR may include a silicon material doped with impurities of the second conductivity type. Bit lines BL1 to BL3 extending in the first direction HD1 and spaced apart from each other by a specific distance along the second direction HD2 are provided on the drains DR.

4B is a perspective view illustrating a memory block BLKb according to an exemplary embodiment of the present disclosure. Referring to FIG. 4B , the memory block BLKb may correspond to one of the plurality of memory blocks BLK1 to BLKz of FIG. 2 . Also, the memory block BLKb corresponds to a modified example of the memory block BLKa of FIG. 4A, and the details described above with reference to FIG. 4A may also be applied to the present embodiment. The memory block BLKb is formed in a direction perpendicular to the substrate SUB. The memory block BLKb may include a first memory stack ST1 and a second memory stack ST2 stacked in the vertical direction VD. However, the present invention is not limited thereto, and the memory block BLKb may include three or more memory stacks.

5 schematically illustrates a memory cell array 110a according to an exemplary embodiment of the present disclosure. Referring to FIG. 5 , the memory cell array 110a includes a common source line CSL and a bit line BL extending in a first direction HD1 and a memory stack ST extending in a vertical direction VD. ) may be included. At this time, the stack ST may be connected to the bit line BL through the drain DR. For example, the memory cell array 110a corresponds to the example of FIG. 4A , the memory stack ST may correspond to the pillar P of FIG. 4A , and correspond to the first cell string NS11 of FIG. 3 . may be In one embodiment, channel recovery (CH_RCY) or channel initialization may be performed from the common source line (CSL) to the bit line (BL), but the present invention is not limited thereto. In some embodiments, channel recovery (CH_RCY) or channel initialization may be performed in the direction from the bit line (BL) to the common source line (CSL), and in other embodiments, the channel recovery (CH_RCY) is performed in both directions. It could be.

The memory cell array 110a further includes a plurality of word lines WL1 to WLk stacked in the vertical direction VD, and a ground select line GSL is provided between the common source line CSL and the word line WL1. is disposed, and a string select line SSL may be disposed between the bit line BL and the word line WLk, where k is a positive integer. Although not shown, an upper GIDL erase control line is further disposed between the string select line SSL and the bit line BL, or a lower GIDL erase control line is disposed between the ground select line GSL and the common source line CLS. more can be placed.

In an embodiment, during a program operation on the selected word line WLn, unselected word lines are grouped into a plurality of word line groups including first to third word line groups WLG1 , WLG2 , and WLG3 . can be, and n is a positive integer. In this case, unselected word lines on which a program operation is performed prior to the selected word line WLn may be grouped into a plurality of word line groups including at least first and second word line groups WLG1 and WLG2. Unselected word lines on which a program operation is performed later than the selected word line WLn may be grouped into at least one word line group including a third word line group WLG3. As such, according to the present embodiment, word lines whose program order is faster than the selected word line WLn are grouped into at least two word line groups, and word lines whose program order is slower than the selected word line WLn are grouped into at least one word line group. may be grouped into word line groups of

For example, programming may be performed in a direction from a word line WLk relatively close to the bit line BL to a word line WL1 relatively close to the common source line CSL. That is, the program operation may be performed according to a top to bottom (T2B) program sequence. At this time, the word lines WLn+1 to WLk disposed above the selected word line WLn are grouped into a plurality of word line groups including first and second word line groups WLG1 and WLG2. can For example, the first word line group WLG1 includes word lines (eg, WLn+1 to WLi) relatively close to the selected word line WLn, and the second word line group WLG2 includes Word lines (eg, WLi+1 to WLk) relatively far from the selected word line group WLn may be included, and i is a positive integer greater than n and less than k.

Meanwhile, the word lines WL1 to WLn−1 disposed under the selected word line WLn may be grouped into at least one word line group including a third word line group WLG3. For example, the third word line group WLG3 may include word lines WL1 to WLn−1 in the selected word line WLn. However, the present invention is not limited thereto, and in some embodiments, the word lines WL1 to WLn-1 disposed below the selected word line WLn include a plurality of word lines including the third word line group WLG3. can be grouped into word line groups of For example, the third word line group WLG3 includes at least one word line (eg, WLn−1) relatively close to the selected word line WLn, and the remaining word lines are the fourth word line group. can be included in

6 illustrates a program operation including a first program operation PGM1 and a second program operation PGM2 for a selected word line WLn according to an embodiment of the present disclosure.

Referring to FIGS. 1 and 6 together, the memory device 100 may receive a command CMD, an address ADDR, and data DATA from the memory controller 200 . In this case, the command CMD may correspond to a program command, the address ADDR may correspond to a write address, and the data DATA may correspond to write data. The selected word line WLn may correspond to the address ADDR, and the memory device 100 selects the data DATA by sequentially performing the first program operation PGM1 and the second program operation PGM2. can be entered in The first program operation PGM1 may include a first channel initialization period (CH_INT1) 61 and a first program execution period (PGM_EXE1) 62, and the second program operation PGM2 may include a second channel initialization period. (CH_INT2) 63 and a second program execution section (PGM_EXE2) 64. There may be a predetermined time interval between the first program operation PGM1 and the second program operation PGM2.

7 illustrates first and second program operations PGM1a and PGM2a according to an embodiment of the present disclosure. A program method including the first and second program operations PGM1a and PGM2a illustrated in FIG. 7 may be referred to as a shadow program method. The first and second program operations PGM1a and PGM2a may respectively correspond to the first and second program operations PGM1 and PGM2 of FIG. 6 . Although FIG. 7 illustrates first and second program operations PGM1a and PGM2a for MLC, the method described in FIG. 7 may be equally applied to TLC or QLC.

The first program operation PGM1a may program memory cells in an erase state into one of M program states, where M is an integer greater than or equal to 2. The initial program distribution 71 may be changed to the program distribution 71' by coupling or interference according to program operations of peripheral memory cells. The second program operation PGM2a may program the memory cells in which the first program operation PGM1a has been performed into one of N program states, where N is an integer greater than M. The initial program distribution 72 may be changed to the program distribution 72' by coupling or interference according to program operations of peripheral memory cells.

8 illustrates first and second program operations PGM1b and PGM2b according to an embodiment of the present disclosure. A program method including the first and second program operations PGM1b and PGM2b illustrated in FIG. 8 may be referred to as a reprogram method. The first and second program operations PGM1b and PGM2b may respectively correspond to the first and second program operations PGM1 and PGM2 of FIG. 6 . Although FIG. 8 illustrates first and second program operations for MLC, the method described in FIG. 18 may be equally applied to TLC or QLC.

The first program operation PGM1b may program memory cells in an erase state into one of N program states, where N is an integer greater than or equal to 2. The initial program distribution 81 may be changed to the program distribution 81' by coupling or interference according to program operations of peripheral memory cells. The second program operation PGM2b may program the memory cells in which the first program operation PGM1b has been performed into one of N program states. The initial program distribution 82 may be changed to the program distribution 82' by coupling or interference according to program operations of peripheral memory cells.

9 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure. The program method according to the present embodiment is a method of controlling voltages applied to unselected word lines in a channel precharge or channel initialization period for a program operation, and is performed in the memory device 100 of FIG. can Details described above with reference to FIGS. 1 to 8 are also applied to the present embodiment, and redundant descriptions will be omitted.

6 and 9 together, in step S110, in the first channel initialization period 61, a first voltage (eg, FIG. 10 ) is applied to the selected word line WLn and the first word line group WLG1. V1 of ) is applied, and a second voltage lower than the first voltage (eg, V2 of FIG. 10 ) is applied to the second word line group WLG2 . Here, the program order of the memory device may correspond to directions of the second word line group WLG2 , the first word line group WLG1 , and the selected word line WLn. In step S130, in the first program execution period 62, a first program voltage (eg, VPGM of FIG. 10) is applied to the selected word line WLn.

In step S150, in the second channel initialization period 63, a first voltage (eg, V1 of FIG. 10) is applied to the selected word line WLn and the first word line group WLG1, and the second word A second voltage (eg, V2 in FIG. 10 ) is applied to the line group WLG2 . In this way, the voltage applied to the first word line group WLG1 in steps S110 and S150 may be the same as the first voltage, and the voltage applied to the second word line group WLG2 may be the same as the second voltage. However, the present invention is not limited thereto. In step S140, in the second program execution period 64, a second program voltage (eg, VPGM of FIG. 10) is applied to the selected word line WLn.

10 is a timing diagram illustrating a program operation of a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 10 , the word line recovery period WL_RCY corresponds to a time period from t0 to t1, and in the word line recovery period WL_RCY, the word line voltage may drop to a predetermined voltage level. Subsequently, the channel initialization period (Unselected String Initial Precharge, USIP) corresponds to the time period from t1 to t2, for example, to correspond to the first channel initialization period 61 or the second channel initialization period 63 of FIG. can Also, the channel initialization period USIP may be substantially the same as the bit line setup period BL_SETUP, and channel initialization and bit line setup operations may be performed in parallel in the channel initialization period USIP.

In the channel initialization period (USIP), the common source line voltage (VCSL) is applied to the common source line (CSL), the string select line voltage (VSSL) is applied to the string select line (SSL), and the ground select line (GSL) A ground select line voltage (VGSL) may be applied to . The string select line voltage VSSL corresponds to a voltage level that turns on the string select transistor (eg, SST of FIG. 3 ), and the ground select line voltage VGSL corresponds to the voltage level of the ground select transistor (eg, GST of FIG. 3 ). ) may correspond to a voltage level that turns on.

In the channel initialization period USIP, the first voltage V1 is applied to the selected word line WLn and the word lines WLn+1 to WLi adjacent to the selected word line WLn, and the word lines WLi+ 1~) may be applied with the second voltage V2. The word lines WLn+1 to WLi may be included in the first word line group WLG1 , and the word lines WLi +1 to WLn may be included in the second word line group WLG2 . Threshold voltages of memory cells connected to the word lines WLn+1 to WLi on which the program operation has been performed may be significantly high. According to the present embodiment, in the channel initialization period USIP, the selected word line WLn and adjacent The same first voltage may be applied to the word lines WLn+1 to WLi. Accordingly, a channel potential difference between the selected word line WLn and the adjacent word lines WLn+1 to WLi may be reduced, and thus, in a channel region corresponding to the adjacent word lines WLn+1 to WLi. Negative busking can be suppressed.

The word line setup period WL_SETUP corresponds to the time period from t2 to t3. In the word line setup period, the string selection line voltage VSSL is continuously applied to the selected string selection line, while the non-selected string selection line A ground voltage may be applied. Also, in the word line setup period WL_SETUP, the common source line voltage VCSL is continuously applied to the common source line CSL, the ground voltage GND is applied to the ground select line GSL, and the selected word line A third voltage V3 may be applied to WLn and the unselected word lines WLn+1 to . In this case, the third voltage V3 may have a lower voltage level than the first and second voltages V1 and V2. For example, the third voltage V3 may correspond to the ground voltage GND, but the present invention is not limited thereto.

The program execution section PGM_EXE may correspond to, for example, the first program execution section 62 or the second program execution section 64 of FIG. 6 and may correspond to a time section from t3 to t4. In the program execution period PGM_EXE, the program voltage VPGM may be applied to the selected word line WLn, and the pass voltage VPASS may be applied to non-selected word lines WLn+1 to . In this case, the program voltage VPGM may have a higher voltage level than the pass voltage VPASS.

11 schematically illustrates a memory cell array 110b according to an exemplary embodiment of the present disclosure. Referring to FIG. 11 , the memory cell array 110b includes a common source line CSL and a bit line BL extending in a first direction HD1 and a first memory stack extending in a vertical direction VD. (ST1) and a second memory stack (ST2). In this case, the first memory stack ST1 is disposed above the common source line CSL, and the second memory stack ST2 is disposed above the first memory stack ST1 and passes through the drain DR to the bit line. (BL). For example, the memory cell array 110b corresponds to the example of FIG. 4B, and the first memory stack ST1 and the second memory stack ST2 correspond to the first memory stack ST1 and the second memory stack ST1 of FIG. 4B. Each may correspond to the stack ST2.

The memory cell array 110b includes a plurality of word lines WL1 to WLk stacked in a vertical direction VD, and a ground select line GSL is provided between the common source line CSL and the word line WL1. A string select line SSL may be disposed between the bit line BL and the word line WLk. In addition, the memory cell array 110b may further include first and second junction dummy word lines CDL1 and CDL2 corresponding to junctions of the first and second memory stacks ST1 and ST2. . However, the present invention is not limited thereto, and the number of junction dummy word lines corresponding to the junction may be variously changed according to embodiments. Also, according to embodiments, a junction dummy word line may not be disposed.

For example, in the case of the first memory stack ST1, a program (that is, a top to bottom (T2B) PGM) is executed in the direction from a word line far from the common source line CSL to a word line close to the common source line CSL. can be performed At this time, the word lines WLa+1 to WLb disposed above the selected word line WLa are grouped into a plurality of word line groups including first and second word line groups WLG1a and WLG2a. can For example, the first word line group WLG1a includes the word line WLa+1 relatively close to the selected word line WLa, and the second word line group WLG2a is the selected word line group WLa. may include relatively distant word lines (eg, WLb-1, WLb), where a and b are positive integers greater than 1, and b is greater than a. Meanwhile, the word lines WL1 to WLa-1 disposed under the selected word line WLa may be grouped into at least one word line group including a third word line group WLG3a.

For example, in the case of the second memory stack ST2, a program (ie, bottom to top (B2T) PGM) is performed in a direction from a word line far from the bit line BL to a word line close to the bit line BL. can At this time, the word lines WLb+1 to WLc disposed under the selected word line WLc are grouped into a plurality of word line groups including first and second word line groups WLG1b and WLG2b. can For example, the first word line group WLG1b includes word lines WLc-1 and WLc-2 relatively close to the selected word line WLc, and the second word line group WLG2b includes the selected word line. The group WLc may include relatively distant word lines WLb+1, where c is a positive integer greater than b. Meanwhile, the word lines WLc+1 to WLk disposed above the selected word line WLc may be grouped into at least one word line group including a third word line group WLG3b.

In an exemplary embodiment, different voltages may be applied to the first and second word line groups WLG1a and WLG2a in a first channel initialization period for a first program operation during a program operation on the selected word line WLa. The same voltage may be applied to the word lines WLb+1 to WLk connected to the second memory stack ST2. In an embodiment, during a program operation on the selected word line WLc, different voltages may be applied to the first and second word line groups WLG1b and WLG2b in a first channel initialization period for the first program operation. The same voltage may be applied to the word lines WL1 to WLb connected to the first memory stack ST1.

In an embodiment, voltages applied to the first to third word line groups WLG1a, WLG2a, and WLG3a in a second channel initialization period for a second program operation during a program operation on the selected word line WLa. At least one of them may be differently controlled, and the same voltage may be applied to word lines WLb+1 to WLk connected to the second memory stack ST2. In an embodiment, voltages applied to the first to third word line groups WLG1a, WLG2a, and WLG3a in a second channel initialization period for a second program operation during a program operation on the selected word line WLc. At least one of them may be differently controlled, and the same voltage may be applied to the word lines WL1 to WLb connected to the first memory stack ST1.

However, the present invention is not limited thereto, and in some embodiments, in the case of the first memory stack ST1, programming is performed in a direction from a word line close to the common source line CSL to a word line far from the common source line CSL. (ie, B2T PGM) is performed, and in the case of the second memory stack ST2, a program (ie, T2B PGM) is performed in the direction from a word line close to the bit line BL to a word line far from the bit line BL. It can be. Also, in some embodiments, in the case of the first memory stack ST1, programming (ie, B2T PGM) is performed in a direction from a word line close to the common source line CSL to a word line far from the common source line CSL. In the case of the second memory stack ST2, programming (ie, B2T PGM) may be performed in a direction from a word line far from the bit line BL to a word line close to the bit line BL. Furthermore, in some embodiments, in the case of the first memory stack ST1, programming (ie, T2B PGM) is performed in a direction from a word line far from the common source line CSL to a word line close to the common source line CSL. In the case of the second memory stack ST2, programming (ie, T2B PGM) may be performed in a direction from a word line close to the bit line BL to a word line far from the bit line BL. In this way, according to different program directions for each memory stack, word line groups in each memory stack may be grouped in various ways.

12A illustratively shows a program sequence according to an embodiment of the present disclosure. Referring to FIG. 12A , the present embodiment may correspond to the first scrambling method and may be a T2B program method in which memory cells adjacent to a bit line are programmed in order of memory cells adjacent to a common source line. For example, the memory block BLK may include word lines WLn−1, WLn, WLn+1, and WLn+2 and first to fourth string select lines SSL1 to SSL4.

For example, memory cells connected to the word line WLn+2 and the first string select line SSL1 , memory cells connected to the word line WLn+2 and the second string select line SSL2 , and word line WLn +2) and the memory cells connected to the third string select line SSL3, and the memory cells connected to the word line WLn+2 and the fourth string select line SSL4, the first program operations PMG1 are sequentially performed. can be performed Subsequently, memory cells connected to the word line WLn+1 and the first string select line SSL1 , memory cells connected to the word line WLn+1 and the second string select line SSL2 , and word line WLn+1 ) and memory cells connected to the third string select line SSL3, and memory cells connected to the word line WLn+1 and the fourth string select line SSL4, the first program operations PMG1 are sequentially performed. can Subsequently, memory cells connected to the word line WLn+2 and the first string select line SSL1 , memory cells connected to the word line WLn+2 and the second string select line SSL2 , and word line WLn+2 ) and memory cells connected to the third string select line SSL3, and memory cells connected to the word line WLn+2 and the fourth string select line SSL4, the second program operations PMG2 are sequentially performed. can

As described above, according to the present embodiment, prior to performing the second program operation PGM2 on the memory cells connected to the word line WLn+2 and the first string select line SSL1, the word line WLn+1 ) and the memory cells connected to the fourth string selection line SSL4, the first program operation PGM1 is performed on the memory cells connected to the word line WLn+2 and the first string selection line SSL1. After the program operation (PGM1), a sufficiently long time can be experienced while maintaining the voltage difference between the word line and the channel. Accordingly, channel trap states of the cell string during the verify operation and during the read operation may be similar, thereby improving distribution of the memory device. Also, since the time between the first program operation PGM1 and the second program operation PGM2 becomes longer, the effect of the shallow trap can be reduced.

12B illustratively shows a program sequence according to an embodiment of the present disclosure. Referring to FIG. 12B, the programming method according to the present embodiment corresponds to a modified embodiment of the T2B program method of FIG. 12A, and performs programming in the order of memory cells adjacent to a bit line in memory cells adjacent to a common source line. It can be programmatic.

For example, memory cells connected to the word line WLn-2 and the first string select line SSL1, memory cells connected to the word line WLn-2 and the second string select line SSL2, and the word line WLn -2) and the memory cells connected to the third string select line SSL3, the memory cells connected to the word line WLn-2 and the fourth string select line SSL4, the first program operations PMG1 are sequentially performed. can be performed Subsequently, memory cells connected to the word line WLn-1 and the first string select line SSL1, memory cells connected to the word line WLn-1 and the second string select line SSL2, and word line WLn-1 ) and memory cells connected to the third string select line SSL3, and memory cells connected to the word line WLn−1 and the fourth string select line SSL4, the first program operations PMG1 are sequentially performed. can Next, memory cells connected to the word line WLn-2 and the first string select line SSL1, memory cells connected to the word line WLn-2 and the second string select line SSL2, and the word line WLn-2 ) and memory cells connected to the third string select line SSL3, and memory cells connected to the word line WLn−2 and the fourth string select line SSL4, the second program operations PMG2 are sequentially performed. can

As described above, according to the present embodiment, prior to performing the second program operation PGM2 on the memory cells connected to the word line WLn-2 and the first string select line SSL1, the word line WLn-1 ) and the memory cells connected to the fourth string selection line SSL4, the first program operation PGM1 is performed on the memory cells connected to the word line WLn-2 and the first string selection line SSL1. After the program operation (PGM1), a sufficiently long time can be experienced while maintaining the voltage difference between the word line and the channel. Accordingly, channel trap states of the cell string during the verify operation and during the read operation may be similar, thereby improving distribution of the memory device. In addition, since the time between the first program operation PGM1 and the second program operation PGM2 becomes longer, the effect of the shallow trap can be reduced.

13 illustrates a program operation including first and second program operations for a selected word line WLn and first and second program operations for an adjacent word line WLn-1 according to an embodiment of the present disclosure. Indicates program operations that include

Referring to FIG. 13 , for example, when the program sequence is a T2B program, program operations for a selected word line WLn and an adjacent word line WLn-1 below the selected word line WLn are sequentially performed. can Specifically, the first program operation PGM1 including the first channel initialization period 131 and the first program execution period 132 for the selected word line WLn is performed, and then, the adjacent word line WLn- The first program operation PGM1 including the first channel initialization period 133 and the first program execution period 134 for 1) is performed, and then, the second channel initialization period for the selected word line WLn A second program operation (PGM2) including 135 and a second program execution period 136 is performed, followed by a second channel initialization period 137 for an adjacent word line WLn-1 and a second program A second program operation PGM2 including the execution section 138 may be performed. As described above, according to the present embodiment, between the first and second program operations PGM1 and PGM2 on the selected word line WLn, the first program operation on the adjacent word line WLn-1 is performed. can

However, the present invention is not limited thereto, and when the program sequence is a B2T program, program operations for the selected word line WLn and the adjacent word line WLn+1 above the selected word line WLn may be sequentially performed. may be Specifically, the first program operation PGM1 is performed on the selected word line WLn, then the first program operation PGM1 is performed on the adjacent word line WLn+1, and then the selected word line A second program operation PGM2 may be performed on WLn, and then a second program operation PGM2 may be performed on an adjacent word line WLn+1. As described above, according to the present embodiment, a first program operation on an adjacent word line WLn+1 is performed between the first and second program operations PGM1 and PGM2 on the selected word line WLn. can

14 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure. 15 is a timing diagram illustrating a first program operation PGM1 of a memory device according to an embodiment of the present disclosure. 16 is a timing diagram illustrating a second program operation PGM2 of a memory device according to an embodiment of the present disclosure. 15 and 16 correspond to a modified example of FIG. 10, and duplicate descriptions will be omitted.

5 and 16 to 18 together, in step S110, in the first channel initialization period USIP1, a first voltage V1 is applied to the selected word line WLn and the first word line group WLG1. and the second voltage V2 is applied to the second word line group WLG2. Here, the first voltage V1 may have a higher voltage level than the second voltage V2 , and memory cells corresponding to the second word line group WLG2 may be turned on. In one embodiment, the first word line group WLG1 may include at least one word line on which only the first program operation PGM1 is performed. In one embodiment, the first word line group WLG1 may include word lines on which both the first and second program operations PGM1 and PGM2 are performed. In an embodiment, the second word line group WLG2 may include word lines on which both the first and second program operations WLG1 and WLG2 are performed.

Meanwhile, in the first channel initialization period USIP1, the ground voltage GND may be applied to the third word line group WLG3, and thus, the boosting potential of the channel corresponding to the third word line group WLG3 can maximize. In an embodiment, the third word line group WLG3 may include word lines on which neither the first nor the second program operations PGM1 and PGM2 are performed. In the first channel initialization period USIP1, since the program operation has not yet been performed on the third word line group WLG3, the memory cells connected to the third word line group WLG3 will be in an erased state. Accordingly, in the first channel initialization period USIP1, the first voltage V1 may not be applied to the third word line group WLG3.

In step S130, in the first program execution period PGM_EXE1, the first program voltage VPGM1 is applied to the selected word line WLn. Also, in the first program execution period PGM_EXE1, the pass voltage VPASS is applied to unselected word lines, that is, to the first to third word line groups WLG1, WLG2, and WLG3. In some embodiments, in the first program execution period PGM_EXE1 , the pass voltage VPASS may be first applied to the selected word line WLn and then the first program voltage VPGM1 may be applied. In step S140, a first program operation PGM1 is performed on the adjacent word line WLn-1 included in the third word line group WLG3.

In step S160, in the second channel initialization period USIP2, the first voltage V1 is applied to the selected word line WLn, the first word line group WLG1, and the adjacent word line WLn−1, and The second voltage V2 is applied to the two word line group WLG2. At this time, the first voltage V1 is applied to an adjacent word line WLn-1 on which the first program operation PGM1 is performed among the word lines included in the third word line group WLG3, and the third word line The ground voltage GND is applied to the remaining word lines included in the group WLG3, that is, to the word line WLn−2 on which the first program operation PGM1 is not performed. Accordingly, memory cells corresponding to the second word line group WLG2 and memory cells corresponding to the adjacent word line WLn−1 may be turned on. Accordingly, a channel potential difference between the selected word line WLn and the adjacent word lines WLn+1 to WLi may be reduced, and thus, in a channel region corresponding to the adjacent word lines WLn+1 to WLi. Negative busking can be suppressed. Similarly, it is possible to reduce the difference in channel potential between the selected word line (WLn) and the adjacent word line (WLn-1), thereby suppressing negative busing in the channel region corresponding to the adjacent word line (WLn-1). there is.

In step S190, in the second program execution period PGM_EXE2, the second program voltage VPGM2 is applied to the selected word line WL2. Also, in the second program execution period PGM_EXE2, the pass voltage VPASS is applied to unselected word lines, that is, to the first to third word line groups WLG1, WLG2, and WLG3. In some embodiments, in the second program execution period PGM_EXE2, the pass voltage VPASS may be first applied to the selected word line WLn, and then the second program voltage VPGM2 may be applied.

17 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure. The program method according to this embodiment corresponds to a modified example of the program method of FIG. 14, and redundant description will be omitted.

Referring to FIG. 17 , in step S110, in the first channel initialization period USIP1, the first voltage V1 is applied to the selected word line WLn and the first word line group WLG1, and the second word line The second voltage V2 is applied to the group WLG2. In step S120, in the first word line setup period WL_SETUP1 between the first channel initialization period USIP1 and the first program execution period PGM_EXE1, the selected word line WLn and the first and second word line groups A third voltage V3 lower than the first and second voltages V1 and V2 is applied to (WLG1 and WLG2).

In step S130, in the first program execution period PGM_EXE1, the first program voltage VPGM1 is applied to the selected word line WLn. In step S140, a first program operation is performed on the adjacent word line WLn−1 included in the third word line group WLG3. In step S170, in the second channel initialization period USIP2, the first voltage V1 is applied to the selected word line WLn, the first word line group WLG1, and the adjacent word line WLn−1, and The second voltage V2 is applied to the two word line group WLG2.

In step S180, in the second word line setup period WL_SETUP2 between the second channel initialization period USIP2 and the second program execution period PGM_EXE2, the selected word line WLn and the first and second word line groups A third voltage V3 lower than the first and second voltages V1 and V2 may be applied to (WLG1 and WLG2). Also, in the second word line setup period WL_SETUP2, a fourth voltage V4 lower than or equal to the first voltage V1 is applied to an adjacent word line WLn-1 included in the third word line group WLG3. may be authorized. Accordingly, in the second word line setup period WL_SETUP2, the memory cell corresponding to the adjacent word line WLn−1 may be turned on, and negative boosting of some channels may be suppressed by reducing FN stress or HCI. Also, boosting potential of a channel corresponding to the selected word line WLn may be maximized. In step S190, in the second program execution period PGM_EXE2, the second program voltage VPGM2 is applied to the selected word line WL2.

18 is a flowchart illustrating a programming method of a memory device according to an exemplary embodiment, and FIG. 19B is a timing diagram illustrating a second program operation for a first selected word line WLn according to an exemplary embodiment. It is also

Referring to FIGS. 18 and 19B together, in step S220, in a first program execution period, a first program voltage is applied to the first selected word line WLn, so that a first program voltage connected to the first selected word line WLn is applied. A first program operation is performed on the memory cells MCn. In step S240, a first program operation is performed on the second memory cells MCn-1 connected to the second selected word line WLn-1 adjacent to the first selected word line WLn.

In step S260, in the word line setup period 192b, the first bias voltage Vbais1 is applied to the first selected word line WLn, and the first bias voltage Vbais1 is applied to the second selected word line WLn-1. ), a second bias voltage Vbais2 higher than that is applied. In step S280, in the second program execution period 193b, by applying a second program voltage to the first selected word line WLn, the first memory cells MCn connected to the first selected word line WLn are A second program operation is performed.

19A is a timing diagram illustrating a second program operation for a first selected word line WLn according to a comparative example of the present disclosure.

Referring to FIG. 19A , when a program operation is performed on the memory device in the T2B direction, after the first program operation is performed on the second selected word line WLn-1, the first selected word line WLn A second program operation may be performed for At this time, both first and second program operations for the word lines WLn+1 to WLn+3 disposed above the first selected word line WLn in the vertical direction VD may be completed. . In other words, the memory cells MCn+1 to MCn+2 respectively connected to the word lines WLn+1 to WLn+3 may be in a program completion state (P).

Meanwhile, after the first program operation for the first selected word line WLn is completed, the first selected memory cell MCn connected to the first selected word line WLn may be in an erase state (E), and the second selected memory cell MCn may be in an erase state (E). After the first program operation on the word line WLn-1 is completed, the second selected memory cell MCn-1 connected to the second selected word line WLn-1 has a higher program than the first selected memory cell MCn. may be in a state For example, the second selected memory cell MCn-1 may be in the fifteenth program state P15, and at this time, the threshold voltage of the second selected memory cell MCn-2 may be about 4.5 V.

In the channel initialization period 191a, the bias voltage Vbias may be applied to the first and second selected word lines WLn and WLn-1. For example, the bias voltage Vbias may be 2.6 V and the channel potential may be 0 V. In the word line setup period 192a, when 0 V is applied to the first and second selected word lines WLn and WLn-1, the voltage level applied to the second selected word line WLn-1 is Since the voltage is lower than the threshold voltage of the second selected memory cell, the second selected memory cell MCn-1 is turned off.

By local boosting according to the turn-off of the second selected memory cell MCn−1, the channel region may be divided into a first channel CH1 and a second channel CH2, and the first selected word line WLn The channel potential of the first channel CH1 corresponding to may correspond to -Vbias, for example, -2.6 V. In the program execution period 193a, the pass voltage VPASS may be first applied to the first and second selected word lines WLn and WLn−1. Although not shown, the program voltage may be applied to the first selected word line WLn, and the pass voltage VPASS may be continuously applied to the second selected word line WLn-1. In the program execution period 193a, the channel potential may rise to the first channel voltage Vch1.

19B is a timing diagram illustrating a second program operation for a first selected word line WLn according to an embodiment of the present disclosure. Hereinafter, differences from FIG. 19A will be mainly described.

Referring to FIG. 19B , in the channel initialization period 191b, the bias voltage Vbias may be applied to the first and second selected word lines WLn and WLn-1. For example, the bias voltage Vbias may be 2.6 V and the channel potential may be 0 V. In the word line setup period 192b, the first bias voltage Vbias1, eg, 0 V, is applied to the first selected word line WLn, while the first selected word line WLn−1 receives the first bias voltage Vbias1. A second bias voltage Vbias2 higher than the bias voltage Vbias1 may be applied. Here, the second bias voltage Vbias2 may correspond to a voltage level turning on the second selected memory cell MCn-1 corresponding to the second selected word line WLn-1. For example, the second bias voltage Vbias2 may correspond to the bias voltage Vbias.

The second bias voltage Vbias2 applied to the second selected word line WLn-1 may be equal to or higher than the threshold voltage of the second selected memory cell MCn-1, and thus, the second selected memory cell MCn-1. ) will be turned on. When the second selected memory cell MCn−1 is turned on, the channel potential of the second channel CH2 corresponding to the first and second selected word lines WLn and WLn−1 may correspond to Vs. In this case, Vs may correspond to a value obtained by subtracting the threshold voltage Vth@P15 of the second selected memory cell MCn-1 from the second bias voltage Vbias2 applied to the second selected word line WLn-1. (i.e. Vs = Vbias2 - Vth@P15). In this case, the magnitude of Vs may be smaller than Vbias.

For example, the second bias voltage Vbias2 is 2.6 V, the threshold voltage Vth@P15 of the second selected memory cell MCn-1 is 4.5 V, and Vs is -1.9 V. Accordingly, the channel potential in the word line setup period 192b according to the present embodiment may be higher than that in the conventional word line setup period 192a. In the program execution period 193b, the channel potential may rise to the second channel voltage Vch2, and the second channel voltage Vch2 is higher than the first channel voltage Vch1 in the conventional program execution period 193a. can

20 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 20 , in step S210, in a first word line setup period, a first bias voltage Vbias1 is applied to the first selected word line WLn and the second selected word line WLn-1 adjacent to each other. . In step S220, a first program for the first memory cells MCn connected to the first selected word line WLn is performed by applying a first program voltage to the first selected word line WLn in the first program execution period. perform the action In step S240, a first program operation is performed on the second memory cells MCn-1 connected to the second selected word line WLn-1 adjacent to the first selected word line WLn.

In step S270, in the second word line setup period 192b, the first bias voltage Vbias1 is applied to the first selected word line WLn, and the first bias voltage is applied to the second selected word line WLn-1. A second bias voltage Vbias2 higher than (Vbias1) is applied. In step S280, in the second program execution period 193b, by applying a second program voltage to the first selected word line WLn, the first memory cells MCn connected to the first selected word line WLn are A second program operation is performed.

21 is a flowchart illustrating a method of programming a memory device according to an exemplary embodiment of the present disclosure. 22 is a timing diagram illustrating a program operation of a memory device according to an embodiment of the present disclosure.

Referring to FIGS. 21 and 22 together, in step S320, in the channel initialization period USIP, the common source line voltage VCSL corresponding to the precharge voltage is applied to the common source line CSL. In step S340, in the bit line setup period BL_SETUP, a first voltage Va is applied to the first word line WLn+1 disposed above the selected word line WLn and the selected word line WLn, , a second voltage Va' lower than the first voltage Va is applied to the second word line WLn+7 disposed above the first word line WLn+1. In this way, by applying the same first voltage Va as the selected word line WLn to word lines adjacent to the selected word line WLn, such as the first word line WLn+1, the channel voltage difference can be reduced. can Accordingly, it is possible to suppress negative boosting in some channels around the selected word line WLn.

In step S360, in the word line setup period WL_SETUP, a third voltage lower than the first and second voltages is applied to the selected word line WLn and the first and second word lines WLn+1 and WLn+7. (Vb) is applied. For example, the third voltage Vb may correspond to the ground voltage, but the present invention is not limited thereto. In step S380, a program operation is performed on memory cells connected to the selected word line in the program execution section.

23 illustrates a memory device 30 having a COP structure, according to an embodiment of the present disclosure.

2 and 23 together, the memory device 30 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may include a second semiconductor layer ( L2) may be stacked in a vertical direction (VD). Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in a vertical direction VD. The memory device 100 of FIG. 1 may have a COP structure like the memory device 30 .

In an exemplary embodiment, the memory cell array 110 may be formed on the first semiconductor layer L1, and may include a control logic circuit 120, a page buffer circuit 130, a voltage generator 140, and a row decoder 150. may be formed on the second semiconductor layer L2. Accordingly, the memory device 30 may have a structure in which the memory cell array 110 is disposed on top of some peripheral circuits, that is, a COP (Cell Over Peri) structure. The COP structure can effectively reduce the area in the horizontal direction and improve the degree of integration of the memory device 30 .

In one embodiment, the second semiconductor layer L2 may include a substrate, and circuits are formed on the second semiconductor layer L2 by forming semiconductor elements such as transistors and patterns for wiring the elements on the substrate. can do. After circuits are formed on the second semiconductor layer L2, a first semiconductor layer L1 including the memory cell array 110 may be formed, and word lines WL and bits of the memory cell array 110 may be formed. Patterns may be formed to electrically connect the lines BL and the circuits formed in the second semiconductor layer L2.

24 is a cross-sectional view illustrating a memory device having a B-VNAND structure, according to an exemplary embodiment. When the nonvolatile memory included in the memory device is implemented as a B-VNAND (Bonding Vertical NAND) type flash memory, the nonvolatile memory may have a structure shown in FIG. 24 .

Referring to FIG. 24 , the cell region CELL of the memory device 500 may correspond to the first semiconductor layer L1, and the peripheral circuit region PERI may correspond to the second semiconductor layer L2. Each of the peripheral circuit area PERI and the cell area CELL of the memory device 500 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. For example, the plurality of word lines WL, the plurality of string selection lines SSL, the plurality of ground selection lines GSL, and the memory cell array 110 of FIG. 2 include the first semiconductor layer L1 , and the control logic circuit 120 , the page buffer circuit 130 , the voltage generator 140 and the row decoder 150 may be formed on the second semiconductor layer L2 .

The peripheral circuit region PERI includes a first substrate 610, an interlayer insulating layer 615, a plurality of circuit elements 620a, 620b, and 620c formed on the first substrate 610, and a plurality of circuit elements 620a. , 620b, 620c) to include the first metal layers 630a, 630b, and 630c connected to each other, and the second metal layers 640a, 640b, and 640c formed on the first metal layers 630a, 630b, and 630c. can In an exemplary embodiment, the first metal layers 630a, 630b, and 630c may be formed of tungsten having relatively high resistance, and the second metal layers 640a, 640b, and 640c may be formed of copper having relatively low resistance. It can be.

In this specification, only the first metal layers 630a, 630b, and 630c and the second metal layers 640a, 640b, and 640c are shown, but are not limited thereto, and at least on the second metal layers 640a, 640b, and 640c. One or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 640a, 640b, and 640c are formed of aluminum having a lower resistance than copper forming the second metal layers 640a, 640b, and 640c. It can be.

The interlayer insulating layer 615 covers the plurality of circuit elements 620a, 620b, and 620c, the first metal layers 630a, 630b, and 630c, and the second metal layers 640a, 640b, and 640c on the first substrate. 610, and may include an insulating material such as silicon oxide or silicon nitride. Lower bonding metals 671b and 672b may be formed on the second metal layer 640b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 671b and 672b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 571b and 572b of the cell area CELL by a bonding method. , The lower bonding metals 671b and 672b and the upper bonding metals 571b and 572b may be formed of aluminum, copper, or tungsten.

The cell area CELL may provide at least one memory block. The cell region CELL may include the second substrate 510 and the common source line 520 . A plurality of word lines 531 to 538 (530) may be stacked on the second substrate 510 along a direction VD perpendicular to the upper surface of the second substrate 510 . String select lines and a ground select line may be disposed on upper and lower portions of the word lines 530 , and a plurality of word lines 530 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CHS may extend in a direction perpendicular to the upper surface of the second substrate 510 and pass through the word lines 530, the string select lines, and the ground select line. there is. The channel structure CHS may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 550c and the second metal layer 560c. For example, the first metal layer 550c may be a bit line contact, and the second metal layer 560c may be a bit line. In an exemplary embodiment, the bit line 560c may extend along the second horizontal direction HD2 parallel to the upper surface of the second substrate 510 .

In an exemplary embodiment, an area where the channel structure CHS and the bit line 560c are disposed may be defined as a bit line bonding area BLBA. The bit line 560c may be electrically connected to the circuit elements 620c providing the page buffer 593 of the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 560c is connected to the upper bonding metals 571c and 572c of the cell region CELL, and the upper bonding metals 571c and 572c are connected to the circuit elements 620c of the page buffer 593. It may be connected to the connected lower bonding metals 671c and 672c. Accordingly, the page buffer 593 may be connected to the bit line 560c through the bonding metals 571c, 572c, 671c, and 672c.

In one embodiment, the memory device 400 may further include a through electrode THV disposed in the bit line bonding area BLBA. The through electrode THV may pass through the word lines 530 and extend in the vertical direction VD. The through electrode THV may be connected to the common source line 520 and/or the upper substrate 510 . Although not shown, an insulating ring may be disposed around the through electrode THV, and the through electrode THV may be insulated from the word lines 530 . The through electrode THV may be connected to the peripheral circuit area PERI through the upper bonding metal 572d and the lower bonding metal 672d.

In the word line bonding area WLBA, the word lines 530 may extend along the first horizontal direction HD1 parallel to the upper surface of the second substrate 510, and the plurality of cell contact plugs 541 to 541 to 547; 540). The word lines 530 and the cell contact plugs 540 may be connected to each other through pads provided by extending at least some of the word lines 530 with different lengths along the vertical direction VD. A first metal layer 550b and a second metal layer 560b may be sequentially connected to upper portions of the cell contact plugs 540 connected to the word lines 530 . The cell contact plugs 540 are connected to peripheral circuits in the word line bonding area WLBA through the upper bonding metals 571b and 572b of the cell area CELL and the lower bonding metals 671b and 672b of the peripheral circuit area PERI. It may be connected to the area PERI.

The cell contact plugs 540 may be electrically connected to circuit elements 620b providing the row decoder 594 in the peripheral circuit area PERI. In an exemplary embodiment, the operating voltage of circuit elements 620b providing row decoder 594 may be different from the operating voltage of circuit elements 620c providing page buffer 593 . For example, operating voltages of circuit elements 620c providing the page buffer 593 may be higher than operating voltages of circuit elements 620b providing the row decoder 594 .

A common source line contact plug 580 may be disposed in the external pad bonding area PA. The common source line contact plug 580 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 520 . A first metal layer 550a and a second metal layer 560a may be sequentially stacked on the common source line contact plug 580 . For example, an area where the common source line contact plug 580, the first metal layer 550a, and the second metal layer 560a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 505 and 605 may be disposed in the external pad bonding area PA. A lower insulating film 601 covering a lower surface of the first substrate 610 may be formed under the first substrate 610 , and a first input/output pad 605 may be formed on the lower insulating film 601 . The first input/output pad 605 is connected to at least one of the plurality of circuit elements 620a, 620b, and 620c arranged in the peripheral circuit area PERI through the first input/output contact plug 603, and the lower insulating layer 601 ) may be separated from the first substrate 610 by. In addition, a side insulating layer may be disposed between the first input/output contact plug 603 and the first substrate 610 to electrically separate the first input/output contact plug 603 from the first substrate 610 .

An upper insulating layer 501 covering the upper surface of the second substrate 510 may be formed on the second substrate 510, and second input/output pads 505 may be disposed on the upper insulating layer 501. The second input/output pad 505 may be connected to at least one of the plurality of circuit elements 620a, 620b, and 620c arranged in the peripheral circuit area PERI through the second input/output contact plug 503.

According to example embodiments, the second substrate 510 and the common source line 520 may not be disposed in an area where the second input/output contact plug 503 is disposed. Also, the second input/output pad 505 may not overlap the word lines 530 in the third direction (Z-axis direction). The second input/output contact plug 503 is separated from the second substrate 510 in a direction parallel to the upper surface of the second substrate 510, and penetrates the interlayer insulating layer of the cell region CELL to form a second input/output pad 505. ) can be connected to

According to embodiments, the first input/output pad 605 and the second input/output pad 505 may be selectively formed. For example, the memory device 500 includes only the first input/output pad 605 disposed on the first substrate 610 or the second input/output pad 505 disposed on the second substrate 510. ) can only be included. Alternatively, the memory device 500 may include both the first input/output pad 605 and the second input/output pad 505 . The metal pattern of the uppermost metal layer exists in a dummy pattern in each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, respectively. The top metal layer may be empty.

In the memory device 500 , in the external pad bonding area PA, the upper metal pattern ( A lower metal pattern 673a having the same shape as 572a) may be formed. The lower metal pattern 673a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, the lower metal pattern of the peripheral circuit area PERI is formed on the upper metal layer of the cell area CELL corresponding to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area PERI in the external pad bonding area PA. An upper metal pattern having the same shape as above may be formed.

Lower bonding metals 471b and 472b may be formed on the second metal layer 640b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 671b and 672b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 571b and 572b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the lower metal pattern 652 is formed on the uppermost metal layer of the cell region CELL corresponding to the lower metal pattern 652 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 592 of the shape may be formed. A contact may not be formed on the upper metal pattern 592 formed on the uppermost metal layer of the cell region CELL.

25 is a block diagram illustrating an SSD system to which a memory device according to an embodiment of the present disclosure is applied.

Referring to FIG. 25 , an SSD system 1000 may include a host 1100 and an SSD 1200 . The SSD 1200 exchanges signals with the host 1100 through a signal connector and receives power through a power connector. The SSD 1200 may include an SSD controller 1210 , an auxiliary power supply 1220 , and memory devices 1230 , 1240 , and 1250 . The memory devices 1230 , 1240 , and 1250 may be vertically stacked NAND flash memory devices. In this case, the SSD 1200 may be implemented using the embodiments described above with reference to FIGS. 1 to 24 .

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

As a programming method of a non-volatile memory device,
In a first channel initialization period, a first voltage is applied to a first word line group relatively close to the selected word line and subjected to the program operation and to the selected word line, and relatively distant from the selected word line and subjected to the program operation. applying a second voltage lower than the first voltage to a second word line group;
applying a first program voltage to the selected word line in a first program execution period for performing a first program on data;
applying the first voltage to the selected word line and the first word line group and applying the second voltage to the second word line group in a second channel initialization period; and
and applying a second program voltage to the selected word line in a second program execution period for performing a second program on the data. According to claim 1,
The nonvolatile memory device may include a third word line group disposed above a substrate, the selected word line between the third word line group and the first word line group, and the first word line disposed above the selected word line. one word line group, and the second word line group disposed above the first word line group;
The method further comprises performing a first program on an adjacent word line included in the third word line group between the first program execution period and the second channel initialization period. According to claim 2,
The second channel initialization period is after the first program for the adjacent word line;
The method further comprises applying the first voltage to the adjacent word line in the second channel initialization period. According to claim 2,
applying a ground voltage to the first word line group in the first channel initialization period; and
and applying the ground voltage to at least one word line other than the adjacent word line in the first word line group during the second channel initialization period. According to claim 2,
Applying a third voltage lower than the second voltage to the first and second word line groups and the selected word line in a word line setup period between the second channel initialization period and the second program execution period; and applying a fourth voltage less than or equal to the first voltage to the adjacent word line. According to claim 5,
In the word line setup period, a program operation for memory cells connected to the first and second word line groups is completed, and a program operation for memory cells connected to the adjacent word line is not completed. How to. According to claim 1,
a third voltage lower than the first and second voltages on the first and first word line groups and the selected word line in a word line setup period between the first channel initialization period and the first program execution period; A method characterized in that it further comprises the step of applying. According to claim 7,
wherein the third voltage corresponds to a ground voltage. According to claim 1,
A program operation of writing the data into a memory cell connected to the selected word line through the first and second programs is completed;
By the first program, the memory cell is programmed from an erase state to one of N program states;
The second program corresponds to reprogramming of the memory cell;
Wherein N is a positive integer. According to claim 1,
A program operation of writing the data into a memory cell connected to the selected word line through the first and second programs is completed;
By the first program, the memory cell is programmed from an erase state to one of M program states;
The memory cell is programmed from one of the M program states to one of N program states by the second program;
Wherein M and N are positive integers, and N is greater than M. According to claim 1,
The non-volatile memory device may include the second word line group disposed on a substrate, the first word line group disposed on the second word line group, and the first word line group disposed on the first word line group. a selected word line and a third word line group disposed above the selected word line;
The method further comprises performing a first program on an adjacent wood line included in the third word line group between the first program execution period and the second channel initialization period. According to claim 1,
In the first and second channel initialization periods, a precharge voltage is applied to a common source line, a bit line program voltage is applied to a selected bit line, and a bit line program inhibit voltage is applied to an unselected bit line. How to. According to claim 1,
The non-volatile memory device includes a plurality of memory stacks including a first memory stack extending vertically on a substrate and a second memory stack extending vertically from an upper portion of the first memory stack,
When the selected word line and the first and second word line groups are connected to the first memory stack, the same word lines are connected to the second memory stack in the first and second channel initialization periods. voltage is applied,
When the selected word line and the first and second word line groups are connected to the second memory stack, in the first and second channel initialization periods, word lines connected to the first memory stack have the same A method characterized in that a voltage is applied. As a programming method of a non-volatile memory device,
In a first program execution period for performing a first program on first data, a first program operation is performed on the first memory cells connected to the first selected word line by applying a first program voltage to the first selected word line. performing;
performing a first program operation on second memory cells connected to a second selected word line adjacent to the first selected word line;
In a word line setup period after performing the first program operation on the second memory cells, a first bias voltage is applied to the first selected word line, and the first bias voltage is applied to the second selected word line. applying a second bias voltage having a higher voltage level than the voltage; and
performing a second program operation on the first memory cells by applying a second program voltage to the first selected word line in a second program execution period for performing a second program on the first data; How to include. According to claim 14,
The first bias voltage corresponds to a ground voltage,
wherein the second bias voltage corresponds to a voltage level turning on the second memory cells. According to claim 14,
The method of claim 1, further comprising applying the first bias voltage to the first and second selected word lines in a word line setup period prior to the first program execution period. According to claim 14,
A program operation of writing the first data into the first memory cells is completed through the first and second program operations;
By the first program operation, the first memory cells are each programmed from an erase state to one of N program states;
The second program operation corresponds to a reprogram operation of the first memory cells;
Wherein N is a positive integer. According to claim 14,
A program operation of writing the first data into the first memory cells is completed through the first and second program operations;
By the first program operation, the first memory cells are each programmed from an erase state to one of M program states;
By the second program operation, the first memory cells are each programmed from one of the M program states to one of N program states;
Wherein M and N are positive integers, and N is greater than M. As a programming method of a non-volatile memory device,
applying a precharge voltage to a common source line in a channel initialization period;
In a bit line setup period, a program operation is performed and a first voltage is applied to a first word line disposed above a selected word line and a first voltage is applied to the selected word line, and the program operation is completed and disposed above the first word line applying a second voltage lower than the first voltage to a second word line;
applying a third voltage lower than the first and second voltages to the selected word line and the first and second word lines in a word line setup period; and
Executing a program operation on memory cells connected to a selected word line in a program execution section;
The method of claim 1, wherein the channel initialization period and the bit line setup period correspond to substantially the same time period. According to claim 19,
wherein the third voltage corresponds to a ground voltage.

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