KR102608958B1 - Storage device and operating method thereof - Google Patents

Abstract

A storage device and a method of operating the same are disclosed. A storage device according to the present disclosure includes a memory controller and a non-volatile memory device, wherein the non-volatile memory device includes a memory cell array including a plurality of memory cells, a plurality of memory cells for selected memory cells among the plurality of memory cells, and a non-volatile memory device. A page buffer including a plurality of latches that perform a sensing operation and store result values of the plurality of sensing operations, respectively, compare data stored in the plurality of latches, and connect the plurality of latches according to the results of the comparison. Control logic for selecting one latch, transmitting read data stored in the selected latch to the memory controller, and generating a status bit representing the selected latch among a plurality of latches, and the generated status bit and a status bit register for storing and transmitting the status bit to the memory controller when a status read command is received from the memory controller, wherein the memory controller performs ECC (error correction code) decoding for the selected data. may be performed, and if the ECC decoding is successful, it may be characterized as determining whether to change the read voltage based on the status bit.

Description

Storage device and operating method thereof {STORAGE DEVICE AND OPERATING METHOD THEREOF}

The technical idea of the present disclosure relates to a storage device, and more specifically, to a storage device that changes a read voltage and a method of operating the storage device.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phospide (InP). am. Semiconductor memory devices can be largely divided into volatile memory devices and nonvolatile memory devices.

Meanwhile, in response to the demand for higher capacity of semiconductor memory devices, multi-leveling techniques to increase the number of bits stored per cell and scaling techniques to reduce circuit line width are being used to improve integration. However, as the number of bits stored per cell increases, the overlap of the threshold voltage distribution increases, and as the circuit line width decreases, the distance between neighboring memory cells decreases, causing coupling, making it difficult to read data accurately based on the optimal read voltage. may be requested.

The problem to be solved by the technical idea of the present disclosure is to provide a non-volatile memory device and a method of operating the same that predict distribution and movement of the threshold voltage using status bits during OVS read operation.

Another problem that the technical idea of the present disclosure seeks to solve is a non-volatile memory device and operating method thereof that change the read voltage even though ECC decoding is successful based on the distribution movement of the threshold voltage predicted using the status bit. is to provide.

In order to achieve the above object, a storage device according to one aspect of the technical idea of the present disclosure includes a memory controller and a non-volatile memory device, and the non-volatile memory device includes a memory cell including a plurality of memory cells. An array, a page buffer including a plurality of latches that perform a plurality of sensing operations on selected memory cells among the plurality of memory cells and store result values of the plurality of sensing operations, respectively, and data stored in the plurality of latches. compares each, selects one latch among the plurality of latches according to the comparison result, transmits read data stored in the selected latch to the memory controller, and represents the selected latch among the plurality of latches. ) Control logic that generates a status bit, and a status bit register that stores the generated status bit and transmits the status bit to the memory controller when a status read command is received from the memory controller, the memory The controller may perform error correction code (ECC) decoding on the selected data and, if the ECC decoding is successful, determine whether to change the read voltage based on the status bit.

A memory controller device according to one aspect of the technical idea of the present disclosure is an ECC module that performs error correction code (ECC) decoding based on read data received from a non-volatile memory device that performs an OVS (On chip valley search) read operation. and receiving, from the non-volatile memory device, a status bit indicating one latch that latched the read data among a plurality of latches included in the non-volatile memory device and each storing result values of the OVS read operation, When ECC decoding is successful, it may include a read voltage change module that determines whether to change the read voltage based on the status bit.

A method of operating a memory controller according to one aspect of the technical idea of the present disclosure includes read data from a non-volatile memory that performs an OVS read operation, and a status bit indicating one latch to which the read data is output among a plurality of latches. Receiving, performing ECC decoding based on the read data, and, if the ECC decoding is successful, determining whether to change the read voltage based on the status bit. there is.

A non-volatile memory device according to the technical idea of the present disclosure uses a status bit generated through an OVS (on chip valley search) read operation to predict the distribution behavior of the threshold voltage, and to predict the distribution behavior of the threshold voltage before failure of ECC decoding. By preemptively changing the read voltage, it is possible to delay the point at which error correction code (ECC) decoding fails.

Figure 1 is a block diagram showing a storage device according to an exemplary embodiment of the present disclosure.
Figure 2 is a block diagram showing a non-volatile memory device according to an exemplary embodiment of the present disclosure.
FIG. 3 is a waveform diagram showing a change in the level of a sensing node when performing an OVS read operation according to an exemplary embodiment of the present disclosure.
Figure 4 is a circuit diagram showing a memory block included in a memory cell array according to an exemplary embodiment of the present disclosure.
FIG. 5 is a circuit diagram illustrating another example of a memory block included in a memory cell array according to an exemplary embodiment of the present disclosure.
Figure 6 is a perspective view showing the memory block BLK0.
Figure 7 is a flowchart showing a method of operating a storage device according to an exemplary embodiment of the present disclosure.
Figure 8 is a signal exchange diagram between a memory controller and a non-volatile memory device according to an exemplary embodiment of the present disclosure.
Figure 9 is a table showing status bits according to an exemplary embodiment of the present disclosure.
FIG. 10 is a flowchart illustrating a method of operating a storage device performing a first operation mode according to an exemplary embodiment of the present disclosure.
FIG. 11 is a flowchart illustrating a method of operating a storage device performing a second operation mode according to an exemplary embodiment of the present disclosure.
Figure 12 is a table showing changed status bits according to an example embodiment of the present disclosure.
FIG. 13 is a flowchart illustrating a method of operating a storage device that performs a second operation mode based on changed status bits according to an exemplary embodiment of the present disclosure.

1 is a block diagram illustrating a non-volatile memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , the storage device 1 may include a memory controller 20 and a non-volatile memory device 10. In one example, the host (HOST), the memory controller 20, and the non-volatile memory device 10 may each be provided as one chip, one package, one module, etc.

The memory controller 20 may control the non-volatile memory device 10 in response to a write request or read request received from a host (HOST). For example, the memory controller 20 may transmit a command (CMD) and an address (ADDR) to the non-volatile memory device 10 in response to a write request or read request received from the host. The address ADDR that the memory controller 20 transmits to the non-volatile memory device 10 may be a physical address of the non-volatile memory device 10. The memory controller 20 can exchange data (DATA) with the non-volatile memory device 10. In one example, when the command (CMD) is a write command, the non-volatile memory device 10 may write data (DATA) received from the memory controller 20 to the memory cell array 110, and the command (CMD) may be written to the memory cell array 110. ) is the read command (CMD_r), the non-volatile memory device 10 may output the data (DATA) stored in the address (ADDR) received from the memory controller 20 to the memory controller 20.

The non-volatile memory device 10 according to an embodiment of the present disclosure may include a memory cell array 110, a page buffer 120, an on chip valley search (OVS) module 130, and a status bit register 140. You can.

The memory cell array 110 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments will be described in detail by taking the case where a plurality of memory cells are NAND flash memory cells as an example. However, the technical idea of the present disclosure is not limited thereto, and in another embodiment, the plurality of memory cells may be resistive memory cells such as resistive RAM (RRAM), phase change RAM (PRAM), or magnetic RAM (MRAM). .

In an embodiment according to the present disclosure, each memory cell included in the memory cell array 110 can store 2 bits or more of data. For example, the memory cell may be a multi level cell (MLC) that stores 2 bits of data. As another example, the memory cell may be a triple level cell (TLC) that stores 3 bits of data or a quadruple level cell (QLC) that stores 4 bits of data. However, the present disclosure is not limited to this, and in another embodiment, some memory cells included in the memory cell array 110 are single level cells (SLC) that store 1-bit data, and some memory cells are Except for this, the remaining memory cells may be multi-level cells (MLC).

The page buffer 120 may include a write driver and a sense amplifier. During a write operation, the page buffer 120 may transmit a bit line voltage corresponding to data to be written to the bit line of the memory cell array 110. During a read operation or verify operation, the page buffer 120 can detect data stored in the selected memory cell through a bit line. The page buffer 120 may include a plurality of latches each connected to at least one bit line.

The OVS module 130 may perform a plurality of sensing operations to identify one state stored in memory cells. The OVS module 130 may store result values sensed by the plurality of sensing operations in a plurality of latches included in the page buffer 120. The OVS module 130 may output data sensed and latched with a valley voltage among the data stored in each of the plurality of latches as read data by comparing result values sensed by a plurality of sensing operations. This will be described later in Figure 3.

The status bit register 140 can store status bits. The status bit may correspond to bits indicating the status of the non-volatile memory device 10. According to various embodiments, the status bit may be generated by the control logic 100. For example, the status bit may be generated by the OVS module 130 included in the control logic 100. For another example, the status bit may be generated by the status bit register 140 based on the control signal (Info_Sel) of the control logic 100. The status bit may indicate one of the “busy” or “ready” states of the non-volatile memory device 10. For example, while the non-volatile memory device 10 is performing an OVS read operation, the status bit may indicate “busy.” As another example, after the non-volatile memory device 10 completes an OVS read operation, the status bit may indicate “ready.” The “ready” or “busy” may correspond to, for example, “1” or “0” of the status bits transmitted through the DQ6 pin, respectively. According to another embodiment, the status bit may indicate one latch selected to output read data among a plurality of latches. That is, when the non-volatile memory device 10 is in the “ready” state, the status bits may further include bits indicating the result of the completed OVS read operation. Status bits indicating one selected latch may include, for example, bits transmitted through pins DQ0 to DQ3. For example, when data latched in the first latch according to the first sensing operation is output as read data, the status bit register 140 may store a status bit of “1010” indicating the first latch. For another example, when data stored in the second latch is output as read data according to a second sensing operation among a plurality of sensing operations, the status bit register 140 displays a status bit of “0000” indicating the second latch. You can save it. For another example, when data stored in the third latch is output as read data according to a third sensing operation among a plurality of sensing operations, the status bit register 140 contains a status bit of “0101” indicating the third latch. can be saved. According to various embodiments, the status bit register 140 may transmit a status bit to the memory controller 20 in response to receiving a status read command from the memory controller 20 . This will be described later with reference to FIGS. 7 and 8.

The memory controller 20 according to an embodiment of the present disclosure may include an ECC module 210 and a read voltage change module 220.

The ECC module 210 can perform ECC encoding or decoding on input and output data. For example, the ECC module 210 may receive a write command from the host and perform ECC encoding on the write data. For another example, the ECC module 210 may receive read data from the non-volatile memory device 10 and perform ECC decoding. According to one embodiment, when decoding the read data fails, the ECC module 210 may request a read retry from the non-volatile memory device 10. If the ECC module 210 succeeds in decoding the read data, it may output the decoded read data to the host.

The read voltage change module 220 can determine whether to change the read voltage. According to one embodiment, the read voltage change module 220 may determine to change the read voltage based on the status bit. The read voltage change module 220 may use the status bit to identify a latch selected to output read data and may increase or decrease the read voltage based on the identified latch. According to one embodiment, the read voltage change module 220 may determine to change the read voltage when ECC decoding is successful. This will be described later with reference to FIGS. 10 and 11.

Figure 2 is a block diagram showing a non-volatile memory device according to an exemplary embodiment of the present disclosure. Content that overlaps with Figure 1 is omitted.

Referring to FIG. 2, the non-volatile memory device 10 includes a control logic 100, a memory cell array 110, a page buffer 120, a voltage generator 150, a row decoder 160, and an input/output circuit 170. may include.

Control logic 100 may include an OVS module 130 and a status bit register 140. The control logic 100 writes data to the memory cell array 110 or writes data to the memory cell array 110 based on the command (CMD_r) and address (ADDR) received from the memory controller (e.g., the memory controller 20 in FIG. 1). Various control signals for reading data from the array 110 can be output.

The OVS module 130 may perform a plurality of sensing operations on memory cells. The OVS module 130 may store values sensed by a plurality of sensing operations in a plurality of latches included in the page buffer 120, respectively. The plurality of sensing operations may each be performed at different times. According to one embodiment, the plurality of sensing operations may include three sensing operations. For example, data obtained by a first sensing operation performed at a first time point may be stored in a first latch among a plurality of latches. For another example, data obtained by a second sensing operation may be stored in a second latch among a plurality of latches, and the second sensing operation may be performed at a second time later than the first time point. . For another example, data obtained by a third sensing operation may be stored in a third latch among a plurality of latches, and the third sensing operation may be performed at a third time later than the second time point. You can.

According to various embodiments, the OVS module 130 may select one latch from a plurality of latches and output data stored in the selected latch as read data. According to one embodiment, the OVS module 130 may compare data stored in the first latch with data stored in the second latch, and compare data stored in the second latch with data stored in the third latch. Based on the comparison, the OVS module 130 may select one latch that stores the read data according to the optimal read voltage. This will be described later in Figure 3.

The page buffer 120 may include a plurality of latches. Each of the plurality of latches may store the results of a sensing operation performed at different times. According to one embodiment of the present invention, a plurality of latches may receive a control signal (Info_Sel) from the OVS module 130, and output data stored in the latch indicated by the control signal as read data. Each of the plurality of latches may select or output optimal data from a plurality of sensed data under the control of the control logic 100.

The voltage generator 150 may generate various types of voltages to perform write, read, and erase operations on the memory cell array 110 based on the voltage control signal (Ctrl_vol). Specifically, the voltage generator 150 generates a word line voltage (VWL), such as a program voltage (or write voltage), a read voltage, a pass voltage (or a word line non-select voltage), a verification voltage, or a recovery voltage, etc. can do.

The row decoder 160 may select some of the word lines WL in response to the row address X-ADDR. The row decoder 160 transfers the word line voltage to the word line. During a program operation, the row decoder 160 may apply a program voltage and a verification voltage to a selected word line and a program inhibit voltage to an unselected word line. During a read operation, the row decoder 160 may apply a read voltage to a selected word line and a read inhibit voltage to an unselected word line. During a recovery operation, the row decoder 160 may apply a recovery voltage to the selected word line. Additionally, the row decoder 160 may select some string selection lines among the string selection lines or some ground selection lines among the ground selection lines in response to the row address (X-ADDR).

The input/output circuit 170 receives data from an external source (eg, the memory controller 20 of FIG. 2) and stores the input data in the memory cell array 140. Additionally, the input/output circuit 170 may read data from the memory cell array 110 and output the read data to the outside.

FIG. 3 is a waveform diagram showing a change in the level of a sensing node when performing an OVS read operation according to an exemplary embodiment of the present disclosure.

Although FIG. 3 describes performing three sensing operations, it is not limited thereto. Referring to FIG. 3, the time from TO to T1 may be referred to as a precharge period (Precharge), the time from T1 to T2 may be referred to as a development period, and the time after T2 may be referred to as a latch period (Latch).

In the precharge period, the bit line voltage may be charged to the first voltage level (V1), and the sensing node may be charged to the sensing node voltage (VSO). At T1, when the development period (Develop) begins, the charge charged in the sensing node can move to the bit line. In the case of a strong off cell where the threshold voltage is relatively higher than the lead voltage, the level change of the sensing node may be relatively small. The change in the potential of the sensing node of a strong off-cell in the development section is shown as a dotted line (C0).

In the case of a strong on cell where the threshold voltage is relatively lower than the lead voltage, the level change of the sensing node may be relatively large. The change in voltage level of the sensing node of a strong on-cell in the development section is shown as the first curve C1. In the case of strong off-cell or strong on-cell, small changes in development time may not be greatly affected. Changes in potential of a sensing node that senses memory cells whose threshold voltage is located around the read voltage are shown as second to fourth curves C2, C3, and C4, respectively. The second curve C2 shows the development trend of memory cells with a threshold voltage slightly lower than the read voltage, and the third curve C3 shows the development trend of memory cells with a threshold voltage almost similar to the read voltage. , and the fourth curve C4 can show the development tendency of a memory cell with a threshold voltage slightly higher than the read voltage.

According to multi-sensing, a first latch signal LTCH_1 may be provided to latch the sensing nodes of memory cells by pulling the latch point a predetermined time point early based on time point T2. When the sensing node is latched by the first latch signal (LTCH_1), in the case of strong off-cell (C0) and strong on-cell (C1), latches may be set to logical values corresponding to the off-cell and on-cell, respectively. However, memory cells corresponding to the second curve C2, which has a relatively low threshold voltage, can be latched with a logic value corresponding to an on-cell. On the other hand, memory cells corresponding to the third and fourth curves C3 and C4 may be latched to a logical value corresponding to an off-cell by the first latch signal LTCH_1.

When the sensing node is latched by the second latch signal (LTCH_2), in the case of strong off-cell (CO) and strong on-cell (C1), logic '0' and logic '1', respectively, as in the first latch signal (LTCH_1). This can be latched. However, memory cells having a threshold voltage corresponding to the second curve C2 may be latched with a logic value corresponding to an on-cell. On the other hand, in the case of the memory cell corresponding to the third curve C3, the trap level V2, where logic '0' and logic '1' are unclear, may be latched by the second latch signal LTCH_2. Memory cells corresponding to the fourth curve C4 may be latched to a logical value corresponding to an off-cell by the second latch signal LTCH_2.

When the sensing node is latched by the third latch signal (LTCH_3), in the case of strong off-cell (C0) and strong on-cell (C1), logic '0' and logic '1', respectively, as in the first latch signal (LTCH_1). This can be latched. However, all memory cells having threshold voltages corresponding to the second and third curves C2 and C3 may be latched with the logic value '1' corresponding to the on-cell. Additionally, in the case of the memory cell corresponding to the fourth curve C4, the memory cell may be latched to a logic value of '0' corresponding to the off-cell by the third latch signal LTCH_3.

As in the above-described method, in order to identify a state, the state of the sensing node is latched with a logic value at different development times, so that read voltages of different levels are substantially applied to the word line depending on the development time. A similar effect may be provided.

Figure 4 is a circuit diagram showing a memory block included in a memory cell array according to an exemplary embodiment of the present disclosure.

Referring to FIG. 4 , a memory cell array (eg, 140 in FIG. 2 ) may be a memory cell array of horizontal NAND flash memory and may include a plurality of memory blocks. Each memory block BLKa may include n (n is an integer of 2 or more) cell strings (STR) in which a plurality of memory cells (MC) are connected in series in the direction of the bit lines (BL0 to BLn-1). . As an example, FIG. 4 shows an example in which each cell string (STR) includes 8 memory cells.

In a NAND flash memory device having the structure shown in FIG. 4, erase is performed on a block basis and programming is performed on a page basis corresponding to each word line (WL0 to WL7). Figure 4 shows an example in which n pages for n word lines (WL1 to WLn) are provided in one block. Additionally, the non-volatile memory device 10 of FIGS. 1 and 2 may include a plurality of memory cell arrays that have the same structure and perform the same operation as the memory cell array 140 described above.

FIG. 5 is a circuit diagram illustrating another example of a memory block included in a memory cell array according to an exemplary embodiment of the present disclosure.

Referring to FIG. 5 , a memory cell array (eg, 140 in FIG. 2 ) may be a memory cell array of vertical NAND flash memory and may include a plurality of memory blocks. Each memory block (BLK0) includes a plurality of NAND cell strings (NS11 to NS33), a plurality of word lines (WL1 to WL8), a plurality of bit lines (BL1 to BL3), and a plurality of ground selection lines (GSL1 to GSL1). GSL3), a plurality of cell string selection lines (SSL1 to SSL3), and a common source line (CSL). Here, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of cell string selection lines may vary depending on the embodiment.

NAND cell strings (NS11, NS21, NS31) are provided between the first bit line (BL1) and the common source line (CSL), and NAND cell strings are provided between the second bit line (BL2) and the common source line (CSL). NAND cell strings (NS12, NS22, and NS32) are provided, and NAND cell strings (NS13, NS23, and NS33) are provided between the third bit line (BL3) and the common source line (CSL). Each NAND cell string (eg, NS11) may include a cell string select transistor (SST), a plurality of memory cells (MC1 to MC8), and a ground select transistor (GST) connected in series.

Cell strings commonly connected to one bit line constitute one column. For example, the cell strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 correspond to the first column, and the cell strings NS12 and NS31 commonly connected to the second bit line BL2. NS22, NS32) may correspond to the second column, and cell strings (NS13, NS23, NS33) commonly connected to the third bit line (BL3) may correspond to the third column.

Cell strings connected to one cell string selection line constitute one row. For example, the cell strings NS11, NS12, and NS13 connected to the first cell string selection line (SSL1) correspond to the first row, and the cell strings NS21 and NS21 connected to the second cell string selection line (SSL2). NS22, NS23) may correspond to the second row, and cell strings (NS31, NS32, NS33) connected to the third cell string selection line (SSL3) may correspond to the third row.

The cell string selection transistor (SST) is connected to the corresponding cell string selection line (SSL1 to SSL3). A plurality of memory cells (MC1 to MC8) are respectively connected to corresponding word lines (WL1 to WL8). The ground select transistor (GST) is connected to the corresponding ground select line (GSL1 to GSL3). The cell string select transistor (SST) is connected to the corresponding bit lines (BL1 to BL3), and the ground select transistor (GST) is connected to the common source line (CSL).

Word lines (e.g., WL1) of the same height are commonly connected to each other, cell string selection lines (SSL1 to SSL3) are separated from each other, and ground selection lines (GSL1 to GSL3) are also separated from each other. . For example, when programming memory cells connected to the first word line (WL1) and belonging to cell strings (NS11, NS12, and NS13), the first word line (WL1) and the first cell string selection line ( SSL1) is selected. The ground selection lines (GSL1 to GSL3) may be commonly connected to each other.

Figure 6 is a perspective view showing the memory block BLK0.

Referring to FIG. 6 , each memory block included in the memory cell array (eg, 140 in FIG. 2 ) is formed in a vertical direction with respect to the substrate SUB. In Figure 5, the memory block is shown as including two select lines (GSL, SSL), eight word lines (WL1 to WL8), and three bit lines (BL1 to BL3), but in reality, There may be more or less than these.

The substrate SUB has a first conductivity type (e.g., p type), extends along the first direction (e.g., Y direction) on the substrate SUB, and has a second conductivity type (e.g., p type). , a common source line (CSL) doped with n-type impurities is provided. On the area of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating films IL extending along the first direction are sequentially provided along the third direction (eg, Z direction). The plurality of insulating films IL are spaced apart from each other by a specific distance along the third direction. For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

A plurality of pillars are sequentially arranged along the first direction on the area of the substrate SUB between the two adjacent common source lines CSL and penetrate the plurality of insulating films IL along the third direction pillars (P) are provided. For example, the plurality of pillars P may penetrate the plurality of insulating films IL and contact the substrate SUB. Specifically, the surface layer (S) of each pillar (P) may include a silicon material of the first type and may function as a channel region. Meanwhile, the inner layer (I) of each pillar (P) may include an insulating material such as silicon oxide or an air gap.

In the area between two adjacent common source lines (CSL), a charge storage layer (CS) is provided along the exposed surfaces of the insulating films (IL), pillars (P), and substrate (SUB). The charge storage layer (CS) may include a gate insulating layer (also referred to as a 'tunneling insulating layer'), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer (CS) may have an oxide-nitride-oxide (ONO) structure. Additionally, in the area between two adjacent common source lines (CSL), gate electrodes such as select lines (GSL, SSL) and word lines (WL1 to WL8) are formed on the exposed surface of the charge storage layer (CS). (GE) is provided.

Drains or drain contacts DR are provided on the plurality of pillars P, respectively. For example, the drains or drain contacts DR may include a silicon material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 are provided on the drains DR, extending in a second direction (eg, X direction) and spaced apart by a specific distance along the first direction.

Figure 7 is a flowchart showing a method of operating a storage device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7 , the non-volatile memory device 10 included in the storage device 1 may receive a read command in operation S110. For example, the memory controller 20 may receive a read request from a host connected to the storage device 1 and, in response to the received read request, transmit a read command (CMD_r) to the non-volatile memory device 10. there is.

In operation S120, the non-volatile memory device 10 may perform a plurality of sensing operations and store the resulting values in a plurality of latches. According to various embodiments, the non-volatile memory device 10 may perform the plurality of sensing operations based on the OVS module 130 in response to receiving the read command.

In operation S130, the non-volatile memory device 10 of the storage device 1 selects one latch among a plurality of latches according to a comparison result of the result values, and outputs the data stored in the selected latch as read data. there is. The non-volatile memory device 10 may compare data values stored in each of the latches and select data stored in one of the plurality of latches according to the comparison result.

In operation S140, the non-volatile memory device 10 of the storage device 1 may receive a status read command and transmit a status bit to the memory controller 20. The status read command may correspond to a command for the memory controller 20 to request information to identify the state of the non-volatile memory device 10. For example, when the non-volatile memory device 10 receives the status read command while performing an OVS read operation, the non-volatile memory device 10 may transmit a status bit indicating “busy” to the memory controller 20. For another example, when the non-volatile memory device 10 completes the OVS read operation and receives the status read command, it may transmit a status bit indicating “ready” to the memory controller 20. When the non-volatile memory device 10 is in a “ready” state, the status bit may further include bits indicating one latch selected to output read data among the plurality of latches.

In operation S150, the memory controller 20 of the storage device 1 may perform ECC decoding on the read data. The memory controller 20 may receive the read data and perform the ECC decoding based on the ECC module 210. For a detailed description of ECC decoding, please refer to the description of the ECC module 210 in FIG. 1.

In operation S160, if ECC decoding is successful, the memory controller 20 of the storage device 1 may determine whether to change the read voltage based on the status bit. If ECC decoding is successful, the memory controller 20 may output the decoded read data to the host. In an embodiment according to the present disclosure, the memory controller 20 identifies the latch selected to output read data and determines whether to change the read voltage, based on the status bits received from the non-volatile memory device 10. You can. This will be described later with reference to FIGS. 10 and 11.

Figure 8 is a signal exchange diagram between a memory controller and a non-volatile memory device according to an exemplary embodiment of the present disclosure. Description of content overlapping with FIG. 7 may be omitted.

Referring to FIG. 8, when the memory controller 20 transmits a read command to the non-volatile memory device 10 (operation S201), the non-volatile memory device 10 responds to the read command and performs an OVS read ( Operation S202) can be performed. According to various embodiments, the non-volatile memory device 10 may correspond to one of a busy state or a ready state. For example, the non-volatile memory device 10 may correspond to the “busy” state while performing an OVS read operation. The “busy” state may refer to a period in which data is latched into the page buffer 120 while the non-volatile memory device 10 performs the OVS read operation. For another example, the non-volatile memory device 10 may be in a “ready” state when the OVS read operation is completed. The “ready” state may refer to a section in which the OVS read operation is completed and data is not latched into the page buffer 120.

The memory controller 20 may transmit a status read command to the non-volatile memory device 10 (operation S203). The status read command may correspond to a command requesting information for identifying the status of the non-volatile memory device 10. The status read command may be referred to as CMD_70. The status read command may be periodically transmitted to the non-volatile memory device 10 when a certain period of time elapses from the time the read command is transmitted. According to one embodiment, the status read command may be transmitted from the memory controller 20 to the non-volatile memory device 10 every 1us cycle. However, the technical idea of the present disclosure is not limited thereto, and the status read command may be transmitted to the non-volatile memory device 10 at a cycle different from the 1us cycle. For example, in the case of the storage device 1 that operates based on a high-speed clock, the status read command may be transmitted in a period shorter than a 1us period. For another example, in the case of a storage device that operates based on a low-speed clock, the status read command may be transmitted every cycle longer than a 1us cycle.

In response to receiving the status read command, the non-volatile memory device 10 may transmit a status bit to the memory controller 20 (operation S204). The status bit may include bits to indicate the status of the non-volatile memory device 10. The status bit may be transmitted through at least one pin among pins DQ0 to DQ7. For example, when the non-volatile memory device 10 is in a “busy” state, the non-volatile memory device 10 may transmit a bit of “1” through the DQ6 pin. For another example, when the non-volatile memory device 10 is in a “ready” state, the non-volatile memory device 10 may transmit a “0” bit through the DQ6 pin. Referring to FIG. 8, while performing an OVS operation, the non-volatile memory device 10 may receive two status read commands and transmit a bit of “1” through the DQ6 pin. The memory controller 20 can identify that the non-volatile memory is performing an OVS read operation through the status bit of “1” received through the DQ6 pin. According to various embodiments, the non-volatile memory device 10 may transmit the status read command again (operation S205). When the non-volatile memory device 10 is performing the OVS read operation, the non-volatile memory device 10 may repeatedly transmit a status bit indicating that it is still in a “busy” state (S206).

The non-volatile memory device 10 may complete the OVS read operation and transmit read data to the memory controller 20 (operation S207). The read data may correspond to one piece of data selected through a comparison operation of data respectively stored in a plurality of latches through a plurality of sensing operations.

After the OVS read operation is completed, the non-volatile memory device 10 may receive a status read command (operation S208) and transmit a status bit in response to the status read command (operation S209). According to various embodiments, when the non-volatile memory device 10 performing an OVS read operation is in a “ready” state, the status bits may further include bits transmitted through pins DQ0 to DQ3. That is, when the non-volatile memory device 10 transmits a status bit after completing an OVS operation, it can indicate the result of the OVS operation by transmitting the status bit. According to one embodiment, Figure 9 shows an example of status bits transmitted through pins DQ0 to DQ3. For example, when the non-volatile memory device 10 is in the first state, the transmitted status bit may be “1010”. The first state may refer to a state in which data stored in the first latch is output to the memory controller 20 as read data through a first sensing operation. For another example, when the non-volatile memory device 10 is in the second state, the transmitted status bit may be “0000”. The second state may refer to a state in which data stored in the second latch is output to the memory controller 20 as read data through a second sensing operation. For another example, when the non-volatile memory device 10 is in the third state, the transmitted status bit may be “0101”. The third state may refer to a state in which data stored in the third latch is output to the memory controller 20 as read data through a third sensing operation. According to various embodiments, the memory controller 20 analyzes the status bits transmitted through the DQ0 pin to the DQ3 pin, so that the read data received by the memory controller 20 is the first latch, the second latch, or the third latch. It is possible to identify which of the latches the data is output from.

The memory controller 20 may perform ECC decoding and determine ECC PASS (operation S210). The memory controller 20 may perform ECC decoding based on read data received from the non-volatile memory device 10. Although not shown in FIG. 8, when ECC decoding fails, the non-volatile memory device 10 is instructed to retry a read, and the read data can be received by changing the read voltage.

If the ECC decoding of the read data is successful, the memory controller 20 may determine whether the read voltage has changed (operation S211). The memory controller 20 performs ECC decoding of the received read data, and if the decoding is successful, the received read data is error-free or corrected data, and may instruct the host to output it. Simultaneously, the memory controller 20 may determine whether to change the read voltage based on the status bit received from the non-volatile memory device 10 before performing ECC decoding. The status bit may correspond to bits transmitted through pins DQ0 to DQ3. The memory controller 20 may refer to the status bit to identify which of the first to third latches the read data was output from. The memory controller 20 can predict the distribution and movement of the threshold voltage by identifying the latch that outputs the read data and determine whether the read voltage will change. This will be described later with reference to FIGS. 10 and 11. In various embodiments, when the memory controller 20 determines to change the read voltage, it may transmit a control signal to the non-volatile memory device 10 (operation S212), and the non-volatile memory device 10 may In response to a control signal, the read voltage may be changed (operation S213).

FIG. 10 is a flowchart illustrating a method of operating a storage device performing a first operation mode according to an exemplary embodiment of the present disclosure. In detail, FIG. 10 is a flowchart showing a specific operation method of operation S160 for determining whether to change the read voltage based on the status bit when the ECC decoding of FIG. 7 is successful.

Referring to FIG. 10 , the memory controller 20 may operate in the first operation mode in operation S301. According to one embodiment, the memory controller 20 may operate based on one of the first operation mode and the second operation mode. For example, the first operation mode may refer to an operation mode that only determines whether to reduce or maintain the read voltage based on the status bit. The second operation mode will be described in detail later in FIG. 11 below.

The memory controller 20 may determine to operate in the first mode by referring to a setting value associated with the operation mode. According to one embodiment, the setting value may be preset to operate in the first mode, or may be changed by the user. According to another embodiment, the setting value may be set to periodically switch between the first operation mode and the second operation mode. According to another embodiment, the set value operates in the first operation mode when the amount of overload or overhead of the memory controller 20 is large or exceeds a preset value, and the memory controller 20 ) may be adaptively changed to operate in the second operation mode when the load or overhead is small or less than the preset value.

In operation S302, the memory controller 20 may identify the state of the non-volatile memory device 10 based on the status bit. The status bit may be transmitted from the non-volatile memory device 10 in response to a status read command that is periodically transmitted after the memory controller 20 transmits the read command. For example, the memory controller 20 may transmit the status read command to the non-volatile memory device 10 after the non-volatile memory device 10 completes the OVS read operation. The non-volatile memory device 10 may identify that the OVS read operation has been completed and transmit a bit of “0” to the DQ6 pin in response to the status read command. Additionally, the non-volatile memory device 10 may further transmit a status bit to indicate the result of the OVS read operation through the DQ0 pin to the DQ3 pin.

In operation S303, the memory controller 20 may determine whether the state of the non-volatile memory device 10 corresponds to the first state. When operating in the first operation mode, the memory controller 20 can check whether the status bits of pins DQ0 to DQ3 are “1010”. For example, the memory controller 20 may perform an If the value of the status bit is equal to “1010,” the memory controller 20 may identify that the data stored in the first latch through the first sensing operation was output as read data. Additionally, the memory controller 20 may identify that the number of cells activated using the first latch is less than the number of cells activated using the second latch and the third latch. Hereinafter, a cell activated using an arbitrary latch may be referred to as an on-cell.

In operation S304, the memory controller 20 may reduce the read voltage by a predetermined offset size. For example, the predetermined offset size may correspond to 0.1V. In the above-described embodiments, the offset size is described as 0.1V, but is not limited thereto. According to various embodiments, the offset size may be set to have a value different from 0.1V. For example, in the case of SLC (single level cell)-based non-volatile memory, since the interval between read voltages for each program is large, the offset size may be set to be greater than 0.1V. For another example, in the case of a non-volatile memory based on a quad level cell (QLC), the interval between read voltages for each program is not large, so the offset size may be set to a value smaller than 0.1V.

In operation S305, the memory controller 20 may maintain the read voltage. If the value of the status bit does not match “1010,” the memory controller 20 may bypass the change in the read voltage. If the status bit value is not “1010,” the memory controller 20 may identify that read data is output from the second or third latch rather than the first latch. When read data is not output from the first latch, the memory controller 20 does not need to reduce the read voltage, so it can maintain the read voltage and end the procedure.

According to the embodiment described above in Figure 10, the memory controller 20 can only determine whether to reduce or maintain the read voltage because it only identifies whether the non-volatile memory corresponds to the first state based on the status bit. there is. According to various embodiments, not only may the threshold voltage value be lowered for reasons such as retention, but the threshold voltage value may also be increased. Accordingly, the memory controller 20 may be required to increase the read voltage based on the status bits of the non-volatile memory device 10.

FIG. 11 is a flowchart illustrating a method of operating a storage device performing a second operation mode according to an exemplary embodiment of the present disclosure. More specifically, FIG. 11 is a flowchart showing a specific operation method of operation S160 for determining whether to change the read voltage based on the status bit when the ECC decoding of FIG. 7 is successful.

Referring to FIG. 11 , in operation S401, the memory controller 20 may operate in a second operation mode. The second operation mode may refer to an operation mode that determines whether to decrease or increase the read voltage based on the status bit. That is, when operating in the second operation mode, the memory controller 20 can determine whether to reduce the read voltage, maintain the read voltage, or increase the read voltage.

In operation S402, the memory controller 20 may identify the state of the non-volatile memory device 10 based on the status bit. Operation S402 may correspond to operation S302 of FIG. 10 . .

In operation S403, the memory controller 20 may determine whether the state of the non-volatile memory device 10 is in the second state. According to various embodiments, while the memory controller 20 operates in the second operation mode, it may be checked whether the status bits of pins DQ0 to DQ3 are “000”. For example, the memory controller 20 may perform an If the value of the status bit is equal to “000”, the memory controller 20 may identify that the data stored in the second latch through the second sensing operation has been output as read data. Additionally, the memory controller 20 may identify that the number of on-cells using the second latch is less than the number of on-cells using the first latch and the third latch.

In operation S404, the memory controller 20 may maintain the read voltage. When the state of the non-volatile memory device 10 is the second state, the read data may correspond to data output from the second latch. If the preset read voltage corresponds to a valley on the threshold voltage distribution graph, the data stored in the second latch may be output as the read data. Accordingly, the memory controller 20 can identify that the preset read voltage is the optimal read voltage and bypass the change in read voltage.

In operation S405, the memory controller 20 may determine whether the state of the non-volatile memory device 10 is the first state. For example, the memory controller 20 may perform an XOR operation of the received status bit and “1010” to determine whether it corresponds to the first state.

In operation S406, the memory controller 20 may obtain activated cell-count information using the first latch. When the status bit indicates the first state, the memory controller 20 may determine that a voltage lower than a preset read voltage is the optimal read voltage. However, even though ECC decoding is successful, if the read voltage is changed every time the status bit indicates the first state, the performance of the read operation may be degraded. Accordingly, the memory controller 20 may transmit a command to the non-volatile memory device 10 to request information about the number of activated memory cells using the first latch. The command may be referred to as a universal internal bus (UIB) OUT command. The memory controller 20 may obtain information about the number of activated memory cells using the first latch transmitted in response to the command from the non-volatile memory device 10.

In operation S407, the memory controller 20 may determine whether the number of on-cells exceeds the threshold. The threshold may be predetermined to be any appropriate value, taking into account the deterioration of read performance due to frequent changes in read voltage and the improvement of read performance through maintaining an optimal read voltage.

In operation S408, the memory controller 20 may reduce the read voltage by a predetermined offset size. When the number of on-cells exceeds the threshold, the memory controller 20 determines to reduce the read voltage in advance because the read data is close to the limit of ECC error correction even though ECC decoding was successful. You can. As described above, the predetermined offset size may correspond to 0.1V, but is not limited thereto.

In operation S409, the memory controller 20 may identify that the state of the non-volatile memory device 10 corresponds to the third state. The memory controller 20 performs operations S403 and S405 to determine whether the status bit indicates the third state since the non-volatile memory device 10 has identified that it does not correspond to the first state and the second state. The XOR operation can be omitted.

In operation S410, the memory controller 20 may obtain on-cell count information using the third latch. When the status bit indicates the third state, the memory controller 20 may determine that a voltage higher than the set read voltage is the optimal read voltage. However, even though ECC decoding is successful, if the read voltage is changed every time the status bit indicates the third state, the performance of the read operation may be degraded. Accordingly, the memory controller 20 may transmit a command to the non-volatile memory device 10 to request information about the number of on-cells using the third latch and obtain information about the number of cells. The command may be referred to as the UIB OUT command.

In operation S411, the memory controller 20 may determine whether the number of on-cells exceeds the threshold. The threshold may be predetermined to be any appropriate value, taking into account the deterioration of read performance due to frequent changes in read voltage and the improvement of read performance through maintaining an optimal read voltage.

In operation S412, the memory controller 20 may increase the read voltage by a predetermined offset size. The description of operation S412 may be replaced with the description of operation S408.

According to the embodiment described above in FIG. 11, when the memory controller 20 identifies that the non-volatile memory device 10 corresponds to the first state or the third state based on the status bit, the non-volatile memory device ( 10) may be configured to transmit a command requesting information about the number of activated memory cells.

However, each time a read operation is performed, the memory controller 20 and the non-volatile memory device (20) transmit a command to determine whether to change the read voltage and receive information about the number of activated memory cells. In 10), it may act as overhead. Therefore, in order to reduce overhead, a method of omitting the command for the number of activated memory cells may be required.

Figure 12 is a table showing changed status bits according to an example embodiment of the present disclosure.

As described above in FIG. 9, a status bit for indicating one latch selected to output read data among a plurality of latches is transmitted from the non-volatile memory device 10 to the memory controller 20 through the DQ0 pin to the DQ3 pin. can be sent to Hereinafter, the bit transmitted through the DQ0 pin is referred to as the first bit, the bit transmitted through the DQ1 pin is referred to as the second bit, the bit transmitted through the DQ2 pin is referred to as the third bit, and the bit transmitted through the DQ3 pin is referred to as the fourth bit. It can be.

Referring to FIG. 12, the state of the non-volatile memory device 10 may be indicated by a combination of the first bit and the second bit. For example, the first state of the non-volatile memory device 10 may be indicated through the first and second bits of “10”. For another example, the second state of the non-volatile memory device 10 may be indicated through the first and second bits of “00”. As another example, the third state of the non-volatile memory device 10 may be indicated through the first and second bits of “01”. However, the logical values of the first bit and the second bit indicating each state are not limited thereto.

Referring to FIG. 12, the third bit may correspond to a bit for indicating whether the read voltage decreases when the non-volatile memory device 10 is in the first state. According to various embodiments, the third bit may correspond to a bit representing the result of comparing the number of on-cells using the first latch and a threshold value. For example, when the third bit has a logical value of “0”, it may indicate that the threshold value exceeds the number of on-cells using the first latch. For another example, when the third bit has a logical value of “1”, it may indicate that the number of on-cells using the first latch exceeds the threshold.

Referring to FIG. 12, the fourth bit may correspond to a bit for indicating whether the read voltage increases when the non-volatile memory device 10 is in the third state. According to various embodiments, the fourth bit may correspond to a bit representing the result of comparing the number of on-cells using the third latch and a threshold value. For example, when the fourth bit has a logical value of “0”, it may indicate that the threshold value exceeds the number of on-cells using the third latch. For another example, when the fourth bit has a logical value of “1”, it may indicate that the number of on-cells using the third latch exceeds the threshold.

In the above-described embodiment, the state of the non-volatile memory device 10 is indicated through a combination of the first bit and the second bit, and when the non-volatile memory device 10 is in the first state through the third bit, the read voltage It is described as indicating whether to decrease and whether to increase the read voltage when the non-volatile memory device 10 is in the third state through the fourth bit, but is not limited thereto. In various embodiments, the non-volatile memory device 10 may not use the first bit and the second bit and may set them as reserved bits. In this case, the non-volatile memory device 10 may simultaneously indicate a decrease in the first state and read voltage of the non-volatile memory device 10 by setting the third bit to “1” and the fourth bit. By setting to "1", the third state of the non-volatile memory device 10 and an increase in the read voltage may be simultaneously indicated.

FIG. 13 is a flowchart illustrating a method of operating a storage device that performs a second operation mode based on changed status bits according to an exemplary embodiment of the present disclosure. Description of content overlapping with FIG. 11 may be omitted.

In operation S501, the memory controller 20 may be in a second operation mode. The memory controller 20 may operate in the second operation mode by referring to the setting value for the operation mode. Operation S501 may correspond to operation S401 of FIG. 11 .

In operation S502, the memory controller 20 may identify the state of the non-volatile memory device 10 based on the status bit. The status bit may correspond to the changed status bit in FIG. 12. For example, when receiving a changed status bit, the memory controller 20 may identify the state of the non-volatile memory device 10 by referring to the first bit and the second bit.

In operation S503, the memory controller 20 may determine whether the state of the non-volatile memory device 10 is the second state. For example, when the memory controller 20 receives the changed state bit, the non-volatile memory device 10 changes to the second state by performing an can be identified.

In operation S504, the memory controller 20 may maintain the read voltage. When the first bit and the second bit have a logical value of “00”, the memory controller 20 may correspond to the second state and read data with a preset read voltage. , Since the number of activated memory cells is the smallest, the preset read voltage can be determined as the optimal read voltage. Accordingly, the memory controller 20 can maintain the read voltage and bypass changes in the read voltage.

In operation S505, the memory controller 20 may determine whether the state of the non-volatile memory device 10 corresponds to the first state. For example, when receiving the changed state bit, the memory controller 20 can identify that the non-volatile memory is in the first state by performing an XOR operation on the first bit and the second bit with the logical value of “10”. there is.

In operation S506, the memory controller 20 may determine whether the status bit transmitted through the DQ2 pin is “1”. After identifying that the state of the non-volatile memory device 10 corresponds to the first state, the memory controller 20 sets the logical value of the bit transmitted through the DQ2 pin to determine whether to reduce the read voltage. can be identified. According to various embodiments, the memory controller 20 receives the changed status bit and checks the status bit value transmitted through the DQ2 pin, thereby providing information about the number of memory cells activated using the first latch. Transmission of the requested command can be bypassed. This is because the status bit of the DQ2 pin of the changed status bit directly indicates the result of comparing the number of memory cells activated using the first latch and the threshold value. Accordingly, when using the changed status bit, the memory controller 20 may not transmit the UIB OUT command to the non-volatile memory device 10, and may change the number of memory cells activated using the first latch and the threshold value. By omitting the comparison operation, overhead due to signaling between the memory controller 20 and the non-volatile memory device 10 can be reduced.

In operation S507, the memory controller 20 may reduce the read voltage by a predetermined offset size. The memory controller 20 may determine to decrease the read voltage when the bit transmitted through the DQ2 pin has a logic value of “1”. A bit of “1” transmitted through the DQ2 pin may indicate that the number of memory cells activated using the first latch exceeds the threshold. Accordingly, the memory controller 20 can reduce the number of memory cells activated using the first latch to below the threshold value by setting the voltage dropped by the predetermined offset size as the read voltage.

In operation S508, the memory controller 20 may identify that the state of the non-volatile memory device 10 corresponds to the third state. A detailed description of operation S508 can be explained with reference to the description of operation S409 in FIG. 11 .

In operation S509, the memory controller 20 may determine whether the status bit transmitted through the DQ3 pin is “1”. After identifying that the state of the non-volatile memory device 10 corresponds to the third state, the memory controller 20 sets the logical value of the bit transmitted through the DQ3 pin to determine whether to increase the read voltage. can be identified. According to various embodiments, the memory controller 20 receives the changed status bit and checks the status bit value transmitted through the DQ3 pin, thereby providing information about the number of memory cells activated using the third latch. Transmission of the requested command can be bypassed. This is because the status bit of the DQ3 pin of the changed status bit directly indicates the result of comparing the number of memory cells activated using the third latch and the threshold value. Therefore, when using the changed status bit, the memory controller 20 may not transmit the UIB OUT command to the non-volatile memory device 10, and the number of activated memory cells and the threshold value may be set using the third latch. By omitting the comparison operation, overhead due to signaling between the memory controller 20 and the non-volatile memory device 10 can be reduced.

In operation S510, the memory controller 20 may increase the read voltage by a predetermined offset size. A detailed description of operation S510 can be explained with reference to the description of operation S412 in FIG. 11 .

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

Claims (10)

memory controller; and
Includes a non-volatile memory device,
The non-volatile memory device,
a memory cell array including a plurality of memory cells;
a page buffer including a plurality of latches that perform a plurality of sensing operations on memory cells selected from among the plurality of memory cells and store result values of the plurality of sensing operations, respectively;
Data stored in the plurality of latches are compared, one latch of the plurality of latches is selected according to the comparison result, read data stored in the selected latch is transmitted to the memory controller, and the plurality of latches Control logic that generates a status bit representing the selected latch; and
a status bit register that stores the generated status bit and transmits the status bit to the memory controller when a status read command is received from the memory controller;
The memory controller is,
Perform ECC (error correction code) decoding on the selected data,
When the ECC decoding is successful and the status bit indicates the first state in which the read data is output from the first latch among the plurality of latches, the number and threshold value of cells activated using the first latch Compare and, if the number of cells activated using the first latch is greater than the threshold, reduce the read voltage by a predefined offset size,
When the ECC decoding is successful and the status bit indicates a third state in which the read data is output from a third latch among the plurality of latches, the number and threshold value of cells activated using the third latch and, if the number of cells activated using the third latch is greater than the threshold, increasing the read voltage by a predefined offset size.
According to paragraph 1,
The memory controller is,
A storage device operating in one of a first operation mode that determines whether to decrease or maintain the read voltage and a second operation mode that determines whether to decrease, maintain, or increase the read voltage.
According to paragraph 2,
The memory controller is,
While operating in the first mode of operation, identify that the non-volatile memory device corresponds to a first state and decrease the read voltage by a predefined offset amount;
The first state corresponds to a state in which the read data is output from a first latch among the plurality of latches.
According to paragraph 2,
The memory controller is,
While operating in the second mode of operation, determine whether the status bit indicates a second state;
When the status bit indicates the second state, bypassing the change in the read voltage based on the second state,
The second state corresponds to a state in which the read data is output from a second latch among the plurality of latches.
According to clause 4,
The memory controller is,
Determine whether the status bit indicates a first state,
When the status bit indicates the first state, transmitting a command requesting information about the number of cells activated using a first latch among the plurality of latches to the non-volatile memory device,
A storage device that bypasses the change in the read voltage when the number of cells activated using the first latch is less than the threshold value.
According to clause 5,
The memory controller is,
Identifying that the status bit indicates a third state,
Transmitting a command requesting information about the number of cells activated using a third latch among the plurality of latches to the non-volatile memory,
A storage device that bypasses the change in the read voltage when the number of cells activated using the third latch is greater than the threshold value.
According to paragraph 1,
The status bits include a first bit, a second bit, a third bit, and a fourth bit,
The first bit and the second bit indicate one of the first to third states,
The third bit indicates a comparison result between a threshold value and the number of cells activated using a first latch among the plurality of latches when the non-volatile memory is in the first state,
The fourth bit indicates a comparison result between the threshold value and the number of cells activated using a third latch among the plurality of latches when the non-volatile memory is in the third state.
In clause 7,
The memory controller is,
Based on the third bit, determine whether to reduce the read voltage by a predefined offset size,
A storage device that determines whether to increase the read voltage by the predefined offset size based on the fourth bit.
An ECC module that performs error correction code (ECC) decoding based on read data received from a non-volatile memory device that performs an on chip valley search (OVS) read operation; and
Receive, from the non-volatile memory device, a status bit indicating one latch that latched the read data among a plurality of latches included in the non-volatile memory device and each storing result values of the OVS read operation, and the ECC When decoding is successful, it includes a read voltage change module that determines whether to change the read voltage based on the status bit,
The lead voltage change module,
When the ECC decoding is successful and the status bit indicates the first state in which the read data is output from the first latch among the plurality of latches, the number and threshold value of cells activated using the first latch Compare and, if the number of cells activated using the first latch is greater than the threshold, reduce the read voltage by a predefined offset size,
When the ECC decoding is successful and the status bit indicates a third state in which the read data is output from a third latch among the plurality of latches, the number and threshold value of cells activated using the third latch and, if the number of cells activated using the third latch is greater than the threshold, increasing the read voltage by a predefined offset size.
In the operation method of the memory controller,
Receiving, from a non-volatile memory performing an OVS read operation, read data and a status bit indicating one latch from among a plurality of latches to which the read data is output;
performing ECC decoding based on the read data;
When the ECC decoding is successful, determining whether to change the read voltage based on the status bit,
The step of determining whether to change the lead voltage is,
When the ECC decoding is successful and the status bit indicates the first state in which the read data is output from the first latch among the plurality of latches, the number and threshold value of cells activated using the first latch Comparing , and if the number of cells activated using the first latch is greater than the threshold, reducing the read voltage by a predefined offset size; and
When the ECC decoding is successful and the status bit indicates a third state in which the read data is output from a third latch among the plurality of latches, the number and threshold value of cells activated using the third latch comparing, and if the number of cells activated using the third latch is greater than the threshold, increasing the read voltage by a predefined offset size. .

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