KR20210135915A - Method for forming a mfmis memory device - Google Patents

Abstract

Various embodiments of the present application relate to a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device as well as a method for forming the MFMIS memory device. In accordance with some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on the opposite side of the internal gate electrode to the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

Description

METHOD FOR FORMING A MFMIS MEMORY DEVICE

Two-dimensional (2D) memory arrays are widely used in electronic devices and may include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random-access memory (DRAM) arrays, and the like. However, 2D memory arrays are reaching their scaling limits, reaching the limits of memory density. Three-dimensional (3D) memory arrays are promising candidates for increasing memory density and may include, for example, 3D NAND flash memory arrays, 3D NOR flash memory arrays, and the like.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that the various features are not drawn to scale in accordance with the standard practice in the industry. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
1A-1C show various views of some embodiments of an MFMIS memory cell.
2A-2C show various views of some embodiments of a three-dimensional (3D) memory array including MFMIS memory cells configured as in FIGS. 1A-1C .
3A-3E show cross-sectional views of various alternative embodiments of the 3D memory array of FIGS. 2A-2C.
4A-4C show various views of some embodiments of an integrated circuit (IC) including the 3D memory array of FIGS. 2A-2C .
5 shows a perspective view of some embodiments of a pair of neighboring rows in the 3D memory array of FIGS. 4A-4C ;
6A and 6B show cross-sectional views of some alternative embodiments of the IC of FIGS. 4A-4C , wherein word lines are at the bottom of the 3D memory array and at the top of the 3D memory array, respectively.
7A and 7B show cross-sectional views of some alternative embodiments of the IC of FIGS. 6A and 6B .
8A and 8B through 15A and 15B, 16A-16C, and 17A and 17B show a series of views of some embodiments of a method of forming an IC including a 3D memory array of MFMIS memory cells. .
18 shows a block diagram of some embodiments of the method from FIGS. 8A and 8B through FIGS. 15A and 15B , FIGS. 16A-16C and FIGS. 17A and 17B .
19A and 19B through 24A and 24B, 25A-25C, and 26A and 26B, word lines represent a 3D memory array of MFMIS memory cells at the bottom of the 3D memory array and at the top of the 3D memory array, respectively. A series of views of some embodiments of a method of forming an IC comprising
27 shows a block diagram of some embodiments of the method from FIGS. 19A and 19B through FIGS. 24A and 24B , FIGS. 25A-25C , and FIGS. 26A and 26B .

This disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, examples only and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact. and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity, and in itself does not represent a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "beneath", "below", "lower", "above" "upper", etc. may be used herein for ease of description to describe a relationship between other elements or features of an element or feature of Spatially relative terms are intended to encompass different orientations of the device in use or in operation, as well as orientations shown in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or otherwise), and spatially relative descriptors used herein may be interpreted similarly accordingly.

In some embodiments, a three-dimensional (3D) memory device includes a plurality of metal-ferroelectric-insulator-semiconductor (MFIS) memory cells defining a plurality of memory arrays at different heights. According to some embodiments of a MFIS memory cell in a 3D memory device, the first source/drain region, the semiconductor channel, and the second source/drain region are vertically stacked and define a common sidewall. A control gate electrode, a ferroelectric layer, and a gate dielectric layer extend vertically through the plurality of memory arrays along a common sidewall. The gate dielectric layer is between the ferroelectric layer and the semiconductor channel and borders the ferroelectric layer and the semiconductor channel, and the ferroelectric layer is between the control gate electrode and the gate dielectric layer and borders the control gate electrode and the gate dielectric layer.

During program and erase operations, program and erase voltages having opposite polarities are applied across the ferroelectric layer and the gate dielectric layer, respectively. The program and erase voltages change the polarity of the ferroelectric layer between a programmed state and an erased state, so that bits of data can be represented by the polarity. Further, during program and erase operations, the MFIS memory cell can be modeled as a first parallel plate capacitor and a second parallel plate capacitor electrically coupled in series and corresponding to a ferroelectric layer and a gate dielectric layer.

A problem with MFIS memory cells is that the ferroelectric layer and the gate dielectric layer can share the same parallel plates (eg, control gate electrode and semiconductor channel) and thus have the same capacitor area. The capacitor region corresponds to an overlap region between the control gate electrode and the semiconductor channel. Also, the ferroelectric layer may have a higher dielectric constant than the gate dielectric layer. For example, the ferroelectric layer may have a dielectric constant greater than about 20 or some other suitable value due to available materials, while the gate dielectric layer may have a dielectric constant of about 3.9 to 15 for high reliability and high time-dependent dielectric breakdown (TDDB). It may have a dielectric constant between or any other suitable value.

For a pair of parallel plate capacitors electrically coupled in series, the electric field ratio is equal to the inverse of the dielectric constant ratio multiplied by the inverse of the capacitor area ratio. In other words, E ₁ /E ₂ =(k ₂ *A ₂ )/(k ₁ *A ₁ ), where E is the electric field, k is the dielectric constant, and A is the capacitor area. area), and the subscript indicates a specific capacitor. Therefore, due to the same capacitor area and higher dielectric constant in the ferroelectric layer, the gate dielectric layer and the ferroelectric layer can have a high electric field and a low electric field during program and erase operations, respectively.

Due to the low electric field across the ferroelectric layer, the polarization of the ferroelectric layer switches weakly during program and erase operations. As a result, the difference between the read currents while the ferroelectric layer is in the programmed and erased states, respectively, is small (eg, the memory window is small). Also, due to the low electric field, the program and erase voltages can be high and thus the power consumption can be high. Due to the high electric field in the gate dielectric layer, the stress on the gate dielectric layer is high. This in turn degrades the reliability of the gate dielectric layer and the TDDB of the gate dielectric layer. Thus, the low electric field across the ferroelectric layer and the high electric field in the gate dielectric layer reduce the durability and retention of the MFIS memory cell.

Various embodiments of the present application relate to an MFMIS memory device as well as a method of forming a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device. Note that MFMIS refers to metal ferroelectric metal insulator semiconductors, however, doped polysilicon and other suitable conductive materials may be used instead of metal. According to some embodiments of the MFMIS memory device, the first source/drain region and the second source/drain region are vertically stacked. The inner gate electrode and the semiconductor channel overlie the first source/drain region and under the second source/drain region. A semiconductor channel extends from the first source/drain region to the second source/drain region, and the inner gate electrode is electrically floating. The gate dielectric layer is between the inner gate electrode and the semiconductor channel and borders the inner gate electrode and the semiconductor channel. The control gate electrode is opposite the semiconductor channel of the inner gate electrode and is uncovered by the second source/drain region. The ferroelectric layer is between the control gate electrode and the inner gate electrode and borders the control gate electrode and the inner gate electrode.

During program and erase operations, the MFMIS memory cell may be modeled as a first parallel plate capacitor and a second parallel plate capacitor electrically coupled in series and corresponding to a ferroelectric layer and a gate dielectric layer. The control gate electrode and the inner gate electrode define parallel plates of the first capacitor, and the inner gate electrode and the semiconductor channel define parallel plates of the second capacitor. Thus, the capacitor region of the ferroelectric layer corresponds to the overlap between the control and inner gate electrodes, while the capacitor region of the gate dielectric layer corresponds to the overlap between the inner gate electrode and the semiconductor channel. Due to the inner gate electrode, the first and second parallel plate capacitors each have a different set of parallel plates and thus may have different capacitor areas. If the inner gate electrode is omitted, the first and second parallel plate capacitors will have the same parallel plate and thus the same capacitor area.

As mentioned above, for a pair of parallel plate capacitors electrically coupled in series, the electric field ratio is equal to the inverse of the dielectric constant ratio multiplied by the inverse of the capacitor area ratio. Tuning the electric field across the ferroelectric layer and the gate dielectric layer using the dielectric constant can be difficult due to material constraints. However, tuning the electric field across the ferroelectric layer and the gate dielectric layer using the capacitor region can be achieved during formation of the MFMIS memory cell by tuning the dimensions of each of the control gate electrode, inner gate electrode and semiconductor channel. Accordingly, the dimensions can be tuned so that the electric field across the ferroelectric layer is high and the electric field across the gate dielectric layer is low.

Since the ferroelectric layer can have a high electric field, the polarization of the ferroelectric layer can switch strongly during program and erase operations. As a result, the difference between the read currents while the ferroelectric layers are in the respectively programmed and erased states can be large (eg, the memory window can be large). Further, since the ferroelectric layer may have a high electric field, program and erase voltages may be low, and thus power consumption may be low. Due to the low electric field in the gate dielectric layer, the stress on the gate dielectric layer may be low. This in turn can improve the reliability of the gate dielectric layer and the TDDB of the gate dielectric layer. Thus, tuning the dimensions of the control and internal gate electrodes can improve the durability and retention of the MFMIS memory cell.

1A-1C , various views 100A-100C of some embodiments of an MFMIS memory cell 102 are provided. FIG. 1A corresponds to cross-section 100A along line A of FIG. 1C , while FIG. 1B corresponds to cross-section 100B along line B in FIG. 1C . Also, FIG. 1C corresponds to a top view 100C. The MFMIS memory cell 102 may be or include, for example, an MFMIS field-effect transistor (FET) or some other suitable semiconductor device having an MFMIS stack.

The semiconductor channel 104, the gate dielectric layer 106, and the inner gate electrode 108 overlie the lower source/drain region 110l and underlie the upper source/drain region 110u. The semiconductor channel 104 , the gate dielectric layer 106 , the inner gate electrode 108 , the lower source/drain region 110l and the upper source/drain region 110u are the control gate electrode 114 and the ferroelectric layer 116 and the It defines an opposing common sidewall 112 . In some embodiments, common sidewalls 112 are flat and/or smooth. The control gate electrode 114 and the ferroelectric layer 116 extend along the common sidewall 112 from the bottom surface of the lower source/drain region 110l to the top surface of the upper source/drain region 110u.

The ferroelectric layer 116 separates the control gate electrode 114 from the common sidewall 112 and has a polarity representing the bit of data. During program and erase operations, the lower and upper source/drain regions 110l and 110u are electrically connected in parallel and used as a proxy for the semiconductor channel 104 . A program voltage is applied from the control gate electrode 114 to the semiconductor channel 104 (eg, via the lower and upper source/drain regions 110l and 110u) to set the polarity to the programmed state. In addition, an erase voltage having a polarity opposite to the program voltage (e.g., via the lower and upper source/drain regions 110l and 110u) from the control gate electrode 114 to the semiconductor channel ( 104) is approved. The programmed state may represent, for example, a binary "1" while the erased state may represent, for example, a binary "0", and vice versa.

The ferroelectric layer 116 conducts the electric field generated by the control gate electrode 114 such that the MFMIS memory cell 102 has the programmed threshold voltage and the erased threshold voltage, respectively, while the polarity is in the programmed and erased states. Screening. Thus, during a read operation, the control gate electrode 114 is biased with a read voltage between the programmed threshold voltage and the erased threshold voltage and the resistance of the semiconductor channel 104 is measured. Depending on whether the semiconductor channel 104 is conducting, the polarity is in a programmed state or an erased state.

Because the lower and upper source/drain regions 1101 and 110u are electrically coupled in parallel during program and erase operations, the MFMIS memory cell 102 is electrically coupled in series during program and erase operations. semiconductor) parallel plate capacitor C _MIS (simply MIS capacitor C _MIS ) and ferroelectric parallel plate capacitor C _FE (simply ferroelectric capacitor C _FE ). _{The inner gate electrode 108 and the semiconductor channel 104 each define a parallel plate of the MIS capacitor C MIS} parallel to the cross-sectional view 100B of FIG. 1B , and the gate dielectric layer 106 is the MIS capacitor C _MIS . Insulation is specified. In some embodiments, the interfacial layer (not shown) on the semiconductor channel 104 between the gate dielectric layer 106 and the semiconductor channel 104 also defines an insulator of the _{MIS capacitor C MIS . Further, the inner and control gate electrodes 108 and 114 each define parallel plates of the ferroelectric capacitor C FE} parallel to the cross-sectional view 100B of FIG. 1B , and the ferroelectric layer 116 is the insulator _{of the ferroelectric capacitor C FE} stipulate

The capacitor area of a parallel plate capacitor corresponds to the overlap between the opposite surfaces of a parallel plate when both surfaces are projected onto a two-dimensional (2D) plane parallel to the two surfaces. Thus, the capacitor region of the MIS capacitor C _MIS corresponds to the overlap between the inner gate electrode 108 and each of the opposite surfaces of the semiconductor channel 104 when both surfaces are projected on a 2D plane parallel to the both surfaces. do. Similarly, the capacitor area of the ferroelectric capacitor C _FE corresponds to the overlap between each of the inner and opposite surfaces of the control gate electrodes 108 , 114 when both surfaces are projected onto a 2D plane parallel to the both surfaces. .

Due to the inner gate electrode 108 , the ferroelectric and MIS capacitors C _FE , C _MIS may have different capacitor regions. If the inner gate electrode 108 is omitted, the ferroelectric and MIS capacitors C _FE , C _MIS will share the same parallel plates and thus have the same capacitor area. In addition, as will be seen below, the MFMIS memory cell 102 can independently define _{the width W cg of the control gate electrode 114 and the width W ig} of the inner gate electrode 108 by a method can be formed. This in turn makes it possible to tune the capacitor regions of the ferroelectric and MIS capacitors (C _FE , C _{MIS ).}

Since the ferroelectric and MIS capacitors (C _FE , C _MIS ) are electrically coupled in series, the electric field ratio (e.g., E _FE /E _{MIS ) for the ferroelectric and MIS capacitors (C FE} , C _MIS ) is equal to the dielectric constant ratio It is equal to the product of the inverse of (eg, k _MIS /k _FE ) and the inverse of the capacitor area ratio (eg, A _MIS /A _{FE ).} In other words, E _FE /E _MIS =(k _MIS *A _MIS )/(k _FE *A _FE ), where E is the electric field, k is the dielectric constant, A is the capacitor area, and the subscript is the specific capacitor (e.g. , C _FE or C _MIS ). Accordingly, the electric field ratio can be tuned by the dielectric constant ratio and/or the capacitor area ratio.

The dielectric constant is a material dependent parameter, and material constraints may limit the ability to tune the electric field ratio (eg, E _FE /E _{MIS ) based on the dielectric constant ratio (eg, k MIS} /k _{FE ).} . For example, the ferroelectric layer 116 may have a dielectric constant greater than about 20 or some other suitable value due to available materials, while the gate dielectric layer 106 may have between about 3.9 and 15 for high reliability and high TDDB. may have a dielectric constant of or any other suitable value. However, as discussed above, the capacitor area may be tuned by the method of forming the MFMIS memory cell 102 . Accordingly, the electric field ratio (eg, E _FE /E _MIS ) can be tuned based on the _{capacitor area ratio (eg, A MIS} /A _FE ) during the method of forming the MFMIS memory cell 102 .

Because the electric field ratio (eg, E _FE /E _MIS ) can be tuned during the method of forming the MFMIS memory cell 102 , the ferroelectric layer 116 can have a high electric field during program and erase operations, whereas The gate dielectric layer 106 may have a low electric field during program and erase operations. Further, the ferroelectric layer 116 may have a high voltage drop during program and erase operations, while the gate dielectric layer 106 may have a low voltage drop during program and erase operations. Since the ferroelectric layer 116 can have a high electric field, the polarization of the ferroelectric layer 116 can switch strongly during program and erase operations. As a result, the difference between the read currents while the ferroelectric layer 116 is in each programmed and erased state can be large (eg, the memory window can be large). In addition, since the ferroelectric layer 116 may have a high electric field, program and erase voltages may be low, and thus power consumption may be low. Because the gate dielectric layer 106 can have a low electric field, the stress on the gate dielectric layer 106 can be low. This in turn may improve the reliability of the gate dielectric layer 106 and the TDDB of the gate dielectric layer 106 . Accordingly, durability of the MFMIS memory cell 102 and retention of the MFMIS memory cell 102 can be improved.

Specifically, referring to FIG. 1B , the inner gate electrode 108 completely overlaps the semiconductor channel 104 , so that the surface area of the inner gate electrode 108 defines the capacitor area of the _{MIS capacitor C MIS .} In addition, the height H _ig of the inner gate electrode 108 is smaller than the height H _{cg of the control gate electrode 114 , and the width W cg} of the control gate electrode 114 is that of the inner gate electrode 108 . Since it is less than the width W _{ig , the capacitor region of the ferroelectric capacitor C FE} is bounded by _{the width W cg} of the control gate electrode 114 _{and the height H ig} of the inner gate electrode 108 . . Therefore, the MIS and the ferroelectric capacitors C _MIS and C _FE have the same capacitor region height, and the ferroelectric capacitor C _FE has a smaller capacitor region width than the MIS capacitor C _{MIS .}

Since the ferroelectric and MIS capacitors have the same capacitor area height, the electric field ratio (eg, E _FE /E _MIS ) can be simplified and equal to _{(k MIS} *W _MIS )/(k _FE *W _{FE )} where W _{FE is the width W cg} of the control gate electrode 114 and W _{MIS is the width W ig} of the inner gate electrode 108 . In addition, the MIS and the ferroelectric capacitor (C _MIS, C _FE) has the same capacitor area, height, and a ferroelectric capacitor (C _FE) is due to its small capacitor area width than MIS capacitor (C _MIS), a ferroelectric capacitor (C _FE) The capacitor area is smaller than the capacitor area of the MIS capacitor C _{MIS .} Thus, the capacitor area ratio (eg, A _MIS /A _FE ) favors a higher electric field in the ferroelectric layer 116 than in the gate dielectric layer 106 . As mentioned above, a higher electric field in the ferroelectric layer 116 improves the durability of the MFMIS memory cell 102 and retention of the MFMIS memory cell 102 .

Referring generally back to FIGS. 1A-1C , the semiconductor channel 104 extends from the lower source/drain region 110l to the upper source/drain region 110u. In addition, a semiconductor channel 104 wraps around a corner of the gate dielectric layer 106 from the sidewalls of the gate dielectric layer 106 to the top surface of the gate dielectric layer 106 and the bottom surface of the gate dielectric layer 106, respectively. In some embodiments, the semiconductor channel 104 has an inverted C-shaped profile. However, other suitable profiles are amenable. The semiconductor channel 104 may be, for example, doped or undoped, and may be or include, for example, polysilicon and/or some other suitable semiconductor material.

The lower and upper source/drain regions 1101 and 110u are doped and may be or include, for example, polysilicon and/or some other suitable semiconductor material. In some embodiments, the lower and upper source/drain regions 1101 and 110u are or include doped polysilicon having a first doping type, and the semiconductor channel 104 is of a second doping type opposite to the first doping type. is or includes doped polysilicon having In some other embodiments, the lower and upper source/drain regions 1101 and 110u are or include doped polysilicon, and the semiconductor channel 104 is or comprises undoped polysilicon.

A gate dielectric layer 106 wraps around a corner of the inner gate electrode 108 from the sidewall of the inner gate electrode 108 to the top surface of the inner gate electrode 108 and the bottom surface of the inner gate electrode 108, respectively. In some embodiments, the gate dielectric layer 106 has an inverted C-shaped profile. However, other suitable profiles are possible. The gate dielectric layer 106 may be, for example, silicon oxide (eg, SiO ₂ ), silicon nitride (eg, Si ₃ N ₄ ), silicon oxynitride (eg, SiON), aluminum oxide (eg, , Al ₂ O ₃ ), hafnium oxide (eg, HfO ₂ ), lanthanum oxide (eg, La ₂ O ₃ ), zirconium oxide (eg, ZrO ₂ ), some other suitable dielectric, or as described above It may be any combination of, or include.

In some embodiments, the gate dielectric layer 106 has a lower dielectric constant than the dielectric constant of the ferroelectric layer 116 , so that the dielectric constant ratio (eg, k _MIS /k _FE ) is the ferroelectric layer ( A higher electric field is preferred in the gate dielectric layer 106 than in 116 . As noted above, this may degrade durability and/or retention of the MFMIS memory cell 102 . _{Thus, in some of these embodiments, the capacitor area ratio (eg, A MIS} /A _FE ) is the dielectric constant ratio (eg, A MIS /A FE ) such that the ferroelectric layer 116 has a higher electric field than the gate dielectric layer 106 during program and erase operations. For example, k _MIS /k _FE ) is tuned to counteract. In some embodiments, the gate dielectric layer 106 is or comprises a high K dielectric material having a dielectric constant greater than about 3.9 or some other suitable value. In some embodiments, the gate dielectric layer 106 has a dielectric constant between about 3.9 and 15 or some other suitable value. If the dielectric constant is greater than about 15 or some other suitable value, the leakage current may be high and/or the reliability of the gate dielectric layer 106 may be low. For example, the TDDB of the gate dielectric layer 106 may be low. When the dielectric constant is less than about 3.9 or some other suitable value, the dielectric constant ratio (eg, k _MIS /k _FE ) is used to compensate for the higher electric field using the capacitor area ratio (eg, A _MIS /A _{FE ).} A higher electric field may be favored in the gate dielectric layer 106 than in the ferroelectric layer 116 to the extent that it may be difficult to do so.

The inner gate electrode 108 is electrically floating, for example titanium nitride, doped polysilicon (eg, N+ or P+), tantalum nitride, tungsten, some other suitable conductive material, or any combination of the foregoing. or may include it. In some embodiments, the inner gate electrode 108 , the gate dielectric layer 106 and the semiconductor channel 104 completely overlie the upper source/drain region 110u and/or completely over the lower source/drain region 110l . .

The control gate electrode 114 and the ferroelectric layer 116 are opposite the gate dielectric layer 106 and the semiconductor channel 104 of the floating gate electrode 108 . Further, the control gate electrode 114 and the ferroelectric layer 116 are on the sides of the lower and upper source/drain regions 110l and 110u. As such, the control gate electrode 114 and the ferroelectric layer 116 are not covered by the upper source/drain region 110u. Control gate electrode 114 may be or include, for example, titanium nitride, doped polysilicon (eg, N+ or P+), tantalum nitride, tungsten, some other suitable conductive material, or any combination of the foregoing. can The ferroelectric layer 116 may include, for example, 1) less than about 20 atomic percent aluminum, 2) less than about 5 atomic percent silicon; 3) less than about 50 atomic percent zirconium; 4) less than about 50 atomic percent lanthanum; 5) less than about 50 atomic percent strontium; or 6) hafnium oxide (eg, HfO ₂ ) doped with any other suitable element. Additionally or alternatively, the ferroelectric layer 116 may be or include other suitable ferroelectric materials, for example.

The ferroelectric layer 116 , the semiconductor channel 104 , the gate dielectric layer 106 , and the inner gate electrode 108 have respective thicknesses laterally (eg, in the X direction) within the cross-sectional view of FIG. 1A . The ferroelectric layer 116 may have an individual thickness of, for example, about 3 to 15 nanometers. The semiconductor channel 104 may have a discrete thickness of, for example, about 5 to 7 nanometers or any other suitable thickness. The gate dielectric layer 106 may have a discrete thickness of, for example, about 1-5 nanometers or any other suitable thickness. The inner gate electrode 108 may have a discrete thickness of, for example, about 4 to 24 nanometers or any other suitable thickness. The semiconductor channel 104 , the gate dielectric layer 106 and the inner gate electrode 108 may have a combined thickness of, for example, about 10-30 nanometers.

A dielectric structure 118 surrounds the MFMIS memory cell 102 . A dielectric structure 118 separates the lower and upper source/drain regions 1101 and 110u from each other, and as will be seen later, when the MFMIS memory cell 102 is integrated into the memory array, the MFMIS memory cell 102 is connected to another MFMIS. separate from the memory cell. Note that the portion of the dielectric structure 118 that separates the lower and upper source/drain regions 110l and 110u may also be known as a source/drain dielectric layer. The dielectric structure 118 may be or include, for example, silicon oxide and/or other suitable dielectric.

2A-2C, various views 200A-200C of some embodiments of a 3D memory array 202 including a plurality of MFMIS memory cells 102 configured as in FIGS. 1A-1C are provided. FIG. 2A corresponds to cross-sectional view 200A along line A' of FIG. 2C. FIG. 2B corresponds to cross-sectional view 200B along line B′ of FIG. 2C . FIG. 2C corresponds to top view 200C along line C of FIGS. 2A and 2B . The 3D memory array 202 can provide high memory density as well as high reliability (eg, high durability and high retention) for high speed and low power consumption applications, for example.

The MFMIS memory cells 102 are grouped into a first memory array 204a and a second memory array 204b. The first and second memory arrays 204a and 204b are stacked vertically over the dielectric substrate 206 , and the second memory array 204b overlies the first memory array 204a. The first and second memory arrays 204a and 204b have the same layout and have 9 rows and 8 columns, respectively. In alternative embodiments, the first and second memory arrays 204a, 204b may have more or fewer rows and/or more or fewer columns. For readability, the rows and columns are unlabeled. However, it is said that rows extend in the X direction (eg, laterally in cross-section 200A of FIG. 2A ), while columns extend in the Y-direction (eg, laterally in cross-section 200B of FIG. 2B ). should understand that

A plurality of control gate electrodes 114 and ferroelectric layer 116 extend through first and second memory arrays 204a and 204b and partially define MFMIS memory cells 102 . Further, the control gate electrode 114 and the ferroelectric layer 116 are shared by the MFMIS memory cells of the first memory array 204a and the MFMIS memory cells of the second memory array 204b. For example, each MFMIS memory cell in the first memory array 204a may share a control gate electrode and a ferroelectric layer 116 with an overlying MFMIS memory cell in the second memory array 204b. The ferroelectric layer 116 may be shared by multiple MFMIS memory cells, for example, because the polarization of the ferroelectric layer 116 is limited to the MFMIS memory cell in which the polarization occurred.

MFMIS memory cells 102 are further grouped into pairs 208 of neighboring MFMIS memory cells (eg, MFMIS pairs 208 ) along corresponding rows. The MFMIS memory cells of each MFMIS pair 208 share a corresponding one of the control gate electrodes 114 . The MFMIS memory cell to the right of the corresponding control gate electrode is as shown and described in Figures 1A-1C. The MFMIS memory cell to the left of the corresponding control gate electrode is shown and described in FIGS. 1A-1C except that FIG. 1A should be flipped horizontally along the Z axis and FIG. 1C should be flipped horizontally along the Y axis. like a bar Figure 1b is the same regardless of whether the MFMIS memory cell is to the left or right of the corresponding control gate electrode.

MFMIS pairs 208 are arranged such that MFMIS pairs occur every two columns along each row and every other row along each column. Further, the MFMIS pairs 208 are staggered along neighboring columns and neighboring rows so that the pitch P _y of the MFMIS pair 208 in the Y direction spans the row and the pitch P of the MFMIS pair 208 in the X direction. _x ) spans 2 columns. In some embodiments, the control gate electrode 114 has _{an individual width W cg in the} Y direction that is less than about half the _{pitch P y} in the Y direction.

A plurality of semiconductor channels 104 , a plurality of gate dielectric layers 106 , a plurality of lower source/drain regions 110l and a plurality of upper source/drain regions 110u define, in part, an MFMIS memory cell 102 . “Lower” and “upper” are relative to the corresponding MFMIS memory cell 102 for the lower and upper source/drain regions 1101 and 110u. Semiconductor channels 104, gate dielectric layers 106, and lower and upper source/drain regions 110l, 110u correspondingly extend along the columns and are shared by MFMIS memory cells in the corresponding columns. Since the electric field generated by the MFMIS memory cell is localized in the MFMIS memory cell, the semiconductor channel may be shared by, for example, multiple MFMIS memory cells. In an alternative embodiment, the semiconductor channel 104 and/or the gate dielectric layer 106 is separate to the MFMIS memory cell 102 and thus is not shared by the MFMIS memory cell.

A plurality of internal gate electrodes 108 partially define an MFMIS memory cell 102 . The inner gate electrode 108 is separate to the MFMIS memory cell 102 and is therefore not shared by the MFMIS memory cell. In some embodiments, the inner gate electrodes 108 are separated from each other along corresponding columns by a _{distance D 1 that} is less than about half the _{Y-direction pitch P y .}

1A-1C , the inner gate electrode 108 is configured such that the ferroelectric layer 116 has a higher electric field than the gate dielectric layer 106 during program and erase operations. ) can be used to tune the electric field across For example, the inner gate electrode 108 has an individual width W greater than _{the individual width W cg} of the control gate electrode 114 to promote a higher electric field in the ferroelectric layer 116 than in the gate dielectric layer 106 . _ig ) can have. A higher electric field in the ferroelectric layer 116 than in the gate dielectric layer 106 may improve durability and/or retention of the MFMIS memory cell 102 .

The plurality of metal lines 210 define a bit line BL and a source line SL. The bit lines BL respectively extend along a row and are respectively electrically coupled to the top surface of the upper source/drain region 110u. The source lines SL each extend along the columns and are respectively electrically coupled to the bottom surface of the lower source/drain region 110l. In an alternative embodiment, the bit line BL and the source line SL are inverted. Metal lines 210 have lower resistances than lower and upper source/drain regions 1101 , 110u and are defined by corresponding metal layers 212 and corresponding barrier layers 214 . The barrier layers 214 are configured to prevent diffusion of material from the metal layers 212 into the overlying and/or underlying structure. Metal layer 212 may be or include, for example, tungsten and/or some other suitable metal. The barrier layers 214 may be or include, for example, titanium nitride (eg, TiN), tungsten nitride (eg, WN), some other suitable barrier material, or any combination of the foregoing. have.

A plurality of array dielectric layers 216 overly the first and second memory arrays 204a and 204b over the bit lines BL, respectively. The array dielectric layers 216 may be of a different material than the dielectric substrate 206 and may be or include, for example, silicon nitride and/or other suitable dielectric. A dielectric structure 118 surrounds the MFMIS memory cell 102 and isolates the MFMIS memory cell 102 from one another. In addition, dielectric structure 118 separates lower and upper source/drain regions 110l and 110u from each other.

2A-2C show a 3D memory array with two memory array levels, more memory array levels are possible. For example, the second memory array 204b may be repeated over the second memory array 204b with corresponding metal lines and corresponding array dielectric layers. Also, while FIGS. 2A-2C show a 3D memory array having two memory array levels, two-dimensional (2D) memory arrays with a single memory array level are also possible. For example, the second memory array 204b may be omitted along with a corresponding metal line and a corresponding array dielectric layer.

Referring to FIG. 3A , a cross-sectional view 300A of some alternative embodiments of the 3D memory array of FIG. 2A is provided with metal lines 210 omitted. As such, the lower source/drain region 110l functions as the source line SL and the upper source/drain region 110u functions as the bit line BL. This may reduce material cost and/or manufacturing complexity, but since the lower and upper source/drain regions 110l, 110u may have a higher resistance than the metal line 210, the BL) may incur the cost of an increased voltage drop. This increased voltage drop may limit the size of the 3D memory array and/or result in increased power consumption.

Referring to FIG. 3B , a cross-sectional view 300B of some alternative embodiment of the 3D memory array of FIG. 2A is provided, wherein a dummy structure 302 is provided on the metal line 210 to protect the metal line 210 from oxidation. on the side wall. Such oxidation may occur, for example, before and/or during deposition of the ferroelectric material from which the ferroelectric layer 116 is formed. Oxidation may increase the resistance of the metal line 210 thereby increasing the voltage drop along the metal line 210 . This in turn may increase power consumption and/or limit the size of the 3D memory array. Also, if the oxidation is significant enough, device failure can occur.

The dummy structure 302 includes a corresponding dummy semiconductor channel 304 , a corresponding dummy gate dielectric layer 306 and a corresponding dummy inner gate electrode 308 . Dummy semiconductor channel 304, dummy gate dielectric layer 306 and dummy inner gate electrode 308 are as described for semiconductor channels 104, gate dielectric layers 106 and inner gate electrodes 108, respectively. This may be due, for example, to formation by the same process or by a similar process.

In some embodiments, the dummy structure 302 is equal to or substantially equal to _{the respective width W mis} of the corresponding MIS structure defined by the semiconductor channel 104 , the gate dielectric layer 106 and the inner gate electrode 108 . It has an individual width (W _dmy ). In an alternative embodiment, the dummy structure 302 is different (eg, _{W mis} ) from the respective width of the corresponding MIS structure defined by the semiconductor channel 104 , the gate dielectric layer 106 and the inner gate electrode 108 . For example, it has an _{individual width (W dmy} ) (larger or smaller). The different widths may be due to, for example, different etching processes during formation of the recesses in which the dummy structure 302 and the MIS structure are formed and/or due to, for example, different etching rates during formation of the recesses. can do. However, other suitable reasons are possible for different widths.

Referring to FIG. 3C , a cross-sectional view 300C of some alternative embodiments of the 3D memory array of FIG. 2A is provided in which a plurality of silicide lines 310 are used instead of a plurality of metal lines 210 . Accordingly, the source line SL and the bit line BL are defined by the silicide line 310 .

As discussed with respect to FIG. 3B , oxidation of the metal line 210 may occur without the dummy structure 302 protecting the sidewalls of the metal line 210 . This oxidation can eventually negatively affect the performance of the 3D memory array. The silicide line 310 may have a resistance comparable to the metal line 210 and thus may perform comparable to the metal line 210 . In addition, the silicide line 310 may have a lower reactivity with respect to oxygen than the metal line 210 . Accordingly, by replacing the metal line 210 with the silicide line 310 , the oxidation-related problem can be alleviated without the dummy structure 302 . Further, dummy structure 302 adds complexity to the formation of a 3D memory array, so omitting dummy structure 302 may reduce cost and/or increase yield.

Referring to FIG. 3D , a cross-sectional view 300D of some alternative embodiments of the 3D memory array of FIG. 3C is provided with the lower and upper source/drain regions 110l and 110u omitted. Instead, the silicide line 310 is used as the source/drain region for the MFMIS memory cell 102 .

Referring to FIG. 3E , a cross-sectional view of some alternative embodiments of the 3D memory array of FIG. 2A in which the gate dielectric layers 106 are separate to the MFMIS memory cells 102 and thus not shared by the MFMIS memory cell along a corresponding column. (300E) is provided. As a result, the gate dielectric layer is no longer visible in the gap 312 between the MFMIS pair 208 . In an alternative embodiment, the semiconductor channel 104 is also separate to the MFMIS memory cell 102 and thus will not be visible in the gap 312 between the MFMIS pair 208 .

3A-3E illustrate cross-sectional views 300A-300E of some alternative embodiments of the 3D memory array of FIG. 2A in the X direction, it should be understood that a top view of an alternative embodiment may be as shown in FIG. 2C . . For example, FIG. 2C may be taken along line C in any one of FIGS. 3A-3E . Similarly, it should be understood that a cross-sectional view of an alternative embodiment in the Y direction may be as shown in FIG. 2B except that the vertical stack of layers will be modified to match FIGS. 3A-3E .

4A-4C, various views 400A-400C of some embodiments of an integrated circuit (IC) including the 3D memory array 202 of FIGS. 2A-2C are provided. FIG. 4A corresponds to cross-section 400A along line D in FIG. 4C , and FIG. 4B corresponds to cross-section 400B along line E in FIG. 4C . Also, FIG. 4C corresponds to a top view 400C along line F in FIGS. 4A and 4B .

A 3D memory array 202 overlies a semiconductor substrate 402 in an interconnect structure 404 . The semiconductor substrate 402 may be or include, for example, a bulk substrate of single crystal silicon and/or some other suitable type of semiconductor substrate. The interconnect structure 404 includes an interconnect dielectric layer 406 , a plurality of wires 408 , and a plurality of vias 410 . Wires 408 and vias 410 are alternately stacked within interconnect dielectric layer 406 to define conductive paths above and below 3D memory array 202 . Interconnect dielectric layer 406 may be or include, for example, silicon oxide and/or some other suitable dielectric. Wires 408 and vias 410 may be or include, for example, metal and/or some other suitable conductive material.

A plurality of wires 408 overlies the 3D memory array 202 and defines a plurality of top word line wires (TWL) that correspondingly extend along rows of the 3D memory array 202 . In addition, the plurality of vias 410 define top electrode vias (TEVs) each extending from the control gate electrodes 114 to the top word line TWL, respectively. Accordingly, the top word line TWL and the top electrode via TEV are electrically coupled and interconnected to the control gate electrode in the corresponding row.

A semiconductor device 412 is on the semiconductor substrate 402 between the semiconductor substrate 402 and the interconnect structure 404 . The semiconductor device 412 includes a corresponding pair of source/drain regions 414 , a corresponding gate electrode 416 and a corresponding gate dielectric layer 418 . The gate electrode 416 corresponds to the pair of source/drain regions 414 and is sandwiched laterally between the corresponding pair of source/drain regions. A gate dielectric layer 418 each underlies the gate electrode 416 , separating the gate electrode 416 from the semiconductor substrate 402 . The semiconductor device 412 may be, for example, a metal-oxide-semiconductor (MOS) FET or some other suitable semiconductor device. In addition, semiconductor devices 412 may implement read and write circuitry for 3D memory array 202 , for example.

A trench isolation structure 420 extends into the semiconductor substrate 402 to provide electrical isolation between the semiconductor device 412 and another semiconductor device (not shown) on the semiconductor substrate 402 . The trench isolation structure 420 may be or include, for example, silicon oxide and/or some other suitable dielectric. Further, the trench isolation structure 420 may be or include, for example, a shallow trench isolation (STI) structure and/or some other suitable type of trench isolation structure.

Although the 3D memory array 202 of FIGS. 4A-4C is configured according to FIGS. 2A-2C , the 3D memory array 202 may alternatively be in accordance with any of FIGS. 3A-3E or some other suitable 3D memory array. can be configured negatively.

5 , a perspective view 500 of some embodiments of a pair of neighboring rows in the 3D memory array 202 of FIGS. 4A-4C is provided. A row has a corresponding top word line (TWL) with a subscript indicating a specific row number starting at row m, where m is an integer value. A column has a corresponding bit line BL and a corresponding source line SL with a subscript indicating a specific column number starting in column n, where n is an integer value.

A top word line TWL correspondingly extends along the row and is electrically coupled to the MFMIS memory cell 102 of the corresponding row through the control gate electrode 114 of the corresponding row. The bit lines BL and the source lines SL correspondingly extend along the columns, and through the lower and upper source/drain regions 1101 and 110u in the corresponding columns, the MFMIS memory cells 102 in corresponding columns. ) (see, for example, FIGS. 4A-4C ). Collectively, top word line TWL, bit line BL, and source line SL facilitate read and write operations to the MFMIS memory cell 102 .

6A and 6B, of the IC of FIGS. 4A-4C in which the word line is electrically coupled to the control gate electrode 114 at the bottom of the 3D memory array 202 and the top of the 3D memory array 202, respectively. Cross-sectional views 600A, 600B of some alternative embodiments are provided. The cross-sectional view 600A of FIG. 6A corresponds to the cross-sectional view 400A of FIG. 4A , and the cross-sectional view 600B of FIG. 6B corresponds to the cross-sectional view 400B of FIG. 4B .

The control gate electrodes of the even rows are electrically coupled to the bottom word line (BWL) at the bottom of the 3D memory array 202 , and the control gate electrodes of the odd rows are the top word lines (TWL) at the top of the 3D memory array 202 . electrically coupled to, or vice versa. In addition, the control gate electrode 114 has a different cross-sectional profile depending on whether it is electrically coupled to a top word line or a bottom word line. Control gate electrodes electrically coupled to the bottom word lines BWL each protrude from the bottom word lines BWL and have a protrusion defining the bottom electrode vias BEV. The control gate electrodes electrically coupled to the top word lines TWL face upward and have no downward protrusions, and are electrically coupled to the top word lines TWL by the top electrode vias TEV.

By splitting the word lines between the bottom of the 3D memory array 202 and the top of the 3D memory array 202, the pitch of the word lines in the Y direction (eg, into and out of a page; for example, FIG. 4C ) ) can be reduced. Design constraints regarding the spacing of word lines can otherwise limit the pitch. By reducing the pitch of the word lines, the scaling down of the 3D memory array 202 can be improved.

7A and 7B , cross-sectional views 700A, 700B of some alternative embodiments of the IC of FIGS. 6A and 6B are provided wherein the bottom electrode vias BEV are independent of the control gate electrodes 114 . Control gate electrodes 114 have the same or substantially the same profile whether electrically coupled to top or bottom word lines. A control gate electrode 114 also extends through the cap dielectric layer 702 between the 3D memory array 202 and the bottom electrode via BEV. Control gate electrodes electrically coupled to the bottom word lines BWL extend through the cap dielectric layer 702 to the bottom electrode vias BEV, respectively. Control gate electrodes electrically coupled to the top word lines TWL extend through the cap dielectric layer 702 into the interconnect dielectric layer 406 . The cap dielectric layer 702 may be or include, for example, silicon nitride and/or some other suitable dielectric.

A plurality of spacers 704 separate the control gate electrode 114 from the ferroelectric layer 116 , and a dielectric structure 118 protrudes through the cap dielectric layer 702 into the interconnect dielectric layer 406 . Spacers 704 may be or include, for example, silicon nitride and/or some other suitable dielectric.

As will be seen later, the spacers 704 may be formed by a self-aligning process and may be used with the top of the array dielectric layer 216 as a mask to form the opening through which the control gate electrode 114 is formed. . This may reduce the number of photomasks used while forming the 3D memory array 202 . Since photolithography is expensive, the reduction can lead to substantial cost savings. Further, as will be described later, the spacer 704 protects the ferroelectric layer 116 while forming an opening in which the control gate electrode 114 is formed. This in turn may reduce the possibility of damage to the ferroelectric layer 116 and thus improve the performance of the MFMIS memory cell 102 . In addition, by forming the bottom electrode via BEV independently of the control gate electrode 114 , the aspect ratio (ratio of height to width) of the opening in which the control gate electrode 114 is formed may be reduced. This in turn can reduce the complexity of the etch used to form the opening and widen the process window (eg, elasticity).

Although the embodiment of the IC in FIGS. 6A and 6B and 7A and 7B is not accompanied by a top view, it should be understood that the top view 400C of FIG. 4C represents such a top view with slight modifications. The top electrode vias (TEV) and the top word line (TWL) in the even or odd rows instead correspond to the bottom electrode vias (BEV) and the bottom word line (BWL) and thus should be shown imaginary, but not both. . Also, the size of the electrode via and/or the shape of the electrode via may be different. Thus, the cross-sectional views 600A, 700A of FIGS. 6A and 7A may be taken along line D in FIG. 4C (as modified above), for example, and the cross-sectional views 600B, 700B of FIGS. 6B and 7B . ) may be taken along line E in FIG. 4C (as modified above).

8A and 8B through 15A and 15B, 16A-16C, and 17A-17B, a series of some embodiments of a method of forming an IC including a 3D memory array of MFMIS memory cells is a series of view is provided. The drawing labeled with the suffix b shows a cross-sectional view taken along line A" in a drawing of similarly numbered suffix a with the suffix a. If present, the drawing labeled with the suffix c is taken from the drawing with the suffix a on line B Shows a cross-sectional view taken along ". The drawing with the suffix a represents a plan view along the line G, G' or G" (whichever exists) in the like numbered drawing with the suffix b and the similarly numbered drawing with the suffix c if present. Although illustrated using embodiments of ICs in FIGS. 4A-4C , other suitable embodiments may be formed.

A semiconductor device 412 and a trench isolation structure 420 are formed on a semiconductor substrate 402 , as illustrated by top and cross-sectional views 800A and 800B of FIGS. 8A and 8B . The semiconductor device 412 includes a pair of source/drain regions 414 , a gate electrode 416 and a gate dielectric layer 418 . A gate electrode 416 and a gate dielectric layer 418 are stacked between the source/drain regions 414 . A trench isolation structure 420 surrounds the semiconductor device 412 and electrically isolates the semiconductor device 412 from other semiconductor devices (not shown).

As illustrated by top and cross-sectional views 800A, 800B of FIGS. 8A and 8B , an interconnect structure 404 is partially formed over a semiconductor device 412 and a semiconductor substrate 402 . The interconnect structure 404 includes a bottom interconnect dielectric layer 406a, a plurality of bottom wires 408a, and a plurality of bottom vias 410a. Bottom wires 408a and bottom vias 410a are alternately stacked in bottom interconnect dielectric layer 406a and a conductive path leading from semiconductor device 412 and other semiconductor devices (not shown) on semiconductor substrate 402 . define them

As illustrated by top and cross-sectional views 900A, 900B of FIGS. 9A and 9B , a first memory film 902a and a second memory film 902b are deposited over the interconnect structure 404 (eg, 8a and 8b). For convenience of illustration, only the top portion of the interconnect structure 404 corresponding to the lower interconnect dielectric layer 406a is shown. The remainder of the interconnect structure 404 is as shown in FIGS. 8A and 8B . The first and second memory films 902a and 902b are vertically stacked corresponding barrier layers 214, corresponding metal layers 212, corresponding source/drain layers 904, and corresponding source/drain dielectric layers 118a. ) and a corresponding array dielectric layer 216 .

Metal layers 212 are each interposed between two barrier layers 214 , which barrier layers 214 are configured to prevent out-diffusion of material from the corresponding metal layers. The source/drain dielectric layers 118a are each interposed between the two source/drain layers 904 , and the two source/drain layers are respectively interposed between the two metal layers 212 . The array dielectric layer 216 is a different material from the material of the lower interconnect dielectric layer 406a at the top surface of the lower interconnect dielectric layer 406a. Also, an array dielectric layer 216 is on top of the first and second memory films 902a and 902b, respectively.

In some embodiments, source/drain layer 904 is or includes doped polysilicon and/or some other suitable semiconductor material. In some embodiments, the source/drain dielectric layer 118a is or includes silicon oxide and/or some other suitable dielectric. In some embodiments, metal layer 212 is or includes tungsten and/or some other suitable metal. In some embodiments, the barrier layers 214 are or include titanium nitride, tungsten nitride, some other suitable barrier material to the metal layers 212 , or any combination thereof. In some embodiments, the array dielectric layer 216 is or includes silicon nitride and/or some other suitable dielectric.

Although two memory films are stacked and deposited over the interconnect structure 404 , more or fewer memory films may be deposited in alternative embodiments. For example, the second memory film 902b can be omitted, so that only a single memory film can be deposited. As another example, the second memory film 902b may be repeatedly deposited, so that three or more memory films may be deposited. In an alternative embodiment, the barrier layer 214 and the metal layer 212 may be omitted to form a 3D memory array according to FIG. 3A . In an alternative embodiment, a silicide layer may be deposited in place of barrier layer 214 and metal layer 212 to form a 3D memory array according to FIG. 3C . In an alternative embodiment, a silicide layer may be deposited in place of barrier layer 214 , metal layer 212 and source/drain layer 904 to form a 3D memory array according to FIG. 3D .

As illustrated by the top and cross-sectional views 1000A, 1000B of FIGS. 10A and 10B , the first and second memory films 902a and 902b are patterned to form a plurality of trenches 1002 . Trench 1002 extends laterally parallel to cross-section 1000A of FIG. 10A (eg, in the Y-direction). In some embodiments, the direction is the direction in which the columns of the 3D memory array being formed extend and/or the trenches 1002 have the same or substantially the same dimensions as each other. The patterning also divides the source/drain layer 904 into a lower source/drain region 110l and an upper source/drain region 110u, and divides the metal and barrier layers 212 and 214 into a metal line 210. . The lower source/drain regions 110l are on the lower sides of the corresponding source/drain dielectric layers, and the upper source/drain regions 110u are on the upper sides of the corresponding source/drain dielectric layers. The patterning may be performed, for example, by a photolithography/etching process and/or some other suitable patterning process. The photolithography/etch process may use, for example, dry etching and/or some other suitable type of etching.

As illustrated by the top and cross-sectional views 1100A, 1100B of FIGS. 11A and 11B , the source/drain dielectric layer 118a is laterally recessed through the trench 1002 . The recessing recesses the sidewalls of the source/drain dielectric layer 118a with respect to neighboring sidewalls of the lower and upper source/drain regions 110l and 110u to form a recess 1102 having a _{lateral depth D 2 .} . Note that recess 1102 is shown phantom in FIG. 11A . In some embodiments, the lateral depth D ₂ is about 10-30 nanometers, about 10-20 nanometers, about 20-30 nanometers, or any other suitable depth. Side recessing may be performed, for example, by wet etching and/or some other suitable type of etching.

In an alternative embodiment, the metal line 210 is further recessed laterally through the trench 1002 to form the 3D memory array according to FIG. 3B . This additional recessing recesses the sidewalls of the metal line 210 with respect to the neighboring sidewalls of the lower and upper source/drain regions 110l and 110u, forming additional recesses. The additional recesses are then filled in the same manner as described below for recess 1102 .

As illustrated by the top and cross-sectional views 1200A and 1200B of FIGS. 12A and 12B , the semiconductor layer 1202 , the gate dielectric layer 106 and the internal electrode layer 1204 (collectively the recessed layer) are formed in the trench 1002 ) (see, for example, FIGS. 11A and 11B ) and the recess 1102 (see, for example, FIGS. 11A and 11B ). A semiconductor layer 1202 and a gate dielectric layer 106 are formed lining and partially filling the trench 1002 and the recess 1102 . The semiconductor layer 1202 also separates the gate dielectric layer 106 from the first and second memory films 902a and 902b. An inner electrode layer 1204 is formed over the gate dielectric layer 106 to fill the remainder of the trench 1002 and the recess 1102 .

In some embodiments, the thickness T _s of the semiconductor layer 1202 is between about 5 and 7 nanometers and/or any other suitable value. Further, in some embodiments, semiconductor layer 1202 is or includes doped or undoped polysilicon and/or some other suitable semiconductor material. In some embodiments, the thickness (T _gd ) of the gate dielectric layer 106 is between about 1 and 5 nanometers and/or any other suitable value. Further, in some embodiments, the gate dielectric layer 106 is or includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, lanthanum oxide, zirconium oxide, some other suitable dielectric, or any combination of the foregoing. do. In some embodiments, the inner electrode layer 1204 is or includes titanium nitride, doped polysilicon, tantalum nitride, tungsten, some other suitable conductive material, or any combination of the foregoing.

A process for forming the recess layers includes, for example, 1) depositing a semiconductor layer 1202; 2) depositing a gate dielectric layer 106; 3) depositing an inner electrode layer 1204; and 4) planarizing the recess layers until reaching the array dielectric layer 216 of the second memory film 902b. Alternatively, other suitable processes may form the recess layer. Planarization may be performed, for example, by chemical mechanical polish (CMP) or any other suitable planarization.

As illustrated by the top and cross-sectional views 1300A, 1300B of FIGS. 13A and 13B , the trench 1002 is cleared. However, the recess 1102 (see, eg, FIGS. 11A and 11B ) is not cleared or is minimally cleared. By doing so, a plurality of semiconductor channels 104 are formed localized in the recess 1102 from the semiconductor layer 1202 (see, for example, FIGS. 12A and 12B ). Further, the inner electrode layer 1204 and the gate dielectric layer 106 are divided into a plurality of inner electrode segments and a plurality of gate dielectric segments each localized in the recess 1102 . Clearing may be performed, for example, by dry etching and/or some other suitable type of etching. Alternatively, other suitable processes for clearing trench 1002 may be performed, for example. In some embodiments, the array dielectric layer 216 of the second memory film 902b is used as a mask during etching.

A ferroelectric layer 116 and a control electrode layer 1402 (collectively a trench layer) are formed while filling the trench 1002, as illustrated by the top and cross-sectional views 1400A and 1400B of FIGS. 14A and 14B. The ferroelectric layer 116 is formed lining and partially filling the trench 1002 , and the control electrode layer 1402 is formed over the ferroelectric layer 116 and filling the remainder of the trench 1002 . In some embodiments, the control electrode layer 1402 is or includes titanium nitride, doped polysilicon, tantalum nitride, tungsten, some other suitable conductive material, or any combination of the foregoing. In some embodiments, ferroelectric layer 116 is or includes doped hafnium oxide (eg, doped with aluminum, silicon, zirconium, lanthanum, strontium, etc.) and/or some other suitable ferroelectric material.

The process for forming the trench layers includes, for example, 1) depositing a ferroelectric layer 116; 2) depositing a control electrode layer 1402 over the ferroelectric layer 116; and 3) performing planarization with the control electrode layer 1402 until reaching the ferroelectric layer 116 . Alternatively, other suitable processes may form the trench layer. Planarization may be performed, for example, by CMP or some other suitable planarization.

As illustrated by the top and cross-sectional views 1500A and 1500B of FIGS. 15A and 15B , a first interlayer extending through the control electrode layer 1402 and dividing the control electrode layer 1402 into a plurality of control gate electrodes 114 . - A gate dielectric layer 118b is formed. The first inter-gate dielectric layer 118b may be or include, for example, silicon oxide and/or any other suitable dielectric. The control gate electrode 114 has a plurality of rows and a plurality of rows, such that the control gate electrodes occur in every other column along each row and the control gate electrodes occur in every other row along each column. arranged in columns. Further, the control gate electrodes 114 are staggered along neighboring columns and neighboring rows so that the pitch P _y of the control gate electrodes 114 in the Y direction spans the rows and the control gate electrodes 114 in the X direction. The pitch P _x spans the column. In some embodiments, the control gate electrode 114 has _{an individual width W cg in the} Y direction that is less than about half the _{pitch P y} in the Y direction.

The process of forming the first inter-gate dielectric layer 118b includes, for example, 1) patterning the control electrode layer 1402 to form an opening dividing the control electrode layer 1402 into the control gate electrode 114 . step; 2) depositing a dielectric layer filling the opening; and 3) performing planarization into the dielectric layer until the ferroelectric layer 116 is exposed. In an alternative embodiment, the first inter-gate dielectric layer 118b is formed by some other suitable process. The patterning may be performed, for example, by a photolithography/etching process and/or any other suitable patterning process. The photolithography/etch process may use, for example, the ferroelectric layer 116 as an etch stop and/or may use dry etching and/or any other suitable type of etching.

As illustrated by the top and cross-sectional views 1600A-1600C of FIGS. 16A-16C , a second inter-electrode layer 1204 , a ferroelectric layer 116 , and a second inter-gate dielectric layer 118b extending through the first inter-gate dielectric layer 118b. A gate dielectric layer 118c is formed. The second inter-gate dielectric layer 118c has a plurality of dielectric segments 1602 that divide the inner electrode layer 1204 into a plurality of inner gate electrodes 108 . Dielectric segments 1602 are arranged alternately with control gate electrodes 114 along each row and along each column. In some embodiments, dielectric segment 1602 has an individual width (W _{d ) of less than about half the Y-direction pitch (P y} ), and/or has a Y-direction pitch (P _y ) with neighboring inner gate electrodes in a row. separated by _{a distance (D 1} ) less than about half of Second inter-gate dielectric layer 118c and thus dielectric segments 1602 may be or include, for example, silicon oxide and/or some other suitable dielectric.

The process of forming the second inter-gate dielectric layer 118c includes, for example, 1) the inner electrode layer 1204, the ferroelectric layer to form an opening dividing the inner electrode layer 1204 into the inner gate electrode 108 . patterning (116) and the first inter-gate dielectric layer (118b); 2) depositing a dielectric layer filling the opening; and 3) performing planarization into the dielectric layer until the ferroelectric layer 116 is exposed. In an alternative embodiment, the second inter-gate dielectric layer 118c is formed by some other suitable process. The patterning may be performed, for example, by a photolithography/etching process and/or some other suitable patterning process. The photolithography/etch process may use, for example, the lower interconnect dielectric layer 406a as an etch stop, and/or may use, for example, dry etching and/or some other suitable type of etching.

After forming the second inter-gate dielectric layer 118c and dividing the internal electrode layer 1204 into a plurality of internal gate electrodes 108, the first memory array 204a and the second memory array 204b are completed. The first and second memory arrays 204a and 204b are stacked vertically over the lower interconnect dielectric layer 406a and are comprised of a plurality of MFMIS memory cells 102 . Each MFMIS memory cell 102 has a respective inner gate electrode 108 and a localized portion of the ferroelectric layer 116 . The localized portion of the ferroelectric layer 116 has a polarity representing the bit of data.

During program and erase operations on any one of the MFMIS memory cells 102, the MFMIS memory cells are electrically coupled in series with a MIS parallel plate capacitor (simply a MIS capacitor) and a ferroelectric parallel plate capacitor (simply a ferroelectric capacitor). can be modeled as The inner gate electrode 108 of the MFMIS memory cell and the semiconductor channel 104 of the MFMIS memory cell define the parallel plates of the MIS capacitor, and the gate dielectric layer 106 defines the insulator of the MIS capacitor. The inner and control gate electrodes 108 and 114 of the MFMIS memory cell define the parallel plates of the ferroelectric capacitor, and the ferroelectric layer 116 defines the insulator of the ferroelectric capacitor. In both MIS capacitors and ferroelectric capacitors, the parallel plates are parallel to cross-section 1600C in FIG. 16C.

The capacitor area of a parallel plate capacitor corresponds to the overlap between each of the opposite surfaces of the parallel plate when both surfaces are projected onto a two-dimensional (2D) plane parallel to the two surfaces. Due to the internal gate electrode 108 , the ferroelectric capacitor of the MFMIS memory cell 102 may have a different capacitor area than the MIS capacitor of the MFMIS memory cell 102 . If the inner gate electrode 108 is omitted, the ferroelectric capacitor and the MIS capacitor will share the same parallel plates and thus will share the same capacitor area. Also, as described above, the acts (acts) of FIGS. 15A and 15B and FIGS. 16A and 16C show the individual width W _cg of the control gate electrode 114 and the individual width W of the inner gate electrode 108 . _ig ) can be independently defined. For example, the operation of FIGS. 15A and 15B _{can be used to define an individual width W cg} of the control gate electrode 114 , while the operation of FIGS. 16A-16C is the operation of the inner gate electrode 108 . It can be used to define an individual width (W _{ig ).} Thus, the capacitor regions of the ferroelectric and MIS capacitors can be tuned independently through _{the respective widths W ig} , W _{cg of the inner and control gate electrodes 108 .}

Because the ferroelectric and MIS capacitors for any one of the MFMIS memory cells 102 are electrically coupled in series during program and erase operations, the electric field ratio for the ferroelectric and MIS capacitors is the inverse of the dielectric constant ratio and the inverse of the capacitor area ratio. equal to the product Accordingly, the electric field ratio can be tuned by the dielectric constant ratio and/or the capacitor area ratio. The dielectric constant is a material dependent parameter, and material constraints may limit the tuning of the electric field ratio based on the dielectric constant. _{However, the individual widths W ig} , W _{cg of the} inner and control gate electrodes 108 , 114 and thus the capacitor area can be tuned by the method of forming the MFMIS memory cell 102 . Accordingly, the electric field ratio can be adjusted based on the capacitor area during the method of forming the MFMIS memory cell 102 .

Because the electric field ratio can be tuned, the ferroelectric layer 116 can have a high electric field during program and erase operations, while the gate dielectric layer 106 can have a low electric field during program and erase operations. Since the ferroelectric layer 116 can have a high electric field, the polarization of the ferroelectric layer 116 can switch strongly during program and erase operations. As a result, the difference between the read currents while the ferroelectric layer 116 is in each programmed and erased state can be large (eg, the memory window can be large). In addition, since the ferroelectric layer 116 may have a high electric field, program and erase voltages may be low, and thus power consumption may be low. Because the gate dielectric layer 106 can have a low electric field, the stress on the gate dielectric layer 106 can be low. This in turn may improve the reliability of the gate dielectric layer 106 and the TDDB of the gate dielectric layer 106 . Accordingly, durability of the MFMIS memory cell 102 and retention of the MFMIS memory cell 102 can be improved.

As illustrated by the top and cross-sectional views 1700A, 1700B of FIGS. 17A and 17B , the interconnect structure 404 is complete. An upper interconnect dielectric layer 406b is formed over the first and second memory arrays 204a and 204b, and a plurality of upper wires 408b and a plurality of upper vias 410b are stacked in the upper interconnect dielectric layer 406b to form a stack. . At least some of the upper wires 408b define top word lines TWL, and at least some of the upper vias 410b define top electrode vias TEV. The top word line TWL correspondingly extends along the row of the control gate electrode 114 , and the top electrode via TEV extends from the top word line TWL to the control gate electrode 114 , respectively.

8A and 8B to 15A and 15B, 16A to 16C, and 17A and 17B are described with reference to various embodiments of the method, and FIGS. 8A and 8B to 15A and 15B, 16A It will be understood that the structures shown in FIGS. 16C, and 17A and 17B are not limited to methods and may be independent of methods. 8A and 8B to 15A and 15B, 16A to 16C, and 17A and 17B are described as a series of operations, but it will be understood that the order of operations may be changed in other embodiments. 8A and 8B through 15A and 15B, 16A-16C, and 17A and 17B show and describe as specific sets of acts, some acts shown and/or described may be omitted in other embodiments. have. Also, operations not shown and/or described may be included in other embodiments.

Referring to FIG. 18 , a block diagram 1800 of some embodiments of the methods from FIGS. 8A and 8B through FIGS. 15A and 15B , 16A-16C , and 17A and 17B is provided.

At 1802 , an interconnect structure is partially formed over the semiconductor device and the semiconductor substrate. See, for example, FIGS. 8A and 8B.

At 1804 , a memory film is deposited over the interconnect structure, wherein the memory film includes a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers. See, for example, FIGS. 9A and 9B.

At 1806 , the memory film is patterned to form a plurality of trenches extending laterally in parallel in a first direction. See, for example, FIGS. 10A and 10B.

At 1808 , sidewalls of the source/drain dielectric layer in the trench are laterally recessed in a second direction transverse to the first direction to form a recess. See, for example, FIGS. 11A and 11B.

At 1810, a semiconductor layer and a gate dielectric layer are deposited lining and partially filling the trenches and recesses. See, for example, FIGS. 12A and 12B.

At 1812 , an inner electrode layer is deposited filling the remainder of the trench and recess. See, for example, FIGS. 12A and 12B.

At 1814 , the semiconductor layer, the gate dielectric layer, and the inner electrode layer are patterned to clear the trench, leaving the semiconductor layer, the gate dielectric layer, and the inner electrode layer in the recess. See, for example, FIGS. 13A and 13B.

At 1816, a ferroelectric layer is deposited lining and partially filling the trench. See, for example, FIGS. 14A and 14B .

At 1818, a control electrode layer is deposited filling the remainder of the trench. See, for example, FIGS. 14A and 14B .

At 1820, the control electrode layer is patterned to divide the control electrode layer into a plurality of control gate electrodes of a plurality of rows and a plurality of columns. See, for example, FIGS. 15A and 15B.

At 1822, the inner electrode layer is patterned to divide the inner electrode layer into a plurality of inner gate electrodes confined in the recess. See, for example, FIGS. 16A-16C.

At 1824, an interconnect structure is completed over the memory film and control gate electrode. See, for example, FIGS. 17A and 17B .

Although the block diagram 1800 of FIG. 18 is illustrated and described herein as a series of acts or events, it will be understood that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some acts may occur in a different order and/or concurrently with other acts or events than those shown and/or described herein. Moreover, not all acts shown may be required to implement one or more aspects or embodiments of the description herein, and one or more acts shown herein may be performed in one or more separate acts and/or phases. can

19A and 19B through 24A and 24B, 25A-25C, and 26A and 26B, word lines represent a 3D memory array of MFMIS memory cells at the bottom and top of the 3D memory array, respectively. A series of drawings of some embodiments of a method of forming an IC comprising The drawing labeled with the suffix b shows a cross-sectional view taken along line A''' in a drawing of similar number with the suffix a. The drawing labeled with the suffix c, where present, represents a cross-sectional view taken along line B''' in the figure of like number with the suffix a. The drawing with the suffix a represents a top view along the line H, H' or H" (whichever exists) in the similarly numbered drawing with the suffix b and the similarly numbered drawing with the suffix c if present. Although illustrated using embodiments of ICs in FIGS. 7A and 7B , other suitable embodiments may be formed.

As illustrated by the top and cross-sectional views 1900A, 1900B of FIGS. 19A and 19B , the semiconductor device 412 and the trench isolation structure 420 are connected to the semiconductor substrate 402 as shown and described in FIGS. 8A and 8B . ) is formed on

As illustrated by top and cross-sectional views 1900A, 1900B of FIGS. 19A and 19B , an interconnect structure 404 is formed in part over a semiconductor device 412 and a semiconductor substrate 402 . The interconnect structure 404 includes a bottom interconnect dielectric layer 406a, a cap dielectric layer 702, a plurality of bottom wires 408a, and a plurality of bottom vias 410a. Bottom wires 408a and bottom vias 410a are alternately stacked in bottom interconnect dielectric layer 406a and a conductive path leading from semiconductor device 412 and other semiconductor devices (not shown) on semiconductor substrate 402 . define them Further, the bottom wires 408a define bottom word lines BWL at the top of the interconnect structure 404 , and the bottom vias 410a have bottom electrode vias respectively overlying the bottom word lines BWL. BEV). The cap dielectric layer 702 covers the bottom interconnect dielectric layer 406a and the bottom electrode via (BEV).

The operations in FIGS. 9A and 9B through 13A and 13B are performed as illustrated by the top and cross-sectional views 2000A and 2000B of FIGS. 20A and 20B . Note that, for convenience of illustration, only the upper portion of the interconnect structure 404 is shown. The remainder of the interconnect structure 404 is as shown in FIGS. 19A and 19B .

According to the operation in FIGS. 9A and 9B through 13A and 13B , the first memory film 902a and the second memory film 902b are interconnect structure 404 as shown and described in FIGS. 9A and 9B . ) is deposited on The first and second memory films 902a and 902b are patterned to form a plurality of trenches 1002 as shown and described in FIGS. 10A and 10B . Source/drain dielectric layer 118a is laterally recessed through trench 1002 to form recess 1102 as shown and described in FIGS. 11A and 11B . 12A and 12B, the semiconductor layer 1202, the gate dielectric layer 106, and the inner electrode layer 1204 form a trench 1002 (see, e.g., FIGS. 11A and 11B) and a recess (see FIGS. 1102) (see, for example, FIGS. 11A and 11B ). As illustrated in FIGS. 13A and 13B , trench 1002 is cleared.

As illustrated by top and cross-sectional views 2100A and 2100B of FIGS. 21A and 21B , a ferroelectric layer 116 is deposited lining and partially filling the trench 1002 . Further, a spacer layer 2102 is deposited over the ferroelectric layer 116 lining and partially filling the trench 1002 . The spacer layer 2102 may be or include, for example, silicon nitride and/or any other suitable dielectric.

An etching process is performed into the spacer layer 2102, the ferroelectric layer 116, and the cap dielectric layer 702 to leave the trench 1002 at the bottom, as illustrated by the top and cross-sectional views 2200A, 2200B of FIGS. 22A and 22B. It extends to the electrode via (BEV). Initially, the spacer layer 2102 is etched back and spacers 704 are formed from the spacer layer 2102 on the sidewalls of the trench 1002 . Thereafter, the spacer 704 and the array dielectric layer 216 of the second memory film 902b function as a mask while etching through the cap dielectric layer 702 and the ferroelectric layer 116 . These two steps of the etching process may be performed, for example, by the same etching or by different etchings.

In an alternative embodiment, instead of forming the spacer layer 2102 in FIGS. 21A and 21B and subsequently performing the etching process in FIGS. 22A and 22B , a photolithography/etching process is performed into the bottom electrode vias (BEV), respectively. may be performed to form an opening at the bottom of the extending trench 1002 . The method may then proceed as described hereinafter. These alternative embodiments may be used, for example, to form an IC according to the embodiment of FIGS. 6A and 6B.

As illustrated by the top and cross-sectional views 2300A and 2300B of FIGS. 23A and 23B , the control electrode layer 1402 is formed while filling the trench 1102 as shown and described in FIGS. 14A and 14B .

The first inter-gate dielectric layer 118b extends through the control electrode layer 1402 and is illustrated and described in FIGS. 15A and 15B, as illustrated by the top and cross-sectional views 2400A, 2400B of FIGS. It is formed by dividing the control electrode layer 1402 into a plurality of control gate electrodes 114 as described above.

As illustrated by the top and cross-sectional views 2500A-2500C of FIGS. 25A-25C , the second inter-gate dielectric layer 118c is an internal electrode layer 1204, a ferroelectric, as shown and described in FIGS. 16A-B. It is formed and extends through the layer 116 , the spacers 704 and the first inter-gate dielectric layer 118b. The second inter-gate dielectric layer 118c divides the inner electrode layer 1204 into a plurality of inner gate electrodes 108 .

After forming the second inter-gate dielectric layer 118c and dividing the internal electrode layer 1204 into a plurality of internal gate electrodes 108, the first memory array 204a and the second memory array 204b are completed. The first and second memory arrays 204a and 204b are stacked vertically over the lower interconnect dielectric layer 406a and are comprised of a plurality of MFMIS memory cells 102 . Each MFMIS memory cell 102 has a respective inner gate electrode 108 and further has a localized portion of a ferroelectric layer 116 . The localized portion of the ferroelectric layer 116 has a polarity representing the bit of data.

As illustrated by the top and cross-sectional views 2600A, 2600B of FIGS. 26A and 26B , the interconnect structure 404 is completed as shown and described in FIGS. 17A and 17B . In contrast to FIGS. 17A and 17B , top word lines TWL and top electrode vias TEV are formed in even or odd rows, but not both.

19A and 19B through 24A and 24B, 25A-25C, and 26A and 26B are described with reference to various embodiments of the method, but from FIGS. 19A and 19B through FIGS. 24A and 24B, 25A It will be understood that the structures shown in FIGS. 25C through 26A and 26B are not limited to a method and may be independent of a method. 19A and 19B to 24A and 24B, 25A to 25C, and 26A and 26B are described as a series of operations, but it will be understood that the order of operations may be changed in other embodiments. 19A and 19B through 24A and 24B, 25A-25C, and 26A and 26B show and describe as a set of specific operations, some operations shown and/or described may be omitted in other embodiments. can Also, operations not shown and/or described may be included in other embodiments.

Referring to FIG. 27 , a block diagram 2700 of some embodiments of the methods from FIGS. 19A and 19B through FIGS. 24A and 24B , 25A-25C , and 26A and 26B is provided.

At 2702 , an interconnect structure is partially formed over the semiconductor device and the semiconductor substrate, the interconnect structure comprising a bottom electrode wire and a bottom electrode via overlying each bottom electrode wire on top of the interconnect structure. See, for example, FIGS. 19A and 19B.

At 2704 , a memory film is deposited over the interconnect structure, wherein the memory film includes a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers. See, for example, FIGS. 20A and 20B.

At 2706 , the memory film is patterned to form a plurality of trenches extending laterally in parallel in a first direction. See, for example, FIGS. 20A and 20B.

At 2708 , sidewalls of the source/drain dielectric layer in the trench are laterally recessed in a second direction transverse to the first direction to form a recess. See, for example, FIGS. 20A and 20B.

At 2710 , a semiconductor layer, a gate dielectric layer, and an internal electrode layer are deposited filling the trenches and recesses. See, for example, FIGS. 20A and 20B.

At 2712 , the semiconductor layer, the gate dielectric layer, and the inner electrode layer are patterned to clear the trench, and the semiconductor layer, the gate dielectric layer, and the inner electrode remain in the recess. See, for example, FIGS. 20A and 20B.

At 2714, a ferroelectric layer and a spacer layer are deposited lining and partially filling the trench. See, for example, FIGS. 21A and 21B .

At 2716, an etch is performed to etch back the spacer layer and extend the trench into the bottom electrode via. See, for example, FIGS. 22A and 22B.

At 2718 , a control electrode layer is deposited filling the trench. See, for example, FIGS. 23A and 23B.

At 2720 , the control electrode layer is patterned to divide the control electrode layer into a plurality of control gate electrodes of a plurality of rows and a plurality of columns. See, for example, FIGS. 24A and 24B.

At 2722 , the inner electrode layer is patterned to divide the inner electrode layer into a plurality of inner gate electrodes confined in the recess. See, for example, FIGS. 25A-25C.

At 2724 , an interconnect structure is completed over the memory film and the control gate electrode. See, for example, FIGS. 26A and 26B.

Although the block diagram 2700 of FIG. 27 is illustrated and described herein as a series of acts or events, it will be understood that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some acts may occur in a different order and/or concurrently with other acts or events than those shown and/or described herein. Moreover, not all acts shown are required to implement one or more aspects or embodiments of the description herein, and one or more acts shown herein may be performed in one or more separate acts and/or steps.

In some embodiments, the present disclosure provides a memory device comprising: a first source/drain region and a second source/drain region overlying the first source/drain region; an internal gate electrode and a semiconductor channel overlying the first source/drain region and under the second source/drain region, the semiconductor channel extending from the first source/drain region to the second source/drain region; a gate dielectric layer between the inner gate electrode and the semiconductor channel and bordering the inner gate electrode and the semiconductor channel; a control gate electrode opposite the semiconductor channel of the inner gate electrode and not covered by the second source/drain region; and a ferroelectric layer between the control gate electrode and the inner gate electrode and in contact with the control gate electrode and the inner gate electrode. In some embodiments, the control gate electrode has a first sidewall facing the inner gate electrode, the inner gate electrode has a second sidewall facing the control gate electrode, and the first and second sidewalls have different widths . In some embodiments, the first sidewall has a width that is less than a width of the second sidewall. In some embodiments, the height of the control gate electrode is greater than a vertical separation between a top surface of the second source/drain region and a bottom surface of the first source/drain region. In some embodiments, a gate dielectric layer wraps around a corner of the inner gate electrode from a sidewall of the inner gate electrode to a top surface of the inner gate electrode. In some embodiments, the semiconductor channel has a C-shaped profile that wraps around the side of the inner gate electrode. In some embodiments, the memory device comprises: a second inner gate electrode opposite the ferroelectric layer of the control gate electrode; and a second ferroelectric layer between the second inner gate electrode and the control gate electrode and in contact with the second inner gate electrode and the control gate electrode.

In some embodiments, the present disclosure provides another memory device, comprising: a first source/drain region and a second source/drain region overlying the first source/drain region; a first gate electrode and a semiconductor layer vertically between the first source/drain region and the second source/drain region, the first gate electrode being electrically floating; a gate dielectric layer laterally between the first gate electrode and the semiconductor layer and bordering the first gate electrode and the semiconductor layer, the first gate electrode, the semiconductor and gate dielectric layers, and the first and second source/drain regions having a common sidewall - stipulates ; a ferroelectric layer lining the common sidewall; and a second gate electrode in contact with the ferroelectric layer on a side opposite to the common sidewall of the ferroelectric layer. In some embodiments, the first and second gate electrodes and the semiconductor layer are laterally spaced apart in a first direction, and the first and second gate electrodes have different widths in a second direction orthogonal to the first direction. In some embodiments, the first and second gate electrodes each have a first sidewall and a second sidewall facing each other, the second sidewall being less than a surface area of the first sidewall, the second source from the first source/drain region /drain surface area. In some embodiments, the common sidewalls are defined in part by respective sidewalls of the first and second source/drain regions and individual sidewalls of the first gate electrode, wherein the ferroelectric layer includes separate sidewalls of the first and second source/drain regions. and on respective sidewalls of the first gate electrode. In some embodiments, the second source/drain region completely covers the first gate electrode and the semiconductor layer. In some embodiments, the memory device comprises: a first memory cell defined by first and second source/drain regions, first and second gate electrodes and a semiconductor layer; and a second memory cell overlying the first memory cell and sharing a second gate electrode with the first memory cell.

In some embodiments, the present disclosure provides a method of forming a memory device, the method comprising: depositing over a substrate a memory film comprising a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers; performing a first etch into the memory film to form a trench through the memory film; recessing the sidewalls of the source/drain dielectric layer relative to the sidewalls of the source/drain layer through the trench to form a recess; depositing a semiconductor layer lining the recesses and trenches; depositing a first electrode layer filling the recesses and trenches over the semiconductor layer; performing a second etch into the semiconductor layer and the first electrode layer to clear the semiconductor layer and the first electrode layer from the trench; depositing a ferroelectric layer lining the trench and further lining the first electrode layer and the semiconductor layer in the recess; and depositing a second electrode layer filling the trench over the ferroelectric layer. In some embodiments the method includes performing a third etch into the second electrode layer to form a control gate electrode bordering the first electrode layer; and performing a fourth etch into the first electrode layer to form a floating gate electrode confined in the recess. In some embodiments, the third etch forms the control gate electrode having a sidewall facing the recess to a first width, and the fourth etch forms the floating gate electrode having a sidewall facing the control gate electrode wider than the first width. It is formed with a large second width. In some embodiments the method further comprises depositing a high K gate dielectric layer lining the recesses and trenches between the deposition of the semiconductor layer and the deposition of the first electrode layer. In some embodiments, a semiconductor layer is deposited on the sidewalls of the source/drain dielectric layer and on the sidewalls of the source/drain layer, then cleared from the sidewalls of the source/drain layer by a second etch, the ferroelectric layer being the source/drain dielectric layer and on the sidewalls of the source/drain layers. In some embodiments, the memory film comprises a second pair of source/drain layers overlying the pair of source/drain layers, further comprising a second source/drain dielectric layer between the second source/drain layers, wherein the recessing comprises: The sidewalls of the second source/drain dielectric layer are recessed with respect to the sidewalls of the second source/drain layer through the trench to form a second recess. In some embodiments, the recessing recesses the second sidewall of the source/drain dielectric layer with respect to the second sidewall of the source/drain layer through the trench to form a second recess, the second recess being the recess of the trench Suwa is on the other side.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and changes can be made herein without departing from the spirit and scope of the present disclosure.

<bookkeeping>

1. A memory device comprising:

a first source/drain region and a second source/drain region overlying the first source/drain region;

an internal gate electrode and a semiconductor channel overlying the first source/drain region and under the second source/drain region, the semiconductor channel extending from the first source/drain region to the second source/drain region;

a gate dielectric layer between the inner gate electrode and the semiconductor channel and in contact with the inner gate electrode and the semiconductor channel;

a control gate electrode opposite the semiconductor channel of the inner gate electrode and not covered by the second source/drain region; and

A ferroelectric layer between the control gate electrode and the inner gate electrode and in contact with the control gate electrode and the inner gate electrode

A memory device comprising:

2. The method of clause 1, wherein the control gate electrode has a first sidewall facing the inner gate electrode, the inner gate electrode has a second sidewall facing the control gate electrode, and wherein the first sidewall and the second sidewall have different widths.

3. The memory device of clause 2, wherein the first sidewall has a width less than a width of the second sidewall.

4. The memory device of clause 1, wherein a height of the control gate electrode is greater than a vertical separation between a top surface of the second source/drain region and a bottom surface of the first source/drain region.

5. The memory device of clause 1, wherein the gate dielectric layer wraps around a corner of the inner gate electrode from a sidewall of the inner gate electrode to a top surface of the inner gate electrode.

6. The memory device of claim 1, wherein the semiconductor channel has a C-shaped profile surrounding a side surface of the inner gate electrode.

7. Clause 1,

a second inner gate electrode opposite to the ferroelectric layer of the control gate electrode; and

a second ferroelectric layer between the second inner gate electrode and the control gate electrode and in contact with the second inner gate electrode and the control gate electrode

Further comprising a memory device.

8. A memory device comprising:

a first source/drain region and a second source/drain region overlying the first source/drain region;

a first gate electrode and a semiconductor layer vertically between the first source/drain region and the second source/drain region, the first gate electrode being electrically floating;

a gate dielectric layer laterally between the first gate electrode and the semiconductor layer and adjoining the first gate electrode and the semiconductor layer - the first gate electrode, the semiconductor layer, the gate dielectric layer, the first source/ a drain region, and the second source/drain region defining a common sidewall;

a ferroelectric layer lining the common sidewall; and

a second gate electrode in contact with the ferroelectric layer on a side opposite to the common sidewall of the ferroelectric layer

A memory device comprising:

9. The method of claim 8, wherein the first gate electrode, the second gate electrode, and the semiconductor layer are spaced apart from each other laterally in a first direction, and the first gate electrode and the second gate electrode include: A memory device having a different width in a second direction orthogonal to the first direction.

10. The method of claim 8, wherein the first gate electrode and the second gate electrode each have a first sidewall and a second sidewall facing each other, the second sidewall being the first sidewall from the first source/drain region. and a surface area of up to two source/drain regions, wherein the surface area of the second sidewall is less than the surface area of the first sidewall.

11. The ferroelectric layer of claim 8, wherein the common sidewall is defined in part by individual sidewalls of the first source/drain region and the second source/drain region and individual sidewalls of the first gate electrode, the ferroelectric layer comprising: on respective sidewalls of the first source/drain region and the second source/drain region and on respective sidewalls of the first gate electrode.

12. The memory device of clause 8, wherein the second source/drain region completely covers the first gate electrode and the semiconductor layer.

13. Item 8,

a first memory cell defined by the first source/drain region, the second source/drain region, the first gate electrode, the second gate electrode, and the semiconductor layer; and

a second memory cell overlying the first memory cell and sharing the second gate electrode with the first memory cell

Further comprising a memory device.

14. A method for forming a memory device, comprising:

depositing a memory film over a substrate, the memory film comprising a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers;

performing a first etch into the memory film to form a trench through the memory film;

recessing a sidewall of the source/drain dielectric layer with respect to a sidewall of the source/drain layer through the trench to form a recess;

depositing a semiconductor layer lining the recess and the trench;

depositing a first electrode layer filling the recess and the trench over the semiconductor layer;

performing a second etch into the semiconductor layer and the first electrode layer to clear the semiconductor layer and the first electrode layer from the trench;

depositing a ferroelectric layer lining the trench and also lining the semiconductor layer and the first electrode layer in the recess; and

depositing a second electrode layer filling the trench over the ferroelectric layer;

A method for forming a memory device comprising:

15. Clause 14,

performing a third etching into the inside of the second electrode layer to form a control gate electrode in contact with the first electrode layer; and

performing a fourth etch into the first electrode layer to form a floating gate electrode confined in the recess;

A method for forming a memory device, further comprising:

16. The method of clause 15, wherein the third etch forms the control gate electrode with a first width having a sidewall facing the recess, and the fourth etch has a sidewall facing the control gate electrode. forming the floating gate electrode with a second width greater than the first width.

17. Clause 14,

depositing a high K gate dielectric layer lining the recess and the trench between depositing the semiconductor layer and depositing the first electrode layer;

A method for forming a memory device, further comprising:

18. The semiconductor layer of clause 14, wherein the semiconductor layer is deposited on the sidewalls of the source/drain dielectric layer and the sidewalls of the source/drain layer, subsequently cleared from the sidewalls of the source/drain layer by the second etch. wherein the ferroelectric layer is deposited on sidewalls of the source/drain dielectric layer and on sidewalls of the source/drain layer.

19. The memory film of clause 14, wherein the memory film comprises a second pair of source/drain layers overlying the pair of source/drain layers, further comprising a second source/drain dielectric layer between the second source/drain layers. wherein the recessing comprises recessing a sidewall of the second source/drain dielectric layer with respect to a sidewall of the second source/drain layer through the trench to form a second recess. method to form.

20. The method of clause 14, wherein the recessing comprises: recessing a second sidewall of the source/drain dielectric layer with respect to a second sidewall of the source/drain layer through the trench to form a second recess. and wherein the second recess is opposite the recess of the trench.

Claims (10)

A memory device comprising:
a first source/drain region and a second source/drain region overlying the first source/drain region;
an internal gate electrode and a semiconductor channel overlying the first source/drain region and under the second source/drain region, the semiconductor channel extending from the first source/drain region to the second source/drain region;
a gate dielectric layer between the inner gate electrode and the semiconductor channel and in contact with the inner gate electrode and the semiconductor channel;
a control gate electrode opposite the semiconductor channel of the inner gate electrode and not covered by the second source/drain region; and
A ferroelectric layer between the control gate electrode and the inner gate electrode and in contact with the control gate electrode and the inner gate electrode
A memory device comprising: The method of claim 1 , wherein the control gate electrode has a first sidewall facing the inner gate electrode, the inner gate electrode has a second sidewall facing the control gate electrode, and the first sidewall and the second sidewall has a different width. The memory device of claim 1 , wherein a height of the control gate electrode is greater than a vertical separation between a top surface of the second source/drain region and a bottom surface of the first source/drain region. The memory device of claim 1 , wherein the gate dielectric layer wraps around a corner of the inner gate electrode from a sidewall of the inner gate electrode to a top surface of the inner gate electrode. The memory device of claim 1 , wherein the semiconductor channel has a C-shaped profile that surrounds a side surface of the inner gate electrode. A memory device comprising:
a first source/drain region and a second source/drain region overlying the first source/drain region;
a first gate electrode and a semiconductor layer vertically between the first source/drain region and the second source/drain region, the first gate electrode being electrically floating;
a gate dielectric layer laterally between the first gate electrode and the semiconductor layer and adjoining the first gate electrode and the semiconductor layer - the first gate electrode, the semiconductor layer, the gate dielectric layer, the first source/ a drain region, and the second source/drain region defining a common sidewall;
a ferroelectric layer lining the common sidewall; and
a second gate electrode in contact with the ferroelectric layer on a side opposite to the common sidewall of the ferroelectric layer
A memory device comprising: The method of claim 6 , wherein the first gate electrode, the second gate electrode, and the semiconductor layer are laterally spaced apart from each other in a first direction, and the first gate electrode and the second gate electrode are disposed in the first direction. having a different width in a second direction orthogonal to . 7. The method of claim 6, wherein the first gate electrode and the second gate electrode each have a first sidewall and a second sidewall facing each other, and the second sidewall is the second source from the first source/drain region. /drain area, wherein the surface area of the second sidewall is less than the surface area of the first sidewall. 7. The ferroelectric layer of claim 6, wherein the common sidewall is defined in part by individual sidewalls of the first source/drain region and the second source/drain region and individual sidewalls of the first gate electrode, and wherein the ferroelectric layer comprises the first on respective sidewalls of one source/drain region and the second source/drain region and respective sidewalls of the first gate electrode. A method for forming a memory device, comprising:
depositing a memory film over a substrate, the memory film comprising a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers;
performing a first etch into the memory film to form a trench through the memory film;
recessing a sidewall of the source/drain dielectric layer with respect to a sidewall of the source/drain layer through the trench to form a recess;
depositing a semiconductor layer lining the recess and the trench;
depositing a first electrode layer filling the recess and the trench over the semiconductor layer;
performing a second etch into the semiconductor layer and the first electrode layer to clear the semiconductor layer and the first electrode layer from the trench;
depositing a ferroelectric layer lining the trench and also lining the semiconductor layer and the first electrode layer in the recess; and
depositing a second electrode layer filling the trench over the ferroelectric layer;
A method for forming a memory device comprising:

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