KR20210086346A - Display apparatus having emission regions arranged in pentile - Google Patents

Abstract

The present invention relates to a display device in which emission regions are arranged in a pentile shape. Two emission regions adjacent in a first direction can be connected to one driving part. Two emission regions connected to one driving part can sequentially emit light. Two emission regions adjacent in a second direction perpendicular to the first direction can sequentially emit light. Accordingly, in the display device, the pentile shape is maintained in each frame, and resolution can be improved.

Description

Display apparatus having emission regions arranged in pentile

The present invention relates to a display device in which light emitting regions are arranged in a pentile shape.

BACKGROUND ART In general, electronic devices such as monitors, TVs, notebook computers, and digital cameras include a display device to implement images. For example, the display device may include a light emitting device. The light emitting device may emit light having a specific color. For example, the light emitting device may include a light emitting layer positioned between the first electrode and the second electrode.

The display device may include light emitting regions. The light emitting device may be positioned in each light emitting area. The light emitting regions may be arranged in a pentile shape. For example, the display device may include first rows in which green light emitting regions are positioned and second rows in which red and blue light emitting regions are repeated, wherein the first rows and the second rows are alternately arranged. have.

Each light emitting region may include a driving circuit for controlling the light emitting device. Accordingly, in the display device, each light emitting area should have an area of a predetermined or more. Accordingly, there is a limit to the increase in resolution in the display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of increasing resolution by minimizing an area occupied by a light emitting area.

The problems to be solved by the present invention are not limited to the aforementioned problems. Problems not mentioned herein will be clearly understood by those skilled in the art from the following description.

A display device according to the technical idea of the present invention for achieving the above object includes first pixel areas and second pixel areas. Each first pixel area includes a first driver, a first light emitting area, and a second light emitting area. The first light emitting region exhibits a first color. The second light emitting region exhibits a second color. The first light emitting area and the second light emitting area are positioned side by side in the first direction. Each second pixel area includes a second driver, a third light emitting area, and a fourth light emitting area. The third light emitting region exhibits a first color. The fourth light emitting region exhibits a third color. The third light emitting area and the fourth light emitting area are positioned side by side in the first direction. The first pixel areas and the second pixel areas are alternately positioned in a second direction perpendicular to the first direction. The first upper power supply lines extend obliquely with respect to the first direction. The first light emitting area of each first pixel area and the fourth light emitting area of each second pixel area are connected to first upper power supply lines. The second upper power supply lines extend parallel to the first upper power supply lines. The second light-emitting area of each first pixel area and the third light-emitting area of each second pixel area are connected to the second upper power supply lines. Each light emitting region includes a light emitting layer positioned between the pixel electrode connected to the corresponding driver and the corresponding upper power supply line. The first color, the second color and the third color are different colors.

The first color may be green.

The pixel electrode of the second light emitting area may be positioned on the same layer as the pixel electrode of the first light emitting area. The pixel electrode of the fourth light emitting area may be positioned on the same layer as the pixel electrode of the third light emitting area.

The pixel electrode of the second light emitting area may include the same material as the pixel electrode of the first light emitting area. The pixel electrode of the fourth emission region may include the same material as the pixel electrode of the third emission region.

The second upper power supply lines may be located on the same layer as the first upper power supply lines. The second upper power supply lines may include the same material as the first upper power supply lines.

The gate line may extend in the second direction. The first pixel regions and the second pixel regions may be connected to a single gate line.

A display device according to the technical idea of the present invention includes light-emitting areas arranged in a pentile shape, wherein two light-emitting areas adjacent in a first direction are connected to a single driving unit, and the first direction and a second light-emitting area perpendicular to the first direction Light emitting regions adjacent in two directions may be sequentially driven. Accordingly, in the display device, the pentile shape may be maintained and the area of the driver controlling each light emitting area may be reduced. Accordingly, the resolution may be improved in the display device.

1 is a diagram schematically illustrating a display device according to an embodiment of the present invention.
FIG. 2 is an enlarged view of area K of FIG. 1 .
FIG. 3A is a view showing a cross-section taken along line I-I' of FIG. 2 .
FIG. 3B is a view showing a cross-section taken along line II-II′ of FIG. 2 .
4A is a diagram illustrating light emitting regions driven by a first upper power supply line in a display device according to an embodiment of the present invention.
4B is a diagram illustrating light emitting regions driven by a second upper power supply line in a display device according to an embodiment of the present invention.
5 is a view showing a display device according to another embodiment of the present invention.

Details regarding the above object and technical configuration of the present invention and the effects thereof will be more clearly understood by the following detailed description with reference to the drawings showing embodiments of the present invention. Here, since the embodiments of the present invention are provided so that the technical idea of the present invention can be sufficiently conveyed to those skilled in the art, the present invention may be embodied in other forms so as not to be limited to the embodiments described below.

In addition, parts indicated with the same reference numerals throughout the specification mean the same components, and in the drawings, the length and thickness of a layer or region may be exaggerated for convenience. In addition, when it is described that a first component is "on" a second component, the first component is not only located on the upper side in direct contact with the second component, but also the first component and the A case in which a third component is positioned between the second component is also included.

Here, terms such as the first, second, etc. are used to describe various components, and are used for the purpose of distinguishing one component from other components. However, within the scope not departing from the spirit of the present invention, the first and second components may be arbitrarily named according to the convenience of those skilled in the art.

Terms used in the specification of the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. For example, elements expressed in the singular include plural elements unless the context clearly means only the singular. In addition, in the specification of the present invention, terms such as "comprises" or "have" are intended to designate the existence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, one or It should be understood that it does not preclude in advance the possibility of the existence or addition of other features or numbers, steps, operations, components, parts, or combinations thereof.

In addition, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and, unless explicitly defined in the specification of the present invention, have an ideal or excessively formal meaning. not interpreted

(Example)

1 is a diagram schematically illustrating a display device according to an embodiment of the present invention. FIG. 2 is an enlarged view of area K of FIG. 1 . FIG. 3A is a view showing a cross-section taken along line I-I' of FIG. 2 . FIG. 3B is a view showing a cross-section taken along line II-II′ of FIG. 2 .

1 , 2 , 3A and 3B , the display device according to an embodiment of the present invention may include a device substrate 110 . The device substrate 110 may include an insulating material. For example, the device substrate 110 may include glass or plastic.

Signal lines GL, DL, PL, 511, 512, 513, 521, 522, and 523 may be positioned on the device substrate 110 . The signal lines GL, DL, PL, 511 , 512 , 513 , 521 , 522 , and 523 include gate lines GL transmitting a gate signal, data lines DL transmitting a data signal, and a first It may include a lower power supply line PL that transmits the power voltage. The signal lines GL, DL, PL, 511, 512, 513, 521, 522, and 523 are the first upper power supply lines 511, 512, and 513 for transferring the second power voltage and the second upper power supply. It may further include supply lines (521, 522, 523).

The gate lines GL and the data lines DL may define pixel areas PA1 and PA2 . For example, the data lines DL may extend in a first direction Y, and the gate lines GL may extend in a second direction X. Each of the pixel areas PA1 and PA2 may be connected to the data driver 200 through one of the data lines DL, and may be connected to the gate driver 300 through one of the gate lines GL.

The lower power supply line PL may transmit a first power voltage to each of the pixel areas PA1 and PA2 . For example, each of the pixel areas PA1 and PA2 may be connected to the lower power supply unit 400 through the lower power supply line PL. The lower power supply line PL may extend in the first direction Y in the display area AA in which the pixel areas PA1 and PA2 are located. For example, each of the pixel areas PA1 and PA2 may be positioned between the data lines DL and the lower power supply lines PL.

The first upper power supply lines 511 , 512 , and 513 and the second upper power supply lines 521 , 522 , and 523 may transmit a second power voltage to each of the pixel areas PA1 and PA2 . For example, each of the pixel areas PA1 and PA2 is connected to the first upper power supply unit 510 through the first upper power supply lines 511 , 512 , and 513 , or is connected to the second upper power supply lines ( It may be connected to the second upper power supply unit 520 through 521 , 522 , and 523 . The first upper power supply lines 511 , 512 , 513 and the second upper power supply lines 521 , 522 , 523 are connected in the display area AA in the first direction Y. It can be extended obliquely. The first upper power supply lines 513 and the second upper power supply lines 523 crossing the display area AA may be positioned parallel to each other. The first upper power supply lines 513 and the second upper power supply lines 523 may be located on the same layer. The first upper power supply lines 513 and the second upper power supply lines 523 may include the same material. For example, the first upper power supply lines 513 and the second upper power supply lines 523 may be alternately positioned in the display area AA.

The pixel areas PA1 and PA2 include first and second pixel areas PA1 and second alternately positioned in the first direction Y and a second direction X perpendicular to the first direction Y. It may include pixel areas PA2 . Each of the pixel areas PA1 and PA2 may include two emission areas E1 , E2 , E3 , and E4 . For example, each of the first pixel areas PA1 includes a first light-emitting area E1 and a second light-emitting area E2 positioned side by side in the first direction Y, and each second pixel area PA2 ) may include a third light-emitting area E3 and a fourth light-emitting area E4 positioned side by side in the first direction (Y).

The light emitting regions E1 , E2 , E3 , and E4 may be arranged in a pentile shape. For example, the first light emitting area E1 and the third light emitting area E3 are a green light emitting area representing green, the second light emitting area E2 is a blue light emitting area representing blue, and the fourth light emitting area E2 is a blue light emitting area. The light emitting area E4 may be a red light emitting area representing red.

Single drivers DA1 and DA2 may be positioned in each of the pixel areas PA1 and PA2 . Each of the drivers DA1 and DA2 may be connected to one of the gate lines GL and one of the data lines DL. Each of the drivers DA1 and DA2 may generate a driving current according to the gate signal and the data signal. For example, each of the drivers DA1 and DA2 may include the thin film transistor 120 . The thin film transistor 120 may include a semiconductor pattern 121 , a gate insulating layer 122 , a gate electrode 123 , an interlayer insulating layer 124 , a source electrode 125 , and a drain electrode 126 .

The semiconductor pattern 121 may include a semiconductor material. For example, the semiconductor pattern 121 may include silicon. The semiconductor pattern 121 may be an oxide semiconductor. For example, the semiconductor pattern 121 may include a metal oxide such as IGZO. The semiconductor pattern 121 may include a source region, a channel region, and a drain region. The channel region may be positioned between the source region and the drain region. The source region and the drain region may have higher electrical conductivity than the channel region.

The gate insulating layer 122 may be positioned on the semiconductor pattern 121 . For example, the semiconductor pattern 121 may be positioned between the device substrate 110 and the gate insulating layer 122 . The gate insulating layer 122 may extend outside the semiconductor pattern 121 . For example, a side surface of the semiconductor pattern 121 may directly contact the gate insulating layer 122 . The gate insulating layer 122 may include an insulating material. For example, the gate insulating layer 122 may include silicon oxide (SiO) and/or silicon nitride (SiN). The gate insulating layer 122 may include a high-k material. For example, the gate insulating layer 122 may include hafnium oxide (HfO). The gate insulating layer 122 may have a multilayer structure.

The gate electrode 123 may be positioned on the gate insulating layer 122 . The gate electrode 123 may overlap the channel region of the semiconductor pattern 121 . For example, the source region and the drain region of the semiconductor pattern 121 may be positioned outside the gate electrode 123 . The gate electrode 123 may include a conductive material. For example, the gate electrode 123 may include a metal such as aluminum (Al), chromium (Cr), molybdenum (Mo), tungsten (W), and copper (Cu).

The interlayer insulating layer 124 may be disposed on the gate electrode 123 . The interlayer insulating layer 124 may extend outside the semiconductor pattern 121 . For example, a side surface of the gate electrode 123 may directly contact the interlayer insulating layer 124 . The interlayer insulating layer 124 may include an insulating material. For example, the interlayer insulating layer 124 may include silicon oxide (SiO).

The source electrode 125 may be positioned on the interlayer insulating layer 124 . The source electrode 125 may be electrically connected to the source region of the semiconductor pattern 121 . For example, the gate insulating layer 122 and the interlayer insulating layer 124 may include a source contact hole partially exposing the source region of the semiconductor pattern 121 . The source electrode 125 may be connected to the source region of the semiconductor pattern 121 through the source contact hole. For example, the source electrode 125 may include a region overlapping the source region of the semiconductor pattern 121 . The source electrode 125 may include a conductive material. For example, the source electrode 125 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The source electrode 125 may include a material different from that of the gate electrode 123 .

The drain electrode 126 may be positioned on the interlayer insulating layer 124 . The drain electrode 126 may be electrically connected to the drain region of the semiconductor pattern 121 . The drain electrode 126 may be spaced apart from the source electrode 125 . For example, the gate insulating layer 122 and the interlayer insulating layer 124 may include a drain contact hole partially exposing the drain region of the semiconductor pattern 121 . The drain electrode 126 may be connected to the drain region of the semiconductor pattern 121 through the drain contact hole. For example, the drain electrode 126 may include a region overlapping the drain region of the semiconductor pattern 121 . The drain electrode 126 may include a conductive material. For example, the drain electrode 126 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The drain electrode 126 may include the same material as the source electrode 125 . For example, the drain electrode 126 may include a material different from that of the gate electrode 123 .

A buffer layer 111 may be positioned between the device substrate 110 and each of the drivers DA1 and DA2 . For example, the thin film transistor 120 may be positioned on the buffer layer 111 . The buffer layer 111 may prevent contamination by the device substrate 110 in the process of forming the thin film transistor 120 . The buffer layer 111 may include an insulating material. For example, the buffer layer 111 may include silicon oxide (SiO) and/or silicon nitride (SiN). The buffer layer 111 may have a multi-layer structure. For example, the buffer layer 111 may have a stacked structure of an insulating layer made of silicon oxide (SiO) and an insulating layer made of silicon nitride (SiN).

A lower passivation layer 112 may be positioned on the drivers DA1 and DA2. The lower protective layer 112 may prevent damage to the driving units DA1 and DA2 due to external moisture and impact. The lower passivation layer 112 may extend along surfaces of the drivers DA1 and DA2 facing the device substrate 110 . The lower passivation layer 112 may extend outside the driving units DA1 and DA2. For example, the lower passivation layer 112 may cover the source electrode 125 and the drain electrode 126 of the thin film transistor 120 . The lower passivation layer 112 may include an insulating material. The lower passivation layer 112 may include an inorganic insulating material. For example, the lower passivation layer 112 may include silicon oxide (SiO) or silicon nitride (SiN).

An overcoat layer 113 may be positioned on the lower passivation layer 112 . The overcoat layer 113 may remove a step difference caused by the driving units DA1 and DA2. For example, the step caused by the thin film transistor 120 may be removed by the overcoat layer 113 . A surface of the overcoat layer 113 facing the device substrate 110 may be a flat surface. The overcoat layer 113 may include an insulating material. The overcoat layer 113 may include a material having relatively high fluidity. For example, the overcoat layer 113 may include an organic insulating material.

Light emitting devices 130a, 130b, 130c, and 130d may be positioned on the overcoat layer 113 . The light emitting devices 130a, 130b, 130c, and 130d may be positioned in each of the light emitting regions E1, E2, E3, and E4. The two light emitting areas E1 , E2 , E3 , and E4 of each of the pixel areas PA1 and PA2 are light emitting devices 130a , 130b and 130c connected to the single drivers DA1 and DA2 of the corresponding pixel areas PA1 and PA2 , respectively. , 130d) may be included. For example, the first light emitting device 130a positioned in the first light emitting area E1 of each of the first pixel areas PA1 and the second light emitting device 130b positioned within the second light emitting area E2 of each of the first pixel areas PA1 ) may be connected to the first driver DA1 of the corresponding first pixel area PA1 . The third light emitting device 130c positioned in the third light emitting area E3 of each second pixel area PA2 and the fourth light emitting device 130d positioned within the fourth light emitting area E4 are the corresponding second light emitting devices 130d. It may be connected to the second driver DA2 of the pixel area PA2 .

The two emission areas E1 , E2 , E3 , and E4 of each of the pixel areas PA1 and PA2 may be connected to different upper power units 510 and 520 . For example, the light emitting devices 130a, 130b, 130c, and 130d of each of the light emitting regions E1, E2, E3, and E4 are connected to the pixel electrode 131a connected to the thin film transistor 120 of the corresponding driving units DA1 and DA2. , 131b, 131c, 131d) and the light emitting layers 132a, 132b, 132c, and 132d positioned between the first upper power supply line 513 or the second upper power supply line 523 . In each frame, each of the pixel areas PA1 and PA2 operates in the pixel areas PA1 and PA2 and the light emitting areas E1, E2, E3, and E4 adjacent in the first direction Y and the second direction X. Location may vary. For example, the first light emitting device 130a positioned in each first light emitting area E1 may include a first pixel electrode 131a connected to the thin film transistor 120 of the first driver DA1 and the The first light emitting layer 132a positioned between the first upper power supply lines 513 and the second light emitting device 130b positioned in each second light emitting area E2 is the first driver DA1. and a second light emitting layer 132b positioned between the second pixel electrode 131b connected to the thin film transistor 120 and the second upper power supply line 523 . The third light emitting device 130c positioned in each third light emitting area E3 includes a third pixel electrode 131c connected to the thin film transistor 120 of the second driver DA2 and the second upper power supply. The thin film transistor of the second driving unit DA2 includes a third light emitting layer 132c positioned between the supply lines 523 , and the fourth light emitting device 130d positioned within each fourth light emitting region E4 . A fourth light emitting layer 132d positioned between the fourth pixel electrode 131d connected to 120 and the first upper power supply line 513 may be included. The pixel electrodes 131a, 131b, 131c, and 132d may be simultaneously formed. For example, the second pixel electrode 131b of the second emission area E2 is located on the same layer as the first pixel electrode 131a of the first emission area E1, and the fourth light emission The fourth pixel electrode 131d of the region E4 may be positioned on the same layer as the third pixel electrode 13c of the third emission region E3 . The first pixel electrode 131a, the second pixel electrode 131b, the third pixel electrode 131c, and the fourth pixel electrode 131d may include the same material. For example, the first pixel electrode 131a, the second pixel electrode 131b, the third pixel electrode 131c, and the fourth pixel electrode 131d may be simultaneously formed.

Each of the emission layers 132a, 132b, 132c, and 132d may be formed by a deposition process using a fine metal mask (FMM). For example, on the overcoat layer 113 , a bank insulating layer 114 positioned between the light emitting regions E1 , E2 , E3 , and E4 and a spacer 115 positioned on the bank insulating layer 114 are formed. may include Accordingly, in the display device according to an embodiment of the present invention, the first light emitting area E1 of each first pixel area PA1 and the fourth light emitting area E4 of each second pixel area PA2 are The second light emitting area E2 of each of the first pixel areas PA1 and the third light emitting area E3 of each of the second pixel areas PA2 are connected to the first upper power supply line 513 , It may be connected to the second upper power supply line 523 . That is, in the display device according to the embodiment of the present invention, the first upper power supply line 513 is connected to the first light emitting device 130a in each of the first pixel areas PA1 and the respective second pixel areas PA2. It functions as an upper electrode of the fourth light emitting device 130d, and the second upper power supply line 523 is connected to the second light emitting device 130b and each second pixel area in each of the first pixel areas PA1. (PA2) may serve as an upper electrode of the third light emitting device 130c. The pixel electrodes 131a, 131b, 131c, and 131d of each of the pixel areas PA1 and PA2 may extend between the corresponding drivers PA1 and PA2 and the bank insulating layer 114 . For example, the overcoat layer 113 may expose the drain electrode 126 of the corresponding thin film transistor 120 under the bank insulating layer 114 .

An encapsulation member 140 may be positioned on the light emitting devices 130a, 130b, 130c, and 130d. The encapsulation member 140 may prevent damage to the light emitting devices 130a, 130b, 130c, and 130d due to external moisture and impact. The encapsulation member 140 may have a multi-layer structure. For example, the encapsulation member 140 may include a first encapsulation layer 141 , a second encapsulation layer 142 , and a third encapsulation layer 143 that are sequentially stacked. The first encapsulation layer 141 , the second encapsulation layer 142 , and the third encapsulation layer 143 may include an insulating material. The second encapsulation layer 142 may include a material different from that of the first encapsulation layer 141 and the third encapsulation layer 143 . For example, the first encapsulation layer 141 and the third encapsulation layer 143 may include an inorganic insulating material, and the second encapsulation layer 142 may include an organic insulating material. Accordingly, in the display device according to an embodiment of the present invention, damage to the light emitting elements 130a, 130b, 130c, and 130d due to external moisture and impact can be effectively prevented. Steps caused by the light emitting devices 130a, 130b, 130c, and 130d may be removed by the second encapsulation layer 142 . For example, an upper surface of the encapsulation member 140 facing the device substrate 110 may be parallel to a surface of the device substrate 110 .

FIG. 4A is a diagram illustrating the light-emitting regions E1, E2, E3, and E4 emitted by the first upper power supply lines 513. Referring to FIG. FIG. 4B is a diagram illustrating the light emitting regions E1 , E2 , E3 , and E4 emitted by the second upper power supply lines 523 .

4A and 4B , the light emitting regions E1 , E2 , E3 , and E4 emitted by the first upper power supply lines 513 or the second upper power supply lines 523 are BG-RG pentagonal. It can keep its shape. That is, in the display device according to an embodiment of the present invention, two light emitting regions E1 , E2 , E3 , E4 adjacent in the first direction Y are connected to one driving unit DA1 and DA2, but the first direction ( The first direction (Y) and the first direction (Y) and the first direction (Y) and the first direction (Y) using the first upper power supply line 513 and the second upper power supply line 523 extending in an inclined direction with respect to Y) By sequentially operating the adjacent light emitting regions E1 , E2 , E3 , and E4 in the second vertical direction X, the pentile shape may be maintained in each frame.

As a result, the display device according to an embodiment of the present invention includes the pixel areas PA1 and PA2 positioned side by side in a first direction (Y) and a second direction (X) perpendicular to the first direction (Y). , each of the pixel areas PA1 and PA2 includes two light-emitting areas E1, E2, E3, and E4 that are positioned side by side in the first direction Y, and the two light-emitting areas of each of the pixel areas PA1 and PA2 ( The first upper power supply lines 513 and the second upper part connecting E1, E2, E3, E4 to the single driving units DA1 and DA2 and extending in an inclined direction with respect to the first direction Y The light emitting regions E1 , E2 , E3 , and E4 adjacent in the first direction Y and the second direction X perpendicular to the first direction Y are sequentially connected using the power supply line 523 . can drive Accordingly, in the display device according to an embodiment of the present invention, the area required for forming the driving units DA1 and DA2 is reduced, and the pentile shape can be maintained in each frame. Accordingly, in the display device according to an embodiment of the present invention, the resolution may be increased.

The display device according to an embodiment of the present invention will be described as including two light emitting areas E1 , E2 , E3 , and E4 in which each pixel area PA1 , PA2 is positioned side by side along the data lines DL. However, as shown in FIG. 5 , in the display device according to another exemplary embodiment of the present invention, each of the pixel areas PA1 and PA2 has two light emitting areas E1 , E2 and E3 positioned side by side along the gate lines GL. , E4) may be included. Accordingly, in the display device according to another embodiment of the present invention, the degree of freedom in the configuration of each pixel area PA1 and PA2 may be improved.

110: device substrate 120: thin film transistor
131a: first lower electrode 131b: second lower electrode
132a: first light-emitting layer 132b: second light-emitting layer
513: first upper power supply line 523: second upper power supply line
DA: drive circuit

Claims (7)

first pixel regions including a first driver, in which a first emission region displaying a first color and a second emission region displaying a second color are positioned side by side in a first direction;
second pixel regions including a second driver, wherein a third emission region displaying the first color and a fourth emission region displaying a third color are positioned side by side in the first direction;
first upper power supply lines extending obliquely in the first direction and connected to the first light emitting area of each first pixel area and the fourth light emitting area of each second pixel area; and
and second upper power supply lines extending parallel to the first upper power supply lines and connected to the second light emitting area of each first pixel area and the third light emitting area of each second pixel area,
the first pixel areas and the second pixel areas are alternately positioned in a second direction perpendicular to the first direction;
Each light emitting region includes a light emitting layer positioned between the pixel electrode connected to the driver and the corresponding upper power supply line,
The first color, the second color, and the third color are different from each other. The method of claim 1,
The first color is green. The method of claim 1,
the pixel electrode of the second light emitting area is located on the same layer as the pixel electrode of the first light emitting area
The pixel electrode of the fourth light emitting area is positioned on the same layer as the pixel electrode of the third light emitting area. 4. The method of claim 3,
The pixel electrode of the second emission region includes the same material as the pixel electrode of the first emission region,
The pixel electrode of the fourth light emitting area includes the same material as the pixel electrode of the third light emitting area. The method of claim 1,
The second upper power supply lines are positioned on the same layer as the first upper power supply lines. 6. The method of claim 5,
The second upper power supply lines include the same material as the first upper power supply lines. The method of claim 1,
and a gate line extending in the second direction and connected to the first pixel regions and the second pixel regions.

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