KR20210067595A - Semiconductor device - Google Patents

Abstract

The embodiment provides a semiconductor device capable of improving reflectance and light output. The semiconductor device includes: a substrate; a semiconductor structure including a first conductivity type semiconductor layer disposed on the substrate, a second conductivity type semiconductor layer, an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a recess formed through the second conductivity type semiconductor layer and the active layer; a first electrode disposed on the first conductivity type semiconductor layer; a second electrode disposed on the second conductivity type semiconductor layer; a first cover electrode disposed on the first electrode and electrically connected to the first electrode; a second cover electrode electrically connected to the second electrode disposed on the second electrode; a first pad electrically connected to the first cover electrode; and a second pad electrically connected to the second cover electrode. The semiconductor structure includes a first area overlapping the first pad in a vertical direction, a second area overlapping the second pad in a vertical direction, and a third area disposed between the first area and the second area. The second cover electrode overlaps the second region and the third region in the vertical direction and does not overlap the first region in the vertical direction. The first cover electrode does not overlap the first region and the third region in the vertical direction, and overlaps the second region in the vertical direction.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device.

A semiconductor device including a compound such as GaN or AlGaN has many advantages, such as having a wide and easily adjustable band gap energy, and thus can be used in various ways as a light emitting device, a light receiving device, and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using group 3-5 or group 2-6 compound semiconductor materials of semiconductors have developed red, green, and Various colors such as blue and ultraviolet can be realized, and efficient white light can be realized by using fluorescent materials or combining colors. Compared to conventional light sources such as fluorescent and incandescent lamps, low power consumption, semi-permanent lifespan, and fast response speed. , safety and environmental friendliness.

In addition, when a light receiving device such as a photodetector or a solar cell is manufactured using a semiconductor group 3-5 or group 2-6 compound semiconductor material, a photocurrent is generated by absorbing light in various wavelength ranges through the development of the device material. This makes it possible to use light of various wavelength ranges from gamma rays to radio wavelengths. In addition, it has advantages of fast response speed, safety, environmental friendliness, and easy adjustment of device materials, so it can be easily used for power control or ultra-high frequency circuits or communication modules.

Therefore, the semiconductor device can replace a light emitting diode backlight, a fluorescent lamp or an incandescent light bulb that replaces a cold cathode fluorescence lamp (CCFL) constituting a transmission module of an optical communication means and a backlight of a liquid crystal display (LCD) display device. The application is expanding to white light emitting diode lighting devices, automobile headlights and traffic lights, and sensors that detect gas or fire. In addition, the application of the semiconductor device may be extended to a high frequency application circuit, other power control devices, and communication modules.

In particular, the light emitting device emitting light in the ultraviolet wavelength region can be used for curing, medical, and sterilization by performing a curing action or a sterilizing action.

Although research on ultraviolet light emitting devices has been active recently, there is a problem in that it is difficult to implement the ultraviolet light emitting device as a flip chip.

The embodiment provides a flip-chip type semiconductor device.

In addition, a semiconductor device having improved current concentration in the center of a chip is provided.

In addition, the present invention provides a semiconductor device having improved reflectance and improved light output.

In addition, there is provided a semiconductor device having improved heat dissipation characteristics and improved reliability.

The problem to be solved in the embodiment is not limited thereto, and it will be said that the purpose or effect that can be grasped from the solution means or embodiment of the problem described below is included.

a substrate according to an embodiment; a first conductivity type semiconductor layer disposed on the substrate, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; a semiconductor structure comprising a semiconductor layer and a recess penetrating the active layer; a first electrode disposed on the first conductivity-type semiconductor layer; a second electrode disposed on the second conductivity-type semiconductor layer; a first cover electrode disposed on the first electrode and electrically connected to the first electrode; a second cover electrode electrically connected to the second electrode disposed on the second electrode; a first pad electrically connected to the first cover electrode; and a second pad electrically connected to the second cover electrode, wherein the semiconductor structure includes a first region overlapping the first pad in a vertical direction, and a first region overlapping the second pad in the vertical direction. a second region and a third region disposed between the first region and the second region, wherein the second cover electrode overlaps the second region and the third region in the vertical direction, and the first region does not overlap with the vertical direction, the first cover electrode does not overlap with the first region and the third region in the vertical direction, but overlaps the second region with the vertical direction.

A thickness of the second cover electrode in the first region or the second region may be smaller than a thickness in the third region.

A thickness of the first cover electrode in the first region or the second region may be greater than a thickness in the third region.

a first channel electrode disposed on the first cover electrode and electrically connected to the first cover electrode; and the second channel electrode disposed on the second cover electrode, wherein the first channel electrode and the second channel electrode may extend in a horizontal direction from the first pad toward the second pad. have.

The first channel electrode and the second channel electrode may be intersected in a direction perpendicular to the horizontal direction.

The first channel electrode and the second channel electrode vertically overlap the first region, the second region, and the third region, and the first channel electrode is a first channel electrode overlapping the recess in the vertical direction. a sub-region and a second sub-region positioned between the recesses in the horizontal direction, wherein the first sub-region has a maximum width in a direction perpendicular to the horizontal direction perpendicular to the horizontal direction in the second sub-region direction may be greater than the maximum width.

An oxide layer disposed between the first ohmic electrode and the first cover electrode may be further included.

The oxide layer includes a first oxide layer overlapping the first region and the second region in the vertical direction, and a second oxide layer overlapping the third region in the vertical direction, the second oxide layer having a through hole; may include

The first ohmic electrode may be exposed through the through hole.

The oxide layer may have a thickness of 3 nm or less.

According to an embodiment, the semiconductor device may be implemented in the form of a flip chip.

In addition, the current concentration in the center of the chip is improved, so that a semiconductor device having an improved light output at the center can be manufactured.

In addition, it is possible to manufacture a semiconductor device with improved light output due to improved reflectance.

In addition, a semiconductor device having improved heat dissipation characteristics and improved reliability may be manufactured.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a plan view of a semiconductor device according to a first embodiment;
Figure 2 is a cross-sectional view taken along II' in Figure 1,
3 is a cross-sectional view taken along line AA' in FIG. 1;
Figure 4 is an enlarged view of part K1 in Figure 3,
5 is an enlarged view of part K2 in FIG. 3,
6 is a cross-sectional view taken along line BB' in FIG. 1,
7 is a plan view of a semiconductor device according to a second embodiment;
8 is a cross-sectional view taken along CC' in FIG. 7;
9 is a cross-sectional view taken along DD' in FIG. 7;
10 is a plan view of a semiconductor device according to a third embodiment;
11 is a cross-sectional view taken along line EE' in FIG. 10;
12 is a cross-sectional view taken along line FF' in FIG. 10;
13 is a plan view of a semiconductor device according to a modified example;
14 is a cross-sectional view taken along line GG' in FIG. 13;
15 is a plan view of a semiconductor device according to a fourth embodiment;
16 is a cross-sectional view taken along line HH' in FIG. 15;
17 is a view showing a first pad, a second pad, a first cover electrode, a second cover electrode, a first channel electrode, and a second channel electrode of the semiconductor device according to the fourth embodiment;
18 is a cross-sectional view of a semiconductor device according to another modification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical spirit of the present invention is not limited to some embodiments described, but may be implemented in various different forms, and within the scope of the technical spirit of the present invention, one or more of the components may be selected between embodiments. It can be combined and substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be generally understood by those of ordinary skill in the art to which the present invention belongs, unless specifically defined and described explicitly. It may be interpreted as a meaning, and generally used terms such as terms defined in advance may be interpreted in consideration of the contextual meaning of the related art.

In addition, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In the present specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when it is described as "at least one (or more than one) of A and (and) B, C", it is combined with A, B, C It may include one or more of all possible combinations.

In addition, in describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are only used to distinguish the component from other components, and are not limited to the essence, order, or order of the component by the term.

And, when it is described that a component is 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected, coupled or connected to the other component, but also with the component It may also include a case of 'connected', 'coupled' or 'connected' due to another element between the other elements.

In addition, when it is described as being formed or disposed on "above (above) or below (below)" of each component, the top (above) or bottom (below) is one as well as when two components are in direct contact with each other. Also includes a case in which another component as described above is formed or disposed between two components. In addition, when expressed as "upper (upper) or lower (lower)", the meaning of not only an upper direction but also a lower direction based on one component may be included.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment, and FIG. 2 is a cross-sectional view taken along line II′ in FIG. 1 .

1 to 2 , the semiconductor device according to the first embodiment of the present invention includes a substrate 110 , a semiconductor structure 120 disposed on the substrate 110 , and a semiconductor structure 120 disposed on the semiconductor structure 120 . The first insulating layer 131 , the first ohmic electrode 141 disposed on the first conductivity type semiconductor layer 121 , the second ohmic electrode 142 disposed on the second conductivity type semiconductor layer 123 , The first cover electrode 151 disposed on the first ohmic electrode 141 , the second cover electrode 152 disposed on the second ohmic electrode 142 , and the first cover electrode 151 and the second cover The second insulating layer 132 disposed on the electrode 152 , the first channel electrode 161 electrically connected to the first cover electrode 151 , and the second electrically connected to the second cover electrode 152 . It may include a channel electrode 162 , a first pad 171 electrically connected to the first channel electrode 161 , and a second pad 172 electrically connected to the second channel electrode 162 .

First, the semiconductor structure 120 according to the embodiment of the present invention may output light in the ultraviolet wavelength band. Illustratively, the semiconductor structure 120 may output light (UV-A) of a near-ultraviolet wavelength band, may output light (UV-B) of a near-ultraviolet wavelength band, or light (UV-B) of a deep ultraviolet wavelength band. C) can be printed. The wavelength range may be determined by the Al composition ratio of the semiconductor structure 120 .

Exemplarily, the light (UV-A) of the near-ultraviolet wavelength band may have a central wavelength in a wavelength band of 320 nm to 420 nm, and the light (UV-B) of the near-ultraviolet wavelength band is centered in a wavelength band of 280 nm to 320 nm. It may have a wavelength, and light (UV-C) in the deep ultraviolet wavelength band may have a central wavelength in a wavelength band of 100 nm to 280 nm.

In an embodiment, since the semiconductor structure 120 outputs ultraviolet light and includes Al, optical polarization may occur. Accordingly, the semiconductor structure 120 may mainly generate tansverse-magnetic (TM) polarized light from the active layer 122 . That is, photometry may mainly occur in the semiconductor device.

Specifically, the substrate 110 _{may be formed of a material selected from sapphire (Al 2} O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge, but is not limited thereto. For example, the substrate 110 may be a light-transmitting substrate capable of transmitting light in an ultraviolet wavelength band.

Additionally, the semiconductor device according to the embodiment may further include a buffer layer (not shown) disposed between the substrate 110 and the semiconductor structure 120 . A buffer layer (not shown) may alleviate a lattice mismatch between the substrate 110 and the semiconductor layers. The buffer layer (not shown) may be a combination of Group III and V elements or may include any one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. In this embodiment, the buffer layer (not shown) may be AlN, but is not limited thereto. The buffer layer (not shown) may include a dopant, but is not limited thereto.

The semiconductor structure 120 according to the embodiment includes a first conductivity-type semiconductor layer 121 disposed on a substrate 110 , an active layer 122 disposed on the first conductivity-type semiconductor layer 121 , and an active layer 122 . A second conductivity type semiconductor layer 123 disposed thereon may be included. In this case, the first conductivity type semiconductor layer 121 , the active layer 122 , and the second conductivity type semiconductor layer 123 may be stacked in a vertical direction. The vertical direction may be a third direction (Z-axis direction) in the present specification.

x1≤1, 0<y1≤1, 0≤x1+y1≤1)의 조성식을 갖는 반도체 재료, 예를 들어 AlGaN, AlN, InAlGaN 등에서 선택될 수 있다. 그리고, 제1 도펀트는 Si, Ge, Sn, Se, Te와 같은 n형 도펀트일 수 있다. 제1 도펀트가 n형 도펀트인 경우, 제1 도펀트가 도핑된 제1 도전형 반도체층(121)은 n형 반도체층일 수 있다.The first conductivity-type semiconductor layer 121 may be implemented with a group III-V group or group II-VI compound semiconductor, and may be doped with a first dopant. The first conductivity type semiconductor layer 121 is In _x1 Al _y1 Ga _1-x1-y1 N(0

It may be selected from a semiconductor material having a composition formula of x1≤1, 0<y1≤1, 0≤x1+y1≤1, for example, AlGaN, AlN, InAlGaN, and the like. In addition, the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductivity-type semiconductor layer 121 doped with the first dopant may be an n-type semiconductor layer.

The active layer 122 may be disposed between the first conductivity type semiconductor layer 121 and the second conductivity type semiconductor layer 123 . The active layer 122 is a layer in which electrons (or holes) injected through the first conductivity type semiconductor layer 121 and holes (or electrons) injected through the second conductivity type semiconductor layer 123 meet. The active layer 122 may transition to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

The active layer 122 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 122 may have a structure. The structure is not limited thereto.

x2≤1, 0<y2≤1, 0≤x2+y2≤1)의 조성식을 가질 수 있다. 우물층은 발광하는 파장에 따라 알루미늄 조성이 달라질 수 있다.The active layer 122 may include a plurality of well layers (not shown) and a barrier layer (not shown). The well layer and barrier layer are In _x2 Al _y2 Ga _1-x2-y2 N(0

x2≤1, 0<y2≤1, 0≤x2+y2≤1). The well layer may have a different aluminum composition depending on the wavelength of light emission.

The second conductivity-type semiconductor layer 123 is formed on the active layer 122 , and may be implemented as a compound semiconductor such as III-V group or II-VI group, and is formed on the second conductivity-type semiconductor layer 123 on the second conductivity-type semiconductor layer 123 . Dopants may be doped.

x5≤1, 0<y2≤1, 0≤x5+y2≤1)의 조성식을 갖는 반도체 물질 또는 AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP 중 선택된 물질로 형성될 수 있다. The second conductivity type semiconductor layer 123 is In _x5 Al _y2 Ga _1-x5-y2 N (0

It may be formed of a semiconductor material having a composition formula of x5≤1, 0<y2≤1, 0≤x5+y2≤1) or a material selected from among AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP.

When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the second conductivity-type semiconductor layer 123 doped with the second dopant may be a p-type semiconductor layer.

Also, in an embodiment, the semiconductor structure 120 may include a recess 129 penetrating the second conductivity-type semiconductor layer 123 and the active layer 122 . The recess 129 may be disposed up to a partial region of the first conductivity type semiconductor layer 121 . Also, the number of recesses 129 may be plural.

The first insulating layer 131 may be disposed between the first ohmic electrode 141 and the second ohmic electrode 142 . Also, a portion of the first insulating layer 131 may be disposed in the recess 129 . In addition, the first insulating layer 131 may include a first hole 131a in which the first ohmic electrode 141 is disposed and a second hole 131b in which the second ohmic electrode 142 is disposed.

The first ohmic electrode 141 may be disposed on the first conductivity type semiconductor layer 121 , and the second ohmic electrode 142 may be disposed on the second conductivity type semiconductor layer 123 .

The first ohmic electrode 141 and the second ohmic electrode 142 include indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), and indium gallium (IGZO). zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In -Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, It may be formed including at least one of In, Ru, Mg, Zn, Pt, Au, and Hf, but is not limited thereto.

The first cover electrode 151 may be disposed on the first ohmic electrode 141 to cover the first ohmic electrode 141 . That is, the first cover electrode 151 may cover the side surface of the first ohmic electrode 141 . Accordingly, the reliability of the electrical connection between the first cover electrode 151 and the first ohmic electrode 141 may be improved, but the present invention is not limited thereto.

Also, the first cover electrode 151 may be electrically connected to the first ohmic electrode 141 through the first hole 131a to form an electrical channel with the first conductivity-type semiconductor layer 121 .

The first cover electrode 151 may extend along an upper portion of the first insulating layer 131 . Accordingly, a portion of the first cover electrode 151 may be positioned on the first insulating layer 131 . Due to this configuration, since the total area of the first cover electrode 151 is increased, the operating voltage of the semiconductor device according to the embodiment may be lowered.

The second cover electrode 152 may be disposed on the second ohmic electrode 142 to cover the second ohmic electrode 142 . In addition, the second cover electrode 152 may cover the side surface of the second ohmic electrode 142 , but is not limited thereto.

Also, the second cover electrode 152 may be electrically connected to the second ohmic electrode 142 through the second hole 131b. Accordingly, the second cover electrode 152 may form an electrical channel with the second ohmic electrode 142 and the second conductivity-type semiconductor layer 123 . And for example, the second cover electrode 152 may be disposed only on the second ohmic electrode 142 .

The first cover electrode 151 and the second cover electrode 152 are Ni/Al/Au, or Ni/IrOx/Au, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru. , Mg, Zn, Pt, Au, may be formed including at least one of Hf, but is not particularly limited. For example, the first cover electrode 151 and the second cover electrode 152 may have a structure in which Cr, Al, Ni, Ti, Ni, Ti, Ni, and Ti are sequentially stacked, and the thickness of each metal is also different. can do.

The second insulating layer 132 may be disposed on the first cover electrode 151 , the second cover electrode 152 , and the first insulating layer 131 . The second insulating layer 132 may include a third hole 132a exposing the first cover electrode 151 and a fourth hole 132b exposing the second cover electrode 152 . The third hole 132a and the fourth hole 132b may be spaced apart from each other.

The first insulating layer 131 and the second insulating layer 132 are formed by selecting at least one from the group consisting _{of SiO 2} , SixOy, Si ₃ N ₄ , SixNy, SiOxNy, Al ₂ O ₃ , TiO _{2 , AlN, and the like.} can be In addition, the first insulating layer 131 and the second insulating layer 132 partially form a boundary between the first insulating layer 131 and the second insulating layer 132 while the second insulating layer 132 is formed. may be removed and exist integrally. For example, the first insulating layer 131 and the second insulating layer 132 may be integrally formed by heating when the second insulating layer 132 is formed. However, the present invention is not limited thereto.

The first channel electrode 161 may be electrically connected to the first cover electrode 151 . The first channel electrode 161 may be disposed in the third hole 132a and may be in contact with the first cover electrode 151 through the third hole 132a.

The first channel electrode 161 may extend in a horizontal direction. The horizontal direction may be a direction from the second pad 172 toward the first pad 171 spaced apart from the second pad 172 . The horizontal direction may be the first direction (X-axis direction) in the present specification, and may be perpendicular to the vertical direction.

Also, at least a portion of the first channel electrode 161 may overlap the recess 129 in a vertical direction. Also, the third hole 132a may be disposed to overlap the recess 129 in a vertical direction. Accordingly, the first channel electrode 161 may contact the first cover electrode 151 disposed in the recess 129 .

The second channel electrode 162 may be electrically connected to the second cover electrode 152 . The second channel electrode 162 may be disposed in the fourth hole 132b and may contact the second cover electrode 152 through the fourth hole 132b.

The second channel electrode 162 may extend in a horizontal direction like the first channel electrode 161 . According to an embodiment, the second channel electrode 162 may be disposed to be spaced apart from the first channel electrode 161 in the second direction (Y-axis direction). In addition, the second channel electrode 162 may be disposed to cross the first channel electrode 161 along the second direction (Y-axis direction). The second direction (Y-axis direction) is a direction perpendicular to both the above-described vertical direction and the horizontal direction.

The first channel electrode 161 and the second channel electrode 162 are Ni/Al/Au, or Ni/IrOx/Au, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru. , Mg, Zn, Pt, Au, may include at least one of Hf. For example, the first channel electrode 161 and the second channel electrode 162 may have a structure in which Cr, Al, Ti, Cu, and Cr are sequentially stacked. Also, each metal layer may have a different thickness. However, it is not limited to this configuration.

The third insulating layer 133 may be disposed on the first channel electrode 161 and the second channel electrode 162 to cover the first channel electrode 161 and the second channel electrode 162 .

Also, in an embodiment, the third insulating layer 133 may include a fifth hole h1 exposing the first channel electrode 161 . Also, the third insulating layer 133 may include a sixth hole h2 exposing the second channel electrode 162 . In other words, the third insulating layer 133 may not overlap the first channel electrode 161 and the second channel electrode 162 at least partially in the vertical direction.

In addition, the third insulating layer 133 may be formed by selecting at least one from the group consisting _{of SiO 2} , SixOy, Si ₃ N ₄ , SixNy, SiOxNy, Al ₂ O ₃ , TiO _{2 , AlN, and the like.} As described above, in the process of forming the third insulating layer 133 , the boundary between the first and second insulating layers 131 and 132 and the third insulating layer 133 may be partially removed to exist integrally. Also, like the first and second insulating layers 131 and 132 , the third insulating layer 133 may be formed of a single layer or multiple layers. With this configuration, the reliability of the insulating layer may be improved and the reflectivity to light may be improved.

The first pad 171 may be electrically connected to the first channel electrode 161 through the fifth hole h1. The fifth hole h1 may vertically overlap the first pad 171 . The fifth hole h1 may be located under the first pad 171 . With this configuration, the path of current injection through the first pad 171 may be reduced, and thus electrical characteristics may be improved.

The second pad 172 may be electrically connected to the second channel electrode 162 through the sixth hole h2 . The sixth hole h2 may vertically overlap the second pad 172 . That is, the sixth hole h2 may be located under the second pad 172 . Accordingly, a current injection path through the second pad 172 may be reduced, and thus electrical characteristics of the semiconductor device may be improved.

In addition, the first pad 171 and the second pad 172 may be eutectic bonded, but is not limited thereto.

Also, like the first pad 171 and the second pad 172 , the fifth hole h1 and the sixth hole h2 may be horizontally spaced apart from each other. Correspondingly, the first pad 171 and the second pad 172 may be disposed to face each other on the semiconductor structure 120 .

In addition, the fifth hole h1 and the sixth hole h2 may exist singly or in plurality on the first channel electrode 161 and the second channel electrode 162 . That is, the number of such holes may be variously changed.

In an embodiment, the first pad 171 may be disposed on one side of the semiconductor device over the fifth hole h1 , and the second pad 172 may be disposed on the other side of the semiconductor device over the sixth hole h2 . have. In addition, the first pad 171 and the second pad 172 may be spaced apart from each other on the semiconductor structure 120 to be electrically separated from each other.

In addition, the semiconductor structure 120 includes a first region S1 that vertically overlaps with the first pad 171 , a second region S2 that vertically overlaps with the second pad 172 , and a first region S A third region S3 disposed between S1) and the second region S2 may be included. That is, the third region S3 may not vertically overlap the first pad 171 and the second pad 172 .

In addition, in the semiconductor device according to the embodiment, the second cover electrode 152 may vertically overlap the third region S3 , but the first cover electrode 151 may not vertically overlap the third region S3 . . A detailed description thereof will be given later.

Furthermore, the second cover electrode 152 may vertically overlap with any one of the first region S1 and the second region S1 , and the first cover electrode 151 includes the first region S1 and the second region S1 . It may overlap with any one of the second regions S2 in the vertical direction. A detailed description thereof will be described in detail in various embodiments (eg, second and third embodiments) to be described later.

FIG. 3 is a cross-sectional view taken along line AA′ in FIG. 1 , FIG. 4 is an enlarged view of part K1 in FIG. 3 , and FIG. 5 is an enlarged view of part K2 in FIG. 3 .

3 to 5 , in the semiconductor device according to the first embodiment, the second cover electrode 152 may vertically overlap the third region S3. Also, the second cover electrode 152 may not overlap the first region S1 in a vertical direction. Also, the second cover electrode 152 may not overlap the first and second regions S1 and S2 in the vertical direction.

The first ohmic electrode 141 is in contact with the first cover electrode 151 on the first region S1 and the second region S3 and is electrically connected to the first channel electrode 161 through the first cover electrode 151 . can be connected

In addition, the first cover electrode 151 forms an electrical channel with the first conductivity-type semiconductor layer 121 through the first ohmic electrode 141 , and the second cover electrode 152 connects the second ohmic electrode 142 . Through this, an electrical channel may be formed with the second conductivity type semiconductor layer 123 .

In addition, according to an embodiment, the contact resistance between the second conductivity type semiconductor layer 123 and the second ohmic electrode 142 may be high. However, the contact resistance between the first conductivity type semiconductor layer 121 and the first ohmic electrode 141 may be relatively lower than the contact resistance between the second conductivity type semiconductor layer 123 and the second ohmic electrode 142 .

Accordingly, in the semiconductor device according to the embodiment, the current spreads within the second cover electrode 152 rather than forming a current toward the second ohmic electrode 142 due to the high electrical resistance of the second ohmic electrode 142 . spreading) may occur. That is, in the second cover electrode 152 , current spreading may be mainly performed compared to the first cover electrode 151 .

In addition, in the embodiment, the current may be mainly formed toward the first ohmic electrode 141 rather than spreading within the first cover electrode 151 due to the low electrical resistance of the first ohmic electrode 141 . In other words, in the first ohmic electrode 141 compared to the second ohmic electrode 142 , current injection may be mainly performed.

In the semiconductor device according to the embodiment, the second cover electrode 152 is disposed to overlap the third region S3 in a vertical direction, so that a cross-sectional area thereof may be increased in a horizontal direction in which current spreading occurs. That is, in the third region S3 , the cross-sectional area of resistance from the second channel electrode 162 to the second ohmic electrode 142 may be increased by the second cover electrode 152 . Accordingly, the resistance of the second cover electrode 152 with respect to the current may be reduced.

Accordingly, the current spreading of the second cover electrode 152 on the third region S3 may be higher than the current spreading of the second cover electrode 152 on the first region S1 or the second region S2. . With this configuration, in the embodiment, the injection of current through the second cover electrode 152 in the third region S3 may further increase, so that the light output in the third region S3 may be improved. Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

Also, in the embodiment, the second cover electrode 152 may not overlap the first region S1 and the second region S2 in the vertical direction. Due to this configuration, the current injection I1 and I2 in the first region S1 and the second region S2 may not be smoothly performed compared to the current injection I3 in the third region S3.

In addition, since the second cover electrode 152 is not disposed on the first region S1 or the second region S2 , the second cover electrode 152 is removed from the second channel electrode 162 on the first region S1 or the second region S2 . Current injection toward the second ohmic electrode 142 may be directly performed without the second cover electrode 152 . Accordingly, the cross-sectional area of resistance between the second channel electrode 162 and the second ohmic electrode 142 may be reduced in correspondence to the absence of the second cover electrode 152 . Accordingly, the resistance Rp1 between the second channel electrode 162 and the second ohmic electrode 142 in the first region S1 and the second region S2 may increase. Accordingly, the resistance Rp2 between the second channel electrode 162 and the second ohmic electrode 142 in the third region S3 increases with the second channel electrode (Rp2) in the first region S1 and the second region S2. It may be smaller than the resistance Rp1 between the 162 and the second ohmic electrode 142 .

Due to this configuration, current injection into the third region S3 from the semiconductor device is concentrated, so that the light output in the first region S1 and the second region S2 is the light output in the third region S3 . may be lower. Accordingly, the semiconductor device according to the embodiment may compensate for optical deflection according to the TM mode.

The first cover electrode 151 may not overlap the third region S3 in the vertical direction. In other words, the first cover electrode 151 may not be disposed on the third region S3 . Due to this configuration, current injection may not be smoothly performed in the first region S1 or the second region S2 compared to the third region S3 .

The first cover electrode 151 may form an electrical channel with the first conductivity-type semiconductor layer 121 through the first ohmic electrode 141 .

In addition, in the embodiment, the current may be mainly formed toward the first ohmic electrode 141 rather than spreading within the first cover electrode 151 due to the low electrical resistance of the first ohmic electrode 141 . In other words, current injection may mainly occur in the first ohmic electrode 141 compared to the second ohmic electrode 142 .

Accordingly, in the semiconductor device according to the embodiment, the first cover electrode 151 may not overlap the third region S3 in the vertical direction. Accordingly, in the region overlapping the third region S3 in the vertical direction, the current flowing from the first channel electrode 161 to the first ohmic electrode 141 may not pass through the first cover electrode 151 .

In the third region S3 , current injection from the first channel electrode 161 to the first ohmic electrode 141 is directly performed without the first cover electrode 151 , and the first cover electrode 151 is absent. Correspondingly, the length of the current between the first channel electrode 161 and the first ohmic electrode 141 may decrease. Accordingly, in the third region S3 , the length of the resistance between the first channel electrode 161 and the first ohmic electrode 141 is reduced, and finally the resistance between the first channel electrode 161 and the first ohmic electrode 141 is reduced. (Rn2) may decrease. Accordingly, the current injection into the third region S3 is concentrated, and the light output in the first region S1 and the second region S2 is lower than the light output in the third region S3, so that it is in the TM mode. Accordingly, optical deflection may be compensated for. Due to this configuration, current injection in the third region S3 may not be smoothly performed compared to the third region S3 .

In addition, the first cover electrode 151 may be disposed on the first region S1 and the second region S2 . That is, the first cover electrode 151 may not overlap the third region S3 in the vertical direction, but may overlap the first region S1 or the second region S2 in the vertical direction.

Since the first cover electrode 151 is vertically overlapped with the first region S1 and the second region S2, the length of the first cover electrode 151 is equal to the length of the first cover electrode 151 based on the vertical direction in which the current injection occurs. The path of current injection may also be increased. That is, in the first region S1 and the second region S2 , the resistance Rn1 from the first channel electrode 161 to the first ohmic electrode 141 may be increased by the first cover electrode 151 . have.

Accordingly, the current injection (I1, I2) of the first cover electrode 151 in the first region S1 and the second region S2 is the current injection (I1, I2) of the first cover electrode 151 in the third region S3. It may be smaller than I3). With this configuration, in the embodiment, the injection of current through the first channel electrode 161 in the third region S3 may further increase, so that the light output in the third region S3 may be improved. Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

In an embodiment, the first channel electrode 161 includes a first sub-region 161a overlapping the recess 129 in the vertical direction, and a second sub-region 161b positioned between the recess 129 . can do. The first sub-region 161a and the second sub-region 161b may be alternately disposed in the first direction (X-axis direction) or the second direction (Y-axis direction).

The first sub-region 161a has a maximum width W1 (refer to FIG. 1 ) in the second direction (Y-axis direction) perpendicular to the first direction (X-axis direction) in the second direction ( Y-axis direction) may be smaller than the maximum width W2. For example, the first sub-region 161a may be circular on the plane XY, and the second sub-region 161b may have a quadrangular shape on the plane XY.

Accordingly, the contact area of the first channel electrode 161 with the first cover electrode 151 or the first ohmic electrode 141 in the recess 129 may increase. With this configuration, it is possible to prevent excessive current from flowing to the first ohmic electrode 141 seated in the recess 129 . Accordingly, the reliability of the semiconductor device according to the embodiment may be improved.

Also, in the embodiment, an oxide layer OL may be further disposed on the first ohmic electrode 141 . The oxide layer OL may be formed of various oxides.

In addition, the oxide layer OL may cover the first ohmic electrode 141 . Accordingly, the oxide layer OL may be positioned between the first ohmic electrode 141 and the first insulating layer 131 . Also, the oxide layer OL may be positioned between the first ohmic electrode 141 and the first cover electrode 151 . In addition, the oxide layer OL may be covered by the first cover electrode 151 . In other words, the oxide layer OL may overlap the first cover electrode 151 in a vertical direction.

In addition, the oxide layer OL may be positioned in the plurality of recesses 129 . Accordingly, the oxide layer OL may vertically overlap the first region S1 , the second region S2 , and the third region S3 .

More specifically, the oxide layer OL includes a first oxide layer OL1 vertically overlapping with the first region S1 or second region S1 and a second oxide layer vertically overlapping with the third region S3. (OL2).

According to an embodiment, the second oxide layer OL2 may include a through hole OLh. In addition, the through hole OLh may be disposed to overlap the third region S3 in a vertical direction. Also, the through hole OLh may not vertically overlap the first area S1 or the second area S2 .

In addition, the first ohmic electrode 141 may be exposed through the through hole OLh. Also, in the third region S3 , the first ohmic electrode 141 may contact the first cover electrode 151 through the through hole OLh. Accordingly, the path of the current between the first ohmic electrode 141 and the first cover electrode 151 may be decreased by the length in the vertical direction of the removed second oxide layer OL2 . In addition, electrical resistance between the first ohmic electrode 141 and the first cover electrode 151 may be reduced.

Alternatively, the first ohmic electrode 141 may not pass through the through hole OLh in the first region S1 or the second region S2 . Accordingly, the contact area between the first ohmic electrode 141 and the first cover electrode 151 may be reduced or limited.

In the first region S1 or the second region S2 , a current path between the first ohmic electrode 141 and the first cover electrode 151 moves in the vertical direction of the first oxide layer OL1 compared to the third region S3 . can be increased by the length. That is, the electrical resistance between the first ohmic electrode 141 and the first cover electrode 151 may increase.

According to this configuration, in the semiconductor device according to the embodiment, current is concentrated in the third region S3 compared to the first region S1 and the second region S2, so that the light output at the center of the semiconductor device is increased, resulting in a TM mode bias can be compensated for.

In an embodiment, the oxide layer OL may have a length (eg, thickness) of 3 nm or less in a vertical direction. When the thickness of the oxide layer OL is higher than 3 nm, there is a problem that the electrical connection from the first cover electrode 151 (or the first channel electrode) to the first ohmic electrode 141 may be opened. do.

FIG. 6 is a cross-sectional view taken along line BB′ in FIG. 1 .

Referring to FIG. 6 , in the third region S3 , as described above, the first ohmic electrode 141 may be electrically connected to the first channel electrode 161 without the first cover electrode. In addition, the first channel electrode 161 may contact the first ohmic electrode 141 through a through hole of the oxide layer OL disposed on the first ohmic electrode 141 . With this configuration, current injection into the third region S3 is concentrated, so that the light output in the first region S1 or the second region S2 is lower than the light output in the third region S3, TM It is possible to compensate for optical deflection according to the mode.

Further, in the third region S3 , the second cover electrode 152 is disposed between the second ohmic electrode 142 and the second channel electrode 162 , and the second ohmic electrode 142 and the second channel electrode ( 162) and may form an electrical channel. With this configuration, the current injection into the third region S3 is more concentrated, and in the semiconductor device, the light output from the first region S1 or the second region S2 is the light from the third region S3. It can be formed to be lower than the output. As a result, optical deflection according to the TM mode may be compensated.

In addition, the first channel electrode 161 and the second channel electrode 162 may be alternately disposed along the second direction (Y-axis direction) on the semiconductor structure 120 .

In addition, the fourth hole 123b may be disposed between adjacent second sub-regions disposed in the second direction. Also, the second cover electrode 152 and the second ohmic electrode 142 may be electrically connected to each other through the fourth hole 123b.

In an embodiment, the fourth hole 123b may not overlap the plurality of recesses 129 on the plane XY. In other words, the fourth hole 123b may not overlap the plurality of recesses 129 in the first direction (X-axis direction) or the second direction (Y-axis direction).

With this configuration, the area of the recess 129 and the first channel electrode 161 is easily secured to prevent overcurrent injection into the first ohmic electrode 141 and, at the same time, the area of the fourth hole 123b is also increased. It is easily secured to prevent overcurrent injection through the second ohmic electrode 142 .

7 is a plan view of a semiconductor device according to a second embodiment, FIG. 8 is a cross-sectional view taken along CC′ in FIG. 7, and FIG. 9 is a cross-sectional view taken along line DD′ in FIG. 7 .

The semiconductor device according to the second embodiment includes a substrate 110 , a semiconductor structure 120 disposed on the substrate 110 , a first insulating layer 131 disposed on the semiconductor structure 120 , and a first conductivity type semiconductor. The first ohmic electrode 141 disposed on the layer 121 , the second ohmic electrode 142 disposed on the second conductivity-type semiconductor layer 123 , and the first ohmic electrode 141 disposed on the first ohmic electrode 141 . The cover electrode 151 , the second cover electrode 152 disposed on the second ohmic electrode 142 , and the second insulating layer ( ) disposed on the first cover electrode 151 and the second cover electrode 152 . 132), a first channel electrode 161 electrically connected to the first cover electrode 151, a second channel electrode 162 electrically connected to the second cover electrode 152, and a first channel electrode 161 It may include a first pad 171 electrically connected to the first pad 171 and a second pad 172 electrically connected to the second channel electrode 162 . That is, it should be understood that the configuration described in the semiconductor device according to the above-described embodiment may be applied in the same manner except for the following description.

In the semiconductor device according to the second embodiment, the second cover electrode 152 may vertically overlap the first region S1 and the third region S3 . Also, the second cover electrode 152 may not overlap the second region S2 in a vertical direction. In addition, the first cover electrode 151 may vertically overlap the second region S2 and may not vertically overlap the first region S1 and the third region S3 . Accordingly, current is concentrated in the first region S1 and the third region S3 , so that the light output may be greater than the light output in the second region S2 . With this configuration, it is possible to easily compensate for the deflection according to the TM mode by adjusting the current concentration.

More specifically, in the semiconductor device according to the second embodiment, the second cover electrode 152 is disposed to overlap the first region S1 and the third region S3 in a vertical direction, so that the horizontal current spreading occurs. A cross-sectional area of the second cover electrode 152 may be increased based on the direction. That is, in the first region S1 and the third region S3 , the cross-sectional area of resistance from the second channel electrode 162 to the second ohmic electrode 142 may be increased by the second cover electrode 152 . . Accordingly, the resistance Rp2 of the second cover electrode 152 with respect to the current may decrease.

In addition, the current spreading of the second cover electrode 152 in the first region S1 and the third region S3 may be higher than the current spreading of the second cover electrode 152 in the second region S2 . With this configuration, in the embodiment, the injection of current through the second cover electrode 152 in the first region S1 and the third region S3 is further increased, so that the first region S1 and the third region S3 are further increased. ) can be improved. Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

Also, the second cover electrode 152 may not overlap the second region S2 in a vertical direction. Due to this configuration, current injection in the second region S2 may not be smoothly performed compared to the first region S1 and the third region S3 .

And since the second cover electrode 152 is not disposed on the second region S2, current injection from the second channel electrode 162 toward the second ohmic electrode 142 on the second region S2 is performed on the second cover. It can be done directly without the electrode 152 . Accordingly, the cross-sectional area of resistance between the second channel electrode 162 and the second ohmic electrode 142 may be reduced in correspondence to the absence of the second cover electrode 152 . Accordingly, the resistance Rp1 between the second channel electrode 162 and the second ohmic electrode 142 in the second region S2 may increase.

In the embodiment, the resistance Rp2 between the second channel electrode 162 and the second ohmic electrode 142 in the first region S1 and the third region S3 is the second channel electrode in the second region S2. It may be smaller than the resistance Rp1 between 162 and the second ohmic electrode 142 .

Accordingly, current injection into the first region S1 and the third region S3 is concentrated, so that the light output in the second region S2 is reduced in the first region S1 and the third region S3. Since it is lower than the optical output, optical deflection according to the TM mode can be compensated.

The first cover electrode 151 may not vertically overlap the first region S1 and the third region S3 . In other words, the first cover electrode 151 may not be disposed on the first region S1 and the third region S3 . Due to this configuration, current injection in the second region S2 may not be smoothly performed compared to the first region S1 and the third region S3 .

In addition, in the region overlapping the first region S1 and the third region S3 in the vertical direction, the current flowing from the first channel electrode 161 to the first ohmic electrode 141 passes through the first cover electrode 151 . may not pass.

In the first region S1 and the third region S3 , current injection from the first channel electrode 161 toward the first ohmic electrode 141 may be directly performed without the first cover electrode 151 . Accordingly, the length of the current between the first channel electrode 161 and the first ohmic electrode 141 may be reduced corresponding to the absence of the first cover electrode 151 . Accordingly, in the first region S1 and the third region S3 , the length of the resistance between the first channel electrode 161 and the first ohmic electrode 141 is reduced, and finally the first channel electrode 161 and the first ohmic electrode 141 are reduced. The resistance Rn2 between the ohmic electrodes 141 may decrease. Accordingly, current injection into the first region S1 and the third region S3 is concentrated, so that the light output in the second region S2 is reduced in the first region S1 and the third region S3. Since it is lower than the optical output, optical deflection according to the TM mode can be compensated. Due to this configuration, current injection in the first region S1 and the third region S3 may not be smoothly performed compared to the first region S1 and the third region S3 .

In addition, the first cover electrode 151 may be disposed on the second region S2 . That is, the first cover electrode 151 may not overlap the first region S1 and the third region S3 in the vertical direction, but may overlap the second region S2 in the vertical direction.

Since the first cover electrode 151 is disposed to overlap the second region S2 in the vertical direction, the current injection path may also increase by the length of the first cover electrode 151 based on the vertical direction in which the current injection occurs. can That is, in the second region S2 , the length of the resistance from the first channel electrode 161 to the first ohmic electrode 141 may be increased by the first cover electrode 151 . Accordingly, in the second region S2 , the resistance Rn1 to the current between the first channel electrode 161 and the first ohmic electrode 141 may increase.

Accordingly, the resistance Rn2 between the first channel electrode 161 and the first ohmic electrode 141 in the first region S3 and the third region S3 increases the resistance Rn2 in the second region S2 by the first channel electrode 161 ) and the first ohmic electrode 141 may be less than the resistance Rn1.

The current injection of the first cover electrode 151 in the second region S2 may be smaller than that of the first cover electrode 151 in the first region S1 and the third region S3 . With this configuration, in the embodiment, the injection of current through the first channel electrode 161 in the first region S1 and the third region S3 is further increased, so that the first region S1 and the third region S3 are further increased. ) can be improved. Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

10 is a plan view of a semiconductor device according to a third embodiment, FIG. 11 is a cross-sectional view taken along line EE′ in FIG. 10, and FIG. 12 is a cross-sectional view taken along line FF′ in FIG. 10 .

The semiconductor device according to the third embodiment includes a substrate 110 , a semiconductor structure 120 disposed on the substrate 110 , a first insulating layer 131 disposed on the semiconductor structure 120 , and a first conductivity type semiconductor The first ohmic electrode 141 disposed on the layer 121 , the second ohmic electrode 142 disposed on the second conductivity-type semiconductor layer 123 , and the first ohmic electrode 141 disposed on the first ohmic electrode 141 . The cover electrode 151 , the second cover electrode 152 disposed on the second ohmic electrode 142 , and the second insulating layer ( 132), a first channel electrode 161 electrically connected to the first cover electrode 151, a second channel electrode 162 electrically connected to the second cover electrode 152, and a first channel electrode 161 It may include a first pad 171 electrically connected to the first pad 171 and a second pad 172 electrically connected to the second channel electrode 162 . That is, it should be understood that the configuration described in the semiconductor device according to the above-described embodiment may be applied in the same manner except for the following description.

In the semiconductor device according to the third embodiment, the second cover electrode 152 may vertically overlap the second region S2 and the third region S3 . Also, the second cover electrode 152 may not overlap the first region S1 in a vertical direction. In addition, the first cover electrode 151 may vertically overlap the first region S1 and may not vertically overlap the second region S2 and the third region S3 . Accordingly, current is concentrated in the first region S1 and the third region S3 , so that the light output may be greater than the light output in the first region S1 . With this configuration, it is possible to easily compensate for the deflection according to the TM mode by adjusting the current concentration.

More specifically, in the semiconductor device according to the third embodiment, the second cover electrode 152 is disposed to overlap the second region S2 and the third region S3 in the vertical direction, so that the horizontal current spreading occurs. A cross-sectional area of the second cover electrode 152 may be increased based on the direction. That is, in the second region S2 and the third region S3 , the cross-sectional area of resistance from the second channel electrode 162 to the second ohmic electrode 142 may be increased by the second cover electrode 152 . . Accordingly, the resistance Rp2 of the second cover electrode 152 with respect to the current may decrease. In particular, since the resistance Rp2 of the second cover electrode 152 is reduced even in the second region S2 to which the current is injected through the second pad 172 , the overall current injection may be facilitated. Accordingly, the current spreading can be further improved.

Accordingly, the current spreading of the second cover electrode 152 in the second region S2 and the third region S3 may be higher than the current spreading of the second cover electrode 152 in the first region S1. . With this configuration, in the embodiment, the injection of current through the second cover electrode 152 in the second region S2 and the third region S3 is further increased, so that the second region S2 and the third region S3 are further increased. ) can be improved. Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

Also, the second cover electrode 152 may not overlap the first region S1 in a vertical direction. With this configuration, current injection in the first region S1 may not be smoothly performed compared to the second region S2 and the third region S3 .

And since the second cover electrode 152 is not disposed on the first region S1 , the current injection from the second channel electrode 162 toward the second ohmic electrode 142 on the first region S1 is performed on the second cover It can be done directly without the electrode 152 . Accordingly, the cross-sectional area of resistance between the second channel electrode 162 and the second ohmic electrode 142 may be reduced in correspondence to the absence of the second cover electrode 152 . Accordingly, the resistance Rp1 between the second channel electrode 162 and the second ohmic electrode 142 in the first region S1 may increase. Accordingly, the resistance Rp2 between the second channel electrode 162 and the second ohmic electrode 142 in the third region S3 and the second region S2 increases with the second channel electrode (Rp2) in the first region S1. It may be smaller than the resistance Rp1 between the 162 and the second ohmic electrode 142 . With this configuration, current injection into the second region S2 and the third region S3 is concentrated, so that the light output in the first region S1 is reduced to the second region S2 and the third region S3 . Since it is lower than the light output at , it is possible to compensate for light deflection according to the TM mode.

The first cover electrode 151 may not vertically overlap the second region S2 and the third region S3 . In other words, the first cover electrode 151 may not be disposed on the second region S2 and the third region S3 . Accordingly, in the region overlapping the second region S2 and the third region S3 in the vertical direction, a current flowing from the first channel electrode 161 to the first ohmic electrode 141 is transferred to the first cover electrode 151 . may not pass through. Due to this configuration, current injection in the first region S1 may not be smoothly performed compared to the second region S2 and the third region S3.

In the second region S2 and the third region S3 , current injection from the first channel electrode 161 to the first ohmic electrode 141 may be directly performed without the first cover electrode 151 . Accordingly, the length of the current between the first channel electrode 161 and the first ohmic electrode 141 may be reduced corresponding to the absence of the first cover electrode 151 . Accordingly, in the second region S2 and the third region S3 , the length of the resistance between the first channel electrode 161 and the first ohmic electrode 141 is reduced, and finally the first channel electrode 161 and the first ohmic electrode 141 are reduced. The resistance Rn2 between the ohmic electrodes 141 may decrease. Accordingly, current injection into the second region S2 and the third region S3 is concentrated, so that the light output in the first region S1 is reduced in the second region S2 and the third region S3. Since it is lower than the optical output, optical deflection according to the TM mode can be compensated. Due to this configuration, current injection in the second region S2 and the third region S3 may not be smoothly performed compared to the second region S2 and the third region S3 .

Also, a first cover electrode 151 may be disposed on the first region S1 . That is, the first cover electrode 151 may not overlap the second region S2 and the third region S3 in the vertical direction, but may overlap the first region S1 in the vertical direction.

Since the first cover electrode 151 is disposed to overlap the first region S1 in the vertical direction, the current injection path may also increase by the length of the first cover electrode 151 based on the vertical direction in which the current injection occurs. can That is, in the first region S1 , the length of the resistance from the first channel electrode 161 to the first ohmic electrode 141 may be increased by the first cover electrode 151 . Accordingly, the resistance Rn1 to the current between the first channel electrode 161 and the first ohmic electrode 141 may increase.

The resistance Rn2 between the first channel electrode 161 and the first ohmic electrode 141 in the second region S2 and the third region S3 increases with the first channel electrode 161 in the first region S1. It may be smaller than the resistance Rn1 between the first ohmic electrodes 141 . Accordingly, the current injection of the first cover electrode 151 in the first region S1 may be smaller than that of the first cover electrode 151 in the second region S2 and the third region S3. Due to this configuration, in the embodiment, the injection of current through the first channel electrode 161 in the second region S2 and the third region S3 is further increased, so that the second region S2 and the third region S3 are further increased. ) can be improved. Accordingly, the light output at the center of the semiconductor device is increased to compensate for the deflection according to the TM mode. FIG. 13 is a plan view of a semiconductor device according to a modified example, and FIG. .

13 and 14 , the semiconductor device according to the modified example includes a substrate 110 , a semiconductor structure 120 disposed on the substrate 110 , and a first insulating layer 131 disposed on the semiconductor structure 120 . ), the first ohmic electrode 141 disposed on the first conductivity type semiconductor layer 121 , the second ohmic electrode 142 and the first ohmic electrode 141 disposed on the second conductivity type semiconductor layer 123 . ) on the first cover electrode 151 disposed on the second ohmic electrode 142 , the second cover electrode 152 disposed on the second ohmic electrode 142 , and on the first cover electrode 151 and the second cover electrode 152 . The disposed second insulating layer 132 , the first channel electrode 161 electrically connected to the first cover electrode 151 , the second channel electrode 162 electrically connected to the second cover electrode 152 , It may include a first pad 171 electrically connected to the first channel electrode 161 and a second pad 172 electrically connected to the second channel electrode 162 . That is, it should be understood that the configuration described in the semiconductor device according to the above-described embodiment may be applied in the same manner except for the following description.

In addition, the semiconductor device may include a first outer surface M1 , a second outer surface M2 , a third outer surface M3 , and a fourth outer surface M4 . The first outer surface M1 and the second outer surface M2 may face each other, and the third outer surface M3 and the fourth outer surface M4 may face each other. In addition, a third outer surface M3 and a fourth outer surface M4 may be positioned between the first outer surface M1 and the second outer surface M2 . And when the first outer surface (M1), the second outer surface (M2), the third outer surface (M3) and the fourth outer surface (M4) are located on the outermost side of the substrate 110 or the semiconductor structure 120, it It will be described below as a reference.

And the second virtual line VL2 is a line that bisects the third outer surface M3 and the fourth outer surface M4. In addition, the first central point C1 may be an intersection of the first virtual line VL1 and the second virtual line VL2 .

Also, the semiconductor device according to the modified example may include a central region CR and an edge region ER surrounding the central region CR. The center area CR and the edge area ER may be divided based on a predetermined distance from the center point C1 . The central region CR may be set in various ways, such as circular or polygonal.

In addition, it should be understood that the central region CR is a partial region of the above-described third region S3 , and a region adjacent to the central point in the third region S3 may be viewed as the central region CR. The edge area ER may include the first area S1 and the second area S2 described above. Also, the edge area ER may further include the remaining area of the third area S3 .

Also, in the semiconductor device according to the modified example, the second cover electrode 152 may vertically overlap the central region CR. Also, the second cover electrode 152 may not overlap the edge region ER in a vertical direction. In addition, the first cover electrode 151 may overlap the edge region ER in a vertical direction and may not overlap the center region CR in a vertical direction. Accordingly, current is concentrated in the first region S1 and the third region S3 , so that the light output may be greater than that of the edge region ER. With this configuration, it is possible to easily compensate for the deflection according to the TM mode by adjusting the current concentration.

Specifically, in the semiconductor device according to the modified example, the second cover electrode 152 is disposed to overlap the central region CR in the vertical direction, and the second cover electrode 152 is based on the horizontal direction in which the current spreading occurs. can be increased in cross-sectional area. That is, in the central region CR, the cross-sectional area of resistance from the second channel electrode 162 to the second ohmic electrode 142 may be increased by the second cover electrode 152 . Accordingly, the resistance of the second cover electrode 152 with respect to the current may be reduced.

Accordingly, the current spreading of the second cover electrode 152 on the center region CR may be higher than the current spreading of the second cover electrode 152 on the edge region ER. With this configuration, in the embodiment, the injection of current through the second cover electrode 152 in the central region CR may further increase, so that the light output in the central region CR may be improved. Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

Also, the second cover electrode 152 may not overlap the edge region ER in a vertical direction. Due to this configuration, current injection in the edge region ER may not be smoothly performed compared to the center region CR.

And since the second cover electrode 152 is not disposed on the edge region ER, current injection from the second channel electrode 162 to the second ohmic electrode 142 on the edge region ER is performed by the second cover electrode ( 152) can be done directly. Accordingly, the cross-sectional area of resistance between the second channel electrode 162 and the second ohmic electrode 142 may be reduced in correspondence to the absence of the second cover electrode 152 . Accordingly, resistance between the second channel electrode 162 and the second ohmic electrode 142 on the edge region ER may increase.

Accordingly, the current injection IER into the edge region ER may be lower than the current injection into the center region CR. In addition, current injection into the central region CR is concentrated, so that the optical output in the edge region ER is lower than the optical output in the central region CR, so that the optical deflection according to the TM mode can be compensated.

The first cover electrode 151 may not overlap the central region CR in a vertical direction. In other words, the first cover electrode 151 may not be disposed on the central region CR. Due to this configuration, current injection in the edge region ER may not be smoothly performed compared to the center region CR.

As described above, the contact resistance between the first conductivity type semiconductor layer 121 and the first ohmic electrode 141 may be relatively lower than the contact resistance between the second conductivity type semiconductor layer 123 and the second ohmic electrode 142 . can

In addition, the first cover electrode 151 forms an electrical channel with the first conductive semiconductor layer 121 through the first ohmic electrode 141 , and the second cover electrode 152 connects through the second ohmic electrode 142 . An electrical channel may be formed with the second conductivity type semiconductor layer 123 .

In addition, in the embodiment, the current may be mainly formed toward the first ohmic electrode 141 rather than spreading within the first cover electrode 151 due to the low electrical resistance of the first ohmic electrode 141 . In other words, current injection may mainly occur in the first ohmic electrode 141 compared to the second ohmic electrode 142 .

Accordingly, in the semiconductor device according to the embodiment, the first cover electrode 151 may not overlap the central region CR in the vertical direction. Accordingly, the current flowing from the first channel electrode 161 to the first ohmic electrode 141 may not pass through the first cover electrode 151 in the region overlapping the central region CR in the vertical direction.

In the central region CR, current injection from the first channel electrode 161 toward the first ohmic electrode 141 may be directly performed without the first cover electrode 151 . Accordingly, the length of the current between the first channel electrode 161 and the first ohmic electrode 141 may be reduced corresponding to the absence of the first cover electrode 151 . Accordingly, in the central region CR, the length of the resistance between the first channel electrode 161 and the first ohmic electrode 141 is reduced, so that the resistance between the first channel electrode 161 and the first ohmic electrode 141 is finally increased. can decrease. Accordingly, current injection into the central region CR is concentrated, and the light output in the edge region ER is lower than the optical output in the central region CR, so that the optical deflection according to the TM mode can be compensated. With this configuration, current injection in the central region CR may not be smoothly performed compared to the central region CR.

Also, the first cover electrode 151 may be disposed on the edge region ER. That is, the first cover electrode 151 may not overlap the center region CR in the vertical direction, but may overlap the edge region ER in the vertical direction.

Since the first cover electrode 151 is disposed to overlap the edge region ER in the vertical direction, the path of current injection can also be increased by the length of the first cover electrode 151 based on the vertical direction in which the current injection occurs. have. That is, in the edge region ER, the length of the resistance from the first channel electrode 161 to the first ohmic electrode 141 may be increased by the first cover electrode 151 . Accordingly, resistance to current between the first channel electrode 161 and the first ohmic electrode 141 may be reduced.

Accordingly, the current injection of the first cover electrode 151 in the edge region ER may be smaller than that of the first cover electrode 151 in the center region CR. According to this configuration, in the embodiment, since the injection of current through the first channel electrode 161 in the central region CR may be further increased, the light output in the central region CR may be improved. Accordingly, the deflection according to the TM mode may be compensated by improving the light output in the central region located at the center of the third region.

15 is a plan view of a semiconductor device according to a fourth exemplary embodiment, FIG. 16 is a cross-sectional view taken along line HH′ in FIG. 15 , and FIG. 17 is a first pad, a second pad, and a second pad of the semiconductor device according to the fourth exemplary embodiment. A diagram showing a first cover electrode, a second cover electrode, a first channel electrode, and a second channel electrode.

15 to 17 , the semiconductor device according to the fourth embodiment includes a substrate 110 , a semiconductor structure 120 disposed on the substrate 110 , and a first insulating layer disposed on the semiconductor structure 120 . 131 , a first ohmic electrode 141 disposed on the first conductivity type semiconductor layer 121 , a second ohmic electrode 142 disposed on the second conductivity type semiconductor layer 123 , and a first ohmic electrode The first cover electrode 151 disposed on the 141 , the second cover electrode 152 disposed on the second ohmic electrode 142 , and the first cover electrode 151 and the second cover electrode 152 . The second insulating layer 132 disposed thereon, the first channel electrode 161 electrically connected to the first cover electrode 151 , and the second channel electrode 162 electrically connected to the second cover electrode 152 . ), a first pad 171 electrically connected to the first channel electrode 161 , and a second pad 172 electrically connected to the second channel electrode 162 . That is, it should be understood that the configuration described in the semiconductor device according to the above-described embodiment may be applied in the same manner except for the following description.

The first channel electrode 161 may be spaced apart from the second channel electrode 162 in the first direction. For example, the first channel electrode 161 may be disposed on one side on the semiconductor structure 120 , and the second channel electrode 162 may be disposed on the other side on the semiconductor structure 120 . In addition, the first channel electrode 161 may overlap the first pad 171 in a vertical direction, and the second channel electrode 162 may overlap the second pad 172 in a vertical direction. Also, the first channel electrode 161 may be spaced apart from the second pad 172 in the first direction, and the second channel electrode 162 may be spaced apart from the first pad 171 in the first direction.

In addition, the recess 129 in the semiconductor structure 120 may be formed in various shapes. As illustrated, the recess 129 may include a first recess 129 - 1 and a second recess 129 - 2 . The first recess 129 - 1 may have a shape extending in the first direction from one side of the semiconductor structure 120 . For example, the length La of the first recess 129 - 1 in the first direction from the left side of the semiconductor structure 120 may be greater than the length Lb in the second direction.

Also, the second recess 129 - 2 is disposed on the other side of the semiconductor structure 120 and may be plural. The second recess 129 - 2 may be formed in a circular shape on the right side of the semiconductor structure 120 .

Also, the first channel electrode 161 may at least partially overlap the first recess 129 - 1 positioned at one side of the semiconductor structure 120 in the vertical direction. In addition, the first channel electrode 161 may be electrically connected to the first recess 129 - 1 .

In addition, the first cover electrode 151 may be disposed to vertically overlap the first region S1 and the second region S2 . Also, the first cover electrode 151 may not overlap the third region S3 in a vertical direction.

Also, the second cover electrode 152 may overlap the third region S3 in a vertical direction. In addition, the second cover electrode 152 may not vertically overlap the first region S1 and the second region S2 .

According to this configuration, the current from the first channel electrode 161 to the first ohmic electrode 141 in the third region S3 may be relatively more concentrated compared to the first and second regions S1 and S2 . Accordingly, the light output in the third area S3 may be greater than the light output in the first area S1 and the second area S2 . Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

18 is a cross-sectional view of a semiconductor device according to another modification.

Referring to FIG. 18 , a semiconductor device according to another modified example includes a substrate 110 , a semiconductor structure 120 disposed on the substrate 110 , a first insulating layer 131 disposed on the semiconductor structure 120 , On the first ohmic electrode 141 disposed on the first conductivity type semiconductor layer 121 , the second ohmic electrode 142 disposed on the second conductivity type semiconductor layer 123 , and the first ohmic electrode 141 The first cover electrode 151 disposed on the , the second cover electrode 152 disposed on the second ohmic electrode 142 , and the first cover electrode 151 and the second cover electrode 152 disposed on the The second insulating layer 132 , the first channel electrode 161 electrically connected to the first cover electrode 151 , the second channel electrode 162 electrically connected to the second cover electrode 152 , and the first It may include a first pad 171 electrically connected to the channel electrode 161 and a second pad 172 electrically connected to the second channel electrode 162 . That is, it should be understood that the configuration described in the semiconductor device according to the above-described embodiment may be applied in the same manner except for the following description.

In the semiconductor device according to another modification, the second cover electrode 152 has the thicknesses H1a and H1b in the first region S1 or the second region S2 in the third region S3. 152 may be smaller than the thickness H2. The thickness may be a length in the vertical direction.

For example, the second cover electrode 152 may have the same thickness H1a in the first region S1 and the thickness H1b in the second region S2 . In addition, the thickness H2 of the second cover electrode 152 in the third region S3 may be greater than the thickness H1a in the first region S1 . With this configuration, the cross-sectional area in the third region S3 of the second cover electrode 152 is larger than the cross-sectional area in the first region S1 or the second region S2 based on the horizontal direction in which the current spreading occurs. can That is, in the third region S3 , the cross-sectional area of the resistance from the second channel electrode 162 to the second ohmic electrode 142 by the second cover electrode 152 is the first region S1 or the second region ( S2), the cross-sectional area of the resistance from the second channel electrode 162 to the second ohmic electrode 142 may be greater than that of the second channel electrode 162 . Accordingly, the resistance of the second cover electrode 152 with respect to the current may be smaller in the third region S3 than in the first region S1 or the second region S2.

With this configuration, since the injection of current through the second cover electrode 152 in the third region S3 is relatively larger than that of the first region S1 or the second region S2, the third region S3 light output can be improved. Accordingly, the light output at the center of the semiconductor device may be increased to compensate for the deflection according to the TM mode.

Additionally, in the semiconductor device according to the modified example, the thicknesses H3a and H3b of the first cover electrode 151 in the first region S1 or the second region S2 are the first cover electrode in the third region S3. It may be greater than the thickness H4 of (151).

Due to the difference in the thickness of the first cover electrode 151 , the length of the current flowing from the first channel electrode 161 to the first ohmic electrode 141 in the first region S1 or the second region S2 becomes the second. The length of the current flowing from the first channel electrode 161 to the first ohmic electrode 141 in the third region S3 may be greater than the length.

In addition, as described above, since the first ohmic electrode 141 has a low contact resistance and thus current injection mainly occurs in the vertical direction, the resistance in the third region S3 is increased in the first region S1 or the second region S2. ) may be less than the resistance.

Accordingly, current injection is relatively concentrated in the third region S3 having a lower resistance compared to the first region S1 or the second region S2, so that the light in the first region S1 or the second region S2 is relatively concentrated. Since the output is lower than the optical output in the third region S3 , the optical deflection according to the TM mode may be compensated.

The semiconductor device may be applied to various types of light source devices. Exemplarily, the light source device may be a concept including a sterilization device, a curing device, a lighting device, a display device, and a vehicle lamp. That is, the semiconductor element may be applied to various electronic devices that are disposed in a case and provide light.

The sterilization apparatus may include a semiconductor device according to an embodiment to sterilize a desired region. The sterilizer may be applied to household appliances such as water purifiers, air conditioners, and refrigerators, but is not limited thereto. That is, the sterilization device may be applied to various products (eg, medical devices) requiring sterilization.

For example, the water purifier may include a sterilizing device according to an embodiment to sterilize circulating water. The sterilizer may be disposed in a nozzle or a discharge port through which water circulates to irradiate ultraviolet rays. In this case, the sterilization device may include a waterproof structure.

The curing apparatus may include a semiconductor device according to an embodiment to cure various types of liquids. Liquid may be the broadest concept including all of the various materials that are cured when irradiated with ultraviolet light. Illustratively, the curing apparatus may cure various types of resins. Alternatively, the curing device may be applied to curing cosmetic products such as nail polish.

The lighting device may include a light source module including a substrate and a semiconductor device according to an embodiment, a heat dissipating unit for dissipating heat from the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing it to the light source module. In addition, the lighting device may include a lamp, a head lamp, or a street lamp.

The display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may constitute a backlight unit.

The reflector is disposed on the bottom cover, and the light emitting module may emit light. The light guide plate may be disposed in front of the reflection plate to guide the light emitted from the light emitting module to the front, and the optical sheet may include a prism sheet and the like and may be disposed in front of the light guide plate. The display panel may be disposed in front of the optical sheet, the image signal output circuit may supply an image signal to the display panel, and the color filter may be disposed in front of the display panel.

When used as a backlight unit of a display device, the semiconductor device may be used as an edge type backlight unit or may be used as a direct type backlight unit.

The semiconductor device may be a laser diode in addition to the light emitting diode described above.

The laser diode may include a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer having the above-described structure in the same manner as the light emitting device. In addition, an electro-luminescence phenomenon in which light is emitted when an electric current flows after bonding a p-type first conductivity type semiconductor and an n-type second conductivity type semiconductor is used, but the directionality of the emitted light and there is a difference in phase. That is, the laser diode uses a phenomenon called stimulated emission and constructive interference, so that light having one specific wavelength (monochromatic beam) can be emitted with the same phase and in the same direction. Therefore, it can be used for optical communication, medical equipment, and semiconductor processing equipment.

As the light receiving element, a photodetector, which is a kind of transducer that detects light and converts its intensity into an electrical signal, may be exemplified. As such a photodetector, a photovoltaic cell (silicon, selenium), an optical output device (cadmium sulfide, cadmium selenide), a photodiode (for example, a PD having a peak wavelength in a visible blind spectral region or a true blind spectral region), a photo A transistor, a photomultiplier tube, a phototube (vacuum, gas-filled), an IR (Infra-Red) detector, etc., but the embodiment is not limited thereto.

In addition, a semiconductor device such as a photodetector may be generally manufactured using a direct bandgap semiconductor having excellent light conversion efficiency. Alternatively, the photodetector has various structures, and the most common structures include a pin-type photodetector using a pn junction, a Schottky-type photodetector using a Schottky junction, and a Metal Semiconductor Metal (MSM) photodetector. have.

A photodiode may include a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer having the above-described structure in the same way as the light emitting device, and has a pn junction or pin structure. The photodiode operates by applying a reverse bias or zero bias, and when light is incident on the photodiode, electrons and holes are generated and a current flows. In this case, the magnitude of the current may be substantially proportional to the intensity of light incident on the photodiode.

A photovoltaic cell or solar cell is a type of photodiode, and may convert light into electric current. The solar cell may include a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer having the above-described structure in the same manner as the light emitting device.

In addition, it may be used as a rectifier of an electronic circuit through the rectification characteristic of a general diode using a p-n junction, and may be applied to an oscillation circuit by being applied to a very high frequency circuit.

In addition, the above-described semiconductor device is not necessarily implemented only as a semiconductor, and may further include a metal material in some cases. For example, a semiconductor device such as a light receiving device may be implemented using at least one of Ag, Al, Au, In, Ga, N, Zn, Se, P, or As, and may be formed using a p-type or n-type dopant. It may be implemented using a doped semiconductor material or an intrinsic semiconductor material.

Claims (10)

Board;
a first conductivity type semiconductor layer disposed on the substrate, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; a semiconductor structure comprising a semiconductor layer and a recess penetrating the active layer;
a first electrode disposed on the first conductivity-type semiconductor layer;
a second electrode disposed on the second conductivity-type semiconductor layer;
a first cover electrode disposed on the first electrode and electrically connected to the first electrode;
a second cover electrode electrically connected to the second electrode disposed on the second electrode;
a first pad electrically connected to the first cover electrode; and
a second pad electrically connected to the second cover electrode; and
The semiconductor structure may include a first area overlapping the first pad in a vertical direction, a second area overlapping the second pad in a vertical direction, and a third area disposed between the first area and the second area. includes an area,
the second cover electrode overlaps the second region and the third region in the vertical direction and does not overlap the first region in the vertical direction;
The first cover electrode does not overlap the first region and the third region in the vertical direction, but overlaps the second region in the vertical direction.
According to claim 1,
The second cover electrode has a thickness in the first region or the second region that is smaller than a thickness in the third region.
According to claim 1,
The first cover electrode is a semiconductor device having a thickness greater than a thickness in the third region in the first region or in the second region.
According to claim 1,
a first channel electrode disposed on the first cover electrode and electrically connected to the first cover electrode; and
It is disposed on the second cover electrode, the second channel electrode; further comprising,
The first channel electrode and the second channel electrode extend in a horizontal direction from the first pad toward the second pad.
5. The method of claim 4,
The first channel electrode and the second channel electrode are disposed to cross each other in a direction perpendicular to a horizontal direction.
6. The method of claim 5,
the first channel electrode and the second channel electrode overlap the first region, the second region, and the third region in a vertical direction;
the first channel electrode includes a first sub-region overlapping the recess in the vertical direction and a second sub-region positioned between the recesses in the horizontal direction;
A maximum width of the first sub-region in a direction perpendicular to the horizontal direction is greater than a maximum width of the second sub-region in a direction perpendicular to the horizontal direction.
According to claim 1,
The semiconductor device further comprising an oxide layer disposed between the first ohmic electrode and the first cover electrode.
8. The method of claim 7,
The oxide layer includes a first oxide layer overlapping the first region and the second region in the vertical direction, and a second oxide layer overlapping the third region in the vertical direction,
The second oxide layer includes a through hole.
9. The method of claim 8,
The first ohmic electrode is a semiconductor device exposed through the through hole.
8. The method of claim 7,
The oxide layer is a semiconductor device having a thickness of 3 nm or less.

Images