KR20210050359A - Display device - Google Patents

Abstract

A display device includes a display panel, a data driving circuit, a gate driving circuit and a timing controller. The timing controller modulates input image data with a modulation pattern, which minutely controls gradations expressed by pixels by temporally and/or spatially dispersing image of two gradations, to deliver the same the source drive IC through a panel interior interface. When gradations of image data of a first area handled by a first source drive IC are the same, first image data of an initial predetermined number of pixel lines of the first area is transmitted to the first source drive IC, and then, the transmission of second image data of remaining pixel lines of the first area is stopped, and a second modulation pattern is generated based on a first modulation pattern applied to the first image data to be transmitted to the first source drive IC.

Description

Display device {DISPLAY DEVICE}

This specification relates to a display device, and more particularly, to a display device and a method for finely adjusting the gray scale of a screen without data transmission during low speed driving.

Display devices include a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), and a quantum dot display panel (QD). Electroluminescent display devices are divided into inorganic light emitting display devices and organic light emitting display devices according to the material of the emission layer.

A liquid crystal panel and an organic light emitting display panel are mainly used for portable information devices, and an organic light emitting display device that does not use a backlight unit is advantageous from the viewpoint of power consumption.

In a display device, particularly in a display device of a portable information device, various methods are known to reduce power consumption. When one of them is the same video data is input to the area in charge of the source drive IC, the timing controller transmits only the first of the video data and the remaining video data when transmitting the video data for the corresponding area to the corresponding source drive IC. The source driver IC is a technology that displays a corresponding area by repeatedly displaying the transmitted image data, and is called a Low Power Tx Driving (LPTD) technique.

Meanwhile, on the screen

If any color or gradation level cannot be displayed,

Similar colors or gradations as possible by collecting pixels of existing colors

Creating levels

On the other hand, when a certain color or gradation level cannot be displayed on the screen, there is a data modulation technique that collects pixels of a color or gradation that can be displayed to create a similar color or gradation level. The gradation expressed by the pixels is finely adjusted by dispersing temporally and/or spatially, and is called FRC (Frame Rate Control). Since a few pixels are collected and gradation is finely adjusted, there is an advantage in that the color depth displayed on the screen can be increased without increasing the cost.

The FRC technique finely adjusts the gradation of pixels for each frame to increase the color depth, so the image data transmitted from the timing controller to the source drive IC is changed for each frame. Therefore, even if the source drive IC displays video data of the same gradation in its own area, the FRC technique cannot be employed in the LPTD technique in which data transmission between the controller and the source drive IC is stopped in order to reduce timing power consumption.

The embodiments disclosed in this specification take this situation into account, and the purpose of this specification is to finely adjust image data to be displayed on a screen without data transmission from a display device.

Another object of this specification is to provide a configuration in which a pattern for finely adjusting the gradation of image data is applied to each output channel without adding complicated logic.

A display device according to an exemplary embodiment includes: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels; A data driving circuit including at least one source drive IC converting image data into a data voltage in a channel unit and supplying it to a plurality of pixels through a data line; A gate driving circuit for supplying a scan signal to a gate line connected to pixels to supply a data voltage among the plurality of gate lines; And modulating the input image data with a modulation pattern that finely adjusts the gradation expressed by the pixels by temporally and/or spatially distributing the image data of two gradations, and transferring the input image data to the source drive IC through the panel internal interface. When the image data in the first area covered by the source drive IC has the same gray level, the first image data of the first predetermined number of pixel lines in the first area is transmitted to the first source drive IC and then the remaining pixel lines in the first area And a timing controller configured to stop transmission of the second image data of the first image data, generate a second modulation pattern based on the first modulation pattern applied to the first image data, and transmit the second modulation pattern to the first source drive IC. .

Accordingly, FRC driving is possible even when the LPTD function is turned on, so that data is not transmitted to the source drive IC, thereby reducing power consumption and richly expressing gradations.

In addition, RFC patterns can be applied to the output channel with a simple configuration without adding complex logic.

1 illustrates that a display panel is divided and driven by a plurality of source drive ICs.
2 and 3 show the principle of operation of the FRC,
4 shows a display device as a functional block,
5 shows an equivalent circuit of a pixel included in an OLED display panel,
6 shows an equivalent circuit of pixels included in a liquid crystal display panel,
7 shows the FRC pattern for the lower 3 bits,
8 is an example in which the source drive IC determines RFC pattern data to be applied to image data in the same gray area to which the LPTD function is applied, referring to the FRC pattern applied to the image data of the first pixel line in the same gray area to which the LPTD function is applied. Is shown,
9(a) shows another FRC pattern data for expressing gray scale 010 in the same gray scale area in which the LPTD function is used,
9(b) shows FRC pattern data for expressing gray scale 100,
10 shows a configuration for transmitting a line pulse for applying an FRC pattern for each pixel line from a timing controller to a data driving circuit,
11 shows an example in which the FRC pattern is changed for each pixel line in synchronization with a line pulse.
12 shows an example of repeating the FRC pattern in units of a predetermined number of output channels and units of a predetermined number of horizontal lines,
13 shows a specific configuration of a data driving circuit,
14 shows a configuration for adding/subtracting/maintaining image data according to RFC pattern data for each output channel unit.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the content of this specification may unnecessarily obscure or obstruct understanding of the content, the detailed description thereof will be omitted.

First, the LPTD technique will be briefly described.

A typical display device includes a timing controller, a data driving circuit, a gate driving circuit, and a panel, and the timing controller receives video data (or image data) and a timing signal from a source (or host) and processes the data to drive a data driving circuit. And the gate driving circuit as an image signal and a control signal, and the data driving circuit and the gate driving circuit are directly connected to a pixel included in the panel through a data line and a gate line to display an image through the pixel.

The host and the timing controller are connected by a wiring line according to the system interface such as Vx1, and the timing controller and the data driving circuit are connected by a pair of wiring lines according to the panel internal interface such as EPI (Embedded Clock PP Interface), and the timing controller and the gate The driving circuit is connected by a predetermined number of lines, and the data driving circuit and the gate driving circuit are physically directly connected to the panel by a number of lines corresponding to the resolution of the panel.

The data driving circuit is composed of a predetermined number, for example, 4 or 6 source drive ICs. The source drive IC receives clock signals, control signals, and image data from a timing controller through an Intra Panel Interface such as an EPI interface. The timing controller and each source drive IC are connected 1:1, point-to-point, through a pair of EPI wires. The source drive IC restores the clock from the signal provided by the timing controller, fixes the phase and frequency of the internal clock, and outputs a lock signal, and the timing controller stores control data and video data after the lock signal is received from the last source drive IC. It transmits the included data packet to the source drive IC.

The timing controller converts the video data and control data of the input image into serial data and distributes it to a plurality of transmission units (Tx ports). It's in the controller. Each transmission unit (Tx port) of the timing controller is connected to the receiving unit of one source drive IC through an EPI interface to transmit video data and control data, and the receiving unit of the source drive IC separates the received data into video data and control data. And supply the video data to the pixels.

When the LPTD function is on and video data to be displayed in a predetermined area is input from the host in the same gray scale, the timing controller may detect this and may not transmit some video data to the source drive IC responsible for the corresponding area. Data transmission On/Off (EPI Tx On/Off) is possible for each unit separately. That is, when the screen is divided into several areas and each area is driven by a separate source drive IC, data transmission of the transmission unit corresponding to the source drive IC in charge of the area to which video data of the same gray level is input is stopped (EPI Tx Off), data transmission can be continued for the transmission unit corresponding to the source drive IC in charge of another area (EPI Tx On).

1 illustrates that a display panel is divided and driven by a plurality of source drive ICs.

In FIG. 1, a first source drive IC (SD-IC#1) receives image data of a first area (Area#1) from a first transmission unit of a timing controller and transmits the image data of a first area (Area#1) to pixels of the first area (Area#1). The image data is supplied, and the second source drive IC (SD-IC#2) receives the image data of the second area (Area#2) from the second transmission unit of the timing controller, and receives the image data of the second area (Area#2). The video data is supplied to the field, and the third source drive IC (SD-IC#3) receives the video data of the third area (Area#1) from the third transmission unit of the timing controller, and the third area (Area#3). The image data is supplied to the pixels of the fourth source drive IC (SD-IC#4), and the fourth source drive IC (SD-IC#4) receives the image data of the fourth area (Area#4) from the fourth transmission unit of the timing controller, and receives the image data of the fourth area (Area#4). Image data is supplied to the pixels of 4).

In FIG. 1, pixels in a fourth area (Area#(4-2)) of a fourth area (all pixels in the horizontal direction and a predetermined number of pixels covered by the fourth source drive IC (SD-IC#4)) It is assumed that image data having the same gray scale is supplied to the fourth source drive IC (SD-IC#4) to all of the pixels of the pixel line.

In order to reduce power consumption, the timing controller converts the image data of the first pixel line of the (4-2)th area (Area#(4-2)) to display the same grayscale to the (4-th) with the LPTD function turned on. 2) After transferring to the fourth source drive IC (SD-IC#4) in charge of the area (Area#(4-2)), the remaining images in the (4-2) area (Area#(4-2)) During a period in which data is to be transmitted, the data transmission operation of the fourth transmission unit is stopped (EPI Tx Off). The fourth source drive IC (SD-IC#4) changes the lock signal to Low during the corresponding period, and stores the image data of the first pixel line in the (4-2)th area (Area#(4-2)). The image data stored in the memory may be repeatedly output even if the pixel line of the (4-2)th area (Area#(4-2)) is changed by maintaining it in the memory (or the channel input buffer).

In the timing controller, the image data of a gray scale different from that of the (4-2)th area (Area#(4-2)), that is, the video data of the (4-3)th area (Area#(4-3)), from the host. Once transmitted, the image data of the last pixel line (or the last few pixel lines) of the (4-2)th area (Area#(4-2)) should be sent to the fourth source drive IC (SD-IC#4). During the period, a clock training pattern is transmitted to wake up the fourth source drive IC (SD-IC#4), and the image data of the next pixel line, that is, the (4-3)th area (Area#) (4-3)) video data can be received.

Next, a data modulation technique that finely adjusts the gradation expressed by a pixel by dispersing image data temporally and/or spatially, that is, an FRC technique, is briefly described. FIGS. 2 and 3 illustrate the operation principle of the FRC. It is shown.

In FIG. 2, the FRC compensation value is temporally dispersed in order to finely adjust the luminance with a small number of grayscales less than one grayscale. As shown in Fig. 2A, if the FRC compensation value '1' is written to a sub-pixel of the pixel array only in one frame period out of four frame periods, the viewer adjusts the gradation of the sub-pixel by 1/4 gradation during the four frame periods. Recognized as (25% luminance). Similarly, as shown in (b) and (c) of Fig. 2, if the FRC compensation value '1' is written to a sub-pixel in two and three frame periods, respectively, of the four frame periods, the viewer The gradation of is recognized as 1/2 gradation (50% luminance) and 3/4 gradation (75% luminance). In FIGS. 2A to 2C, the order in which the FRC compensation value '1' is written to the sub-pixels of the pixel array may be changed.

In FIG. 3, a dithering method in which a compensation value is spatially distributed in order to finely adjust the luminance to a small number of grayscales less than one grayscale is described. In the dithering method, in order to finely adjust the luminance to a small number of grayscales less than one grayscale, the subpixels to which the FRC compensation value is written within a dither mask of a constant size including a plurality of subpixels D1 to D4 are used. By adjusting the number, the compensation value is spatially distributed. Assuming a dither mask including 2x2 sub-pixels as shown in Fig. 3A, if the FRC compensation value '1' is written to one sub-pixel D1 within the dither mask, the viewer will receive the dither mask. The gradation of is recognized as 1/4 gradation (25%). As shown in (b) of FIG. 3, if the FRC compensation value '1' is written to two sub-pixels (D2, D3) within the dither mask, the viewer recognizes the gray level of the dither mask as 1/2 gray level (50%). do. And, as shown in (c) of FIG. 3, if the FRC compensation value '1' is written to the three sub-pixels D2 to D4 in the dither mask, the viewer sets the gradation of the dither mask to 3/4 gradation (75%). Recognize. In FIGS. 3A to 3C, a combination of sub-pixels to which the FRC compensation value '1' is to be written can be changed.

In general, the FRC applied to the display device may be implemented by applying the temporal dispersion method of FIG. 2 and the spatial dispersion method of FIG. 3 together.

When driving a display device using the FRC technique, the timing controller changes the data sent to the source drive IC even when the image data of the same gray scale is displayed over a plurality of pixel lines in an area covered by one source drive IC or a part of it. For this reason, the LPTP function used in the case of continuously transmitting image data of the same gray scale to a plurality of pixel lines cannot be used.

Recently, the use of the FRC technique is increasing while displaying images of the same gradation only in some areas on portable electronic devices, monitors, or TV screens.In order to further reduce power consumption, it is necessary to utilize the LPTD function in the area displaying images of the same gradation. There is.

The timing controller supplies image data to the source drive IC while applying the FRC technique to some areas (the (4-1)th area (Area#(4-1) in FIG. 2) Consider the case of applying the LPTD function while supplying the image data of the same gradation to the area (Area#(4-2)) Source drive IC adds the LPTD function and the FRC technique to the area (4-2). When applied to (4-1), the timing controller applies the FRC pattern in advance to transmit the image data to be displayed in the area (4-1). Therefore, if an arbitrary FRC pattern is applied to the image data in the (4-2) area, the There is a possibility that a gradation level difference occurs due to a mismatch of the FRC pattern at the boundary between the (4-1) area and the area (4-2), and is noticeable to the user.

In this specification, the data modulation pattern (or FRC pattern) for FRC driving is transmitted using the EPI control packet so that the LPTD function can be applied to the area using the FRC technique, and the FRC pattern is separately applied for each line. The timing controller delivers line pulses to the source drive IC through the lines of the source drive IC, and adds a summer for each channel of the source drive IC to apply the FRC pattern to the data applied to the pixel without complex logic.

4 illustrates a display device as a functional block.

The display device of FIG. 4 may include a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a power supply unit 16.

On the screen AA on which the input image is displayed on the display panel 10, a plurality of data lines 14 are arranged in a column direction (or a vertical direction) and a row direction (or a horizontal direction). A plurality of gate lines 15 cross each other, and pixels PXL are arranged in a matrix form for each crossing region to form a pixel array.

The display panel 10 applies a pixel driving voltage (or a first power line for supplying a high-potential power voltage Vdd) to the pixels PXL, a low-potential power voltage Vss, or a common voltage Vcom. It may further include a second power line for supplying to the field PXL, etc. The first and second power lines are connected to the power supply unit 16.

Touch sensors may be disposed on the pixel array of the display panel 10. The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors are on-cell type or add-on type, and are arranged on the screen AA of the display panel PXL, or in-cell type touch that is built into the pixel array. It can be implemented with sensors.

In the pixel array, the pixels PXL arranged on the same horizontal line are connected to any one of the data lines 14 and one of the gate lines 15 to form a pixel line. The pixel PXL is electrically connected to the data line 14 in response to a scan signal applied through the gate line 15, receives a data voltage, and expresses a gray level corresponding to the data voltage. The pixels PXL arranged on the same pixel line operate simultaneously according to a scan signal applied from the same gate line 15.

One pixel unit may be composed of three sub-pixels including a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or four sub-pixels including a red sub-pixel, green sub-pixel, blue sub-pixel, and white sub-pixel. , It is not limited thereto. Hereinafter, a pixel means a subpixel.

FIG. 5 shows an equivalent circuit of pixels included in an OLED display panel, and FIG. 6 shows an equivalent circuit of pixels included in a liquid crystal display panel. The liquid crystal display panel of FIG. 5 is applied to the display panel 10 Or, the OLED display panel of FIG. 6 may be applied.

When the display panel 10 is an OLED panel, each of the R/G/B or R/W/B/G subpixels is a high-potential power supply voltage (Vdd) line and a low-potential power supply voltage (Vss), as shown in FIG. 5. A light emitting element (OLED) connected between the lines and a pixel circuit connected to the data line 14 and the gate line 15 and driving the OLED element are provided. The pixel circuit includes at least a switching transistor ST, a driving transistor DT, and a storage capacitor Cst. The switching transistor ST charges the data voltage from the data line 14 to the storage capacitor Cst in response to the scan pulse from the gate line 15, and the driving transistor DT charges the storage capacitor Cst. The amount of light emitted by the OLED is controlled by controlling the current supplied to the OLED according to the voltage.

When the display panel 10 is a liquid crystal panel, each of the R/G/B or R/W/B/G subpixels is a switching transistor connected to the data line 14 and the gate line 15 as shown in FIG. 6. (ST), and a liquid crystal capacitor Clc and a storage capacitor Cst connected in parallel to the switching transistor ST. The liquid crystal capacitor Clc charges a voltage difference between the data voltage supplied to the pixel electrode and the common voltage Vcom supplied to the common electrode through the switching transistor ST, and drives the liquid crystal according to the charged voltage to increase light transmittance. Adjust. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

The timing controller 11 supplies image data (RGB) transmitted from an external host system (not shown) to each source drive IC of the data driving circuit 12. The image data is transmitted as it is or modulated by applying an FRC pattern. Image data (RGB') can also be transmitted.

The timing controller 11 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DCLK) from the host system, and Control signals for controlling the operation timing of the gate driving circuit 13 are generated. The control signals include a gate timing control signal GCS for controlling the operation timing of the gate driving circuit 13 and a data timing control signal DCS for controlling the operation timing of the data driving circuit 12.

The data driving circuit 12 converts digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DCS, and converts the data voltage into an output channel and data lines ( 14) to the pixels PXL. The data voltage may be a value corresponding to a gray level to be expressed by a pixel. The data driving circuit 12 may be composed of a plurality of source drive ICs.

The gate driving circuit 13 generates a scan signal and a light emission signal based on the gate control signal GCS, and generates the scan signal and the light emission signal in a row-sequential manner in the active period, and the gate line 15 connected to each pixel line It is provided sequentially. The scan signal and the light emission signal of the gate line 15 are synchronized with the supply of the data voltage of the data line 14. The scan signal and the emission signal swing between the gate-on voltage VGL and the gate-off voltage VGH.

The gate driving circuit 13 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a pixel, an output buffer, and the like. have. Alternatively, the gate driving circuit 13 may be directly formed on the lower substrate of the display panel 10 in a GIP (Gate Drive IC in Panel) method. In the case of the GIP method, the level shifter is mounted on a printed circuit board (PCB), and the shift register may be formed on a lower substrate of the display panel 10.

The power supply unit 16 uses a DC-DC converter to adjust the DC input voltage provided from the host to provide a gate-on voltage required for the operation of the data driving circuit 12 and the gate driving circuit 13. (VGL). A gate-off voltage (VGH) or the like is generated, and a high-potential power supply voltage (Vdd) and a low-potential power supply voltage (Vss) or a common voltage (Vcom) required for driving the pixel array are generated.

The host system may be an application processor (AP) in mobile devices, wearable devices, and virtual/augmented reality devices. Alternatively, the host system may be a main board such as a television system, a set-top box, a navigation system, a personal computer, and a home theater system, but is not limited thereto.

When the LPTD function is turned on, the timing controller 11 analyzes the image data transmitted from the host system, and the gray scale of all pixels of the same pixel line in the area of the display panel 10 that is in charge of at least one source drive IC When there is an identical grayscale area in which the same grayscale line spans a plurality of pixel lines, and when the image data of the second pixel line of the same grayscale area and subsequent pixel lines need to be transmitted, the transmission unit corresponding to the corresponding source drive IC While stopping the data transmission of the (Tx port) (EPI Tx Off), it informs the source driver IC to repeat the transmitted image data for the first pixel line in the same gradation region while driving the same gradation region.

When data transmission from the corresponding transmission unit is stopped, the source drive IC repeatedly outputs the transmitted image data for the first pixel line in the same gray scale area.

Alternatively, the timing controller 11 transmits the image data of the pixel lines of the first predetermined number (for example, the number of rows of the FRC block constituting the FRC pattern) of the same gray scale area to the source drive IC, and then the next pixel Transmission of the line video data can also be stopped. In this case, when data transmission from a corresponding transmission unit is stopped, the source drive IC may repeatedly output the image data of the last transmitted pixel line when outputting the image data of the remaining grayscale region.

Thereafter, for convenience of explanation, an embodiment in which the timing controller 11 transmits the image data of the first pixel line in the same grayscale region and then stops the transmission of the image data of the pixel line afterwards will be described.

When the region in charge of the source drive IC includes both a different gradation region in which image data having different gradations of at least one pixel is input and a same gradation region in which image data having the same gradation of all pixels is input, the timing controller 11 Is, by controlling the corresponding transmission unit to transmit the image data to be displayed in the different grayscale area (LPTD Off period), and applying the LPTD function only while transmitting the data to be displayed in the same grayscale area (LPTD On period) corresponding transmission The negative data transmission can be stopped (EPI Tx Off). After transmitting the image data of the first pixel line in the same grayscale area, the image data of the remaining pixel lines in the same grayscale area is not transmitted.

When the FRC function is on, the timing controller 11, for example, from the host system, the image data of the high-order bit from which the three low-order bits have been removed and the FRC pattern (or the FRC to be applied) to express the removed low-order bits over a plurality of frames. Information indicating a pattern) is supplied, and image data is generated by combining the image data of the upper bit and the RFC pattern, and then supplied to the data driving circuit 12. Since the FRC pattern is changed for each frame, even the same image is transmitted to the data driving circuit 12 with image data changed for each frame. In addition, even in the same grayscale area displaying the same grayscale, different image data for each pixel may be transferred to the data driving circuit 12.

In the LPTD On section applied to the same grayscale area, the timing controller 11 transmits the image data of the first pixel line of the same grayscale area and then does not transmit the remaining image data of the same grayscale area to the corresponding source drive IC. , When transmitting the image data of the first pixel line, a new FRC pattern to be applied by the source drive IC can be provided to the corresponding source drive IC through an EPI control packet.

In the LPTD On period, the new FRC pattern provided by the timing controller 11 to the source drive IC does not cause a gray scale step difference between the rest of the same gray scale area and the first pixel line of the same gray scale area corresponding to the LPTD On period. To avoid this, it may be generated by referring to the FRC pattern applied to the first pixel line in the same gray scale area.

Each pattern data constituting the FRC pattern used when the timing controller 11 generates image data to be output in the different grayscale region adds a bit value of 1 to the last bit among the upper bits of the image data transmitted from the host system ( 1) or to add (or keep) the bit value 0 (0).

For example, the image data consists of 14 bits from the lower 1 bit to the highest 14 bits, and the lower 1 to 3 bits are cut off from the original image data, and the upper 11 bits (lower 4th bit to the 14th bit) are When only the image data is transmitted from the host system, if the pattern data constituting the FRC pattern used by the timing controller 11 is 1, the lower 1 to 3 bits are 0, and the lower 4th bit to the image data of the upper 11 bits. The value of adding 1 to the bit position becomes the image data combined with the FRC pattern, and if the pattern data constituting the FRC pattern is 0, the lower 1 to 3 bits are 0, and the image data of the upper 11 bits is combined as it is. Becomes image data.

For pixels of the same grayscale, FRC pattern data 1 may be applied to the first pixel and FRC pattern data 0 may be applied to the second pixel. Conversely, FRC pattern data 0 is applied to the first pixel, and FRC pattern data 0 is applied to the second pixel. Pattern data 1 can be applied.

Since the timing controller 11 transmits the video data combined with the FRC pattern to the source drive IC, the video data transmitted by the timing controller 11 to the source drive IC by applying one of the FRC patterns is the original video data from the source drive IC. It will be a larger value than the data.

When the source drive IC stops transmitting data in the same grayscale area from the corresponding transmission unit and repeatedly outputs the image data of the first pixel line in the same grayscale area that has already been transmitted to the remaining pixel lines in the same grayscale area, the first In order for the timing controller 11 to apply the data 0 of the FRC pattern to the image data of the pixel to which the FRC pattern data 1 is applied, among the image data stored for the first pixel line, it is necessary to reduce the image data of the corresponding pixel.

Therefore, when the timing controller 11 transmits the image data of the last pixel line in the same grayscale region to the source drive IC, each data constituting the FRC pattern to be transmitted together in the control packet is pattern data 0, pattern data +1, pattern data- Can be one of 1.

On the other hand, the source drive IC must apply the FRC pattern provided by the timing controller 11 while changing for each pixel line in the same gray scale area to which image data is not transmitted. When outputting to a line, the FRC pattern must be changed for each pixel line and applied to the image data of the first pixel line in the same gray scale area.

The timing controller 11 and the source drive IC must be connected by separate wiring so that the source drive IC can distinguish between when the FRC pattern is applied and when the FRC pattern is not applied, and the timing controller 11 has the same gray scale as the source drive IC. When the FRC pattern is applied to the image data of the region, a line pulse may be supplied through the corresponding wiring, which will be described with reference to FIGS. 10 and 11.

The source drive IC includes a latch for holding the image data in order to apply the FRC pattern to the image data of the first pixel line in the same gradation region and output to the data line, which is transmitted and stored by the timing controller 11. By adding a subtractor between the level shifters, the value corresponding to the FRC pattern data in the image data output from the latch can be increased, maintained, or decreased.Refer to FIGS. 13 and 14 for details. Explain.

7 shows the FRC pattern for the lower 3 bits.

The host system removes, for example, the lower 3 bits from the input image data, configures the image data with only the upper bits, and provides it to the timing controller 11, and provides a FRC pattern to express the deleted lower 3 bits temporally/spatially. .

In FIG. 7, the FRC pattern has a size of 4X4 and is applicable when pixels constituting an area corresponding to a natural multiple of a 4X4 area output image data of the same gray scale. In addition, the FRC pattern is applied to the image data while changing for each frame, and the same pattern is applied to the image data of the same frame.

For example, to express the gray scale value 001 (Gray 001) of the lower 3 bits, add 1 to the lower 4th bit value of the image data from which the data of the lower 3 bits has been removed from only 2 pixels of 16 pixels of 4X4. (Pattern data 1), and image data from which lower 3 bits of data are removed is used as it is for the remaining 14 pixels (pattern data 0). Two pixels to which pattern data 1 is applied change their position (or a combination of two pixels) as the frame progresses.For example, four frames can be repeated in the order shown in FIG. 6 in a basic unit. In addition, the number or order of repeating basic units may be changed.

Similarly, to express the gray scale value 010 (Gray 010) of the lower 3 bits, only 4 pixels are used by adding 1 to the 4th lower bit value of the image data from which the data of the lower 3 bits has been removed (pattern data 1), For the remaining 10 pixels, the image data from which the lower 3 bits of data have been removed is used as it is (pattern data 0).

The FRC pattern to be applied for each frame from the grayscale value 001 (Gray 001) of the lower 3 bits to the grayscale value 111 (Gray 111) may be defined as shown in FIG. 7.

On the other hand, the timing controller 11 applies the FRC pattern to generate image data and provides the same to the source drive IC when image data of the same gray scale is input to a partial area or the entire area covered by the source drive IC. The LPTD function is applied from the second pixel line to the grayscale area to stop the data transmission of the transmission unit so that the image data is not transmitted, but applied to the image data received and stored by the source drive IC for the first pixel line in the same grayscale area. When the image data of the first pixel line in the same grayscale area is transmitted by generating the FRC pattern to be performed, it is provided to the source drive IC through EPI packet data.

8 is an example in which the source drive IC determines RFC pattern data to be applied to image data in the same gray area to which the LPTD function is applied, referring to the FRC pattern applied to image data of the first pixel line in the same gray area to which the LPTD function is applied. Is shown.

In FIG. 8, the upper part shows the FRC pattern (first pattern) applied to the image data of the first pixel line in the same grayscale area in which the LPTD function is not used (LTPD Off), and the lower part shows the LPTD function used (LTPD On) It shows the FRC pattern (second pattern) applied to the image data of the remaining pixel lines in the same gray scale area.

The first pattern is that the timing controller 11 combines the image data received from the host system (the first pixel line in the same gradation region and the image data in a different gradation region other than the same gradation region), and the second pattern is the source drive IC Is combined with the image data of the first pixel line of the same grayscale region transmitted by the timing controller 11, and is generated by the timing controller 11 and transmitted to the source drive IC.

In Fig. 8, in the timing controller 11, (1,1), (2,3), (3,4), in the FRC block of 4X4 among the FRC patterns in which the grayscale value of the lower 3 bits is 010 (Gray 010), (4,2) The FRC pattern with coordinates of 1 as the pattern data value (the pattern of Frame #2 of Gray 010 in Fig. 7) (the first pattern) is the image data of the grayscale area different from the first pixel line in the same grayscale area Applies to

The timing controller 11 includes image data of a first pixel line in the same grayscale area and a grayscale area different from each other (image data of pixels having the same grayscale of the pixels in the 4X4 area and grayscale values of 010 (Gray 010) of the lower 3 bits) To, apply the first pattern.

In this case, the first pattern should be applied to the image data of the remaining pixel lines in the same grayscale area so that a grayscale step does not occur between the first pixel line and the second pixel line in the same grayscale area.

The source drive IC in charge of the same gray scale area stores the image data of the first pixel line of the same gray scale area transmitted from the timing controller 11 while the LPTD function is not used (LTPD Off) in a memory.

In FIG. 8, the image data of the first pixel line in the same grayscale region is transmitted by applying the last row in the first pattern. Among the pixels of the pixel group consisting of four pixels as a unit, the pixel arranged second from the left The image data of is higher in gradation than the original data.

In order for the source drive IC to continuously apply the FRC pattern (first pattern) applied to the first pixel line of the same grayscale area to the image data of the remaining pixel lines in the same grayscale area, the first pixel line is applied to the second pixel line of the same grayscale area. Among the FRC patterns (first pattern) applied to the image data of the first pixel line, the row applied to the image data of the first pixel line (the last row of the FRC pattern in Fig. 8) is the next row (the row applied to the image data of the first pixel line). If it is the last row of the FRC pattern, the pattern data of the first row of the FRC pattern) must be applied, and the pattern data of the next row must be applied to the third pixel line.

The source drive IC outputs pixel lines after the second pixel line in the same gray scale area by continuing to use the image data of the first pixel line in the same gray scale area which is transmitted from the timing controller 11 and stored in the memory. Whenever it is changed, the image data of the first pixel line is changed by changing the row of the FRC pattern.

In FIG. 8, since the fourth row of the FRC pattern (first pattern) shown at the top of FIG. 8 is applied to the last pixel line of the LPTD Off period (the first pixel line in the same grayscale region), the first of the LPTD On period The pattern data of the first row of the first pattern should be applied to the first pixel line, that is, the second pixel line of the same grayscale area, and the first pixel line (the second pixel line of the LPTD On period) of the same grayscale area The pattern data of the second row of the pattern must be applied, and the pattern data of the third row of the first pattern must be applied to the fourth pixel line of the same grayscale area (the third pixel line of the LPTD On period), and the same grayscale area The pattern data of the fourth row of the first pattern should be applied to the fifth pixel line (the fourth pixel line in the LPTD On period) of.

When generating the image data of the pixel lines in the LPTD On period, the source drive IC must use the image data of the last pixel line (the first pixel line in the same grayscale region) in the LPTD Off period and also apply the FRC pattern.

To apply the pattern data of the first row of the first pattern to the first pixel line of the LPTD On period, the FRC pattern data applied to the corresponding pixel line from the image data of the first pixel line of the same grayscale area (the last Pattern data of the row), i.e., lowering the gradation value of the second pixel to which pattern data 1 is applied, and increasing the gradation value of the first pixel with pattern data 1 by applying the first row of the first pattern, and The third and fourth pixels must retain their values as the image data of the first pixel line. Accordingly, pattern data to be applied to the first pixel line (the second pixel line in the same grayscale region) of the LPTD On period becomes (+1, -1, 0, 0).

In order to apply the pattern data of the second row of the first pattern to the second pixel line of the LPTD On period, the grayscale value of the second pixel to which the pattern data 1 is applied from the image data of the first pixel line of the same grayscale region is lowered, By applying the second row of the first pattern, the gradation value of the third pixel having the pattern data of 1 is increased, and the remaining first and fourth pixels must maintain the value as the image data of the first pixel line. Accordingly, pattern data to be applied to the second pixel line (third pixel line in the same grayscale region) of the LPTD On period becomes (0, -1, +1, 0).

Similarly, pattern data to be applied to the third pixel line in the LPTD On period (the fourth pixel line in the same grayscale region) becomes (0, -1, 0, +1).

The image data to be displayed on the fourth pixel line in the LPTD On period (the fifth pixel line in the same grayscale area) is the same as the image data on the first pixel line in the same grayscale area. The pattern data to be applied to the fifth pixel line of the gradation area) becomes (0, 0, 0, 0).

Since the last pixel line of the LPTD Off period and all of the pixel lines of the LPTD On period belong to the same grayscale area and the image data is the same, the image data to be displayed on the pixel line of the LPTD On period is the LPTD transmitted from the timing controller 11. The FRC pattern to be applied to the pixel line of the LPTD On section by subtracting the pattern data of the FRC pattern applied to the last pixel line (the pattern data of the row applied to the pixel line in the FRC pattern) from the image data of the last pixel line in the Off section. It can be obtained by adding the pattern data of (the pattern data of the row corresponding to the pixel line in the FRC pattern).

9(a) shows different FRC pattern data for expressing grayscale 010 in the same grayscale area in which the LPTD function is used.Images of pixels having the same grayscale value of the 4x4 block and the grayscale value of the lower 3 bits are 010 This is the FRC pattern to be applied to the data.

In FIG. 9(a), the upper FRC pattern has a gray scale value of 010 (Gray 010) of the lower 3 bits in FIG. 7 and an FRC pattern of the third frame (Frame#3) ((1,2) in the FRC block of 4X4). , (2,4), (3,4), (4,1) corresponds to an FRC pattern with 1 as the pattern data value). In Fig. 9(a), the image data of the last pixel line (the first pixel line of the same gradation area) of the LPTD Off period is applied to the original image data of the corresponding pixel line with the pattern data of the third row of this FRC pattern applied. It is transferred to the source drive IC and stored.

The pattern data of the next row of the row applied to the previous pixel line (the first pixel line in the same gradation area or the last pixel line in the LPTD Off period) in the first pixel line in the LPTD On section (the second pixel line in the same gradation area) In other words, the pattern data of the next row of this FRC pattern, that is, the fourth row, must be applied.

Therefore, when generating the image data of the first pixel line of the LPTD On period, the pattern data (0, 0, +1, 0) of the third row of the FRC pattern is extracted from the image data of the last pixel line of the LPTD Off period. Subtract, and add the pattern data (+1, 0, 0, 0) of the fourth row of the FRC pattern.

That is, when the source drive IC generates image data of the first pixel line in the LPTD On period (the second pixel line in the same grayscale area), the FRC pattern data to be applied to the image data of the last pixel line in the LPTD Off period is (+). 1, 0, -1, 0).

Similarly, when the source drive IC generates image data of the second pixel line in the LPTD On period (the third pixel line in the same grayscale area), the FRC pattern data to be applied to the image data of the last pixel line in the LPTD Off period is FRC (0, +1, -1) minus (0, 0, +1, 0), the pattern data of the third row of the FRC pattern, from (0, +1, 0, 0), which is the pattern data of the first row of the pattern. , 0).

Similarly, when the source drive IC generates the image data of the third pixel line of the LPTD On period (the fourth pixel line of the same grayscale area), the FRC pattern data to be applied to the image data of the last pixel line of the LPTD Off period is FRC (0, 0, -1) minus (0, 0, +1, 0), which is the pattern data of the third row of the FRC pattern, from (0, 0, 0, +1), which is the pattern data of the second row of the pattern. It becomes +1).

Similarly, when the source drive IC generates image data of the fourth pixel line in the LPTD On period (the fifth pixel line in the same gradation area), the FRC pattern data to be applied to the image data of the last pixel line in the LPTD Off period is FRC (0, 0, 0, 0) minus (0, 0, +1, 0), the pattern data of the third row of the FRC pattern, from (0, 0, +1, 0), which is the pattern data of the third row of the pattern. ).

9(b) shows FRC pattern data for expressing gray level 100, which is an FRC pattern to be applied to image data of pixels having the same gray level value of a 4x4 block and a gray level value of 011 of the lower 3 bits.

In FIG. 9(b), the upper FRC pattern has a gray scale value of 100 (Gray 100) of the lower 3 bits in FIG. 7 and the FRC pattern of the first frame (Frame#1) ((1,1) in the FRC block of 4X4) , (1, 3) (2,1), (2,3), (3,2), (3,4), (4,2), (4,4) coordinates having 1 as the pattern data value FRC pattern). In Fig. 9(b), the image data of the last pixel line (the first pixel line in the same grayscale region) of the LPTD Off period is applied to the original image data of the corresponding pixel line in a state in which the pattern data of the first row of the FRC pattern is applied. It is transferred to the source drive IC and stored.

When creating the image data of the first pixel line of the LPTD On period, subtract the pattern data (+1, 0, +1, 0) of the first row of the FRC pattern from the image data of the last pixel line of the LPTD Off period. , The pattern data (+1, 0, +1, 0) of the second row of the FRC pattern must be added.

That is, when the source drive IC generates image data of the first pixel line in the LPTD On period (the second pixel line in the same grayscale area), the FRC pattern data to be applied to the image data of the last pixel line in the LPTD Off period is (0). , 0, 0, 0).

Similarly, when the source drive IC generates image data of the second pixel line in the LPTD On period (the third pixel line in the same grayscale area), the FRC pattern data to be applied to the image data of the last pixel line in the LPTD Off period is FRC (-1, +1) minus (+1, 0, +1, 0), which is the pattern data of the first row of the FRC pattern, from (0, +1, 0, +1), which is the pattern data of the third row of the pattern. , -1, +1).

Similarly, when the source drive IC generates the image data of the third pixel line of the LPTD On period (the fourth pixel line of the same grayscale area), the FRC pattern data to be applied to the image data of the last pixel line of the LPTD Off period is FRC (-1, +1) minus (+1, 0, +1, 0), the pattern data of the first row of the FRC pattern, from (0, +1, 0, +1), the pattern data of the fourth row of the pattern. , -1, +1).

Similarly, when the source drive IC generates image data of the fourth pixel line in the LPTD On period (the fifth pixel line in the same gradation area), the FRC pattern data to be applied to the image data of the last pixel line in the LPTD Off period is FRC (0, 0, 0) minus (+1, 0, +1, 0), which is the pattern data of the first row of the pattern, and (+1, 0, +1, 0), which is the pattern data of the first row of the FRC pattern. , 0).

In this way, the timing controller 11 stores the FRC pattern applied to the last pixel line (the first pixel line in the same gradation area) immediately before the LTPD function is turned on and the pattern data of the row of the FRC pattern applied to the last pixel line. The FRC pattern is obtained as a basis and transmitted to the source drive IC. In addition, the source drive IC adjusts the image data by applying the FRC pattern transmitted by the timing controller 11 to the image data of the pixel line last transmitted by the timing controller 11, so that the LTPD function is not employed and the LTPD function is applied. It is possible to prevent a gradation step from occurring at the boundary of the applied area.

The FRC pattern to be applied to the image data in the same grayscale region in which the LTPD function is adopted may be in the form of a 4X4 block, and the 16 data values constituting the 4X4 block increase (+1), decrease (-1), and maintain (0). ) Can be any one of. Therefore, each data value can be represented by 2 bits.

The timing controller 11 generates an FRC pattern of (16*2) bits, that is, 32 bits, for one of the seven gradations shown in Fig. 7 except for 000 among the gradations of the lower 3 bits. It can be put in a control packet and delivered to the source drive IC.

Since the timing controller 11 stops data transmission of the transmission unit during the LPTD function on period (LPTD On period), the FRC pattern is transmitted to the source drive IC through the EPI control packet in the LPTD Off period immediately before the LPTD function is on. can send.

FIG. 10 shows a configuration for transmitting a line pulse for applying an FRC pattern for each pixel line from a timing controller to a data driving circuit, and FIG. 11 shows an example in which the FRC pattern is changed for each pixel line in synchronization with the line pulse. I did it.

Among the areas that the source drive IC is in charge of, some areas are the same grayscale areas with the LPTD function on, and some are grayscale areas with the LPTD function off (in Fig. 1, the fourth source drive IC (SD-IC#) is responsible for As with area 4), the source drive IC should apply the FRC pattern only to the image data in the same grayscale area (precisely from the second pixel line in the same grayscale area).

Although it has been briefly mentioned above and will be described later with reference to FIGS. 12 to 14, the source drive IC uses a logic circuit such as a pixel counter or a line counter to do not apply the FRC pattern to the image data of the fixed image area, but the latch and Since the FRC pattern is applied to the image data by adding a sum/subtracter for each output channel between the level shifts, a trigger for applying the FRC pattern is required at the time when the image data of the same grayscale region is output from the latch.

To this end, as shown in FIG. 10, a plurality of source drive ICs #1 to #6 of the timing controller 11 and the data driving circuit 12 are connected by separate lines, and the timing controller 11 A line pulse may be generated in synchronization with a data enable signal EPI_DE indicating a time point at which data of each pixel line is to be output and output to the corresponding line.

The timing controller 11 may output a line pulse only when the source drive IC outputs image data from the second pixel line in the same gray scale area. Also, the source drive IC counts the number of line pulses, applies the data of the first row of the FPC pattern to the image data output from the latch when the first line pulse (?) is output, and applies the second line pulse (?) to the image data output from the latch. ), the data of the second row of the FPC pattern is applied to the image data output from the latch, and the data of the third row of the FPC pattern is applied to the image data output from the latch for the third line pulse (?), For the fourth line pulse (?), the data from the fourth row of the FPC pattern is applied to the image data output from the latch, and for the fifth line pulse (?), the data from the first row of the FPC pattern is output from the latch. It can be applied to video data. That is, four line pulses may be used as one unit and the rows of the FPC pattern may be cycled and applied to image data.

The timing controller 11 must transmit the image data of the next different grayscale area to the corresponding source drive IC before the point in time at which the source drive IC outputs the image data of the same grayscale area ends. Accordingly, the timing controller 11 transmits the clock training pattern to the source drive IC while the source drive IC drives the last few pixel lines (or transmits the last few line pulses) before the end of the same grayscale region. This wakes up the source drive IC so that the image data in the grayscale area can be received.

12 illustrates an example of repeating the FRC pattern in units of a predetermined number of output channels and units of a predetermined number of horizontal lines.

In FIG. 12, for example, when the grayscale region is different from the (m-1)th pixel line (or horizontal line) and the grayscale region is from the mth pixel line, the source drive IC does not apply the FRC pattern to the mth pixel line. Instead, the FRC pattern is applied from the (m+1)th pixel line PL#(n+1).

Further, as described with reference to FIG. 11, the source drive IC applies data of a row of each FRC pattern to the image data of each pixel line in units of the number of rows of the FRC pattern block. In FIG. 12, data of the first row of the FRC pattern is applied to the image data of the (m+1)th pixel line PL#(n+1), and the (m+2)th pixel line PL#(n +2)), the data of the second row of the FRC pattern is applied, and the image data of the (m+3)th pixel line (PL#(n+3)) contains the data of the third row of the FRC pattern. Is applied, the data of the fourth row of the FRC pattern is applied to the image data of the (m+4)th pixel line PL#(n+4), and the (m+5)th pixel line PL#(n+4) The data of the first row of the FRC pattern may be applied to the image data of 5)) again.

In addition, the source drive IC applies the data of the columns of each FRC pattern to the image data of each channel in units of the number of columns of the FRC pattern block. In FIG. 12, the data of the first column of the FRC pattern is applied to the image data of the first channel (CH#1), and the data of the second column of the FRC pattern is applied to the image data of the second channel (CH#2). The data of the third column of the FRC pattern is applied to the image data of the third channel (CH#3), the data of the fourth column of the FRC pattern is applied to the image data of the fourth channel (CH#4), Data of the first column of the FRC pattern may be applied to the image data of the fifth channel CH#5 again.

13 shows a specific configuration of a data driving circuit.

Referring to FIG. 13, the data driving circuit 12 includes a shift register 121, a first latch 122, a second latch 123, a sum/subtractor 124, and a level shifter 125. , A DAC 126, a fur 127, a receiver 128, and a pattern control signal generator 129. Since the data driving circuit 12 is composed of one or more source drive ICs, each source drive IC may include the configuration of FIG. 13.

The source drive IC receives a timing control signal (DCS) including a clock, image data (or pixel data) (RGB), and an FRC pattern through a control packet from the timing controller 11 through an EPI wiring pair. Further, the source drive IC receives a line pulse from the timing controller 11 through a separate wiring from the EPI wiring pair.

The receiving unit 128 stores pixel data (RGB) transmitted from the timing controller 11 and FRC pattern data transmitted through a control packet, and serially stores the pixel data (RGB) in bit units, and the first latch 122 And transmits the FRC pattern data to the pattern control signal generator 129.

The shift register 121 shifts the clock input from the timing controller 11 and sequentially outputs the clock for sampling. The first latch 122 samples and latches the pixel data RGB of an input image at a sampling clock timing sequentially input from the shift register 121, and simultaneously outputs the sampled pixel data RGB. The second latch 123 simultaneously outputs the pixel data RGB input from the first latch 122 in bit units in parallel.

The adder/subtracter 124 applies FRC pattern data to the pixel data RGB output from the second latch 123, and adds 1 to a predetermined lower bit of the pixel data RGB or subtracts 1 to the corresponding bit. The corresponding bit is retained and output.

The level shifter 125 shifts the voltage of the pixel data RGB input from the sum/subtracter 124 into the input voltage range of the DAC 126. The DAC 126 converts the pixel data RGB from the level shifter 125 into a data voltage based on the gamma compensation voltages GMA1 to GMA8 and outputs the converted data voltage. The data voltage output from the DAC 126 is supplied to the data line 14 through the buffer 127.

The pattern control signal generator 129 receives and stores the FRC pattern data from the receiving unit 128, and responds to the RFC pattern data in synchronization with a line pulse transmitted from the timing controller 11 through a separate wiring. A pattern control signal (PCS) is generated and provided to the sum/subtracter 124.

The FRC pattern is defined as a kxk block size, and the pattern control signal generator 129 counts line pulses and divides the count value of the line pulse in the kxk block by k, and the FRC pattern data of the row corresponding to the remainder. A pattern control signal (PCS) can be generated by using.

The timing controller 11 does not transmit image data by turning on the LPTD function for the same grayscale area of the same grayscale of pixels, and a control packet of the LPTD Off period immediately before the LPTD On period (or a control packet of the last line of the LPTD Off period. ), LPTD information indicating that the LPTD function is turned on (or information indicating the time point of the LPTD On period) and FRC pattern data may be transmitted from the next line.

The receiving unit 128 analyzes LPTD information in the control packet transmitted from the timing controller 11 to check the LPTD On section, and when the LPTD On section is reached, the LPTD Off section lasts for the same grayscale region corresponding to the LPTD On section. The image data (image data of the last pixel line in the LPTD Off period or image data of the first pixel line in the same grayscale area) that has been transmitted and stored is transferred to the first latch 122 whenever the pixel line is changed. The image data of the first pixel line in the same gray scale area is repeatedly transmitted to the first latch 122.

In addition, the reception unit 128 generates an FRC pattern in which all of the pattern data are 0 if there is no FRC pattern in the control packet transmitted by the timing controller 11, and transmits the generated FRC pattern to the pattern control signal generation unit 129, and the control packet If the FRC pattern is included, it may be transmitted to the pattern control signal generator 129.

Alternatively, the receiver 128 transmits the FRC pattern to the pattern control signal generator 129 only when the control packet contains the FRC pattern, and the pattern control signal generator 129 transmits the FRC pattern to the pattern control signal generator 129 when there is no line pulse or the receiver 128 When the FRC pattern is not transmitted from, a pattern control signal (PCS) can be generated and output according to the FRC pattern in which the pattern data is 0.

14 shows a configuration for adding/subtracting/maintaining image data according to RFC pattern data for each output channel unit.

The FRC pattern is in the form of a kxk block, and each pattern data constituting the block changes the gray level of the pixel data of a corresponding channel. Accordingly, the sum/subtractor 124 may include a summer (+1) 1241, a subtractor (-1) 1242, and a multiplexer (MUX) 1243 for each channel.

The n-bit data output of the second latch 123 corresponding to one channel is divided into three, one is directly connected to the multiplexer 1243, and the other two are connected to the summer 1241 and the subtractor 1242, respectively. Via the multiplexer 1243. The multiplexer 1243 is based on the pattern control signal (PCS) output from the pattern control signal generator 129, one of three, that is, the second latch 123 output, the summer 1241 output, and the subtractor 1242 output. One of them is selected and output to the level shifter 125.

When the first line pulse is input, the pattern control signal generator 129 is a multiplexer of the sum/subtracter 124 based on the pattern data in the first row among, for example, a 4x4 block-shaped FRC pattern. A pattern control signal (PCS) to control 1243) is generated. When the pattern data is 0, the multiplexer 1243 sends a pattern control signal to select the output of the second latch 123, and when the pattern data is 1, the multiplexer 1243 ) Generates and outputs a pattern control signal for selecting the output of the summer 1241, and when the pattern data is -1, the multiplexer 1243 selects the output of the subtractor 1242.

The pattern control signal generator 129 generates a pattern control signal (PCS) for each of the four pattern data in the first row, and generates a pattern control signal (PCS) from the pattern data in the first column as a first channel. To the multiplexer 1243 connected to (CH#1) (channels whose remainder is 1 by dividing the channel number by 4), the pattern control signal (PCS) generated from the pattern data in the second column is transferred to the second channel (CH). #2) To the multiplexer 1243 connected to (channels that divide the channel number by 4 and the remainder becomes 2), the pattern control signal (PCS) generated from the pattern data in the third column is transferred to the third channel (CH#3). ) (Channels that divide the channel number by 4 and the remainder is 3) to the multiplexer 1243 connected to the fourth channel (CH#4) (the pattern control signal (PCS) generated from the pattern data in the fourth column) ( The channel number is divided by 4 and the remainder is output to the multiplexer 1243 connected to 0 channels).

The multiplexers 1243 which divide the channel number by 4 and connect the remainder to the same channels receive the same pattern control signal PCS from the pattern control signal generator 129. In other words, since the same pattern data is applied to the same channels as the result of processing the channel number with 4 modules, the source drive IC does not need to use a complex logic circuit that counts pixels or channels to apply the FRC pattern. .

When a second line pulse is input, the pattern control signal generator 129, for example, of the sum/subtracter 124 based on the four pattern data in the second row among the 4x4 block-shaped FRC patterns. Four pattern control signals PCS to control the multiplexer 1243 are generated.

Similarly, when the third and fourth line pulses are input, the pattern control signal generator 129 is a multiplexer of the sum/subtracter 124 based on the four pattern data in the third row and the fourth row among the FRC patterns. 1243) to control 4 pattern control signals (PCS) are generated.

As described with reference to FIGS. 11 and 12, the image data of the pixel lines corresponding to the LPTD On period (or the same grayscale region) are repeatedly applied with the same pattern data in units of the number of rows of the FRC pattern to increase the data. Become, decrease, or remain unchanged.

On the other hand, when the FRC pattern is applied to the image data from which the lower 3 bits are removed as shown in FIG. 7, pattern data 1 in the FRC pattern indicates adding 1 to the lower fourth bit, and pattern data -1 is the lower fourth bit. Refers to subtracting 1 from the digit.

Accordingly, in FIG. 13, the summer 1241 and the subtractor 1242 add 1 or subtract 1 to the lower fourth bit position of the corresponding channel in the image data output from the second latch 123, respectively. For example, an operation of adding 1000b or subtracting 1000b to 14-bit image data output from the second latch 123 is performed.

In the video data transmitted to the source drive IC by applying the FRC pattern from the timing controller 11, since the lower three bits are 000b, the summer 1241 and the subtractor 1242 do not need to change the lower three bits.

When a line pulse is not input, the pattern control signal generator 129 generates and outputs a pattern control signal PCS that allows the multiplexer 1243 to select the output of the second latch 123 and output it to the level shifter 125. do.

Accordingly, even when data transmission between the timing controller and the source drive IC is stopped, the source drive IC can output while finely adjusting the gradation of the image, thereby reducing power consumption and expressing the gradation richly.

The display device described in the specification may be described as follows.

A display device according to an exemplary embodiment includes: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels; A data driving circuit including at least one source drive IC converting image data into a data voltage in a channel unit and supplying it to a plurality of pixels through a data line; A gate driving circuit for supplying a scan signal to a gate line connected to pixels to supply a data voltage among the plurality of gate lines; And modulating the input image data with a modulation pattern that finely adjusts the gradation expressed by the pixels by temporally and/or spatially distributing the image data of two gradations, and transferring the input image data to the source drive IC through the panel internal interface. When the image data in the first area covered by the source drive IC has the same gray level, the first image data of the first predetermined number of pixel lines in the first area is transmitted to the first source drive IC and then the remaining pixel lines in the first area And a timing controller configured to stop transmission of the second image data of the first image data, generate a second modulation pattern based on the first modulation pattern applied to the first image data, and transmit the second modulation pattern to the first source drive IC. .

In an embodiment, when transmitting the second image data to the first source drive IC, the timing controller may transmit the second modulation pattern to the first source drive IC through a control packet of the panel internal interface.

In one embodiment, when the first source drive IC drives the image data of the remaining pixel lines in the first area, the timing controller generates a pulse indicating a time point at which the second modulation pattern is applied, and the at least one source drive IC and the inside of the panel. It can be transferred through a separate wiring from the interface.

In one embodiment, the third modulation pattern has a size of kxk blocks, and the pattern data of the row applied to the first image data of the last pixel line transmitted to the first source drive IC from the pattern data of each row of the first modulation pattern It may be the result of subtracting.

In an embodiment, the second modulation pattern may include a combination of a first value for increasing the image data, a second value for decreasing the image data, and a third value for maintaining the image data.

In one embodiment, the first source drive IC includes a latch for simultaneously outputting the image data transmitted from the timing controller in parallel in bit units, and a predetermined number of bits expressing the image data of the corresponding channel, output by the latch in a channel unit. A level shifter that adds or subtracts a predetermined value or changes the size of the output of the sum/subtracter and adds or subtracts a predetermined value to the data based on the second modulation pattern, and a digital converter that converts the output of the level shifter into an analog signal. It may include an analog converter.

In one embodiment, the first source drive IC stores the third image data of the last pixel line of the first region, received from the timing controller, and locks the latch when driving the image data of the remaining pixel lines of the first region. Through this, the third image data may be repeatedly output in units of pixel lines, and a second modulation pattern may be applied to the output of the latch through a sum/subtracter.

In one embodiment, the sum/subtracter includes a summer, a subtractor, and a multiplexer for each channel, and in each channel, the summer is 1 is added to the bit value, the subtractor subtracts 1 from the bit value of a predetermined digit, and the multiplexer may select one of a first output, a second output, and a third output to output to the level shifter.

In an embodiment, the first source drive IC further comprises a pattern control signal generator for generating and outputting a pattern control signal for the multiplexer to select and output one of the first to third outputs based on the second modulation pattern. Can include.

In one embodiment, the pattern control signal generator selects one row of pattern data from a kxk block of the second modulation pattern based on a pulse transmitted from the timing controller through a wiring separate from the panel internal interface, and A pattern control signal may be generated based on the pattern data and supplied to the multiplexer.

In an embodiment, the pattern control signal generator may generate and output a pattern control signal that causes the multiplexer to select the first output when no pulse is input.

In an embodiment, the timing controller may transmit the clock training pattern to the first source drive IC while the first source drive IC drives the last predetermined number of pixel lines in the first area.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: gate line
16: power supply

Claims (12)

A display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels;
A data driving circuit including at least one source drive IC converting image data into a data voltage in a channel unit and supplying it to the plurality of pixels through the data line;
A gate driving circuit for supplying a scan signal to a gate line connected to pixels to supply the data voltage among the plurality of gate lines; And
The input image data is modulated with a modulation pattern that finely adjusts the gradation expressed by the pixels by dispersing the image data of two gradations temporally and/or spatially, and transferring the input image data to the source drive IC through an internal interface When the image data of the first area covered by the source drive IC has the same gray level, the first image data of the first predetermined number of pixel lines of the first area is transmitted to the first source drive IC and then And a timing controller that stops transmission of the second image data of the remaining pixel lines, generates a second modulation pattern based on the first modulation pattern applied to the first image data, and transmits the second modulation pattern to the first source drive IC Display device. The method of claim 1,
The timing controller, when transmitting the first image data to the first source drive IC, transmits the second modulation pattern to the first source drive IC through a control packet of the panel internal interface. Device. The method of claim 1,
The timing controller, when the first source drive IC drives the image data of the remaining pixel lines in the first region, generates a pulse indicating a time point at which the second modulation pattern is applied, the one or more source drive ICs and the The display device, characterized in that the transmission through a wiring separate from the inner interface of the panel. The method of claim 1,
The second modulation pattern has a size of kxk blocks, and the pattern data of the row applied to the first image data of the last pixel line transmitted to the first source drive IC is subtracted from the pattern data of each row of the first modulation pattern. Display device, characterized in that the result. The method of claim 4,
The second modulation pattern comprises a combination of a first value for increasing image data, a second value for decreasing image data, and a third value for maintaining image data. The method of claim 1,
The first source drive IC includes a latch for simultaneously outputting the image data received from the timing controller in parallel in bit units, and a predetermined number of bit data that is output by the latch in a channel unit, representing the image data of a corresponding channel. A sum/subtracter that adds or subtracts a predetermined value or maintains the bit data based on the second modulation pattern, a level shifter that changes the size of the output of the sum/subtracter, and converts the output of the level shifter into an analog signal. A display device comprising a digital-to-analog converter. The method of claim 6,
The first source drive IC stores third image data of the last pixel line of the first region, received from the timing controller, and releases the latch when driving image data of the remaining pixel lines of the first region. And repeatedly outputting the third image data for each pixel line and applying the second modulation pattern to the output of the latch through the sum/subtracter. The method of claim 6,
The adder/subtracter includes a summer, a subtractor, and a multiplexer for each channel,
In each channel, the summer adds 1 to a bit value of a predetermined digit among a predetermined number of bit data, which is a first output output for a corresponding channel by the latch, and the subtracter subtracts 1 from the bit value of the predetermined digit, And the multiplexer selects one of the first output, the second output, and the third output and outputs the selection to the level shifter. The method of claim 8,
The first source drive IC further includes a pattern control signal generator for generating and outputting a pattern control signal that causes the multiplexer to select and output one of the first to third outputs based on the second modulation pattern. A display device, characterized in that. The method of claim 9,
The pattern control signal generator may select one row of pattern data from a kxk block of the second modulation pattern based on a pulse transmitted from the timing controller through a separate line from the panel internal interface, and And generating the pattern control signal based on pattern data and supplying the pattern control signal to the multiplexer. The method of claim 10,
And the pattern control signal generator generates and outputs a pattern control signal that causes the multiplexer to select the first output when the pulse is not input. The method of claim 1,
And the timing controller transmits a clock training pattern to the first source drive IC while the first source drive IC drives a last predetermined number of pixel lines in the first area.

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