KR102470338B1 - Compensation device for OLED Display and the Display - Google Patents

Abstract

The present invention relates to a compensation device for an organic light emitting display device, and more particularly, to a device for compensating for deterioration of a pixel of an organic light emitting display device and a display device thereof.
The present invention includes: a compensation value calculator for receiving pixel characteristic information and calculating a compensation value required for a pixel in gray units; a storage control unit which stores the calculated compensation value in gray units in a compensation value storage unit and reads the stored compensation value; Receive input grays in gray units, receive compensation values in gray units, and perform an addition operation on the received input grays and compensation values to obtain

Description

Compensation device for OLED Display and the Display

The present invention relates to a compensation device for an organic light emitting display device, and more particularly, to a device for compensating for deterioration of a pixel of an organic light emitting display device and a display device thereof.

As information technology develops, the market for display devices, which are communication media between users and information, is growing. Accordingly, organic light emitting diode (OLED) display devices, quantum dot displays (ODD), liquid crystal displays (LCD) and plasma display panels (PDP) The use of display devices such as the like is increasing.

Since an organic light emitting display device is a self-light emitting device, it consumes less power and can be manufactured thinner than a liquid crystal display device requiring a backlight. The organic light emitting display device has a wide viewing angle and a fast response speed. Such an organic light emitting display device is expanding its market while competing with a liquid crystal display device as the process technology has been developed to the level of large-screen mass production technology.

The pixels of the organic light emitting display device include a driving thin film transistor (TFT) that controls a driving current flowing through the OLED according to data of an input image. Device characteristics such as threshold voltage and mobility of the driving TFT may change according to process variation, driving time, driving environment, etc., and pixels are deteriorated due to the change in device characteristics. Deterioration of these pixels degrades the quality of the organic light emitting display and shortens its lifespan. Accordingly, a technology for compensating for deterioration of pixels by sensing a change in element characteristics of a pixel and appropriately changing input data according to a sensing result is applied to the organic light emitting display device. A change in device characteristics of a pixel includes a change in characteristics of a driving TFT, such as a threshold voltage and mobility of the driving TFT.

Conventional compensation values are expressed in the following format.

Here, k is a gain, Vgs is the voltage of sensing data applied to the gate of the driving TFT, and V _th is an offset value. Although the above formula is expressed as a current value, it is displayed in the same format even when expressed as a luminance.

That is, assuming that compensation values are conventionally expressed as parameters of gain and offset, and that an 8-bit storage space is required to store gain and an 8-bit storage space is required to store offset, memory for storing compensation values (storage unit) requires a space of at least 16 bits per pixel. In addition, a 16-bit space is a storage space required for each of the R, G, and B pixels, and since the display device includes millions of pixels, the storage capacity is inevitably large.

In addition, a component (eg, a timing controller) performing compensation using a stored value inevitably requires a large bandwidth for communication with a host system, a gate driver, and a data driver.

In addition, as can be seen from the above equation, since a multiplier is essential to calculate the multiplication of the gain (k) in the configuration for generating the compensation value in the prior art, the circuit configuration may be complex and the physical size may be large. There was only

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a device for compensating for pixel deterioration of an organic light emitting display device and a display device therefor.

The present invention includes: a compensation value calculator for receiving pixel characteristic information and calculating a compensation value required for a pixel in gray units; a storage control unit which stores the calculated compensation value in gray units in a compensation value storage unit and reads the stored compensation value; An adder for receiving input grays in gray units, receiving compensation values in gray units, performing an addition operation on the received input grays and compensation values, and outputting the received input grays and compensation values in gray units.

The storage controller divides the compensation value into an integer part and a decimal part and stores the compensation value in the compensation value storage unit.

The storage controller variably controls the number of bits of the integer part and the number of bits of the decimal part.

The number of bits of the compensation value is stored as the same as or less than the number of bits of the input gray.

The display device may further include a compensation value storage unit for each gradation, wherein the compensation value storage unit for each gradation stores a representative compensation value.

The compensation value storage unit for each gray level stores a representative compensation value for each range of gray levels.

The compensation value storage unit for each gray level stores a representative compensation value at a specific interval.

The compensation value storage unit for each gray level stores a specific number of representative compensation values.

The present invention, a timing controller; a data driver receiving a driving signal from the timing controller; a gate driver receiving a driving signal from the timing controller; a display panel including a plurality of pixels and displaying an image based on signals received from the data driver and the gate driver; and a power driver supplying power to the data driver, the gate driver, and the display panel, wherein the timing controller: receives pixel characteristic information, calculates a compensation value required for a pixel in gray units, and calculates the compensation value A display device that stores values in units of grays, reads the stored compensation values, receives input grays in units of grays, and performs an addition operation on the input grays and the compensation value.

The timing controller stores the compensation value by dividing it into an integer part and a decimal part.

The number of bits of the compensation value is stored as the same as or less than the number of bits of the input gray.

The timing controller stores a representative compensation value for each gray level.

The timing controller stores the representative compensation value for each grayscale range.

The timing controller stores the representative compensation value at specific intervals.

The timing controller stores a specific number of the representative compensation values.

According to the present invention, the capacity of the memory for storing the compensation value can be reduced.

Also, according to the present invention, a bandwidth required for transmitting and receiving a compensation value can be reduced.

In addition, according to the present invention, in generating a compensation value, a circuit can be configured only with an adder, and thus, the physical size of the configuration can be reduced.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of sub-pixels of the display device shown in FIG. 1 .
3 is a flowchart for explaining compensation according to the present invention.
4 is an exemplary view of compensation according to the present invention.
5A is a diagram showing the structure of a display device for performing external compensation according to the present invention.
5B is a diagram showing a detailed structure of a pixel SP applied to an organic light emitting display device according to the present invention.
5C is a diagram showing the configuration of a timing controller applied to an organic light emitting display device according to the present invention.
6 is a graph for explaining pixel deterioration and compensation according to the present invention.
7 is a diagram for explaining the structure of a memory for storing a compensation value according to the present invention.
8 is a diagram showing a compensating device and a display device according to the present invention.
9 is a diagram showing a compensating device and a display device according to the present invention.

Hereinafter, specific details for the implementation of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of sub-pixels of the display device shown in FIG. 1 .

As shown in FIG. 1 , the display device includes a host system 100 , a timing controller 70 , a data driver 130 , a power supply 140 , a gate driver 150 and a display panel 11 .

The host system 100 includes a System on Chip (SoC) with a built-in scaler, converts digital video data of an input image into a data signal in a format suitable for display on the display panel 110 and outputs the converted data signal. The host system 100 provides various timing signals together with data signals to the timing controller 170 .

The timing controller 170 receives video data from the host system 100 . Timing signals such as a vertical sync signal (V_Sync), a horizontal sync signal (V_Sync), a data enable signal (DE), and a main clock signal (Pixel Clock) input from the host system 100 Based on this, operation timings of the data driver 130 and the gate driver 150 are controlled.

The timing controller 170 processes data signals input from the host system 100 and supplies them to the data driver 130 . For example, the timing controller 170 compensates for a data signal input from the host system 100 and supplies it to the data driver 130 .

The data driver 130 performs an operation in response to a signal supplied from the timing controller 170 . For example, the data driver 130 operates in response to the first driving signal DDC provided from the timing controller 170 . The data driver 130 converts the digital data signal DATA provided from the timing controller 170 into an analog data signal and outputs the converted data signal.

Specifically, the data driver 130 converts the digital data signal DATA into an analog data signal in response to the gamma voltage of the gamma unit provided inside or outside. The data driver 130 provides data signals to the data lines DL1 to DLn of the display panel 110 .

The gate driver 150 performs an operation in response to a signal supplied from the timing controller 170 . For example, the gate driver 150 operates in response to the second driving signal GDC provided from the timing controller 170 . The gate driver 150 outputs a gate signal of a gate high voltage or a gate low voltage. This gate signal is also referred to as a scan signal.

The gate driver 150 may sequentially output gate signals in a forward direction or in a reverse direction. Also, the gate driver 150 may simultaneously output gate signals. The gate driver 150 provides gate signals to the gate lines GL1 to GLm of the display panel 110 .

The power supply 140 outputs first voltage sources VCC and GND for driving the data driver 130 and the like and second voltage sources EVDD and EVSS for driving the display panel 110 . In addition, the power supply 140 generates voltages necessary for driving the display device, such as a gate high voltage or a gate low voltage to be transmitted to the gate driver 150 .

The display panel 110 includes a plurality of subpixels SP, data lines DL1 to DLn connected to the subpixels SP, and gate lines GL1 to GLm connected to the subpixels SP. do. The display panel 110 displays an image corresponding to the gate signal output from the gate driver 150 and the data signal output from the data driver 130 . The display panel 110 includes a lower substrate and an upper substrate. Sub-pixels SP may be formed between the lower substrate and the upper substrate.

As shown in FIG. 2 , one sub-pixel is supplied through the switching thin film transistor SW connected to (or formed at the intersection of) the gate line GL1 and the data line DL1 and the switching thin film transistor SW. A pixel circuit (PC) operating in response to the received data signal is included.

The pixel circuit PC includes circuits such as a driving transistor, a storage capacitor, and an organic light emitting diode and a compensation circuit for compensating for them. The compensation circuit is a circuit for compensating for the threshold voltage of the driving transistor. The compensation circuit is composed of one or more thin film transistors and capacitors. The composition of the compensation circuit varies according to the compensation method.

The display panel 110 is implemented as a liquid crystal display panel or an organic light emitting display panel according to the configuration of the pixel circuit (PC) of the sub-pixels (SP). For example, when the display panel 110 is implemented as a liquid crystal display panel, it is a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in plane switching (IPS) mode, a fringe field switching (FFS) mode, or an ECB ( Electrically Controlled Birefringence) mode.

For another example, when the display panel 110 is implemented as an organic light emitting display panel, it operates in a top-emission method or a bottom-emission method.

The display panel of the display device described above may be a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, a plasma display panel, or the like. However, it should be understood that the present invention is not limited to any one.

In addition, the above-described display devices are small, medium, or large, such as televisions, set-top boxes, navigation devices, video players, Blu-ray players, personal computers, wearable devices, home theaters, mobile phones, and virtual reality display devices (VR). can be implemented with The display device described below has a greater advantage when implementing virtual reality based on a display device having an organic light emitting display panel, and this will be described as an example. However, it should be understood that the present invention is not limited to any one.

3 is a flowchart for explaining compensation according to the present invention.

4 is an exemplary view of compensation according to the present invention.

Referring to FIG. 3 , deterioration of the organic light emitting diode may be detected (S110), a compensation value may be generated (S120), and compensation may be performed (S130).

That is, after generating compensation data (Gain Data) for the degraded area, the image data value of the degraded area is allocated in a manner of applying it to the image data signal. Accordingly, as shown in the luminance profile after compensation rather than the luminance profile before compensation, the organic light emitting diode can recover the previous luminance according to the compensation gain value (see FIG. 4 ).

5A is a diagram showing the structure of a display device for performing external compensation according to the present invention.

5B is a diagram showing a detailed structure of a pixel SP applied to an organic light emitting display device according to the present invention.

5C is a diagram showing the configuration of a timing controller applied to an organic light emitting display device according to the present invention.

Referring to FIG. 5B , the pixel SP includes an organic light emitting diode OLED, a driving transistor Tdr controlling a current flowing through the organic light emitting diode OLED, a data line DL, a driving transistor Tdr, and a gate line. (GL) and a switching transistor (Tsw1) connected between them. In addition, the pixel SP includes a sensing transistor Tsw2 for external compensation.

The signal lines include a gate line GL, a sensing pulse line SPL, a data line DL, a sensing line SL, a first driving power line PLA, and a second driving power line PLB.

The gate lines GL are formed parallel to each other at regular intervals along the second direction of the display panel, for example, the horizontal direction. The sensing pulse lines SPL may be formed at regular intervals parallel to the gate lines GL. Also, the gate line GL and the sensing pulse line SPL formed on one horizontal line may be common and formed as one line.

The data lines DL may be formed parallel to each other at regular intervals along the first direction of the display panel, for example, the vertical direction, to cross each of the gate line GL and the sensing pulse line SPL. However, the arrangement structure of the data line DL and the gate line GL may be variously changed.

The sensing lines SL may be formed at regular intervals parallel to the data lines DL. However, it should be understood that it is not limited thereto.

The first driving power line PLA may be formed parallel to the data line DL at regular intervals. Here, the first driving power line PLA may be formed parallel to the sensing line SL at regular intervals. The first driving power line PLA is connected to the power supply 140 and supplies the first driving power EVDD supplied from the power supply 140 to each pixel SP.

The second driving power line PLB may be formed at regular intervals parallel to each of the data lines DL1 to DLn or the gate lines GL1 to GLm. The second driving power line PLB supplies the second driving power EVSS supplied from the power supply 140 to each pixel SP. For example, the second driving power lines PLB may be electrically grounded to a metal case (or cover) constituting the organic light emitting display device. In this case, the second driving power line is connected to each pixel SP. Provides ground power (ground).

Each of the plurality of pixels SP is formed in each pixel area defined by each of the gate lines GL1 to GLm and the data lines DL1 to DLn. Here, each of the plurality of pixels SP may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. As shown in FIG. 5B , each of the plurality of pixels SP may include a pixel driving circuit PDC and an organic light emitting diode OLED.

The pixel driving circuit PDC includes a switching transistor Tsw1, a sensing transistor Tsw2, a driving transistor Tdr, and a capacitor Cst. Here, the transistors Tsw1, Tsw2, and Tdr are thin film transistors (TFTs), and may be a-Si TFTs, poly-Si TFTs, oxide TFTs, organic TFTs, and the like.

The switching transistor Tsw1 is switched by the gate pulse GP and outputs the data voltage Vdata supplied to the data line DL. To this end, the switching transistor Tsw1 has a gate connected to the adjacent gate line GL, a first electrode connected to the adjacent data line DL, and a second electrode connected to the first node n1 that is the gate of the driving transistor Tdr. contains electrodes.

The sensing transistor Tsw2 is switched by the sensing pulse SP and supplies the reference voltage Vref supplied to the sensing line SL to the second node n2 which is the source electrode of the driving transistor Tdr. To this end, the sensing transistor Tsw2 includes a gate connected to the adjacent sensing pulse line SPL, a first electrode connected to the adjacent sensing line SL, and a second electrode connected to the second node n2.

The capacitor Cst charges the voltage difference between the voltages supplied to the first and second nodes n1 and n2 according to the switching of the switching transistor Tsw1 and the sensing transistor Tsw2, respectively, and then charges the capacitor Cst according to the charged voltage. The driving transistor Tdr is switched.

The driving transistor Tdr is turned on by the voltage of the capacitor Cst to control the amount of current flowing from the first driving power line PLA to the organic light emitting diode OLED. To this end, the driving transistor Tdr includes a gate connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the first driving power line PLA.

The organic light emitting diode OLED emits light by the data current supplied from the driving transistor Tdr and emits light having luminance corresponding to the data current. To this end, the organic light emitting diode OLED includes a second node n2, that is, a first electrode (eg, an anode electrode) connected to the first electrode of the driving transistor Tdr, an organic layer formed on the first electrode, and and a second electrode (eg, a cathode electrode) connected to the organic layer. The second electrode of the organic light emitting diode OLED is the second driving power line PLB formed on the organic layer or may be additionally formed on the organic layer to be connected to the second driving power line PLB.

External compensation means calculating the amount of change in the threshold voltage or mobility of the driving transistor Tdr formed in the pixel SP, and varying the magnitude of the data voltages supplied to the unit pixel according to the amount of change. Accordingly, the structure of the pixel SP may be changed in various forms so that the amount of change in the threshold voltage or mobility of the driving transistor Tdr can be calculated.

The gate driver 150 sequentially supplies gate pulses GP to the gate lines GL1 to GLm using the gate control signals GCS transmitted from the timing controller 170 . The gate pulse GP means a signal capable of turning on the switching transistor Tsw1 connected to the gate lines GL1 to GLm. A signal capable of turning off the switching transistor Tsw1 is referred to as a gate off signal. A gate pulse (GP) and a gate off signal are collectively referred to as a gate signal.

The gate driver 150 is formed independently of the display panel 110 and may be connected to the display panel 110 through a tape carrier package (TCP) or a flexible printed circuit board (FPCB). It may also be directly mounted in the panel 110 using an In Panel (GIP) method.

The power supply 140 supplies power to the gate driver 150 , the data driver 130 and the timing controller 170 .

As shown in FIG. 5C , the timing controller 170 generates a gate control signal (GCS) for controlling driving of the gate driver 150 using the timing synchronization signal (TSS) input from the host system 100. and a data control signal DCS for controlling driving of the data driver 130 are respectively generated.

In a sensing mode in which sensing for external compensation is performed, the timing controller 170 transmits sensed image data to be supplied to pixels formed on a horizontal line where external compensation is performed to the data driver 130 .

The blanking period is inserted between video output periods in which video is output. That is, the blanking period means a period in which no video is output during one frame period, and the video output period means a period in which an video is output during one frame period. When a power-on control signal is received from the host system 100, the organic light emitting display device is driven, and accordingly, one frame period is repeated to output an image.

When a power-off control signal transmitted from the host system 100 is detected, the organic light emitting display device stops functions for outputting an image. Accordingly, an image is not output from the display panel 110 . However, since the output of the image is blocked, even if the user does not see the image, power is supplied to the organic light emitting display device for a certain period of time. The organic light emitting display device performs a sensing operation for compensating the threshold voltage of the driving transistors Tdr for a predetermined time after the output of the image is blocked. The sensing operation may be performed immediately or for a predetermined time after the output of the image is blocked by the power-off control signal.

The timing controller 170 calculates an external compensation value based on the sensing data Sdata provided from the data driver 130 in the sensing mode and stores the external compensation value in the storage unit 200 . In addition, new threshold voltages and new compensation voltages calculated in the sensing mode are stored in the storage unit 200 . In addition, the storage unit 200 may also store existing threshold voltages and existing compensation voltages measured during manufacturing of the organic light emitting display device. The storage unit 200 may be included in the timing controller 170 or may be independently formed outside the timing controller 170 .

The timing controller 170 compensates the input image data (Ri, Gi, Bi) transmitted from the host system 100 during the image display period when the image is output using an external compensation value and converts it into external compensation image data or inputs The image data is rearranged without external compensation, converted into general image data, and output. The data driver 130 converts external compensation image data or normal image data into data voltage Vdata and then supplies the data voltage Vdata to the data line.

In order to perform the functions described above, the timing controller 170, as shown in FIG. 5C, transmits from the host system 100 using the timing synchronization signal (TSS) transmitted from the host system 100. The data alignment unit 173 rearranges the input image data (Ri, Gi, Bi) and supplies the rearranged image data to the data driver 130, and generates a gate control signal (GCS) using the timing synchronization signal (TSS) Formed in each of the pixels (SP) using the sensing data (Sdata) transmitted from the control signal generator 172 and the data driver 130 to generate the data control signal (DCS) and the power control signal (PCS) An image generated by the determination unit 171 for calculating an external compensation value for compensating for a change in the characteristic of the driving transistor Tdr, the storage unit 200 for storing the external compensation value, and the data alignment unit 173 An output unit 174 for outputting data and control signals (DCS, PCS, GCS) to the data driver 130 or the gate driver 150 or the power supply 140 is included.

The data driver 130 is connected to data lines DL1 to DLn and sensing lines SL1 to SLk, and operates in a sensing mode or a display mode according to a control signal transmitted from the timing controller 170 . The sensing mode and the display mode are executed during a period in which an image is output through the display panel 110 according to the power-on control signal.

6 is a graph for explaining pixel deterioration and compensation according to the present invention.

Referring to FIG. 6, the horizontal axis is input gray [unit: Gray] and the vertical axis is luminance [unit: nit]. Input gray is data input to the timing controller from the host system and has a range of 0 to 255, and is input as 8 bits accordingly.

The luminance emitted by a pixel is defined by the following equation.

That is, when 255 [gray] is input as the input gray, the measured luminance in an ideal case (no degradation) is 150 [nit].

However, in the pixel, degradation of luminance occurs due to a process or use environment. For example, 255 [gray] is input as the input gray, but a loss of 10 [nit] occurs, so the actually measured luminance may be 140 [nit]. Considering that degradation has occurred, gray corresponding to the measured luminance is referred to as effective gray.

255 [gray] was entered as the input gray, and the luminance should be 150 [nit] in an ideal case, but the case where 140 [nit] is emitted due to deterioration is calculated as follows.

Calculate effective gray = 247.13 [gray].

Therefore, the compensation value [gray] = input gray - effective gray = 7.87 [gray] is calculated.

That is, if 7.87 [gray] is added as a compensation value when 255 [gray] is received as an input gray, a target luminance of 150 [nit] can be emitted.

As described above, in calculating the compensation value, the present invention proposes a concept of using the same unit as [gray], which is a unit of data input to a pixel. Accordingly, it is possible to replace the gain and offset used to store the conventional compensation value. In addition, the gain and offset are stored in the storage unit in units of 8 bits each, requiring 16 bits of storage space for each pixel. However, according to the present invention, the compensation value can be used in [gray] units representing 0 to 255, and therefore, only 8-bit storage space is required to store the compensation value, and the storage space can be reduced by more than 50% compared to the prior art. can

7 is a diagram for explaining the structure of a memory for storing a compensation value according to the present invention.

Referring to FIG. 7, a memory structure for storing a compensation value in units of [gray] will be described.

In the example referring to FIG. 6 , the compensation value is 7.87 [gray].

Referring to row 1 of FIG. 6, a memory structure for storing a compensation value of 7.87 [gray] is shown. 8 bits are allocated as a memory for storing the compensation value, of which 7 bits can be used as an integer part and the remaining 1 bit can be used as a decimal part. In this case, the compensation value approximates the compensation value 7.87 [gray] calculated as 4 + 2 + 1 + 0.5 = 7.5 [gray].

Referring to row 2 of FIG. 6, a memory structure for storing the compensation value 7.87 [gray] is shown. 8 bits are allocated as a memory for storing the compensation value, of which 6 bits can be used as an integer part and the remaining 2 bits can be used as a decimal part. In this case, the compensation value approximates the compensation value 7.87 [gray] calculated as 4 + 2 + 1 + 0.5 + 0.025 = 7.75 [gray]. In addition, it can be seen that it is closer than the example referring to row 1 of FIG. 6 .

Referring to row 3 of FIG. 6, a memory structure for storing the compensation value 7.87 [gray] is shown. 8 bits are allocated as a memory for storing the compensation value, of which 5 bits can be used as an integer part and the remaining 3 bits can be used as a decimal part. In this case, the compensation value approximates the compensation value 7.87 [gray] calculated as 4 + 2 + 1 + 0.5 + 0.25 + 0.125 = 7.875 [gray]. In addition, it can be seen that it is closer than the example referring to row 1 of FIG. 6 and the example referring to row 2 of FIG. 6 .

That is, the memory structure for storing the compensation value proposed by the present invention is composed of the same bits as the input gray, but some of the bits are used as integer parts and the remaining bits are used as fractional parts. The number of bits to be used for the fractional part will be determined according to the number of bits to be used for the integer part. It is possible to control how many bits are used as the integer part. For example, when the compensation value 7.87 [gray] is calculated, if a 7-bit integer part and a 1-bit fractional part are allocated, 7.5 [gray] will be stored as the compensation value in the storage unit. If a 6-bit integer part and a 2-bit fractional part are allocated, 7.75 [gray] will be stored as a compensation value in the storage unit. If a 5-bit integer part and a 3-bit fractional part are allocated, 7.75 [gray] will be stored as a compensation value in the storage unit. In addition, in order to minimize the memory space, in some cases, the memory structure for storing the compensation value proposed by the present invention may be configured with fewer bits than the input gray.

According to the present invention, a specific example of a method for controlling the number of bits to be used as an integer part and the number of bits to be used as a fractional part in a memory structure for storing a compensation value will be described below. In this example, it is described that the memory for storing the compensation value is 8 bits, but it should be understood that the scope of the present invention is not limited thereto and extends to an equal range.

The number of bits to be used as the integer part is determined according to the integer value of the calculated compensation value [gray], and the number of bits to be used as the fractional part is determined according to the determined number of bits of the integer part. Specifically, when the calculated compensation value is greater than 128 [gray], the number of bits to be used as the integer part is 8 bits, and accordingly, the number of bits to be used as the decimal part will be 0 bits. The reason is that the maximum value of the compensation value that can be expressed with 7 bits of the integer part is smaller than 128 [gray], so it is determined as 8 bits larger than 7 bits.

If the calculated compensation value is greater than 64 [gray] and less than 128 [gray], the number of bits to be used as the integer part is 7 bits or more, and accordingly, the number of bits to be used as the decimal part will be 1 bit or less. The reason is that the maximum value of the compensation value that can be expressed with 6 bits of the integer part is less than 64 [gray], so it is determined to be more than 7 bits greater than 6 bits. For example, in this case, 7 bits of the integer part and 1 bit of the fractional part, or 8 bits of the integer part and 0 bit of the fractional part may be used. In addition, the larger the number of bits to be used as the fractional part, the closer the actual compensation value will be.

If the calculated compensation value is larger than 32 [gray] and smaller than 64 [gray], the number of bits to be used as the integer part is 6 bits or more, and accordingly, the number of bits to be used as the decimal part will be 2 bits or less. The reason is that the maximum value of the compensation value that can be expressed with 5 bits of the integer part is less than 32 [gray], so it is determined to be 6 bits or more larger than 5 bits. For example, in this case, 6 bits of an integer part and 2 bits of a fractional part, 7 bits of an integer part and 1 bit of a fractional part, or 8 bits of an integer part and 0 bit of a fractional part may be used. In addition, the larger the number of bits to be used as the fractional part, the closer the actual compensation value will be.

If the calculated compensation value is greater than 16 [gray] and less than 32 [gray], the number of bits to be used as the integer part is 5 bits or more, and accordingly, the number of bits to be used as the decimal part will be 3 bits or less. The reason is that the maximum value of the compensation value that can be expressed with 4 bits of the integer part is less than 16 [gray], so it is determined to be 5 bits or more larger than 4 bits. For example, in this case, 5 bits of an integer part and 3 bits of a fractional part, 6 bits of an integer part and 2 bits of a fractional part, 7 bits of an integer part and 1 bit of a fractional part, or 8 bits of an integer part and 0 bit of a fractional part may be used. In addition, the larger the number of bits to be used as the fractional part, the closer the actual compensation value will be.

If the calculated compensation value is larger than 8 [gray] and smaller than 16 [gray], the number of bits to be used as the integer part is 4 bits or more, and accordingly, the number of bits to be used as the decimal part will be 4 bits or less. The reason is that the maximum value of the compensation value that can be expressed with 3 bits of the integer part is less than 8 [gray], so it is determined as 4 bits or more that are greater than 3 bits. For example, in this case, 4 bits of the integer part and 4 bits of the fractional part, 5 bits of the integer part and 3 bits of the fractional part, 6 bits of the integer part and 2 bits of the fractional part, 7 bits of the integer part and 1 bit of the fractional part, or 8 bits of the integer part and 0 bit of the fractional part are used in this case. can In addition, the larger the number of bits to be used as the fractional part, the closer the actual compensation value will be.

If the calculated compensation value is greater than 4 [gray] and less than 8 [gray], the number of bits to be used as the integer part is 3 bits or more, and accordingly, the number of bits to be used as the decimal part will be 5 bits or less. The reason is that the maximum value of the compensation value that can be expressed with 2 bits of the integer part is less than 4 [gray], so it is determined to be 3 bits or more larger than 2 bits. For example, in this case, 3 bits of the integer part and 5 bits of the fractional part, 4 bits of the integer part and 4 bits of the fractional part, 5 bits of the integer part and 3 bits of the fractional part, 6 bits of the integer part and 2 bits of the fractional part, 7 bits of the integer part and 1 bit of the fractional part, or the integer part 8 bits and 0 bits for the fractional part can be used. In addition, the larger the number of bits to be used as the fractional part, the closer the actual compensation value will be.

If the calculated compensation value is larger than 2 [gray] and smaller than 4 [gray], the number of bits to be used as the integer part is 2 bits or more, and accordingly, the number of bits to be used as the decimal part will be 6 bits or less. The reason is that since the maximum value of the compensation value that can be expressed with 1 bit of the integer part is less than 2 [gray], it is determined to be 2 bits or more larger than 1 bit. For example, in this case, 2 bits of the integer part and 6 bits of the fractional part, 3 bits of the integer part and 5 bits of the fractional part, 4 bits of the integer part and 4 bits of the fractional part, 5 bits of the integer part and 3 bits of the fractional part, 6 bits of the integer part and 2 bits of the fractional part, and 7 bits of the fractional part bit and 1 bit for the fractional part, or 8 bits for the integer part and 0 bit for the fractional part may be used. In addition, the larger the number of bits to be used as the fractional part, the closer the actual compensation value will be.

As a representative example, it is assumed that the compensation value storage memory is composed of n [bits] and an integer part m [bits] is allocated thereto. In this case, an integer part m [bit] that satisfies the following formula will be determined.

Also, in the above case, the fractional part will be determined as (n-m) [bit].

8 is a diagram showing a compensating device and a display device according to the present invention.

Referring to FIG. 8 , the compensation device 810 includes a compensation value calculator 811 , a storage controller 812 , and an adder 813 .

The compensation value calculator 811 receives pixel characteristics from the pixel characteristic detector 820 . The pixel characteristics are measured for each pixel, and include light emission luminance in an ideal case due to input gray and reduced light emission luminance due to deterioration.

The compensation value calculator 811 calculates a compensation value required for a corresponding pixel based on the received pixel characteristics. In addition, the compensation value calculator 811 calculates a necessary compensation value in gray units. In the embodiment with reference to FIG. 6, 255 [gray] was input as the input gray, but when the actually measured luminance was 140 [nit], the effective gray was calculated as 247.13 [gray], and accordingly, the compensation value was calculated as 7.87 [gray]. do.

The storage controller 812 stores the calculated compensation value in the compensation value storage unit 830 . Specifically, the storage control unit 812 stores the compensation values in the compensation value storage unit 830 in gray units. Also, the storage controller 812 may variably control the number of bits of the integer part and the number of bits of the fractional part. For example, assuming that the compensation value is calculated as 7.87 [gray] and a total of 8 bits are allocated, control is performed so that the integer part is 7 bits and the fractional part is 1 bit, and 7.5 [gray] as the compensation value is stored in the compensation value storage unit. (830). Alternatively, 7.75 [gray] may be stored in the compensation value storage unit 830 as a compensation value by controlling to have a 6-bit integer part and a 2-bit fractional part. Alternatively, 7.785 [gray] may be stored in the compensation value storage unit 830 as a compensation value by controlling to have a 5-bit integer part and a 3-bit fractional part.

The adder 813 receives input grays in gray units and receives compensation values in gray units. For example, input gray can be received from the host system 100 . The compensation value may be received from the storage controller 812 or the compensation value storage unit 830 . In addition, the adder 813 performs an addition operation on the received input grays and the compensation value and outputs them in units of grays. For example, the adder 813 may output gray output to the data driver 130 or the gate driver 150 in gray units. An image will be displayed on the display panel 110 based on the output gray.

Also, the number of bits of the compensation value may be the same as the number of bits of the input gray. For example, when input gray is received in 8 bits, the compensation value may also be stored in 8 bits.

As described above in the background art, the compensation value is conventionally expressed as parameters of gain and offset, but according to the present invention, the compensation value is expressed in gray units. Accordingly, conventionally, 8 bits were required to store gain values and 8 bits were required to store offset values, resulting in a storage space of 16 bits for one pixel. However, since the present invention expresses the compensation value in gray units, an 8-bit storage space is required, thereby reducing the memory capacity.

In addition, in the prior art, a bandwidth for communicating 16-bit data was required to transmit and receive a compensation value, but since the present invention requires only a bandwidth for communicating 8-bit data, the bandwidth can be reduced.

In addition, in the prior art, a multiplier for multiplying a gain value was required to calculate a compensation value, and accordingly, the circuit configuration was complicated and the physical size was inevitably large. However, according to the present invention, a circuit can be configured with only an adder having a simple structure.

In addition, although FIG. 8 shows that the compensating device is included in the timing controller 800, other configurations may also fall within the scope of the present invention. For example, the compensation device 810 may be configured separately from the timing controller 800 to communicate with each other.

In addition, although FIG. 8 shows that the compensation value storage unit 830 communicates with the compensation device 810, other configurations may also fall within the scope of the present invention. For example, the compensation value storage unit 830 may be configured to belong to the compensation device 810 .

9 is a diagram showing a compensating device and a display device according to the present invention.

Referring to FIG. 9 , a compensation value storage unit 814 for each gray level is added compared to FIG. 8 .

The compensation value storage unit 814 for each gray level may store a representative compensation value within a specified range. For example, the compensation value storage unit 814 for each gray level stores a representative compensation value for a low gray level, a representative compensation value for a medium gray level, and a representative compensation value for a high gray level.

The low gradation representative compensation value is a representative compensation value when a low gradation range is input. For example, the grayscale of the low range includes an input gray range of 0 to 80 [gray]. Also, the low grayscale representative compensation value may be, for example, 8.38 [gray]. The representative compensation value for the low gray level may be generated by the compensation value calculation unit 811 based on information received from the pixel characteristic detection unit 820 . The storage controller 812 stores the representative compensation value for the low gray level in the compensation value storage unit 814 for each gray level.

The representative compensation value for grayscale is a representative compensation value when grayscales in the middle range are input. For example, a low range grayscale includes a range of 80 to 160 [gray] in input gray. Also, a representative compensation value for grayscale may be, for example, 8.10 [gray]. The grayscale representative compensation value may be generated by the compensation value calculation unit 811 based on the information received from the pixel characteristic detection unit 820 . The storage controller 812 stores representative compensation values for grayscale levels in the compensation value storage unit 814 for each grayscale level.

The high gradation representative compensation value is a representative compensation value when a high gradation range is input. For example, a high-range grayscale includes a range of 160 to 255 [gray] in input gray. Also, the representative compensation value for the high gray level may be, for example, 7.87 [gray]. The high grayscale representative compensation value may be generated by the compensation value calculation unit 811 based on the information received from the pixel characteristic detection unit 820 . The storage controller 812 stores the representative compensation value for the high gray level in the compensation value storage unit 814 for each gray level.

The adder 813 may determine a grayscale range to which the input gray belongs and receive a representative compensation value of the corresponding range. For example, when the input grayscale is 50 [gray], a compensation value of 8.38 [gray] representing the low grayscale is received from the compensation value storage unit 814 for each grayscale and added to the input grayscale. For example, when the input gray level is 130 [gray], a compensation value of 8.10 [gray], which is a representative compensation value for gray levels, is received from the compensation value storage unit 814 for each gray level and added to the input gray level. For example, when the input grayscale is 210 [gray], a compensation value of 7.87 [gray] representing the high grayscale is received from the compensation value storage unit 814 for each grayscale and added to the input grayscale.

Alternatively, the compensation value storage unit 814 for each gray level may store a representative compensation value of a specific interval. For example, the compensation value storage unit 814 for each gray level may store representative compensation values of 50 gray intervals. That is, 0 [gray] representative compensation value, 50 [gray] representative compensation value … 250 [gray] The representative compensation value can be stored. The adder 813 may receive a representative compensation value of a gray closest to the input gray. For example, when the input grayscale is 120 [gray], a representative compensation value of 100 [gray] is received and added to the input gray.

Alternatively, the compensation value storage unit 814 for each gray level may store a specific number of representative compensation values. For example, the compensation value storage unit 814 for each gray level includes a total of four compensation values of 10 [gray] representative compensation value, 50 [gray] representative compensation value, 80 [gray] representative compensation value, and 230 [gray] representative compensation value. A representative compensation value can be stored. The adder 813 may receive a representative compensation value of a gray closest to the input gray. For example, when the input grayscale is 120 [gray], a representative compensation value of 80 [gray] is received and added to the input gray.

Accordingly, it is not necessary to store compensation values for each input gray in the compensation value storage unit 830, and it is sufficient if a small number of representative compensation values are stored in the compensation value storage unit 814 for each gray level. Accordingly, the consumption of storage space can be reduced, and the bandwidth for transmitting and receiving the compensation value can be reduced.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

800: timing controller
810: compensation device
811: compensation value calculation unit
812: storage control unit
813: adder
820: pixel characteristic detection unit
830: compensation value storage unit

Claims (15)

a compensation value calculator for receiving pixel characteristic information and calculating a compensation value required for a pixel in gray units;
a storage control unit which stores the calculated compensation value in gray units in a compensation value storage unit and reads the stored compensation value;
An adder for receiving input grays in units of grays, receiving compensation values in units of grays, performing an addition operation on the received input grays and compensation values, and outputting them in units of grays,
The storage control unit,
Dividing the compensation value into an integer part and a fractional part and storing it in the compensation value storage unit, and variably controlling the number of bits of the integer part and the number of bits of the fractional part,
compensation device. delete delete According to claim 1,
The number of bits of the compensation value is stored as the same or smaller number of bits than the input gray.
compensation device. According to claim 1,
Further comprising a compensation value storage unit for each gradation,
The compensation value storage unit for each gray level stores a representative compensation value,
compensation device. According to claim 5,
The compensation value storage unit for each gray level stores representative compensation values for each range of gray levels.
compensation device. According to claim 5,
The compensation value storage unit for each gray level stores a representative compensation value of a specific interval,
compensation device. According to claim 5,
The compensation value storage unit for each gray level stores a specific number of representative compensation values,
compensation device. timing controller;
a data driver receiving a driving signal from the timing controller;
a gate driver receiving a driving signal from the timing controller;
a display panel including a plurality of pixels and displaying an image based on signals received from the data driver and the gate driver; and
a power driver supplying power to the data driver, the gate driver, and the display panel;
The timing controller:
Receiving pixel characteristic information and calculating a compensation value required for a pixel in gray units;
Storing the calculated compensation value in gray units and reading the stored compensation value;
Receiving input grays in units of grays, performing an addition operation on the input grays and the compensation value;
The timing controller,
Dividing and storing the compensation value into an integer part and a decimal part, and variably controlling the number of bits of the integer part and the number of bits of the fractional part,
display device. delete According to claim 9,
The number of bits of the compensation value is stored as the same or smaller number of bits than the input gray.
display device. According to claim 9,
The timing controller stores representative compensation values for each gray level.
display device. According to claim 12,
The timing controller stores the representative compensation value for each range of gray levels.
display device. According to claim 12,
The timing controller stores the representative compensation value at specific intervals.
display device. According to claim 12,
The timing controller stores a specific number of the representative compensation values,
display device.

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