KR20210043414A - Vertical field-effect transistor(vfet) devices and methods of forming the same - Google Patents

Abstract

Provided are vertical field effect transistor (VFET) devices to provide increased reliability and a forming method thereof. According to the present invention, the method comprises: a step of forming a preliminary VFET on a substrate; a step of forming a contact opening extending through an insulating layer; a step of forming a cavity between a channel region and the insulating layer by removing a patterned sacrificial layer through the contact opening; and a step of forming a gate electrode in the cavity. The preliminary VFET includes a lower source/drain region disposed on the substrate, the channel region disposed on the lower source/drain region, an upper source/drain region disposed on the channel region, the patterned sacrificial layer disposed on the side surfaces of the channel region, and the insulating layer. The lower source/drain region, the channel region, and the upper source/drain region are sequentially stacked on the substrate, the upper source/drain region and the patterned sacrificial layer are surrounded by the insulating layer, and the contact opening can expose a part of the patterned sacrificial layer.

Description

A vertical field effect transistor device and a method of forming a vertical field effect transistor device {VERTICAL FIELD-EFFECT TRANSISTOR(VFET) DEVICES AND METHODS OF FORMING THE SAME}

TECHNICAL FIELD The present invention relates generally to the electronics field and in particular to vertical field-effect transistor (VFET) devices.

Due to the high scalability of vertical field effect transistor devices, various structures and manufacturing processes of vertical field effect transistor devices have been studied. Accordingly, it may be advantageous to develop a manufacturing process that improves the performance and/or reliability of vertical field effect transistor devices.

The problem to be solved by the present invention is to provide a method of manufacturing a vertical field effect transistor device with improved reliability.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

According to some embodiments of the inventive concept, the gate electrode may be formed after the upper source/drain regions are formed. Accordingly, the characteristics of the gate electrode may not be affected by the process of forming the upper source/drain regions. Specifically, the gate electrode may not be oxidized or damaged by heat. In some embodiments, the gate electrode may be formed by a replacement gate process performed through a gate contact opening in which the gate contact is formed later. In some embodiments, the upper source/drain region may be formed within the opening of the insulating layer and the upper source/drain region may be defined within the opening.

According to some embodiments of the present inventive concept, a method of forming a vertical field effect transistor device includes forming a preliminary vertical field effect transistor on a substrate, forming a contact opening extending through the insulating layer, and forming a pattern through the contact opening. Forming a cavity between the channel region and the insulating layer by removing the sacrificial layer, and forming a gate electrode in the cavity, wherein the preliminary vertical field effect transistor includes: a lower source/drain region on a substrate; A channel region on the lower source/drain region; An upper source/drain region on the channel region and a sacrificial layer patterned on a side surface of the channel region; And an insulating layer, wherein a lower source/drain region, a channel region, and an upper source/drain region are sequentially stacked on the substrate, the upper source/drain region and the patterned sacrificial layer are surrounded by the insulating layer, and contact openings May expose a portion of the patterned sacrificial layer.

According to some embodiments of the present inventive concept, a method of forming a vertical field effect transistor device includes forming a mask layer on a substrate, etching the substrate using the mask layer as an etch mask, thereby forming a channel region, and forming a channel region on the substrate. A lower source/drain region is formed, a first liner extending on a side surface of the channel region and a side surface and an upper surface of the mask layer is formed, a patterned sacrificial layer is formed under the side surface of the channel region, and An upper spacer is formed on the upper side of the side surface, an insulating layer is formed on the substrate, and a portion of the mask layer and the upper spacer is removed to form an upper source/drain opening in the insulating layer. A drain region is formed, a contact opening extending through the insulating layer is formed, and the sacrificial layer patterned through the contact opening is replaced with a gate electrode, thereby forming a gate electrode on the lower side of the side of the channel region, The spacer and the patterned sacrificial layer may be surrounded by an insulating layer, and the contact opening may expose a portion of the patterned sacrificial layer.

According to some embodiments of the inventive concept, a method of forming a vertical field effect transistor device includes forming a vertical field effect transistor on a substrate, wherein the vertical field effect transistor includes a lower source/drain region and a lower portion on the substrate. A channel region on the source/drain region, an upper source/drain region on the channel region, and a gate electrode on the side of the channel region, wherein the lower source/drain region, the channel region, and the upper source/drain region are on the substrate. It is sequentially stacked, and the gate electrode includes a work function layer and a metal electrode sequentially stacked on side surfaces of the channel region, and the work function layer may surround the metal electrode in a cross-sectional view.

1 is a flowchart illustrating methods of forming a vertical field effect transistor device according to some embodiments of the inventive concept.
2 is a flowchart illustrating methods of forming a vertical field effect transistor device according to some embodiments of the inventive concept.
3 to 11, 13 to 16, 18 to 21, and 23 are cross-sectional views illustrating methods of forming a vertical field effect transistor device according to some embodiments of the inventive concept.
12, 17, and 22 are plan views illustrating methods of forming a vertical field effect transistor device according to some embodiments of the inventive concept.
24 to 28 are cross-sectional views illustrating methods of forming a vertical field effect transistor device according to some embodiments of the inventive concept.
29 to 33 are cross-sectional views illustrating methods of forming a vertical field effect transistor device according to some embodiments of the inventive concept.

In the present specification, exemplary embodiments will be described with reference to the accompanying drawings. Many other forms and embodiments are possible without departing from the spirit and teachings of the present invention, and thus the present invention should not be construed as being limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided to complete the present invention and convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals refer to the same components.

Exemplary embodiments of the technical idea of the present invention are described below with reference to sectional views which are schematic diagrams of ideal embodiments and intermediate structures of exemplary embodiments. As such, variations from the shape of the illustration as a result, for example manufacturing techniques and/or tolerances, should be expected. Accordingly, exemplary embodiments of the technical idea of the present invention should not be construed as being limited to the specific shape exemplified herein, and include, for example, variations in shape resulting from the manufacturing process.

1 is a flowchart illustrating methods of forming a vertical field effect transistor device according to some embodiments of the inventive concept. Referring to FIG. 1, the method comprises forming a preliminary vertical field effect transistor (e.g., vertical field effect transistor shown in FIG. 13) and sequentially forming contact openings (e.g., contact opening 62 in FIG. 14). ) Forming a gate electrode (eg, the gate electrode 74 of FIG. 18) may be included. The preliminary vertical field effect transistor may include an upper source/drain region (e.g., the upper source/drain region 52 of FIG. 18), whereby the gate electrode is formed after forming the upper source/drain region. I can.

The preliminary vertical field effect transistor includes a lower source/drain region (e.g., lower source/drain region 22 of FIG. 13), a channel region (e.g., the channel region 12 of FIG. 13), and patterned sacrificial A layer (eg, the patterned sacrificial layer 33p of FIG. 13) and an insulating layer (eg, the second insulating layer 46 of FIG. 13) may be further included. The lower source/drain regions, the channel regions, and the upper source/drain regions are sequentially stacked on a substrate (eg, the substrate 10 of FIG. 13 ).

2 is a flowchart illustrating a method of forming a vertical field effect transistor device according to some embodiments of the inventive concept. Specifically, FIG. 2 is a flow chart showing a process of forming portions of a preliminary vertical field effect transistor.

3 to 11, 13 to 16, 18 to 21, and 23 are cross-sectional views illustrating methods for forming a vertical field effect transistor device according to some embodiments of the inventive concept. 17 and 22 are plan views illustrating methods for forming a vertical field effect transistor according to some embodiments of the inventive concept.

13 and 18 are cross-sectional views taken along line A-A' of FIGS. 12 and 17, respectively, and FIGS. 14 and 19 are cross-sectional views taken along line B-B' of FIGS. 12 and 17, respectively. 23 is a cross-sectional view taken along line B-B' of FIG. 22. FIG. 20 is an enlarged view of area C of FIG. 18, and FIG. 21 is an enlarged view of area D of FIG. 19.

2 and 3, forming the preliminary vertical field effect transistor includes forming a lower source/drain region 22 and a channel region 12 on the substrate 10. In some embodiments, forming the channel region 12 comprises forming the mask layer 14 on the substrate 10 (block 110 in FIG. 2) and using the mask layer 14 as an etch mask to form the substrate 10. ) Is etched to form the channel region 12 (block 120). For example, the mask layer 14 may be a hard mask layer including SiN and/or SiON. The channel region 12 may protrude from the substrate 10 in the third direction D3. The third direction D3 may be a vertical direction, and the third direction D3 may be perpendicular to the upper surface 10u of the substrate 10.

The substrate 10 may include one or more semiconductor materials (eg, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and/or InP). In some embodiments, the substrate 10 may be a bulk substrate (eg, a bulk silicon substrate) or a semiconductor on insulator (SOI) substrate. As shown in FIG. 3, two channel regions 12 may be formed on the substrate 10. The two channel regions 12 may be spaced apart from each other in the first horizontal direction D1. The first horizontal direction D1 may be parallel to the upper surface 10u of the substrate 10.

The lower source/drain regions 22 may be formed on the substrate 10 before or after the channel region 12 is formed. In some embodiments, the lower source/drain region 22 is formed by implanting impurity elements (eg, boron (B), phosphorus (P) and/or arsenic (As)) into the substrate 10. I can. In some embodiments, the lower source/drain region 22 is an epitack including impurity elements (eg, boron (B), phosphorus (P) and/or arsenic (As)) on the substrate 10. It can be formed by forming an epitaxial layer. The epitaxial layer of the lower source/drain region 22 may be formed by performing an epitaxial growth process using the substrate 10 as a seed layer.

The lower spacer 24 is formed on the lower source/drain region 22, and is formed from the elements sequentially formed on the lower source/drain region 22 (for example, the gate electrode 74 in FIG. 18). The source/drain regions 22 may be electrically separated. The lower spacer 24 may include insulating materials (eg, silicon oxide, silicon nitride, or silicon oxynitride).

As shown in FIG. 3, the first liner 26 may be formed on the lower spacer 24, the side surface of the channel region 12, and the side surface and the upper surface of the mask layer 14 (block 130 of FIG. 2 ). ). The first liner 26 may be formed to protect the channel region 12 during a subsequent process. In some embodiments, the first liner 26 may have a uniform thickness along a side surface of the channel region 12 and a side surface and an upper surface of the mask layer 14 as shown in FIG. 3. The first liner 26 may include a material different from the channel region 12 so that the first liner 26 can be selectively removed from the side surface of the channel region 12. For example, the first liner may be a silicon oxide layer.

Throughout this specification, removing the layer X may mean removing the layer X using a wet etch process and/or a dry etch process. Although the first liner 26 in FIG. 3 is shown as a single layer, in some embodiments, the first liner 26 includes a plurality of stacked layers sequentially stacked on the side of the channel region 12. can do.

Referring to FIG. 4, the method may include sequentially forming a preliminary sacrificial layer 32 and a preliminary second liner 34 on the first liner 26. Each of the preliminary sacrificial layer 32 and the preliminary second liner 34 may have a uniform thickness as shown in FIG. 4. For example, the preliminary sacrificial layer 32 may be a silicon layer (eg, an amorphous silicon layer and/or a polysilicon layer) and/or a metal layer (eg, a TiN layer and/or a Ti layer). For example, the preliminary second liner 34 may be a layer including an insulating material (eg, a silicon layer including oxygen and/or nitride).

Referring to FIG. 5, the method may further include forming the first insulating layer 36 under the side surface of the channel region 12. Side surfaces of the channel region 12 may include upper and lower portions between the upper portion of the channel region 12 and the substrate 10. The first insulating layer 36 may include an insulating material (eg, a low dielectric layer having a dielectric constant lower than that of oxygen and/or nitride or silicon dioxide). The first insulating layer 36 is formed only on the lower side of the side surface of the channel region 12, and the first insulating layer 36 is a preliminary sacrificial layer 32 and a preliminary second insulating layer on the first insulating layer 36. Parts of the liner 34 are exposed.

6, portions of the preliminary sacrificial layer 32 and the preliminary second liner 34 on the first insulating layer 36 are removed, so that the sacrificial layer 33 and the second liner 35 are formed. I can. The sacrificial layer 33 and the second liner 35 may be formed on the lower side of the channel region 12 as shown in FIG. 6. In some embodiments, portions of the preliminary sacrificial layer 32 and the preliminary second liner 34 on the first insulating layer 36 may be removed until the lower first liner 26 is exposed. A portion of the channel region 12 and the mask layer 14 may protrude in a third direction D3 beyond the upper surfaces of the sacrificial layer 33 and the second liner 35 as shown in FIG. 6.

Referring to FIG. 7, the upper spacer layer 42 may be formed on the mask layer 14, the sacrificial layer 33, the second liner 35, and the first insulating layer 36. The upper spacer layer 42 may directly contact the sacrificial layer 33, the second liner 35, and the upper surfaces of the first insulating layer 36 and the first liner 26 as shown in FIG. 7. have. In some embodiments, the upper spacer layer 42 may have a uniform thickness along the mask layer 14 as shown in FIG. 7. For example, the upper spacer layer 42 may include an insulating material (eg, silicon oxide, silicon nitride, and/or silicon oxynitride). In some embodiments, the upper spacer layer 42 may be a SiN layer. In some embodiments, the upper spacer layer 42 may be a plurality of stacked layers.

Referring to FIG. 8, portions of the upper spacer layer 42 may be removed until the lower first insulating layer 36 is exposed. Portions of the upper spacer layer 42 on the top surface of the mask layer 14 may also be removed to form the upper spacer 44. In some embodiments, the upper spacer 44 may overlap the upper surface of the sacrificial layer 33 and the second liner 35 as shown in FIG. 8.

Referring to FIG. 9, a first insulating layer 36 and a second liner as shown in FIG. 9 are used as an etching mask using the mask layer 14, the first liner 26, and the upper spacer 44 as an etching mask. The patterned sacrificial layer 33p and the patterned second liner 35p may be formed by removing portions of the 35 and the sacrificial layer 33. The first insulating layer 36, the second liner 35, and the sacrificial layer 33 may be removed until a portion of the first liner 26 extending on the lower spacer 24 is exposed. In some embodiments, a portion of the first insulating layer 36 may remain on the side surface of the patterned second liner 35p as shown in FIG. 9.

Referring to FIG. 10, a second insulating layer 46 may be formed on the substrate 10. The upper spacer 44, the patterned sacrificial layer 33p, and the patterned second liner 35p may be located in the second insulating layer 46. A portion of the first insulating layer 36 on the side surfaces of the patterned second liner 35p and the second insulating layer 46 may be referred to as an insulating layer as a whole. The second insulating layer 46 may include an insulating material (eg, a silicon layer or a low dielectric layer including oxygen and/or nitride). In some embodiments, the second insulating layer 46 and the first insulating layer 36 may include the same material, and an interface between the second insulating layer 46 and the first insulating layer 36. ) May not be visible. In some embodiments, the upper surface of the second insulating layer 46 and the upper surface of the upper spacer 44 and the mask layer 14 may be on the same plane as shown in FIG. 10.

Referring to FIG. 11, portions of the first liner 26 on the upper spacer 44, the mask layer 14 and the channel region 12 are removed, and the upper source/drain in the second insulating layer 46 is removed. An opening 48 may be formed. A portion of the second insulating layer 46 defines an upper source/drain opening 48 on the channel region 12 as shown in FIG. 9. The upper source/drain opening 48 may expose the upper spacer 44 and the channel region 12. After forming the upper source/drain opening 48, the first liner 26 can remain between the upper spacer 44 and the channel region 12, and the first liner 26 is removed from the channel region 12. The upper spacer 44 can be separated.

12 and 13, the upper source/drain region 52 may be formed in the upper source/drain opening 48. To simplify the description, FIG. 12 does not show all elements shown in FIGS. 13 and 14. For example, the upper source/drain regions 52 may be formed by performing an epitaxial growth process using the channel region 12 as a seed layer. The epitaxial growth process for forming the upper source/drain regions 52 may be performed at a high temperature (eg, about 400°C to about 700°C). The upper source/drain region 52 may contact the lower portion of the upper source/drain region 52, the upper spacer 44, and the channel region 12. In some embodiments, the third insulating layer 56 may be formed in the upper source/drain opening 48 on the upper source/drain region 52. Since the upper source/drain regions 52 are formed in the upper source/drain openings 48, a patterning process of patterning the upper source/drain regions 52 may not be performed.

12 and 14, the lower source/drain regions 22 may be formed in the field isolation layer 11. In some embodiments, the lower source/drain region 22 may be an upper portion of the active region formed on the substrate 10. Specifically, the active region may be located on the side of the field isolation layer 11, and the field isolation layer 11 may surround the active region. Each of the channel regions 12 may extend in a vertical direction, which is the second horizontal direction D2. The second horizontal direction D2 may be parallel to the upper surface of the substrate 10 (eg, 10u of FIG. 3 ). In some embodiments, the second horizontal direction D2 may be perpendicular to the first horizontal direction D1. In some embodiments, the field isolation layer 11 may surround the lower source/drain region 22 as illustrated in FIG. 12.

The contact opening 62 may be formed to extend through the second insulating layer 46. The contact opening 62 may also extend through portions of the patterned sacrificial layer 33p and the patterned second liner 35p extending on the field isolation layer 11. In some embodiments, a portion of the first liner 26 extending over the field isolation layer 11 may be removed while forming the contact opening 62, and the contact opening 62 is shown in FIG. As described above, the field isolation layer 11 may be exposed. In some embodiments, a portion of the first liner 26 extending over the field isolation layer 11 may not be removed while forming the contact opening 62, and the contact opening 62 may be formed of the field isolation layer ( A part of the first liner 26 extending on 11) may be exposed.

The contact opening 62 may overlap the field isolation layer 11, and the contact opening 62 may be spaced apart from the channel region 12 in the second horizontal direction D2. The patterned sacrificial layer 33p may have a first thickness T1 on the side surface of the channel region 12, and the patterned sacrificial layer 33p may also have a field isolation layer ( 11) It may have a first thickness T1 on it.

15 and 16, the patterned sacrificial layer 33p is removed through the contact opening 62 to form a cavity 64 between the channel region 12 and the second insulating layer 46. I can. For example, an etchant for removing the patterned sacrificial layer 33p may be supplied through the contact opening 62. In some embodiments, the cavity 64 may be defined by the first liner 26, the patterned second liner 35p and the second insulating layer 46.

Referring to FIG. 16, the cavity 64 may include a portion extending over the field isolation layer 11. The etchant for removing the patterned sacrificial layer 33p extends on the channel region 12 so that the channel region 12 can be protected by the first liner 26 while removing the patterned sacrificial layer 33p. The first liner 26 may not be removed. The cavity 64 may have the same width as the first thickness T1 of the patterned sacrificial layer 33p. The cavity 64 may be connected to the contact opening 62.

17, 18, and 19, the gate insulator 72 and the gate electrode 74 may be sequentially formed in the cavity 64 through the contact opening 62. To simplify the description, FIG. 17 does not show all elements shown in FIGS. 18 and 19. Each of the gate insulator 72 and the gate electrode 74 may be formed by performing an atomic layer deposition (ALD) process. The gate insulator 72 may be formed conformally in the cavity 64 as shown in FIGS. 18 and 19. The gate insulator 72 may have a uniform thickness as shown in FIGS. 18 and 19. In some embodiments, the gate insulator 72 may surround the gate electrode 74 in a cross-sectional view as shown in FIG. 18. The gate insulator 72 may include silicon oxide and/or a high dielectric constant material (eg, hafnium oxide or aluminum oxide).

The gate electrode 74 may be formed in the cavity 64. For example, the gate electrode 74 may include a metal layer (eg, tungsten (W), titanium (Ti), copper (Cu), and/or cobalt (Co)). After forming the gate electrode 74, a portion of the first liner 26 may still be positioned between the upper spacer 44 and the channel region 12.

20 is an enlarged view of area C of FIG. 18. Referring to FIG. 20, the gate electrode 74 may include a work function layer 75 and a metal electrode 77. The work function layer 75 and the metal electrode 77 may be sequentially formed on the gate insulator 72. In some embodiments, the work function layer 75 may surround the metal electrode 77 in a cross-sectional view as shown in FIG. 20. The work function layer 75 may be used to tune the work function of the gate electrode 74, and the work function layer 75 is a metal nitride (eg, TiN, TiAlN, TaAlN), TiAl, TaC, TiC, or HfSi may be included. Although the work function layer 75 is shown as a single layer in FIG. 20, the work function layer 75 may be a plurality of stacked layers. The work function layer 75 may have a uniform thickness along the surface of the gate insulator 72 as shown in FIG. 20.

The metal electrode 77 may include a metal (eg, aluminum (Al), tungsten (W), and/or copper (Cu)). In some embodiments, the metal electrode 77 may be formed by repeatedly depositing an atomic layer on the surface of the work function layer 75 until the metal electrode 77 has a second thickness T2. The metal electrode 77 may include a seam 78 spaced apart from the surface of the work function layer 75 by a certain distance (ie, the second thickness T2). In some embodiments, the shim 78 of the metal electrode 77 can be seen.

21 is an enlarged view of area D of FIG. 19. Referring to FIG. 19, the gate insulator 72 may have portions spaced apart from each other in the third direction D3, and the gate electrode 74 may be formed between other portions of the gate insulator 72. The shim 78 of the metal electrode 77 may be spaced apart from the work function layer 75 by a uniform distance (ie, the second thickness T2).

In some embodiments, the gate insulator 72 and the gate electrode 74 may be formed on the side 46s of the second insulating layer 46 defining the contact opening 62, and the gate insulator 72 And a portion of the gate electrode 74 may be removed.

To simplify the description, FIG. 22 also does not show all elements shown in FIG. 23. Referring to FIGS. 22 and 23, the gate electrode 74 includes a self-aligned portion 74s formed on the lower source/drain region 22 and a field gate portion 74f extending on the field isolation layer 11. Can include. The gate contact 82 may be formed in the contact opening 62. The gate contact 82 may overlap the field isolation layer 11, and the gate contact 82 may contact the field gate portion 74f of the gate electrode 74. In some embodiments, the gate insulator 72 may surround a lower portion of the gate contact 82 in a plan view as shown in FIG. 22, and the lower portion of the gate contact 82 may be It can be located within the electrode 74. The gate contact 82 may include a conductive material (eg, a doped semiconductor material and/or a metal material).

In some embodiments, the gate voltage may be applied to the gate electrode 74 through the gate contact 82 while the vertical field effect transistor device is operating. The gate contact 82 may electrically connect the gate electrode 74 to the word line of the vertical field effect transistor device.

24 to 28 are cross-sectional views illustrating methods for forming a vertical field effect transistor device according to some embodiments of the inventive concept. Referring to FIG. 24, in some embodiments, the gate insulator 72 includes a preliminary sacrificial layer (eg, the preliminary sacrificial layer 32 of FIG. 4) and a preliminary second liner (eg, the preliminary sacrificial layer 32 of FIG. 4 ). It may be formed before the second liner 34 is formed. After the gate insulator 72 is formed, the structures shown in FIGS. 25 and 26 may be formed by performing a process similar to that described with reference to FIGS. 4 to 19. 25 and 26 are views corresponding to FIGS. 18 and 19.

Referring to FIG. 25, the gate insulator 72 may not surround the gate electrode 74. The gate insulator 72 may be positioned between the channel region 12 and the gate electrode 74 and between the lower spacer 24 and the gate electrode 74. The gate insulator 72 may not be present on the surface of the other gate electrode 74. In some embodiments, the first liner 26 may be positioned between the channel region 12 and the gate insulator 72 and between the lower spacer 24 and the gate insulator 72 as shown in FIG. 25. have. Referring to FIG. 26, the contact opening 62 may not penetrate a part of the gate insulator 72.

FIG. 27 is an enlarged view of the area E of FIG. 25, and FIG. 28 is an enlarged view of the area F of FIG. 26. The gate electrode 74 may include a work function layer 75 and a metal electrode 77. The work function layer 75 may surround the metal electrode 77 as shown in FIG. 27. The metal electrode 77 may be formed to have a second thickness T2, and the shim 78 may have a predetermined distance from the work function layer 75 in the first horizontal direction D1 (eg, a second thickness ( It can be formed to be spaced apart by T2)). A part of the metal electrode 77 extending on the field isolation layer 11 may be formed to have a second thickness T2 as shown in FIG. 28, and the shim 78 may be formed in a third direction D3. It may be formed to be spaced apart from the work function layer 75 by a certain distance (eg, the second thickness T2).

29 to 33 are cross-sectional views illustrating a method of forming a vertical field effect transistor device according to some embodiments of the inventive concept. 29 to 33, the preliminary sacrificial layer (eg, the preliminary sacrificial layer 32 of FIG. 4) and the preliminary second liner (eg, the preliminary second liner 34 of FIG. 4) are 1 The insulating layer (for example, the first insulating layer 36 of FIG. 5) may be patterned before being formed, and thus, the patterned preliminary sacrificial layer 32p and the patterned preliminary second liner 34p ) To form. The preliminary sacrificial layer and the preliminary second liner may be patterned using a mask pattern (eg, a photoresist pattern) as an etching mask.

Referring to FIG. 30, the first insulating layer 36 may be formed on the patterned preliminary sacrificial layer 32p and the patterned preliminary second liner 34p. Part of the patterned preliminary sacrificial layer 32p and the patterned preliminary second liner 34p are removed, thereby forming the patterned sacrificial layer 33p and the patterned second liner 35p. I can.

Referring to FIGS. 31 to 33, similarly to the processes described with reference to FIGS. 8, 10 and 11 may be performed. The first insulating layer 36 and the second insulating layer 46 may be sequentially stacked on the lower spacer 24 as shown in FIG. 33. The first insulating layer 36 and the second insulating layer 46 may be referred to as insulating layers as a whole.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used as meanings that can be commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, it will be understood that terms such as terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of a related technology and not to be interpreted as an ideal or excessively formal meaning. However, cases explicitly defined are excluded.

The terms used in this specification are for describing only specific embodiments, and are not intended to limit the technical idea. In the context of describing the invention (especially in the context of the following claims), the terms "a", "an", "the" and similar terms refer to the singular and plural unless otherwise specified herein or clearly contradicted by context. It is interpreted to be all inclusive. As used herein, the terms “comprises”, “comprising”, “includes”, and/or “including” refer to the recited features, Specifies the presence of steps, operations, elements, and/or components, but one or more other features, steps, actions, elements, components And/or the presence or addition of groups. The term "and/or" as used herein includes all combinations of one or more related items.

Terms such as first and second may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component may be referred to as a second component without departing from the present technical idea.

It should be noted that, in some other embodiments, the functions/actions recorded in the flowchart blocks herein may occur out of the order indicated in the flowchart. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order depending on the function/actions involved. Further, the functionality of a given block of flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the illustrated blocks, and/or blocks/operations may be omitted without departing from the scope of the present technical idea.

The technical idea of the present invention described above should be regarded as illustrative, not restrictive, and the appended claims are intended to cover all such modifications, improvements and other embodiments that fall within the technical spirit and scope of the present invention. Accordingly, to the maximum extent permitted by law, the scope is determined by the widest acceptable interpretation of the following claims and their equivalents, and should not be limited by the foregoing detailed description.

10: substrate 11: field isolation layer
12: channel region 14: mask layer
22: lower source/drain area 24: lower spacer
26: first liner 33, 33p: patterned sacrificial layer
35, 35p: patterned second liner 44: upper spacer
52: upper source/drain region 62: contact opening
72: gate insulator 74: gate electrode
75: work function layer 77: metal electrode
78: Sim 82: Gate Contact

Claims (20)

Forming a preliminary vertical field effect transistor on the substrate,
Forming a contact opening extending through the insulating layer,
A cavity is formed between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening,
Forming a gate electrode in the cavity,
The preliminary vertical field effect transistor,
A lower source/drain region on the substrate;
The channel region on the lower source/drain region;
An upper source/drain region on the channel region,
A sacrificial layer patterned on a side surface of the channel region; And
Including an insulating layer,
The lower source/drain regions, the channel regions, and the upper source/drain regions are sequentially stacked on the substrate,
The upper source/drain region and the patterned sacrificial layer are surrounded by the insulating layer,
The contact opening is a method of forming a vertical field effect transistor exposing a portion of the patterned sacrificial layer. The method of claim 1,
After forming the gate electrode, further comprising forming a gate contact in the contact opening,
The method of forming a vertical field effect transistor device in which the gate contact is in contact with the gate electrode. The method of claim 2,
Further comprising forming an active region and a field isolation layer on the substrate,
The active region is positioned on a side surface of the field isolation layer, the channel region is formed on the active region, and the gate contact overlaps the field isolation layer. The method of claim 1,
Further comprising forming a gate insulator in the cavity prior to forming the gate electrode in the cavity,
The gate insulator is a method of forming a vertical field effect transistor device surrounding the gate electrode in a cross-sectional view. The method of claim 1,
Forming the gate electrode includes sequentially forming a work function layer and a metal electrode in the cavity,
The work function layer is a method of forming a vertical field effect transistor device surrounding the metal electrode in a cross-sectional view. The method of claim 1,
The preliminary vertical field effect transistor,
An upper spacer separating the patterned sacrificial layer from the upper source/drain regions; And
A method of forming a vertical field effect transistor device further comprising a first liner separating the channel region from the patterned sacrificial layer and the upper spacer. The method of claim 6,
The method of forming a vertical field effect transistor device wherein the first liner comprises a silicon oxide layer. The method of claim 1,
Forming the preliminary vertical field effect transistor,
Forming a mask layer on the substrate,
The channel region is formed by etching the substrate using the mask layer as an etching mask,
Forming a first liner extending to a side surface of the channel region and a side surface and an upper surface of the mask layer,
Forming the patterned sacrificial layer below the side surface of the channel region, and forming an upper spacer on the side surface of the channel region,
The first liner is a method of forming a vertical field effect transistor device separating the channel region from the patterned sacrificial layer and the upper spacer. The method of claim 1,
Forming the preliminary vertical field effect transistor,
Forming the lower source/drain regions and the channel regions on the substrate;
Forming the patterned sacrificial layer on a side surface of the channel region;
Forming an upper spacer on the patterned sacrificial layer;
Forming the insulating layer on the substrate;
Including forming the upper source/drain region in the upper source/drain opening,
The upper spacer and the patterned sacrificial layer are surrounded by the insulating layer, and the insulating layer includes an upper source/drain opening on the upper spacer. The method of claim 9,
Forming the upper source/drain region,
A method of forming a vertical field effect transistor device comprising performing an epitaxial growth process using the channel region as a seed layer. The method of claim 10,
The method of forming a vertical field effect transistor device in which the upper source/drain region contacts a portion of the insulating layer defining the upper source/drain opening. The method of claim 1,
Further comprising forming an active region and a field isolation layer on the substrate,
The active region is located on the side of the field isolation layer, the channel region is formed on the active region, and a portion of the patterned sacrificial layer overlaps the field isolation layer. . Forming a mask layer on the substrate;
Etching the substrate using the mask layer as an etching mask to form a channel region;
Forming a lower source/drain region on the substrate;
Forming a first liner extending on a side surface of the channel region and a side surface and an upper surface of the mask layer;
Forming a patterned sacrificial layer under the side surface of the channel region;
Forming an upper spacer on the side of the channel region;
Forming an insulating layer on the substrate;
An upper source/drain opening is formed in the insulating layer by removing a portion of the mask layer and the upper spacer;
An upper source/drain region is formed in the upper source/drain opening;
Forming a contact opening extending through the insulating layer;
Forming the gate electrode under the side surface of the channel region by replacing the patterned sacrificial layer with a gate electrode through the contact opening,
The upper spacer and the patterned sacrificial layer are surrounded by the insulating layer,
The contact opening is a method of forming a vertical field effect transistor device exposing a portion of the patterned sacrificial layer. The method of claim 13,
Forming an active region and a field isolation layer on the substrate,
Further comprising forming a gate contact in the contact opening after forming the gate electrode,
The active region is located in the field isolation layer, the channel region is formed on the active region,
Wherein the gate contact contacts the gate electrode and overlaps the field isolation layer. The method of claim 13,
The first liner is a method of forming a vertical field effect transistor device positioned between the upper spacer and the upper side of the channel region after forming the gate electrode. The method of claim 13,
Forming the gate electrode,
Forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening,
Including sequentially forming a gate insulator and the gate electrode in the cavity,
Wherein the gate insulator surrounds the gate electrode in a cross-sectional view. Forming a vertical field effect transistor on the substrate,
The vertical field effect transistor,
A lower source/drain region on the substrate;
A channel region on the lower source/drain region;
An upper source/drain region on the channel region; And
Including a gate electrode on the side of the channel region,
The lower source/drain regions, the channel regions, and the upper source/drain regions are sequentially stacked on the substrate,
The gate electrode includes a work function layer and a metal electrode sequentially stacked on a side surface of the channel region, wherein the work function layer surrounds the metal electrode in a cross-sectional view. The method of claim 17
The vertical field effect transistor further includes a gate insulator extending between the side surface of the channel region and the gate electrode,
The gate insulator is a method of forming a vertical field effect transistor device surrounding the gate electrode in a cross-sectional view. The method of claim 17,
Forming an active region and a field isolation layer on the substrate,
Further comprising forming a gate contact in contact with the field gate portion of the gate electrode,
The active region is positioned on a side surface of the field isolation layer, the channel region is positioned on the active region, and the gate electrode includes a vertical field effect transistor device including the field gate portion extending on the field isolation layer. How to form. The method of claim 19,
A method of forming a vertical field effect transistor device wherein a lower portion of the gate contact is located within the field gate portion of the gate electrode.

Images