KR20210040602A - Cell control circuit of embeded flash memory - Google Patents

Abstract

The present invention relates to a cell control circuit of an embedded flash memory, which satisfies a hot carrier injection-type program operation and an FN tunneling-type erasing operation, and can increase pumping current by boosting a gate of an NMOS precharging transistor with a grounded body to normally precharge a precharging node with input voltage in place of using a cross-coupled NMOS precharging circuit. The cell control circuit of the embedded flash memory according to the present invention can satisfy both of the hot carrier injection-type program operation and the FN tunneling-type erasing operation, and increase the pumping current by normally precharging a precharging node of a VPP unit charge pump with input voltage (VIN) using a circuit for boosting a gate of a 12V NMOS precharging transistor with a body functioning as the ground.

Description

Cell control circuit of embedded flash memory {CELL CONTROL CIRCUIT OF EMBEDED FLASH MEMORY}

The present invention relates to a cell control circuit of an embedded flash memory, and more particularly, satisfies the erasing operation of the program of the hot carrier injection method and the FN tunneling method, and the body is grounded instead of using a cross-coupled NMOS precharging circuit. The present invention relates to a cell control circuit of an embedded flash memory capable of increasing a pumping current by boosting a gate of an NMOS precharging transistor to normally precharge a precharging node with an input voltage.

The demand for embedded system design has increased with the development of embedded memory, low power design technology, and 3D integration technology such as chip stack. Among these factors, embedded memory is the most in terms of system cost, performance and power. It is an important basic technology, and SRAM and embedded Flash (eFlash) memory dominate the market.

Mask ROM memory was used for code storage as an embedded non-volatile memory in early MCU systems, and an EEPROM memory chip was used separately for storing large amounts of data. Since then, embedded flash (eFlash) memory that combines mask ROM for code storage and data ROM was developed in the 1990s, and eFlash memory is used more than EEPROM for large-capacity memory of 512Kb or more depending on application products.

The nonvolatile memory was commercialized in 256x8bit Mask ROM chip in 1969, PROM chip in 1970, and EPROM chip in 1971. In 1983, 16Kb EEPROM was released. Triple Poly Flash EEPROM cell was released in 1984 as a flash memory cell capable of electrically block erase. In 1988, ETOX (EEPROM Tunnel Oxide) Flash EEPROM was released for the first time in the world.

1 is a cross-sectional view of a cell process of an embedded flash memory according to the prior art.

The cells of an embedded flash (eFlash) memory are often used as floating gate (FG) devices with a storage layer to store electric charges, and the number of transistors used in the cells of the embedded flash (eFlash) memory is largely used. Accordingly, it is divided into 1T cells, 1.5T cells and 2T cells. The 1T cell is a NOR type cell suitable for large-capacity memory due to its small cell size, and requires additional processing and is vulnerable to over-erase and data retention, so it cannot be used if the capacity of the embedded flash (eFlash) memory is not very large. Does not. Split gate floating gate (FG) cells, 1.5T FG cells and 2T FG cells, are larger in cell size than 1T FG cells, but are used more than 1T FG cells because of their superior performance and power consumption characteristics.

The first generation SuperFlash memory cell, which is a 1.5T FG cell, has a pointed floating gate (FG) tip as shown in FIG. 1. The high source line (SL) voltage is coupled to the floating gate (FG), and the low control gate (CG) voltage slightly above the cell threshold voltage is the floating gate (FG) and the control gate (CG). Induces a high electric field in the gap region between them. Since the magnitudes of the horizontal and vertical electric fields have a maximum in the gap region, hot electrons are efficiently created in the gap region and injected into the floating gate FG.

So Super Flash (SuperFlash) memory cell is being programmed through the source-side electron injection method, the program current is small as 5 oi A. And it is erased by a poly-to-poly FN (Fowler-Nordheim) tunneling method through a pointed floating gate (FG) tip. Since these embedded flash (eFlash) it is not Super Flash (SuperFlash) the memory cell is over-erase problems of the memory cells of the program current is also as small as 5 oi A has been used most frequently from the prior art.

Meanwhile, in recent years, the supply voltage of DRAM has been decreasing to 1.8V or 1.5V, which can be seen to reduce power consumption and to improve reliability problems that occur when the size of the device is reduced. When the power supply voltage decreases, the threshold voltage Vt of the DRAM transistor must decrease accordingly. However, when the threshold voltage of the transistor decreases, a problem may occur in a refresh characteristic due to a leakage current that increases due to a low threshold voltage. In order to solve this problem, a high voltage generator circuit (VPP Generator) is used. The high voltage generation circuit solves the threshold voltage problem of the NMOS transistor used in DRAM by raising the word-line voltage of the selected transistors.

As such a high voltage generation circuit, a PWM (Pulse Width Modulation) method using an inductor and a charge pump method using a switched capacitor are mainly used.In general, DRAM has advantages in terms of area, etc. A charge pump circuit is mainly used.

FIG. 2 is a circuit diagram of a charge pump circuit of a cross-couple precharging method according to the prior art. As shown, cross-couple between the input voltage VIN and the first pumping node N1 and the second pumping node N2. The first and second NMOS transistors (MN1) and (MN2), the first and second PMOS transistors cross-coupled between the first and second pumping nodes (N1) and (N2) and the output voltage (VOUT) ( MP1), (MP2), the terminals of the first pumping capacitor C1 and the second clock signal CLK2 connected between the terminals of the first clock signal CLK1 and the first pumping node N1, and the second And a second pumping capacitor C2 connected between the pumping nodes N2. Here,'MN' means an N-channel MOS transistor, and'MP' means a P-channel MOS transistor.

When the charge pump circuit of the cross-coupled precharging method as shown in FIG. 2 is used, the first and second PMOS transistors MP1 and MP2 cross-coupled as the output transistors are the first and second pumping nodes N1 without loss of the threshold voltage. Transfers the pumped charge of ), (N2) to the output terminal where the output voltage VOUT is output.

Since the bodies of the first and second PMOS transistors MP1 and MP2 are connected to the boost voltage, the first and second PMOS transistors MP1 and MP2 ,2 The body voltages of the PMOS transistors MP1 and MP2 are lower than the voltages of the source or the drain and are placed in the active region.

For this reason, in the conventional charge pump circuit of the cross-couple precharging method, some of the pumped charges of the pumping node leak to the substrate (p-substrate) through the output transistor, causing charge loss.

That is, when the first clock signal CLK1 and the second clock signal CLK2 are 0V and VCC, respectively, the voltages of the first pumping node N1 and the second pumping node N2 are input voltage VIN and pumping, respectively. A voltage boosted through the first PMOS transistor MP1 as the voltage VIN+VCC is transferred to the output, and the first pumping node N1 must be precharged with the input voltage VIN.

However, when the VCC voltage is 2.5V, the body voltage of the 12V HV (High Voltage) NMOS transistor is connected to the ground, so the threshold voltage increases to about 2V due to the body effect, and the first pumping occurs. There is a problem in that the voltage of the node N1 is not sufficiently precharged to the input voltage VIN. In addition, while the voltages of the first and second pumping nodes N1 and N2 are crossing, the first NMOS transistor MN1 must be turned off, but the backward current is the input voltage ( VIN) There is a problem that the pumping current falls because it flows to the node.

3 is another circuit diagram of a charge pump circuit of a cross-couple precharging method according to the prior art.

As shown in FIG. 3, the 11th and 12th NMOS transistors MN11 and MN12 cross-coupled between the input voltage VIN and the 11th and 12th pumping nodes N11 and N12, and the eleventh. , Terminals of the 11th and 12th PMOS transistors MP11, MP12, and the 11th clock signal CLK11 cross-coupled between the 12 pumping nodes N11 and N12 and the output voltage VOUT. The 11th pumping capacitor C11 connected between the 11 pumping nodes N11, the 12th pumping capacitor C12 connected between the terminal of the 12th clock signal CLK12 and the 12th pumping node N12, 11 A first bulk-potential biasing circuit (BPBC) connected to the NMOS transistor (MN11) 330, a second bulk potential biasing circuit (340) connected to the 12th NMOS transistor (MN12) , A third bulk potential biasing circuit 350 connected to the eleventh PMOS transistor MP11 and a fourth bulk potential biasing circuit 360 connected to the twelfth PMOS transistor MP12.

Among the 11th and 12th NMOS transistors MN11 and MN12 and the 11th and 12th PMOS transistors MP11 and MP12, the 1-4 bulk potential biasing circuits 330 to 360 respectively connected to the corresponding transistors are It is connected to solve the charge loss problem.

Since the DRAM uses isolated NMOS transistors such as the 11th NMOS precharging transistor MN11 and the 12th NMOS precharging transistor MN12, the body effect can be removed, and the tenth to thirteenth Since the clock signals CLK10, CLK11, CLK12 and CLK13 are non-overlap clock signals, backward through the 11th NMOS precharging transistor MN11 and the 12th NMOS precharging transistor MN12 (backward) There is no problem of dropping the pumping current due to the current.

On the other hand, the first precharge circuit 310 and the second precharge circuit 320 of the 11th NMOS precharging transistor (MN11) and the 12th NMOS precharging transistor (MN12) in the standby (stand-by) mode. This is to precharge the gate node voltage to the VCC voltage, and this precharges the boosted voltage to VCC when entering the standby mode after charge pumping.

On the other hand, in the embedded flash memory, the boosting node voltage is cross-coupled during charge pumping in the conventional unit charge pump circuit that supplies VPP (Boosted Voltage) voltages of 9.5V and 11.5V in program mode and erase mode, respectively. coupled) As charge is transferred through the PMOS transistor, the voltage of the boosting node drops, and when the voltages of the two pumping nodes are crossed, the body effect as the backward current flows to the input voltage (VIN) node. A cross-coupled NMOS transistor having a high threshold voltage due to) does not normally precharge the precharging node to the input voltage VIN, so that the pumping current decreases.

However, unlike the DRAM process, in the embedded flash process, an isolated NMOS such as the 11th NMOS precharging transistor MN11 and the 12th NMOS precharging transistor MN12 shown in FIG. There was a problem that the transistor could not be used.

The problem to be solved by the present invention satisfies the hot carrier injection program and the erase operation of the FN tunneling method. Instead of using a cross-coupled NMOS precharging circuit, the body is boosted by boosting the gate of the grounded NMOS precharging transistor. It is to provide a cell control circuit of an embedded flash memory that can increase the pumping current by normally precharging the charging node with an input voltage.

A cell control circuit of an embedded flash memory according to an embodiment of the present invention for achieving the above technical problem includes a cell array of an embedded flash memory; A cell array driving circuit for driving the cell array; A control logic circuit for generating a control signal according to an operation mode for the cell array; A charge pump circuit for supplying a program voltage to the cell array; And a bit line sense amplifier circuit for reading the current of the cell array, amplifying and outputting data corresponding thereto.

According to the cell control circuit of an embedded flash memory according to the present invention, there is an advantage of satisfying both a program of a hot carrier injection method and an erase operation of an FN tunneling method.

On the other hand, according to the cell control circuit of the embedded flash memory according to the present invention, instead of using a cross-coupled NMOS precharging circuit, a circuit that boosts the gate of a 12V NMOS precharging transistor whose body is GND is used to pre-charge the VPP unit charge pump. There is an advantage of increasing the pumping current by normally precharging the charging node with the input voltage (VIN).

1 is a process cross-sectional view of an embedded flash memory cell according to the prior art.
2 is a circuit diagram of a charge pump circuit of a cross-couple precharging method according to the prior art.
3 is another circuit diagram of a charge pump circuit of a cross-couple precharging method according to the prior art.
4 is a block diagram of a cell control circuit of an embedded flash memory according to the present invention.
5 is a circuit diagram of a row driving circuit of a cell control circuit of an embedded flash memory according to the present invention.
6 is a circuit diagram of a bit line driving circuit of a cell control circuit of an embedded flash memory according to the present invention.
7 is a circuit diagram of a read bit line switch circuit of a cell control circuit of an embedded flash memory according to the present invention.
8 is a circuit diagram of a bit line sense amplifier circuit of a cell control circuit of an embedded flash memory according to the present invention.
9 is a circuit diagram of a charge pump circuit of a cell control circuit of an embedded flash memory according to the present invention.
10 is a waveform diagram showing an output experiment result of a cell control circuit of an embedded flash memory according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to a control circuit of a 512Kb embedded flash (eFlash) memory using a 110nm embedded flash (eFlash) cell for USB type-C application. The control circuit of an embedded flash memory according to the present invention satisfies both a hot carrier injection type program and an FN tunneling type erase operation.

4 is a block diagram of a cell control circuit of an embedded flash memory according to the present invention.

Referring to FIG. 4, the cell control circuit 400 of the embedded flash memory according to the present invention includes a cell array 410 in which embedded flash memory cells are arranged in a matrix form, and the cell array 410 according to an input address A. ), a cell array driving circuit 420 for supplying a voltage to a control gate CG and a source line SL node by selecting one of the rows, a program mode for the cell array 410, or A control logic circuit 430 that generates a control signal according to the erase mode, a charge pump circuit 440 that supplies a program voltage (VPP) to the cell array 410, and the current of the embedded flash memory cell connected to the selected bit line. It includes a bit line sense amplifier circuit 450 that reads out, amplifies and outputs data corresponding thereto.

The cell array 410 is a split gate type cell array in which embedded flash memory cells are arranged in a matrix form. In the cell array 410, a control gate (CG), a floating gate (FG), and a source line (SL) are routed in a row direction, and a bit line (BL) is routed in a column direction. A plurality of embedded flash memory cells are disposed between BL and the source line SL.

In the present invention, a cell control circuit for a 512Kb embedded flash memory based on a 110nm eFlash process using an embedded flash memory cell was developed, and a cell bias condition selected for each operation mode of the embedded flash memory cell according to the present invention is as follows.

In the program mode, when the voltages of the control gate (CG), bit line (BL), and source line (SL) are applied at 1.5V, 0.8V, and 9.5V, respectively, the source side to which the source line SL is connected. ), electrons are accelerated by a high electric field in the horizontal direction to generate hot electrons, and are injected into the floating gate FG by the high electric field in the vertical direction. In this way, the threshold voltage of the embedded flash memory cell rises to about 4V by hot electron injection.

Meanwhile, in the erase mode, the cell bias condition is when the voltages of the control gate (CG), bit line (BL), and source line (SL) are applied at 11.5V, 0V, and 0V, respectively, electrons are erased from FG poly to CG poly by FN tunneling. (electron ejection) occurs. In this way, the threshold voltage of the embedded flash memory cell is reduced to 0.8V or less by the electronic erase.

On the other hand, in the read mode, when the voltage of the control gate (CG), bit line (BL), and source line (SL) is applied at 2.5V, 0.8V, and 0V, the erased cell remains ON and the ON current is 40. While ㅅA flows, the program cell maintains the OFF state and the OFF current flows less than 1㎁. BL S/A separates ON current and OFF current, so it outputs data '0' and '1' respectively.

Table 1 shows the main features of the 512Kb embedded flash memory designed using the 110nm eFlash process.

The embedded flash memory cell uses a split-gate embedded flash memory cell, and the control gate (CG) and source line (SL) are routed in a row direction using a first metal, and the bit line (BL) is It is routed in the column direction using the second metal.

The voltage used is the dual power of VCC and VDD, and the VCC voltage has a wide operating voltage range of 2.5V~5.5V, and the VDD voltage is 1.5V, 10%, which is the voltage used for 1.5V logic devices. The operation mode is a normal operation mode, and there are read, page erase, and program modes, and there are erase-verify-read and program-verify-read modes as write-verify-read mode. And it supports all erase mode. The embedded flash memory cell array consists of 512 rows and 1,024 columns, and page erase, program and read operations are performed in units of 1Kbit, 32bit, and 32bit, respectively.

The main characteristics of a 512Kb embedded flash memory device designed using a 0.13㎛ BCD process according to the present invention are shown in Table 1 below.

[Table 1]

The cell array driving circuit 420 of the cell control circuit of an embedded flash (eFlash) memory according to the present invention includes a row driving circuit 421, a bit line driving circuit 422, and a bit line switch circuit 423. .

5 is a circuit diagram showing a row driving circuit of a cell control circuit of an embedded flash memory according to the present invention. The row driving circuit 421 includes a control gate (CG) driving circuit and a source line (SL) driving circuit. FIG. 5A is a circuit diagram of a control gate CG driving circuit, and FIG. 5B is a circuit diagram of a source line SL driving circuit.

The control gate CG driving circuit drives CG_HV for the control gate CG selected according to the operation mode, and 0V for the control gate CG that is not selected. Table 2 shows the switching output voltage of CG_HV according to the operation mode. The CG_HV voltage supplies 2.5V in read mode, 1.5V in program mode, and 11.5V in page erase mode.

In the source line (SL) driving circuit, the SL_ENb signal becomes VDD only in the erase mode, and the remaining operation mode becomes 0V. So, in the erase (page erase / all erase) mode, the SL_SEL and SL_SELb signals are output as 0V and VPP, respectively, and MN0 is turned ON, and SL drives the VSL_UNSEL voltage of 0V. In the other modes other than the erasing mode, the SL_ENb signal is 0V, so the source line (SL) selected by the row address RA[8:0] outputs the SL_SEL and SL_SELb signals VPP and 0V, respectively, so the MP1 and MN1 MOS transistors are turned on. SL voltage is driven with VSL_SEL voltage, whereas SL not selected by RA[8:0] outputs SL_SEL and SL_SELb signals of 0V and VPP, respectively, so MP1 and MN1 MOS transistors are turned off to drive SL voltage with VSL_UNSEL voltage. do.

Table 2 shows the selected VSL voltage VSL_SEL and the unselected VSL voltage VSL_UNSEL for each operation mode.

[Table 2]

6 is a circuit diagram showing a bit line driving circuit.

The bit line driving circuit 422 shown in FIG. 6 is a WBL (Write Bit-Line) switching circuit that switches the corresponding voltage to the bit line BL in the erase mode and the write mode, which is a program mode, and 32 WDb_BLs in the program mode. It includes a PBL_SEL circuit that selects.

As shown in FIG. 6, the bit line driving circuit 422 outputs 0V for the PBL_ENb signal only in the program mode to turn on the MP3 transistor, and outputs the BL_HV voltage for the other modes including the erase mode and the read mode. It is turned off.

6(a) is a WBL switch circuit. In the program mode, the PBL_ENb signal outputs 0V, and the PBL_SEL and PBL_SELb signals selected by the column address CA[4:0] output BL_HV and 0V, respectively. And MN5 transistors are turned on. In this case, the bit line BL switches the WDb_BL voltage as it is, and the WDb_BL drives 0V and BL_HV (=3.3V) for the program data VDD and 0V, respectively.

And since the PBL_SEL and PBL_SELb signals that are not selected in the program mode output 0V and BL_HV, respectively, MP5 and MN5 of the corresponding bit line (BL) are OFF, and MP3 and MP4 are ON, so the bit line (BL) voltage is inhibited voltage. Drive the BL_HV voltage.

Meanwhile, in the erase mode, the PBL_ENb signal outputs the BL_HV (=2.5V) voltage, so the MP3 transistor is turned off, and the PBL_SEL and PBL_SELb signals output BL_HV and 0V, respectively. Drives 0V by.

Also, in the read mode, since the PBL_ENb signal outputs the BL_HV (=2.5V) voltage, the MP3 transistor is turned off, and the PBL_SEL and PBL_SELb signals output 0V and BL_HV, respectively, so that the MP5 and MN5 transistors are turned off and all bit lines (BL) are Maintain a high impedance state.

6B shows a PBL_SEL signal for selecting 32 WDb_BLs and a PBL_SEL circuit for generating a PBL_SELb signal in a program mode.

7 is a circuit diagram showing a bit line switch circuit for selecting a bit line in a read mode.

As shown in FIG. 7, the bit line switch circuit 423 divides 1024 bit lines BL into 32 bit lines BL in the read mode, and selects 32 bit lines BL by RBL_SEL[31: The data of the corresponding bit line BL is transmitted to the data line DL by the 0] signal. Data of 32 embedded flash memory cells transferred to the data line DL[31:0] are output as output data DOUT.

8 is a circuit diagram of a bit line sense amplifier circuit of an embedded flash memory cell control circuit according to the present invention.

The bit line sense amplifier circuit 450 illustrated in FIG. 8 reads the current of an embedded flash memory cell connected to the selected bit line BL and outputs output data DOUT.

Referring to FIG. 8, since the DL_PCGb voltage is 0V in the stand-by mode, the MP1 transistor is in the ON state, the RD node voltage is precharged to VDD, and the MN2 transistor is turned on, so the RDb node voltage is discharged to 0V ( discharging). When entering the read mode, since the DL_CLAMPb signal becomes 0V, the data line DL is clamped to about 0.8V by the operation of the DL clamping circuit 451, and the voltage of the bit line BL is also precharged to 0.8V. In a state in which the voltage of the bit line BL is sufficiently precharged, when the DL_PCGb signal, which is a signal for precharging the data line DL, is disabled from 0V to VDD, the MN2 transistor and the MP1 transistor are turned off.

On the other hand, if the cell of the embedded flash memory is a programmed cell, the pull-down current through MN1 is negligibly small at the level of 1㎁, so the RD, RDb, and DOUT node voltages are VDD, 0V, and VDD voltages when the DL_PCGb signal is 0V. Keep each. On the other hand, in the case of an erased embedded flash memory cell, the ON current of the embedded flash memory cell 40 µA flows to GND through the MN1 transistor, and the ON current of the embedded flash memory cell is reduced to the PMOS current mirror (452). ), and when the mirrored current of RDb is greater than the reference current flowing through the MN3 transistor, the RDb node voltage rises to VDD and the output data DOUT outputs 0V.

9 is a circuit diagram of a charge pump circuit of a cell control circuit of an embedded flash memory according to the present invention.

In the present invention, instead of using a cross-coupled NMOS precharging circuit, instead of using a cross-coupled NMOS precharging circuit, a circuit that boosts the gate of a 12V NMOS precharging transistor whose body is GND is used to solve the problem of the charge pump circuit dropping. The pumping current was increased by normally precharging the precharging node with the input voltage (VIN).

That is, in the present invention, the charge pump circuit of FIG. 9 using an NMOS pumping capacitor while using a 12V NMOS precharging transistor and a 12V PMOS cross-coupled charge transfer switch based on an embedded flash memory process is used. Suggested.

As shown in FIG. 9, the charge pump circuit 440 of the cell control circuit of the embedded flash memory according to the present invention includes a first NMOS transistor MN21 formed between an input voltage and a first pumping node N21, an input Second NMOS transistor MN22 formed between voltage and second pumping node N22, first and second PMOS transistors cross-coupled between the first pumping node and the second pumping node and the output voltage (MP21, MP22), a first pumping capacitor MN24 connected between the terminal of the first clock signal CLK11 and the first pumping node, a second clock signal having a phase opposite to the first clock signal CLK11 A second pumping capacitor MN25 connected between the terminal of (CLK12) and the second pumping node, third and fourth PMOS transistors MP23 and MP24 cross-coupled, and the first NMOS transistor MN21 ) Connected to the first body potential biasing circuit 443, cross-coupled fifth and sixth PMOS transistors MP25 and MP26, and a second body potential biasing connected to the second NMOS transistor MN22 A circuit 444 is connected between the input voltage VIN and the first pumping node N21 to precharge the first pumping node N21 to the input voltage VIN in a standby mode. A second charging circuit 441 is connected between the input voltage VIN and the second pumping node N22 to precharge the second pumping node N22 to the input voltage VIN in a standby mode. The third and fourth NMOS transistors MN29 and MN30 cross-coupled between the precharging circuit 442 and the first precharging node N20 and the second precharging node N23 and the input voltage VIN. Includes.

In the embedded flash memory process, isolated NMOS transistors such as the first NMOS transistor MN11 and the second NMOS transistor MN12 of FIG. 2 are not supported. 2 A 12V NMOS transistor with GND as the same body as the NMOS transistor MN22 was used.

In addition, the bodies of 12V PMOS transistors such as the first PMOS transistor MP21 and the second PMOS transistor MP22 are the first body potential biasing circuit 443 and the second body potential biasing circuit 444 of FIG. 9. Use to connect the high voltage of the first node N21 and the output voltage VOUT to the body of the first PMOS transistor MP21, and the higher of the second node N22 and the output voltage VOUT. The voltage was connected to the body of the second PMOS transistor MP22. In this case, without using the first body potential biasing circuit 443 and the second body potential biasing circuit 444, the bodies of the first PMOS transistor MP21 and the second PMOS transistor MP22 are supplied with an output voltage ( VOUT) node can also be connected.

When the charge pump circuit 440 does not operate, the first precharge circuit 441 and the second precharge circuit 442 are the gate node voltages of the first NMOS transistor MN21 and the second NMOS transistor MN22. Is precharged with the input voltage (VIN). However, the output voltage node of each pumping stage has a separate VCC precharging circuit, so when VPP is turned off, the VOUT node of each unit charge pump circuit is precharged to VCC. It is not necessary to precharge the gate node voltage of the transistor MN21 and the second NMOS transistor MN22 to VCC.

The first pumping capacitor MN24 and the second pumping capacitor MN25 of the VPP unit charge pump circuit may use a PMOS transistor, an NMOS transistor, and a native NMOS transistor. However, when examining the pumping current and the layout area, the native NMOS pumping capacitor has a larger pumping current and a smaller layout area than the PMOS pumping capacitor, so it is more preferable to use a 12V native NMOS pumping capacitor in the present invention. Meanwhile, the charge pump circuit in the present invention may be used by connecting the unit charge pump circuit of FIG. 9 in a seven-stage cascade.

10 is a waveform diagram showing an experimental result of an output of a cell control circuit of an embedded flash memory according to the present invention.

In the present invention, simulation of the waveform of the output wave was performed under the simulation conditions of VCC=2.5V, VDD=135V, Temp.=125℃, and slow model parameter. FIG. 10(a) shows the simulation results of the output wave of the selected signal and the unselected signal related to the cell array in the program mode, and FIG. 10(b) is It shows the simulation result of the output wave of the signal that is not available.

Referring to (a) of FIG. 10, it is shown that the selected CG and unselected CG voltages in the program mode are 1.5V and 0V, respectively, and the voltages of the selected source line SL and the unselected source line SL Is 9.5V and 0.8V, respectively, and the voltages of the selected bit line BL and the unselected bit line BL are 0.8V and 3.3V, respectively. Meanwhile, the selected CG and unselected CG voltages in the erase mode are shown to be 11.5V and 0V, respectively, and both the source line (SL) and the bit line (BL) voltages are shown to be 0V.

Meanwhile, referring to FIG. 10B, it is shown that the CG selected and the unselected CG voltage in the erase mode are 11.7 to 11.8V and 0V, respectively.

Table 3 shows the comparison of the simulation results of the pumping current according to the charge pump circuit of the cell control circuit of the embedded flash memory according to the present invention and the conventional charge pump circuit.

In Table 3, the unit charge pump circuit shown in FIG. 2 was used as the conventional unit charge pump circuit, and the unit charge pump circuit shown in FIG. 9 was used as the unit charge pump circuit of the embedded flash memory according to the present invention. Meanwhile, the results were compared using three types of pumping capacitors: a 12V PMOS pumping capacitor operating in the accumulation region, a 12V normal NMOS pumping capacitor operating in the inversion region, and a 12V native NMOS pumping capacitor.

As a result of the comparison, it can be seen that when a native NMOS pumping capacitor is used in the unit charge pump circuit shown in FIG. 9, the layout area is small and the pumping current is also increased. Therefore, in the present invention, it is preferable to use a unit charge pump circuit to which a 12V native NMOS pumping capacitor is applied.

[Table 3]

As described above, the cell control circuit of the embedded flash memory according to the present invention uses a 110nm eFlash cell for USB type-C application to control a cell of a large-capacity memory of 512Kb or more. That is, the cell control circuit of the embedded flash memory according to the present invention includes a row driving circuit that satisfies a program operation and an erase operation, a BL driving circuit and a bit line sense amplifier circuit (BL S/A).

Meanwhile, the charge pump circuit of the cell control circuit of the embedded flash memory according to the present invention uses a 12V NMOS precharging transistor and a 12V native NMOS pumping capacitor whose body is GND instead of using a cross-coupled NMOS precharging circuit. The precharging node of the VPP unit charge pump is precharged with the input voltage (VIN) through the unit charge pump circuit that boosts the gate of the NMOS precharging transistor to increase the pumping current so that the precharging node can be normally precharged. I did.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, but may be implemented in more various embodiments based on the basic concept of the present invention defined in the following claims, These embodiments also belong to the scope of the present invention.

Claims (10)

In the cell control circuit of the embedded flash memory,
Cell array of embedded flash memory;
A cell array driving circuit for driving the cell array;
A control logic circuit for generating a control signal according to an operation mode for the cell array;
A charge pump circuit for supplying a program voltage to the cell array; And
And a bit line sense amplifier circuit for reading the current of the cell array, amplifying and outputting data corresponding thereto. The method of claim 1, wherein the cell array driving circuit
A row driving circuit for driving the control gate and the source line;
A bit line driving circuit for switching the corresponding voltage to the bit line in the erase mode and the program mode; And
A cell control circuit for an embedded flash memory, comprising: a bit line switch circuit for selecting a bit line in a read mode. The method of claim 2, wherein the row driving circuit,
A control gate driving circuit; And
A cell control circuit of an embedded flash memory, comprising: a source line driving circuit. The method of claim 1, wherein the charge pump,
A first NMOS transistor formed between the input voltage and the first pumping node N21; (MN21)
A second NMOS transistor formed between the input voltage and the second pumping node N22; (MN22)
First and second PMOS transistors cross-coupled between the first pumping node and the second pumping node and an output voltage; (MP21, MP22)
A first pumping capacitor connected between the terminal of the first clock signal and the first pumping node; (MN24)
A second pumping capacitor connected between a terminal of a second clock signal having a phase opposite to that of the first clock signal and the second pumping node; (MN25)
A first body potential biasing circuit having third and fourth PMOS transistors cross-coupled and connected to the first NMOS transistor; (MP23, MP24)
A second body potential biasing circuit having fifth and sixth PMOS transistors cross-coupled and connected to the second NMOS transistor; (MP25, MP26)
A first precharge circuit connected between the input voltage and the first pumping node to precharge the first pumping node with the input voltage in a standby mode;
A second precharge circuit connected between the input voltage and the second pumping node to precharge the second pumping node with the input voltage in a standby mode; And
Embedded flash comprising: third and fourth NMOS transistors cross-coupled between the first precharging node N20 and the second precharging node N23 and the input voltage; (MN29, MN30); Memory cell control circuit. The method of claim 4,
The cell control circuit of an embedded flash memory, wherein the body of the first NMOS transistor and the second NMOS transistor is grounded. The method of claim 4, wherein the first body potential biasing circuit
The cell control circuit of an embedded flash memory, comprising providing a higher voltage among the voltage of the first pumping node and the output voltage to the body of the first PMOS transistor. The method of claim 4, wherein the second body potential biasing circuit is
A cell control circuit of an embedded flash memory, comprising providing a higher voltage among the voltage of the second pumping node and the output voltage to the body of the second PMOS transistor. The method of claim 4, wherein the first precharge circuit
The cell control circuit of an embedded flash memory, characterized in that precharging the gate voltage of the first NMOS transistor to the input voltage. The method of claim 4, wherein the second precharge circuit
A cell control circuit of an embedded flash memory, characterized in that precharging the gate voltage of the second NMOS transistor to the input voltage. The method of claim 4, wherein the first pumping capacitor and the second pumping capacitor
A cell control circuit of an embedded flash memory, characterized in that it is a native NMOS pumping capacitor.

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