KR20210036660A - Sensing circuit and display device including the same - Google Patents

Abstract

A display device of the present invention comprises: a display panel including pixels; an integrator receiving a sensing current from the pixels through a system input line connecting a sensing channel and a first input terminal, receiving a reference voltage through a reference voltage line connected to a second input terminal, and including a capacitor connected to the system input line to store a potential difference between a potential of the system input line and a potential of the reference voltage; a sampling unit sampling the output voltage of the integrator; and an analog-to-digital converter (ADC) converting the voltage received from the sampling unit into a digital sensing value and outputting the converted digital sensing value.

Description

Sensing circuit and display device including the same

The present invention relates to a sensing circuit and a display device including the same.

The organic light emitting display device arranges pixels, each including OLED, in a matrix form, and adjusts the luminance of the pixels according to the gradation of the video data. Each of the pixels includes a driving element, that is, a driving TFT (Thin Film Transistor), which controls a driving current flowing through the OLED according to a voltage applied between the gate electrode and the source electrode. The electrical characteristics of OLEDs and driving TFTs change due to temperature or deterioration. If the electrical characteristics of the OLED and/or the driving TFT are different for each pixel, the luminance between the pixels for the same video data is different, so it is difficult to realize a desired image.

External compensation techniques are known to compensate for changes in electrical properties for OLEDs or driving TFTs. The external compensation technology senses changes in the electrical characteristics of OLEDs or driving TFTs, and modulates digital video data based on the sensing results. As an external compensation technology, a voltage sensing method and a current sensing method are known. Among them, the current sensing method using a current integrator is advantageous in relatively shortening the sensing time because it enables low current and high speed sensing. Accordingly, research for improving the performance of a current sensing circuit using a current integrator is ongoing.

An object of the present invention for solving the problems of the above-described background art is to provide a sensing circuit capable of sensing current characteristics of pixels and a display device including the same.

In addition, an object of the present invention is to reduce the size of a sensing circuit capable of sensing current characteristics of pixels, and consequently, to reduce the size of a data drive IC.

In addition, an object of the present invention is to improve the increase in the initialization time before sensing by increasing the load of the sensing line as the display device of a large area and high resolution increases.

As the above-described problem solving means, a display device of the present invention includes: a display panel including pixels; A sensing current is supplied from the pixels through a system input line connecting a sensing channel and a first input terminal, a reference voltage is supplied through a reference voltage line connected to a second input terminal, and the system is connected to the system input line. An integrator including a scaling capacitor for storing a potential difference between a potential of an input line and the reference voltage; A sampling unit that samples the output voltage of the integrator; And an analog-to-digital converter (ADC) converting the voltage received from the sampling unit into a digital sensing value and outputting the converted voltage.

One end of the scaling capacitor may be connected to the first input terminal and the other end may be connected to the sensing channel.

A switch connected between the scaling capacitor and the first input terminal may be further included.

It may include a first switch connected between the sensing channel and the scaling capacitor.

A second switch for applying or releasing a system reference voltage to the system input line may be included.

The integrator may include an amplifier (AMP) including the first input terminal, the second input terminal, and an output terminal outputting the output voltage; An integrating capacitor connected between the first input terminal and the output terminal of the amplifier (AMP) and connected in parallel with the scaling capacitor; And a reset switch connected to both ends of the integrating capacitor and the scaling capacitor.

The scaling capacitor may have a higher capacitance than the integrating capacitor.

The sampling unit may include a sampling capacitor for storing an output voltage output from the integrator; And a sampling switch connected between the integrator and the sampling capacitor, wherein at least two or more reference voltages of different sizes may be selectively connected to the sampling capacitor.

The sampling capacitor may output an output voltage output from the integrator in a voltage range that can be input to the analog-to-digital converter according to the reference voltage.

The sampling capacitor may further include at least one switch selectively connecting the at least two different reference voltages.

The sensing circuit of the present invention as the above-described problem solving means includes: an amplifier (AMP) including a first input terminal, a second input terminal, and an output terminal; A scaling capacitor connected to a system input line connecting the sensing channel and the first input terminal; An integrating capacitor connected between the first input terminal and the output terminal of the amplifier (AMP) and connected in parallel with the scaling capacitor; And a reset switch connected to both ends of the integrating capacitor and the scaling capacitor.

A sampling switch connected to the output terminal; A sampling capacitor for storing the output voltage of the amplifier supplied through the sampling switch; And a switch selectively connecting at least two or more reference voltages having different sizes to the sampling capacitor.

According to the present invention, by adding a scaling function to the integrator circuit and the sampling unit circuit to configure the sensing unit, the design area required by the scaler can be reduced, and as a result, the size of the sensing circuit can be reduced.

In addition, according to a configuration change of the integrator circuit, the load of the sensing line increases as a display device having a large area and high resolution increases, and thus, an increase in an initialization time before sensing may be improved.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
2 is a diagram schematically showing the configuration of an external compensation circuit using a timing controller and a data driver IC according to an embodiment of the present invention.
3 is a schematic diagram illustrating a configuration of a sensing unit according to a first embodiment of the present invention.
4 is a diagram showing in detail the configuration of a sensing unit according to the first embodiment of the present invention.
5 is a diagram illustrating an operation waveform of a sensing unit according to the first embodiment of the present invention and a voltage change at each node according to the operation waveform.
6 is a schematic diagram illustrating a configuration of a sensing unit according to a second embodiment of the present invention.
7 is a diagram showing in detail the configuration of a sensing unit according to a second embodiment of the present invention.
8 is a diagram illustrating a signal waveform input to a sensing unit according to a second embodiment of the present invention and a voltage change at each node according to the signal waveform.
9 to 12 are diagrams for explaining a method of operating a sensing unit according to a second embodiment of the present invention.
13 is a diagram showing an operation process and an output voltage of a sensing unit according to a second embodiment of the present invention.

Advantages and features of the present specification, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the present embodiments are intended to complete the disclosure of the present specification, and common knowledge in the technical field to which the present specification pertains. It is provided to completely inform the scope of the invention to those who have, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and the present specification is not limited to the illustrated matters. The same reference numerals refer to the same elements throughout the specification. When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of the two parts is described as'on the top','on the top of the ~','the bottom of the','the next to the', etc.,'right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

First, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be a second component within the technical idea of the present specification.

The same reference numerals refer to substantially the same constituent elements throughout the specification.

Hereinafter, exemplary embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device includes a display panel 10 in which a plurality of pixels are formed, a scan driver 13, a data driver IC 12, a timing controller 11, and the like.

A plurality of data lines 14A, a plurality of sensing lines 14B, and a plurality of scan lines 15 are disposed on the display panel 10. Pixels PXL are disposed in an intersection area of the plurality of data lines 14A, the plurality of sensing lines 14B, and the plurality of scan lines 15. The pixels PXL each include an organic light emitting device (hereinafter, referred to as OLED) that emits light, and a driving transistor (hereinafter, referred to as a driving TFT) for driving the same.

The timing controller 11 receives a data enable signal DE or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like from the image processing unit and a data signal DATA. The timing controller 11 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 13 and a data timing control signal DDC for controlling the operation timing of the data driver IC 12 based on the driving signal. ) Is displayed.

The scan driver 13 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 11. The scan driver 13 outputs a scan signal consisting of a scan high voltage and a scan low voltage through the scan lines 15. The scan driver 13 may be formed in the form of an integrated circuit (IC) or may be formed on the display panel 10 in a gate-in panel method.

The data driver IC 12 converts the digital data signal DATA into an analog data voltage based on the gamma reference voltage in response to the data timing control signal DDC supplied from the timing controller 11.

An element such as an OLED or a driving TFT included in the pixels PXL may deteriorate in proportion to the driving time, and characteristics (eg, a threshold voltage) may be deteriorated. To compensate for this, the data driver IC 12 senses a characteristic of a device included in at least one of the pixels PXL and feeds back the sensed sensing data SD to the timing controller 11. The timing controller 11 may correct the data signal DATA to be written to the pixel P based on the sensing data SD fed back from the data driver IC 12. A circuit that senses a device included in a pixel may be implemented as a separate sensing circuit other than the data driver IC 12. However, hereinafter, the sensing circuit included in the data driver IC 12 will be described as an example.

2 is a diagram schematically showing the configuration of an external compensation circuit using a timing controller and a data driver IC according to an embodiment of the present invention.

Referring to FIG. 2, the timing controller 11 includes a compensation memory 28 in which sensing data SD for data compensation is stored, and a data signal DATA to be written in the pixel P based on the sensing data SD. It includes a compensation unit 26 to compensate for.

The timing controller 11 may control all operations for sensing driving according to a predetermined sensing process. That is, sensing driving may be performed in a state in which only the screen of the display device is turned off while the system power is applied, for example, in a standby mode, a sleep mode, a low power mode, or the like. However, it is not limited thereto.

The compensation unit 26 corrects the data signal DATA to be written to the pixel P based on the sensing data SD stored in the compensation memory 28 and then outputs the corrected data to the data drive IC 12.

The data driver IC 12 includes a voltage supply unit 20 for outputting a data voltage to be written to the pixel P and a sensing unit 24 for sensing characteristics of devices included in the pixel P.

The voltage supply unit 20 may output a display data voltage or a sensing data voltage through a data channel connected to the data line 14A. The voltage supply unit 20 may have a plurality of data channels. The voltage supply unit 20 includes a digital to analog converter (DAC) that converts a digital signal into an analog signal, and generates a display data voltage or a sensing data voltage.

The voltage supply unit 20 generates a display data voltage in response to a data timing control signal DDC provided by the timing controller 11 when driving the display. The voltage supply unit 20 supplies a display data voltage to the data line 14A. During display driving, the display data voltage supplied to the data line 14A is applied to the pixel P in synchronization with the turn-on timing of the display scan signal SCAN.

When sensing is driven, the voltage supply unit 20 generates a preset sensing data voltage. The voltage supply unit 20 supplies a sensing data voltage to the data line 14A. During sensing driving, the sensing data voltage supplied to the data line 14A is applied to the pixel P in synchronization with the turn-on timing of the sensing scan signal SCAN. The gate-source voltage of the driving TFT included in the pixel P is programmed by the sensing data voltage, and the driving current flowing through the driving TFT is determined according to the gate-source voltage of the driving TFT.

The sensing unit 24 may sense the display panel 10 through a sensing channel connected to the sensing line 14B. The sensing unit 24 may have a plurality of sensing channels. The sensing unit 24 senses a characteristic of a device included in the pixel P through the sensing line 14B. The sensing unit 24 may sense a sensing node defined between the drain electrode of the driving TFT included in the pixel P and the anode electrode of the OLED. The sensing unit 24 performs sensing driving under the control of the timing controller 11. The sensing unit 24 senses and samples a signal from the pixel P, converts the sampling result to an analog to digital converter (hereinafter, referred to as an ADC), and outputs it to the timing controller 11.

The sensing driving may be performed in a vertical blank period during display driving, in a power-on sequence period before display driving is started, or in a power-off sequence period after display driving is finished. However, the present invention is not limited thereto, and sensing driving may be performed in a vertical active period during display driving. The vertical blank period is a period in which input image data is not written, and is disposed between vertical active sections in which one frame of input image data is written. The power-on sequence period refers to a transient period from when the driving power is turned on until an input image is displayed. The power-off sequence period refers to a transient period from the end of the display of the input image until the driving power is turned off.

3 is a schematic diagram illustrating a configuration of a sensing unit according to a first embodiment of the present invention.

The sensing unit 24 may include an integrator 210, a sampling unit 220, a scaler 230, an analog-to-digital converter 240, and the like.

The integrator 210 integrates the sensing current IPXL input from the display panel 10 and outputs an integral value.

The sampling unit 220 outputs a sampling signal based on the integral value output from the integrator 210 during the sensing period.

The analog-to-digital converter 240 converts the sampling signal of the sensing current IPXL output from the sampling unit 220 into digital sensing data SD and outputs it. Here, the analog-to-digital converter 240 has an input voltage range determined. When the input of the analog-to-digital converter 240 is outside the predetermined input range, the output value may underflow to the lower limit of the input voltage range or overflow to the upper limit of the input voltage range. Accordingly, the scaler 230 is connected between the sampling unit 220 and the analog-to-digital converter 240.

The scaler 230 scales the voltage range of the sampling signal output from the sampling unit 220 according to the input voltage range of the analog-to-digital converter 240.

4 is a circuit diagram showing in detail the configuration of the sensing unit 24 according to the first embodiment of the present invention, and FIG. 5 is an operation waveform of the sensing unit of FIG. 4 and a voltage change at each node according to the operation waveform. It is a drawing.

Referring to FIG. 4, the sensing unit 24 receives a sensing current IPXL from the display panel 10 through a channel CH. The channel CH is connected to the integrator 210 through a system input/output line (SIO Line), and a sensing current IPXL input through the channel CH may be input to the integrator 210. Since the sensing line 14b (refer to FIG. 2) of the display panel 10 is connected to the channel CH, the driving reference voltage VPRER is applied to the system input/output line (SIO Line) connected to the channel CH when the display is driven. When sensing is driven, the system input/output line (SIO Line) should be connected to the integrator 210. Thus, between the channel CH and the system input/output line (SIO Line), the first switch SW1 operates to input the sensing current IPXL to the integrator 210 according to the system signal SIO applied during sensing driving. When driving the display, a second switch SW2 that operates to apply a driving reference voltage VPRER to the system input/output line (SIO Line) is connected.

The integrator 210 includes an amplifier (AMP) having an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. An integrating capacitor (CFB) is connected between the inverting input terminal (-) of the amplifier (AMP) and the output terminal, and a fourth switch (SW4) that is turned on and off by an initialization signal (INIT) is connected to both ends of the integrating capacitor (CFB). Are connected in parallel.

The integrator reference voltage VREF_CI is input to the non-inverting input terminal (+) of the amplifier (AMP).

The system input/output line (SIO Line) is connected to the inverting input terminal (-) of the amplifier (AMP). During sensing driving, the first switch SW1 connected to the system input/output line (SIO Line) is turned on and the sensing current IPXL is input to the inverting input terminal (-) of the amplifier (AMP). The amplifier (AMP) integrates and outputs the sensing current (IPXL) input during sensing driving. When the display is driven, the first switch SW1 is maintained in an off state, so that the connection between the inverting input terminal (-) of the amplifier AMP and the system input/output line (SIO Line) is disconnected. When the display is driven, the second switch SW2 is turned on instead of the first switch SW1 being turned off, so that the driving reference voltage VPRER is input to the system input/output line SIO Line.

The sampling unit 220 includes a third switch SW3 and a sampling capacitor CSAM that are turned on and off by the sampling signal SAM. The integral value output from the amplifier AMP is sampled by the sampling capacitor CSAM according to the on/off operation of the third switch SW3. One end of the sampling capacitor CSAM is connected to the amplifier output terminal CI_OUT and the other end is connected to the second reference voltage EVREF2.

The scaler 230 scales the voltage range of the sampling signal output from the sampling unit 220 according to the input voltage range of the analog-to-digital converter 240. To this end, the scaler 230 includes a plurality of switches and a plurality of capacitors, receives the first reference voltage EVREF1 and scales the voltage range of the sampling signal.

FIG. 5 is a waveform diagram for explaining the operation of the sensing unit 24 having the configuration of FIG. 4, and illustrates a case of sensing driving during a blank period (V-blank) between display driving periods (Active).

During the display driving period (Active), only the control signal (RPRE) of the second switch (SW2) is applied at the ON level, and the control signal of the first switch (SW1), the control signal (INIT) of the fourth switch, and the third switch are All of the control signals SAM are applied at an off level.

During the display driving period (Active), as the first switch SW1 is turned off, the connection between the system input/output line (SIO Line) and the integrator 210 is released. On the other hand, as the second switch SW2 is turned on, the driving reference voltage VPRER is applied to the system input/output line SIO Line. Since the fourth switch SW4, which is the initialization switch of the integrator 210, is maintained in the off state, the output terminal CI_OUT of the amplifier AMP is the integrator reference voltage VREF_CI equal to the voltage of the non-inverting input (+) of the amplifier AMP. ). The third switch SW3, which is a sampling switch of the sampling unit 220, is also maintained in an off state.

Sensing driving is performed during the blank period (V-blank). During sensing driving, the control signal of the first switch SW1 is maintained at the on level and the control signal RPRE of the second switch SW2 is maintained at the off level.

During sensing driving, the first switch SW1 connected to the system input/output line (SIO Line) is turned on and the sensing current IPXL is input to the inverting input terminal (-) of the amplifier (AMP). In order to drive the amplifier as an integrator during sensing driving, the voltage of the inverting input terminal (-) must rise to the integrator reference voltage (VREF_CI) equal to the voltage of the non-inverting input terminal (+). Accordingly, the voltage of the system input/output line (SIO Line) is set to the integrator reference voltage (VREF_CI).

The sensing driving period may include an initialization period Tini, a sensing period Tsen, and a sampling period Tsam.

In the initialization period Tini, the initialization signal INIT and the sampling signal SAM are applied at a turn-on level.

As the initialization signal INIT is applied at the turn-on level, the fourth switch SW4 is turned on. Due to the turn-on of the fourth switch SW4, which is an initialization switch, the amplifier AMP operates as a unit gain buffer having a gain of 1. In the initialization period Tini, the input terminals (+,-) of the amplifier AMP, the output terminals CI_OUT, and the system input/output line SIO Line are all initialized to the integrator reference voltage VREF_CI.

In the sensing period Tsen, the initialization signal INIT is applied at the off level, the sampling signal SAM is maintained at the turn-on level, and is switched to the off level when the sampling time elapses.

As the initialization signal INIT is applied at the off level, the fourth switch SW4 is turned off. As the fourth switch SW4, which is an initialization switch, is turned off, the amplifier AMP operates as a current integrator CI, and integrates the sensing current IPXL using the integrating capacitor CFB.

The potential difference between both ends of the integrating capacitor CFB by the sensing current (IPXL) flowing into the inverting input terminal (-) of the amplifier (AMP) during the sensing period (Tsen) increases as the sensing time elapses, that is, the accumulated sensing current (IPXL). It increases as is increased. However, due to the characteristics of the amplifier (AMP), the inverting input terminal (-) and the non-inverting input terminal (+) are shorted through a virtual ground, so that the potential difference between them is 0, so in the sensing period (Tsen), the inverting input terminal ( The potential of -) is maintained at the integrator reference voltage VREF_CI regardless of an increase in the potential difference of the integrating capacitor CFB. Instead, the potential of the output terminal CI_OUT of the amplifier AMP is lowered corresponding to the potential difference between both ends of the integrating capacitor CFB. With this principle, the sensing current IPXL input to the channel CH during the sensing period Tsen is output as an integral value, which is a voltage value, through the integrating capacitor CFB. The integral value output from the integrator 210 is stored in the sampling capacitor Csam via the third switch SW3 which is a sampling switch.

When the sampling switch SAM is turned off in the sampling period Tsam, the sampling signal stored in the sampling capacitor CSAM is input to the ADC 240 via the scaler 230. The sampling signal is converted into a digital sensing value SD in the ADC 240 and then transmitted to the timing controller 11.

The capacitance of the integrating capacitor CFB included in the current integrator 210 of the present invention is as small as a few hundredths of the parasitic capacitance existing in the sensing line SIO, and the current sensing method of the present invention is a senseable integral value. Since the time required to draw the sensing current (IPXL) up to the (Vsen) level is significantly shorter than that of the conventional voltage sensing method, there is an advantage that low-current high-speed sensing is possible.

6 to 11 are diagrams for explaining the configuration and operation of a sensing unit according to a second embodiment of the present invention. The second embodiment of the present invention eliminates the configuration of the scaler 230 of the first embodiment. Since the scaler 230 used to scale the sampling signal is composed of a plurality of capacitors, a large design area is required. In the second embodiment of the present invention, in order to reduce the design area required by the scaler, a sensing unit is constructed by adding a scaling function to the integrator circuit and the sampling unit circuit. In addition, according to the configuration change of the integrator circuit, the initialization period Tini during sensing driving may be shortened compared to the first embodiment.

6 is a schematic diagram illustrating a configuration of a sensing unit according to a second embodiment of the present invention.

The sensing unit 24 according to the second embodiment of the present invention may include an integrator/scaler 250, a sampling unit 260, an analog-to-digital converter 240, and the like.

The integrator/scaler 250 scales down the voltage of the system input/output line (SIO Line) to which the sensing current IPXL is input, and integrates and outputs only the change in voltage.

The sampling unit 260 outputs a sampling signal based on the integral value output from the integrator 210 during the sensing period. In the sensing unit 24 according to the second embodiment of the present invention, the sampling unit 260 may output a level of the sampling signal down. Since the sampling signal output from the sampling unit 260 has already been scaled down by the integrator/scaler 250 and the level down process has been completed by the sampling unit 260, the analog-to-digital converter 240 is immediately without an additional scaling process. Can be processed as input.

The analog-to-digital converter 240 converts the sampling signal of the sensing current IPXL output from the sampling unit 260 into digital sensing data SD and outputs it.

As described above, in the second embodiment of the present invention, it is possible to configure the sensing unit without adding a separate scaler circuit.

7 is a circuit diagram showing in detail the configuration of a sensing unit according to a second embodiment of the present invention, and FIG. 8 is a diagram showing a signal waveform input to the sensing unit of FIG. 7 and a voltage change at each node according to the signal waveform to be.

Referring to FIG. 7, the sensing unit 24 receives a sensing current IPXL from the display panel 10 through a channel CH. The channel CH is connected to the integrator/scaler 250 through a system input/output line (SIO Line), and a sensing current IPXL input through the channel CH may be input to the integrator/scaler 250. Since the sensing line 14b (refer to FIG. 2) of the display panel 10 is connected to the channel CH, the driving reference voltage VPRER is applied to the system input/output line (SIO Line) connected to the channel CH when the display is driven. When sensing is driven, the system input/output line (SIO Line) must be connected to the integrator (210 integrator/scaler 250). Accordingly, the system applied when sensing is driven between the channel (CH) and the system input/output line (SIO Line) A driving reference voltage (VPRER) is applied to the system input/output line (SIO Line) when driving the display and the first switch (SW1) that operates to input the sensing current (IPXL) to the integrator/scaler (250) according to the signal (SIO). The operating second switch SW2 is connected.

The integrator/scaler 250 includes an inverting input terminal (-), a non-inverting input terminal (+), and an amplifier (AMP) having an output terminal. Compared to the integrator 210 of the first embodiment, the integrator/scaler 250 according to the second embodiment of the present invention further includes a scaling capacitor CADD in the system input/output line (SIO Line), and the scaling capacitor CADD is The fifth switch (SW5) that connects the connected system input/output line (SIO Line) to the inverting input terminal (-) and the sixth switch (SW6) that connects the system input/output line (SIO Line) to the inverting input terminal (-) directly. ).

A system input/output line (SIO Line) in which one end is connected to the output terminal (CI_OUT) of the amplifier (AMP) and the other end is connected to the input terminal (-) between the inverting input terminal (-) of the amplifier (AMP) and the output terminal (CI_OUT). The integrating capacitor CFB connected to is connected.

The system input/output line (SIO Line) connected to the inverting input terminal (-) of the amplifier (AMP) has a scaling capacitor (CADD), one end connected to the inverting input terminal (-) and the other end connected to the integrating capacitor (CFB). Connected.

A fourth switch SW4, which is an initialization switch that interconnects one end of the scaling capacitor CADD and one end of the integration capacitor CFB, is connected so that the scaling capacitor CADD and the integration capacitor CFB can be connected in parallel.

A fifth switch SW5 operating on and off is connected between the scaling capacitor CADD and the inverting input terminal (-) of the amplifier AMP.

One end is connected to the system input/output line (SIO Line) to which the scaling capacitor (CADD) and the integrating capacitor (CFB) are connected, and the other end is connected between the inverting input terminal (-) and the fifth switch (SW5) to operate on-off. The switch SW6 is connected.

The integrator reference voltage VREF_CI is input to the non-inverting input terminal (+) of the amplifier (AMP).

The amplifier (AMP) integrates and outputs the sensing current (IPXL) input during sensing driving. When the display is driven, the first switch SW1 is maintained in an off state, so that the connection between the inverting input terminal (-) of the amplifier AMP and the system input/output line (SIO Line) is disconnected. When the display is driven, the second switch SW2 is turned on instead of the first switch SW1 being turned off, so that the driving reference voltage VPRER is input to the system input/output line SIO Line.

A method of operating the integrator 250 having such a configuration will be described later in more detail with reference to FIGS. 8 to 12.

The sampling unit 260 includes a third switch SW3 and a sampling capacitor CSAM that are turned on and off by the sampling signal SAM. The sampling unit 260 according to the second embodiment of the present invention sets the reference voltage of the sampling capacitor CSAM to the first reference voltage EVREF1 or the second reference voltage EVREF2 compared to the sampling unit 220 of the first embodiment. There is a difference connecting with ). The second reference voltage EVREF2 is set larger than the first reference voltage EVREF1. While the integral value of the amplifier (AMP) is stored in the sampling capacitor (CSAM), the second reference voltage (EVREF2) is connected, and the sampling value stored in the sampling capacitor (CSAM) is leveled down to the range that can be input to the ADC 240. For this purpose, the first reference voltage EVREF1 is connected. The second reference voltage EVREF2 may be set to about 6.5V, and the first reference voltage EVREF1 may be set to about 0.4V.

One end of the sampling capacitor CSAM is connected to the third switch SW3, and the other end is connected to the first reference voltage EVREF1 or the second reference voltage EVREF2. To this end, the sampling unit 260 connects the eighth switch SW8 to select the connection between the sampling capacitor CSAM and the first reference voltage EVREF1, and the sampling capacitor CSAM and the second reference voltage EVREF2. It includes a seventh switch (SW7) to select.

8 is a diagram illustrating a signal waveform input to the sensing unit of FIG. 7 and a voltage change at each node according to the signal waveform.

Referring to FIG. 8, the sensing driving period may include an initialization period (Tini), a sensing period (Tsen), and a sampling period (Tsam), and the sampling period (Tsam) is a first scale period (tscale1) and a second It can be divided by the scale period (tscale2).

The control signal RPRE of the second switch SW2 is applied at an ON level only during the initialization period Tini to turn on the second switch SW2, and is maintained at an off level for the remainder of the period.

The initialization signal INIT is applied to the on level in the initialization period Tini and then converted to the off level, and is applied to the on level again in the first scale period tscale1. Accordingly, the fourth switch SW4 is turned on during the initialization period Tini and the first scale period tscale1.

The control signal SIO of the first switch SW1 is applied at an on level during the initialization period Tini and the sensing period Tsen to turn on the first switch SW1, and then, is maintained at an off level.

The control signal of the fifth switch SW5 is applied at an on level during the initialization period Tini and the sensing period Tsen to turn on the fifth switch SW5, and thereafter, is maintained at the off level.

The control signal of the sixth switch SW6 is applied at an ON level only during the first scale period tscale1 to turn on the sixth switch SW6, and is maintained at an off level for the remainder of the period.

The sampling signal SAM is input at an ON level during the first scale period tscale1 among the initialization period Tini, the sensing period Tsen, and the sampling period Tsam to turn on the third switch SW3 and the second scale. During the period (tscale2), it is switched to the off level.

The control signal of the seventh switch SW7 is input at an ON level during the first scale period tscale1 among the initialization period Tini, the sensing period Tsen, and the sampling period Tsam, and in the second scale period tscale2. It switches to the off level.

The control signal of the eighth switch SW8 is applied at the ON level only during the second scale period tscale2 to turn on the eighth switch SW8, and is maintained at the OFF level for the remainder of the period.

Upon receiving such a driving signal, the sensing unit of FIG. 7 may perform an initialization operation, a sensing operation, and a sampling operation, and may perform a first scale operation and a second scale operation during the sampling operation.

Hereinafter, operations of the initialization period Tini, the sensing period Tsen, and the sampling period Tsam according to the second embodiment of the present invention will be described step by step with reference to FIGS. 9 to 11.

9 is a diagram illustrating an equivalent circuit of a sensing unit corresponding to an initialization period Tini, a signal waveform input to the sensing unit, and a voltage change at each node according to the signal waveform.

9, in the initialization period Tini, only the control signal of the sixth switch SW6 and the control signal of the eighth switch SW8 are applied at the off level, and the control signal RPRE of the second switch SW2 , The initialization signal INIT, the control signal SIO of the first switch SW1, the control signal of the fifth switch SW5, the sampling signal SAM, and the control signal of the seventh switch SW7 are all at turn-on levels. It is authorized.

In response to the control signal SIO of the first switch SW1 and the control signal RPRE of the second switch SW2 being input at a turn-on level, the first switch SW1 and the second switch SW2 are turned on.

As the first switch SW1 is turned on, the system input/output line SIO line and the integrator/scaler 250 are connected. As the second switch SW2 is turned on, the driving reference voltage VPRER is applied to the system input/output line SIO Line. Accordingly, the potential of the system input/output line (SIO Line) is set to the driving reference voltage (VPRER).

In response to the initialization signal INIT and the control signal of the fifth switch SW5 being input at the turn-on level, the fourth switch SW4 and the fifth switch SW5 are turned on.

As the fifth switch SW5 is turned on, the scaling capacitor CADD connected to the system input/output line SIO Line connected to the inverting input terminal (-) of the amplifier AMP is connected.

As the fourth switch SW4 is turned on, the integrating capacitor CFB and the scaling capacitor CADD are connected in parallel, and the inverting input terminal (-) of the amplifier AMP and the output terminal CI_OUT are connected. Since the potential of the inverting input terminal (-) of the amplifier (AMP) has the same potential as the integrator reference voltage (VREF_CI) supplied to the non-inverting input terminal (+), the input terminals (+,-) of the amplifier (AMP) Both the and output stages (CI_OUT) are initialized to the integrator reference voltage (VREF_CI).

One end of the integrating capacitor CFB and the scaling capacitor CADD connected in parallel is connected to the inverting input terminal (-) of the amplifier (AMP), and the other end is connected to the system input/output line (SIO Line). Since the driving reference voltage VPRER is supplied to the system input/output line (SIO Line), the potential of the system input/output line (SIO Line) is set to the driving reference voltage (VPRER). Accordingly, a voltage difference between the driving reference voltage VPRER and the integrator reference voltage VREF_CI is stored in the integrating capacitor CFB and the scaling capacitor CADD. For example, if the driving reference voltage VPRER is 1.5V and the integrator reference voltage VREF_CI is 4.5V, the difference, -Δ3V, is stored in the integrating capacitor CFB and the scaling capacitor CADD, respectively.

As both the sampling signal SAM and the control signal of the seventh switch SW7 are applied at turn-on levels, one end of the sampling capacitor Csam is connected to the output terminal CI_OUT of the amplifier and the other end is the second reference voltage. It is connected to (EVREF2). The second reference voltage EVREF2 may be set to about 6.5V.

By performing the above initialization operation, the potential of the system input/output line (SIO Line) is initialized to the driving reference voltage (VPRER), and the input terminals (+,-) and output terminals (CI_OUT) of the amplifier (AMP) are all integrator reference voltages. It is initialized to (VREF_CI). The voltage difference between the driving reference voltage VPRER and the integrator reference voltage VREF_CI is stored in the integrating capacitor CFB and the scaling capacitor CADD.

10 is a diagram illustrating an equivalent circuit of a sensing unit corresponding to a sensing period Tsen, a signal waveform input to the sensing unit, and a voltage change at each node according to the signal waveform.

Referring to FIG. 10, in the sensing period Tsen, the control signal RPRE and the initialization signal INIT of the second switch SW2 are applied at a turn-off level, and the control signal SIO of the first switch SW1 , The control signal of the fifth switch SW5, the sampling signal SAM, and the seventh switch SW7 are applied at a turn-on level. The control signal of the sixth switch SW6 and the control signal of the eighth switch SW8 are maintained at the off level. Switches for inputting the sensing current IPXL to the inverting input terminal (-) of the amplifier AMP through the system input/output line SIO Line are turned on in the sensing period Tsen by the above control signals.

In response to the control signal SIO of the first switch SW1 being input at the turn-on level and the control signal RPRE of the second switch SW2 at the turn-off level, the first switch SW1 and the second switch ( SW2) is turned off.

As the second switch SW2 is turned on and off, the driving reference voltage VPRER is disconnected. As the first switch SW1 is turned on, the sensing current IPXL input to the channel CH is applied to the system input/output line SIO Line.

In response to the initialization signal INIT being input at the off level and the control signal of the fifth switch SW5 at the turn-on level, the fourth switch SW4 is turned off and the fifth switch SW5 is turned on.

As the fourth switch SW4, which is an initialization switch, is turned off, the amplifier AMP operates as a current integrator CI. During the sensing period Tsen, the sensing current IPXL flowing into the system input/output line SIO is accumulated in the integrating capacitor CFB.

Due to the characteristics of the amplifier (AMP), the inverting input terminal (-) and the non-inverting input terminal (+) are shorted through the virtual ground, and the potential difference between them is 0. Therefore, the inverting input terminal (-) in the sensing period (Tsen) The potential of is maintained as the integrator reference voltage (VREF_CI) regardless of the increase in the potential difference of the integrating capacitor (CFB), and the voltage difference between the driving reference voltage (VPRER) stored in the scaling capacitor (CADD) and the integrator reference voltage (VREF_CI) is also maintained. . Instead, the potential of the output terminal CI_OUT of the amplifier AMP is lowered corresponding to the potential difference between both ends of the integrating capacitor CFB. Since the voltage difference between the driving reference voltage (VPRER) of the system input/output line (SIO Line) and the integrator reference voltage (VREF_CI) of the output terminal (CI_OUT) of the amplifier (AMP) is previously stored in the integrating capacitor (CFB), the sensing current ( IPXL) A change in the potential of the integrating capacitor CFB due to the inflow may be directly reflected on the potential of the output terminal CI_OUT of the amplifier AMP.

For example, the condition set in the initialization period (Tini), the reference voltage (VPRER) is 1.5V, the integrator reference voltage (VREF_CI) is 4.5V, and the difference between the integrating capacitor (CFB) and the scaling capacitor (CADD) is -△3V. In each of the stored states, the sensing current IPXL may flow into the sensing period Tsen. When the sensing current (IPXL) flows in 2V and the voltage of the integrating capacitor (CFB) fluctuates from -△3V to -△1V, the one end of the integrating capacitor (CFB) is fixed at the reference voltage (VPRER) of 1.5V. The potential of the other terminal connected to the output terminal (CI_OUT) of) changes from 4.5V to 2.5V. Accordingly, the potential of the output terminal CI_OUT of the amplifier AMP is lowered by 2V due to the input of the sensing current IPXL.

The integral value output from the output terminal CI_OUT of the amplifier AMP is stored in the sampling capacitor Csam through the third switch SW3 which is a sampling switch.

FIG. 11 is a diagram showing an equivalent circuit of a sensing unit corresponding to a first scaling period tscale1 of the sampling period Tsam, a signal waveform input to the sensing unit, and voltage changes at each node according to the signal waveform.

Referring to FIG. 11, in the first scaling period tscale1, the control signal SIO of the first switch SW1, the control signal RPRE of the second switch SW2, and the control signal of the fifth switch SW5 are It is applied at the turn-off level. The initialization signal INIT and the control signal of the sixth switch SW6 are applied at a turn-on level. The sampling signal SAM and the seventh switch SW7 are applied at the turn-on level, and the control signal of the eighth switch SW8 is maintained at the off level. Due to the above control signals, in the first scaling period tscale1, the integrating capacitor CFB and the scaling capacitor CADD are connected in parallel, and the connection with the system input/output line SIO line is disconnected to become a floating state.

The first switch SW1 and the second switch SW2 are turned off in response to the input of the control signal SIO of the first switch SW1 and the control signal RPRE of the second switch SW2 at the turn-off level. do. In addition, in response to the control signal of the fifth switch SW5 being applied at the turn-off level and the control signal of the sixth switch SW6 being applied at the turn-on level, the fifth switch SW5 is turned off and the sixth switch SW6 ) Is turned on. Accordingly, the system input/output line (SIO Line) is connected to the inverting input terminal (-) of the amplifier (AMP) through the sixth switch (SW6). Therefore, the potential of the system input/output line (SIO Line) varies from the driving reference voltage VPRER to the voltage of the inverting input terminal (-) of the amplifier AMP, that is, the integrator reference voltage VREF_CI.

In response to the initialization signal INIT being input at the turn-on level, the fourth switch SW4 is turned on. As the fourth switch SW4 is turned on, the integrating capacitor CFB and the scaling capacitor CADD are connected in parallel. The integrating capacitor CFB and the scaling capacitor CADD connected in parallel have one end connected to the inverting input terminal (-) of the amplifier AMP, and the other end connected to the output terminal CI_OUT of the amplifier AMP. That is, the integrating capacitor CFB and the scaling capacitor CADD connected in parallel are connected between the inverting input terminal (-) of the amplifier AMP and the output terminal CI_OUT.

One end of the integrating capacitor (CFB) and scaling capacitor (CADD) connected in parallel is set as the integrator reference voltage (VREF_CI), and the other end is connected to the output terminal (CI_OUT) of the amplifier (AMP). The integrating capacitor CFB and the scaling capacitor CADD charge-share the stored charge according to their respective capacitances, and the increased voltage is reflected to the output terminal CI_OUT of the amplifier AMP. The capacitance of the integrating capacitor CFB is set to about 1pF, and the scaling capacitor CADD is set to about 3pF. The voltage at one end of the integrating capacitor CFB and the scaling capacitor CADD has risen from 1.5V to 4.5V, and the voltage is charge-sharing, so that the amount of charge in the integrating capacitor CFB goes from △1V to △2.5V, and the scaling capacitor ( The charge amount of CADD) is changed from △3V to △2.5V, and the potential of the output terminal (CI_OUT) of the amplifier (AMP) rises from 2.5V to 7V. As a result, the amount of charge in the integrating capacitor CFB varies from Δ1V to Δ2.5V, so the 2V increased due to the sensing current IPXL is scaled down and measured as a 0.5V change.

The integral value 7V output from the output terminal CI_OUT of the amplifier AMP is stored in the sampling capacitor Csam via the third switch SW3 which is a sampling switch. Since the seventh switch SW7 is applied at the turn-on level, and the control signal of the eighth switch SW8 is maintained at the off level, the second reference voltage EVREF2 connected to the seventh switch SW7 is applied to the sampling capacitor Csam. ) Is connected. Since the second reference voltage EVREF2 is set to 6.5V, an integral value of 7V output from the output terminal CI_OUT of the amplifier AMP is sampled as 0.5V in the sampling capacitor Csam.

FIG. 12 is a diagram illustrating an equivalent circuit of a sensing unit corresponding to a second scaling period tscale during a sampling period Tsam, a signal waveform input to the sensing unit, and a voltage change at each node according to the signal waveform.

Referring to FIG. 12, in the second scaling period tscale2, only the control signal of the eighth switch SW8 is input as a turn-on level, and the off-level control signal is input to the remaining first to seventh switches SW1 to SW7. .

As the sampling signal SAM is input at the off level, the third switch SW3 is turned off, and as the control signal of the eighth switch SW8 is input at the turn-on level, the eighth switch SW8 is in the sampling capacitor Csam. The first reference voltage EVREF1 connected to is connected. The first reference voltage EVREF1 is set to 0.4V. Accordingly, the final output sampling value is output as 0.9V obtained by adding 0.5V stored in the sampling capacitor Csam and 0.4V of the first reference voltage EVREF1.

As described above, in the second embodiment of the present invention, the potential of the system input/output line (SIO Line) is initialized to the driving reference voltage (VPRER) in the initialization period (Tini), and the integrating capacitor (CFB) and the scaling capacitor (CADD) are After the voltage difference between the driving reference voltage VPRER and the integrator reference voltage VREF_CI is stored, the sensing current IPXL is sensed. Therefore, since it is not necessary to raise the potential of the input/output line (SIO Line) to the integrator reference voltage (VREF_CI), the initialization time can be significantly shortened.

Thereafter, the sensing current (IPXL) flowing into the integrating capacitor (CFB) is integrated, and when the sensing result is output, the parallel-connected integrating capacitor (CFB) and the scaling capacitor (CADD) calculate the sensing result and the integrator reference voltage (VREF_CI). A scale-down effect can be obtained by reflecting the increased voltage to the output terminal CI_OUT of the amplifier AMP through charge sharing. Thereafter, the sampling capacitor Csam may output the lowered voltage level of the sampling signal by changing the reference voltage. As a result, even if a separate scaler circuit is not added, a sampling signal in a range that can be input to the ADC 240 can be output.

Meanwhile, the voltage numerical information described in the detailed description is only exemplified to aid understanding of the present invention, and the numerical value of the input/output voltage may be variously changed according to the characteristics of the display device to which the circuit of the present invention is applied. It is not limited to

13 is a waveform diagram showing an operation process of a sensing unit and an output voltage according to the second embodiment of the present invention, illustrating a case of sensing driving during a blank period (V-blank) between display driving periods (Active).

During the display driving period (Active), only the control signal (RPRE) of the second switch (SW2) is applied at the ON level, and the control signal of the first switch (SW1), the control signal (INIT) of the fourth switch, and the third switch are All of the control signals SAM are applied at an off level.

During the display driving period (Active), as the first switch SW1 is turned off, the connection between the system input/output line (SIO Line) and the integrator 210 is released. On the other hand, as the second switch SW2 is turned on, the driving reference voltage VPRER is applied to the system input/output line SIO Line. Since the fourth switch SW4, which is the initialization switch of the integrator 210, is maintained in the off state, the output terminal CI_OUT of the amplifier AMP is the integrator reference voltage VREF_CI equal to the voltage of the non-inverting input (+) of the amplifier AMP. ). The third switch SW3, which is a sampling switch of the sampling unit 220, is also maintained in an off state.

Sensing driving is performed during the blank period (V-blank). The sensing driving period may include an initialization period Tini, a sensing period Tsen, and a sampling period Tsam.

The sensing unit according to the second embodiment of the present invention applies an initialization signal INIT, a sampling signal SAM, and a control signal RPRE of the second switch SW2 at a turn-on level during the initialization period Tini. During the initialization period (Tini) and sensing period (Tsen), the first switch (SW1) connected to the system input/output line (SIO Line) is turned on, and the sensing current (IPXL) is input to the inverting input terminal (-) of the amplifier (AMP). do. In addition, as the second switch SW2 is also turned on, the system input/output line SIO line is maintained at the driving reference voltage VPRER. As described above, unlike the first embodiment, since it is not necessary to increase the potential of the system input/output line (SIO Line) to the integrator reference voltage (VREF_CI), the sensing unit according to the second embodiment is required for the initialization period (Tini). It is possible to significantly shorten the time required.

In the sensing period Tsen, the initialization signal INIT and the control signal RPRE of the second switch SW2 are applied at a turn-off level. As the initialization signal INIT is applied at the off level, the fourth switch SW4 is turned off, so that the amplifier AMP operates as the current integrator CI. Accordingly, the sensing current (IPXL) input to the system input/output line (SIO Line) is integrated and output. Accordingly, the potential of the output terminal VI_OUT of the amplifier AMP gradually decreases as the time in which the sensing current IPXL flows elapses.

In the sampling period Tsam, a potential change, that is, an integral value, of the output terminal VI_OUT of the amplifier AMP is sampled and output.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

10: display panel 11: timing control unit
12: data driver IC 13: scan driver
20: voltage supply unit 24: sensing unit
26: compensation unit 28: compensation memory
210: integrator 220, 260: sampling unit
230: scaler 240: ADC
250: integrator/scaler

Claims (12)

A display panel including pixels;
A sensing current is supplied from the pixels through a system input line connecting a sensing channel and a first input terminal, a reference voltage is supplied through a reference voltage line connected to a second input terminal, and the system is connected to the system input line. An integrator including a scaling capacitor for storing a potential difference between a potential of an input line and the reference voltage;
A sampling unit that samples the output voltage of the integrator; And
An analog to digital converter (ADC) converting the voltage received from the sampling unit into a digital sensing value and outputting the converted voltage;
Display device comprising a. The method of claim 1,
The scaling capacitor has one end connected to the first input terminal and the other end connected to the sensing channel. The method of claim 1,
The display device further comprises a switch connected between the scaling capacitor and the first input terminal. The method of claim 2,
And a first switch connected between the sensing channel and the scaling capacitor. The method of claim 4,
And a second switch for applying or releasing a system reference voltage to the system input line. The method of claim 1,
The integrator is
An amplifier (AMP) including the first input terminal, the second input terminal, and an output terminal outputting the output voltage;
An integrating capacitor connected between the first input terminal and the output terminal of the amplifier (AMP) and connected in parallel with the scaling capacitor; And
A reset switch connected between one end of the integrating capacitor and one end of the scaling capacitor;
Display device comprising a. The method of claim 6,
And the scaling capacitor has a larger capacitance than the integrating capacitor. The method according to claim 1 or 6,
The sampling unit,
A sampling capacitor for storing an output voltage output from the integrator; And
A sampling switch connected between the integrator and the sampling capacitor,
The sampling capacitor is a display device to which at least two or more different reference voltages are selectively connected. The method of claim 8,
The sampling capacitor outputs an output voltage output from the integrator according to the reference voltage in a voltage range inputtable to the analog-to-digital converter. The method of claim 9,
And at least one switch selectively connecting the at least two or more different reference voltages to the sampling capacitor. An amplifier (AMP) including a first input terminal, a second input terminal, and an output terminal;
A scaling capacitor connected to a system input line connecting the sensing channel and the first input terminal;
An integrating capacitor connected between the first input terminal and the output terminal of the amplifier (AMP) and connected in parallel with the scaling capacitor;
A reset switch connected between one end of the integrating capacitor and one end of the scaling capacitor;
Sensing circuit comprising a. The method of claim 11,
A sampling switch connected to the output terminal;
A sampling capacitor for storing the output voltage of the amplifier supplied through the sampling switch; And
A switch selectively connecting at least two reference voltages having different sizes to the sampling capacitor;
Sensing circuit comprising a.

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