KR20210034461A - Semiconductor apparatus - Google Patents

Abstract

A semiconductor device according to an exemplary embodiment of the present invention comprises: a system substrate; a semiconductor package mounted on the system substrate and having a first length in a horizontal direction; a conductive label, as a flexible conductive label on the semiconductor package, including a first adhesion layer in contact with the semiconductor package, a conductive layer attached to the semiconductor package by the first adhesion layer and having a second length greater than the first length in a horizontal direction; and a second adhesion layer in contact with a partial surface of the conductive layer and not overlapped with the semiconductor package in a vertical direction; a thermal interface material (TIM) existing on the conductive layer to be overlapped with the semiconductor package in a vertical direction; and a cover including a first cover portion overlapped with the semiconductor package in a vertical direction and in contact with the TIM, and a second cover portion to which the conductive layer is attached by the second adhesion layer. The present invention can rapidly radiate the heat, generated by the semiconductor package, to the outside.

Description

Semiconductor device {SEMICONDUCTOR APPARATUS}

The technical idea of the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a semiconductor package.

The semiconductor package may generate a lot of heat due to its high performance and implementation of various functions. Accordingly, the heat dissipation performance of a semiconductor device including a semiconductor package is essential to secure operation stability and product reliability of a semiconductor chip in the semiconductor package. Accordingly, studies on a structure of a semiconductor device capable of efficiently discharging heat generated from a semiconductor package to the outside within a limited space provided by a cover of the semiconductor device are actively conducted.

One of the problems to be solved by the technical idea of the present disclosure is to provide a semiconductor device capable of rapidly discharging heat generated from a semiconductor package to the outside.

One of the problems to be solved by the technical idea of the present disclosure is to provide a semiconductor device capable of suppressing the occurrence of a short defect.

In order to achieve the above object, as an exemplary embodiment of the present disclosure, a system substrate; A semiconductor package mounted on the system substrate and having a first length in a horizontal direction; A flexible conductive label on the semiconductor package, comprising: a first adhesive layer abutting on the semiconductor package; A conductive layer attached to the semiconductor package by the first adhesive layer and having a second length greater than the first length in a horizontal direction; And a second adhesive layer contacting a partial surface of the conductive layer not overlapping the semiconductor package in a vertical direction; A thermal interface material (TIM) on the conductive layer to overlap the semiconductor package in a vertical direction; And a first cover portion overlapping the semiconductor package in a vertical direction and contacting the thermally conductive interface material. And a second cover portion to which the conductive layer is attached by the second adhesive layer.

In an exemplary embodiment of the present disclosure, a system substrate; A semiconductor package mounted on the system substrate and having a first length in a horizontal direction; A cover exposing an upper surface of the semiconductor package and surrounding a side surface of the semiconductor package; And a conductive label connecting the semiconductor package and the cover, the first adhesive layer contacting the semiconductor package. And a conductive layer on the first adhesive layer and having a second length greater than the first length in a horizontal direction.

In an exemplary embodiment of the present disclosure, a first system substrate; A second system substrate spaced apart from the first system substrate in a vertical direction; A flexible substrate connecting the first system substrate and the second system substrate; A cover surrounding the first system substrate, the second system substrate, and the flexible substrate; A first semiconductor package mounted on the first system substrate and having a first length in a horizontal direction; A second semiconductor package mounted on the second system substrate and having a second length in a horizontal direction; A first conductive label between the first semiconductor package and the cover, the first adhesive layer contacting the first semiconductor package; A first conductive layer on the first adhesive layer and having a third length greater than the first length in a horizontal direction; And a second adhesive layer abutting the cover on the first conductive layer and configured to attach the first conductive layer to the inner surface of the cover; And a second conductive label between the second semiconductor package and the cover, the third adhesive layer contacting the second semiconductor package. A second conductive layer on the third adhesive layer and having a fourth length greater than the second length in a horizontal direction; And a fourth adhesive layer configured to abut the cover on the second conductive layer and attach the second conductive layer to the inner surface of the cover. .

The semiconductor device according to the technical idea of the present disclosure may include a conductive label interposed between the semiconductor package and the cover, so that heat generated from the semiconductor package can be quickly released to the outside.

A semiconductor device according to the technical idea of the present disclosure may include a conductive label on which an insulating layer is formed, so that occurrence of a short defect can be suppressed.

1 is a cross-sectional view of a first conductive label according to an exemplary embodiment of the present disclosure.
2 is a cross-sectional view of a second conductive label according to an exemplary embodiment of the present disclosure.
3 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
4 is a cross-sectional view of a conductive layer of a semiconductor device according to an exemplary embodiment of the present disclosure taken along line IV-IV' of FIG. 3.
5 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
6 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
7 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
8 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
9 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
10 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
11 is a plan view of portion A of the semiconductor device of FIG. 10 according to an exemplary embodiment of the present disclosure.
12 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
13 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
14 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
15 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.
16 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a first conductive label 100a according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1, a first conductive label 100a according to an exemplary embodiment of the present disclosure may include a first adhesive layer 110 and a conductive layer 120.

In an exemplary embodiment, the first conductive label 100a may be a flexible label configured to transfer heat generated from the semiconductor package (FIGS. 3 and 20) to the cover (FIGS. 3 and 30 ). In addition, the first conductive label 100a may be a label having adhesive properties. For example, the first conductive label 100a is attached to the upper surface of the semiconductor package 20 and the inner surface of the cover 30, and has a plate shape configured to transfer heat generated from the semiconductor package 20 to the cover 30 Can be

In an exemplary embodiment, the length (ie, thickness, T1) in the vertical direction of the first conductive label 100a may have a value significantly smaller than the length L1 in the horizontal direction of the first conductive label 100a. For example, the length T1 in the vertical direction of the first conductive label 100a may be about 10 to about 100000 times smaller than the length L1 in the horizontal direction. As described above, since the length T1 in the vertical direction of the first conductive label 100a may have a value significantly smaller than the length L1 in the horizontal direction, the first conductive label 100a may have flexibility. . In other words, the first conductive label 100a may be bent.

In an exemplary embodiment, the length T1 in the vertical direction of the first conductive label 100a may be about 0.10 millimeters (mm) to 0.50 millimeters. More specifically, the length T1 in the vertical direction of the first conductive label 100a may be about 0.20 millimeters to about 0.35 millimeters. However, the present invention is not limited thereto, and the length T1 of the first conductive label 100a in the vertical direction may have various values depending on the size of the semiconductor device (FIGS. 3 and 1) including the semiconductor package 20.

The first adhesive layer 110 of the first conductive label 100a may be configured to attach the conductive layer 120 on the semiconductor package 20. The first adhesive layer 110 may be a non-conductive film (NCF). For example, the first adhesive layer 110 may be a film made of an insulating polymer. In addition, the first adhesive layer 110 may be a film having adhesive properties on its own. For example, the first adhesive layer 110 may be a double-sided adhesive film.

The conductive layer 120 of the first conductive label 100a is on the first adhesive layer 110 and may be configured to transfer heat generated from the semiconductor package 20 to the cover 30. The thickness of the conductive layer 120 may be greater than the thickness of the first adhesive layer 110.

The conductive layer 120 may include a material having excellent thermal conductivity. In an exemplary embodiment, the conductive layer 120 may include a metal material having excellent thermal conductivity. For example, the conductive layer 120 may include a metal material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), nickel (Ni), and the like.

In an exemplary embodiment, the conductive layer 120 may include a carbon-based material having excellent thermal conductivity. For example, the conductive layer 120 may include graphite, diamond, carbon fiber, or the like. In addition, the conductive layer 120 may include a polymer-based material having excellent thermal conductivity. However, the conductive layer 120 is not limited to the above-described materials, and may include a combination of the above materials or other materials not shown.

2 is a cross-sectional view of a second conductive label 100b according to an exemplary embodiment of the present disclosure.

2, the second conductive label 100b according to an exemplary embodiment of the present disclosure includes a first adhesive layer 110, a conductive layer 120, a second adhesive layer 130, and an insulating layer ( 140). For example, the second conductive label 100b may have a structure in which a first adhesive layer 110, a conductive layer 120, a second adhesive layer 130, and an insulating layer 140 are sequentially stacked. Since the technical concept of the first adhesive layer 110 and the conductive layer 120 of the second conductive label 100b is substantially the same as that described in the first conductive label 100a, detailed information will be omitted.

The second conductive label 100a may be a label having flexibility configured to transfer heat generated from the semiconductor package 20 to the cover 30. In addition, the second conductive label 100a may be a label having adhesive properties.

In an exemplary embodiment, the length (ie, thickness, T2) in the vertical direction of the second conductive label 100b may have a value significantly smaller than the length L2 in the horizontal direction of the second conductive label 100b. For example, the length T2 in the vertical direction of the second conductive label 100b may be about 10 to about 100000 times smaller than the length L2 in the horizontal direction. Since the length T2 in the vertical direction of the second conductive label 100b may have a value significantly smaller than the length L2 in the horizontal direction, the second conductive label 100b may have flexibility. In other words, the second conductive label 100b may be bent.

In an exemplary embodiment, the length T2 in the vertical direction of the second conductive label 100b may be about 0.10 millimeters to about 3.00 millimeters. More specifically, the length T2 in the vertical direction of the second conductive label 100b may be about 0.20 millimeters to about 0.50 millimeters. However, the present invention is not limited thereto, and the length T2 in the vertical direction of the second conductive label 100b may be formed in various values depending on the size of the semiconductor device (Figs. 3 and 1) including the semiconductor package (Figs. 3 and 20). I can.

In an exemplary embodiment, the second adhesive layer 130 of the second conductive label 100b may be configured to attach the insulating layer 140 onto the conductive layer 120. The second adhesive layer 130 may be a non-conductive film. For example, the second adhesive layer 130 may be a film made of an insulating polymer. In addition, the second adhesive layer 130 may be a film having adhesive properties on its own. For example, the second adhesive layer 130 may be a double-sided adhesive film. In addition, the second adhesive layer 130 may include a material substantially the same as the material of the first adhesive layer 110.

In an exemplary embodiment, the insulating layer 140 of the second conductive label 100b may be configured to prevent direct contact between the conductive layer 120 and the system substrate (FIGS. 3 and 10 ). That is, the insulating layer 140 of the second conductive label 100b may electrically insulate the conductive layer 120 from the system substrate 10. In other words, the insulating layer 140 may be a layer for suppressing the occurrence of a short defect by preventing contact between the conductive layer 120 and the system substrate 10.

Insulation layer 140 is, for example, epoxy resin, polybenzobisoxazole (polybenzobisoxazole; PBO), benzocyclobutene (benzocyclobutene, BCB), polyimide (polymide), and at least any of a polyimide derivative (polymide derivative) It may contain one insulating material. However, the present invention is not limited to the above, and the insulating layer 140 may include various insulating materials.

Unlike shown in FIG. 2, the second conductive label 100b includes the first adhesive layer 110, the conductive layer 120, and the second adhesive layer 130, but does not include the insulating layer 140. May not. For example, the second conductive label 100b includes a first adhesive layer 110 attached to both sides of the conductive layer 120, respectively, in order to interpose the conductive layer 120 between the first configuration and the second configuration. The second adhesive layer 130 may be included and the insulating layer 140 may not be included.

Hereinafter, semiconductor devices capable of rapidly discharging heat generated from a semiconductor package to the outside by using a conductive label having substantially the same or similar structure as the first and second conductive labels 100a and 100b described above. It will be described in more detail.

3 is a cross-sectional view of a semiconductor device 1 according to an exemplary embodiment of the present disclosure. The semiconductor device 1 according to the exemplary embodiment of the present disclosure includes a system substrate 10, a semiconductor package 20, a cover 30, a conductive label 100, and a thermal interface material (TIM). 150).

The system substrate 10 may be a substrate for connecting the semiconductor package 20 to an external device. The system substrate 10 may include a substrate pad 101 in contact with the package connection terminal 250 of the semiconductor package 20. In an exemplary embodiment, the system substrate 10 may be a single layer PCB including the substrate pad 101 on only one side. However, the present invention is not limited thereto, and the system substrate 10 may be a double layer printed circuit board including the substrate pads 101 on both sides. The system substrate 10 is not limited to the structure and material of the printed circuit board, and may include various types of substrates such as, for example, a ceramic substrate.

The semiconductor package 20 may include a semiconductor chip 200 mounted on the system substrate 10 and connected to the substrate pad 101 of the system substrate 10. In an exemplary embodiment, the semiconductor package 20 may include a semiconductor chip 200, a molding layer 230, a wiring structure 240, and a package connection terminal 250. The semiconductor package 20 may have a first length P1 in a horizontal direction (ie, an X direction). The horizontal direction may be defined as a direction substantially parallel to a direction in which the upper surface of the semiconductor chip 200 extends.

In FIG. 2, the semiconductor package 20 is illustrated as including one semiconductor chip 200, but the semiconductor package 20 may include two or more semiconductor chips 200. The semiconductor chips 200 included in the semiconductor package 20 may be of the same type or may be different types of semiconductor chips. In an exemplary embodiment, the semiconductor package 20 may be a System In Package (SIP) in which different types of semiconductor chips 200 are electrically connected to each other to operate as a single system.

The semiconductor chip 200 may include a semiconductor device layer (not shown), and the semiconductor device layer may be formed under the semiconductor chip 200. A plurality of individual devices of various types may be formed in the semiconductor device layer. In an exemplary embodiment, the plurality of individual devices are various microelectronic devices, for example, a CMOS transistor (complementary metal-insulator-semiconductor transistor), a metal-oxide-semiconductor filed effect transistor (MOSFET), and a system LSI. (large scale integration), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, and a passive device.

The semiconductor chip 200 may include a memory semiconductor chip. The memory semiconductor chip may include, for example, a volatile memory semiconductor chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), and may include phase-change random access memory (PRAM), magneto-resistive memory (MRAM), etc. Random Access Memory), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

Also, the semiconductor chip 200 may include a logic semiconductor chip. The logic semiconductor chip may include, for example, a logic semiconductor chip such as a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

In an exemplary embodiment, the semiconductor chip 200 may include silicon (Si). However, the present invention is not limited thereto, and the semiconductor chip 200 includes a semiconductor element such as germanium (Ge, germanium), or silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). It may also contain the same compound semiconductor.

In an exemplary embodiment, the semiconductor chip 200 may include a chip pad 210. The chip pad 210 may be electrically connected to a plurality of individual devices of various types described above.

In an exemplary embodiment, the semiconductor chip 200 may include a passivation layer 220 that surrounds a side surface of the chip pad 210 and exposes one surface of the chip pad 210. The passivation layer 220 may include an insulating material. Further, the passivation layer 220 may be about 2 micrometers to about 100 micrometers thick. More specifically, the passivation layer 220 may be about 3 micrometers to 50 micrometers thick. However, the present invention is not limited thereto, and the passivation layer 220 may have various thickness values.

The molding layer 230 may wrap at least a portion of the side surface of the semiconductor chip 200 on the wiring structure 240. In an exemplary embodiment, the molding layer 230 may surround both the top and side surfaces of the semiconductor chip 200. However, the present invention is not limited thereto, and as will be described later, the molding layer 230 covers the side surface of the semiconductor chip 200, but the upper surface of the semiconductor chip 200 may be exposed.

In an exemplary embodiment, the molding layer 230 may include an epoxy molding compound (EMC). However, the present invention is not limited thereto, and the molding layer 230 may include various insulating materials such as an epoxy-based material, a thermosetting material, a thermoplastic material, and a UV treatment material.

In an exemplary embodiment, the wiring structure 240 may be a structure for electrically connecting the semiconductor chip 200 to the package connection terminal 250. For example, the wiring structure 240 may be a redistribution structure including a redistribution pattern and an insulating material surrounding the redistribution pattern. However, the present invention is not limited thereto, and the wiring structure 240 may be a printed circuit board configured to electrically connect the semiconductor chip 200 and the package connection terminal 250.

The semiconductor package 20 of the present disclosure is not limited to the above-described structure, and may include semiconductor packages having various structures. For example, as shown in FIG. 3, the semiconductor package 20 may be a fan-out wafer level package (FOWLP), but is not limited thereto, and a fan-in wafer level package ( It may also be a Fan-In Wafer Level Package, FIWLP). In addition, the semiconductor package 20 may be a panel level package (PLP).

The conductive label 100 may be attached to both the upper surface of the semiconductor package 20 and the inner surface of the cover 30. More specifically, despite the difference in height between the upper surface of the semiconductor package 20 and the inner surface of the cover 30, the conductive label 100 is the upper surface and the cover of the semiconductor package 20 due to the flexibility of the conductive label 100 It can be attached to the inner surface of (30).

The conductive label 100 may include a first adhesive layer 110, a conductive layer 120, and a second adhesive layer 130. The first adhesive layer 110 may contact the upper surface of the semiconductor package 20. More specifically, the first adhesive layer 110 may be interposed between the semiconductor package 20 and the conductive layer 120. The first adhesive layer 110 may be configured to attach a portion of the conductive layer 120 to the upper surface of the semiconductor package 20.

The conductive layer 120 may be configured to transfer heat generated from the semiconductor package 20 to the cover 30. In an exemplary embodiment, the conductive layer 120 may have a plate shape in which the length in the vertical direction (Z direction) is considerably smaller than the length in the horizontal direction (X direction). Due to the above structure of the conductive layer 120, the conductive layer 120 can be flexible. In addition, the length C1 of the conductive layer 120 in the horizontal direction (X direction) may be greater than the length P1 of the semiconductor package 20 in the horizontal direction (X direction). Accordingly, a part of the conductive layer 120 may be on the top of the semiconductor package 20, and a part of the conductive layer 120 may be on the bottom of the cover 30.

The second adhesive layer 130 may contact the inner surface of the cover 30. More specifically, the second adhesive layer 130 may be interposed between the cover 30 and the conductive layer 120. The second adhesive layer 130 may be configured to attach a portion of the conductive layer 120 to the inner surface of the cover 30.

In an exemplary embodiment, the conductive layer 120 may include a first conductive portion 120a, a second conductive portion 120b, and a third conductive portion 120c. The first conductive part 120a may be a part of the conductive layer 120 overlapping the semiconductor package 20 in a vertical direction and interposed between the first adhesive layer 110 and the thermally conductive interface material 150. . The first conductive portion 120a may be configured to transfer heat generated from the semiconductor package 20 to the lower portion of the thermally conductive interface material 150.

The second conductive portion 120b may be a portion of the conductive layer 120 that is bent upward in the first conductive portion 120a and surrounds the side surface of the thermally conductive interface material 150. The second conductive portion 120b may be configured to transfer heat generated from the semiconductor package 20 to the side of the thermally conductive interface material 150.

The third conductive part 120c may be a part of the conductive layer 120 that is laterally bent at the second conductive part 120b and attached to the inner surface of the cover 30 by the second adhesive layer 130. . In addition, the third conductive portion 120c may not overlap the semiconductor package 20 in a vertical direction. The third conductive portion 120c may be configured to transfer heat generated from the semiconductor package 20 to a portion of the cover 30 that does not overlap the semiconductor package 20 in a vertical direction.

The thermally conductive interface material 150 may be interposed between the semiconductor package 20 and the cover 30, and may be configured to transfer heat generated from the semiconductor package 20 to the cover 30.

In an exemplary embodiment, the thermally conductive interface material 150 may be on the conductive layer 120 to overlap the semiconductor package 20 in a vertical direction. More specifically, the thermally conductive interface material 150 may be interposed between the cover 30 and the first conductive portion 120a. In addition, the side and bottom surfaces of the thermally conductive interface material 150 may be surrounded by the first conductive portion 120a and the second conductive portion 120b, and the upper surface of the thermally conductive interface material 150 is a cover 30. Can be surrounded by

In an exemplary embodiment, the thermally conductive interface material 150 is a mineral oil, a grease, a gap filler putty, a phase change gel, and a phase change material pad. change material pads) or particle filled epoxy. However, the present invention is not limited thereto, and the thermally conductive interface material 150 may include various materials having excellent thermal conductivity.

The cover 30 may be configured to cover the semiconductor package 20 in order to protect the semiconductor package 20 from external impact. 3, the cover 30 may surround the upper surface of the semiconductor package 20. However, the present invention is not limited thereto, and the cover 30 may surround all of the side surfaces, the upper surface, and the lower surface of the system substrate 10 of the semiconductor package 20.

In an exemplary embodiment, the cover 30 may be a case forming the exterior of the semiconductor device 1 or a case for packaging the semiconductor package 20. However, the present invention is not limited thereto, and the cover 30 may be a heat dissipation member for heat dissipation of the semiconductor package 20.

In an exemplary embodiment, the cover 30 may include a material having excellent thermal conductivity in order to rapidly dissipate heat generated from the semiconductor package 20 to the outside. For example, the cover 30 may include a metal material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), nickel (Ni), and the like. However, the present invention is not limited thereto, and the cover 30 may include a carbon-based material having excellent thermal conductivity, such as graphite, diamond, and carbon fiber.

The cover 30 may include a first cover portion 30a and a second cover portion 30b. The first cover portion 30a may be a part of the cover 30 overlapping the semiconductor package 20 in a vertical direction and in contact with the thermally conductive interface material 150. In addition, the second cover portion 30b may not overlap with the semiconductor package 20 in a vertical direction, but may be a portion of the cover 30 in contact with the second adhesive layer 130.

The semiconductor device 1 according to the exemplary embodiment of the present disclosure may be a solid state drive apparatus. In addition, the cover 30 may be a case that forms the exterior of the solid state drive device. For example, the cover 30 may surround the exterior of the system substrate 10 and the semiconductor package 20.

The thermally conductive interface material 150 included in a general semiconductor device may be within an area defined by the upper surface of the semiconductor package 20. In other words, when the thermally conductive interface material 150 is viewed from a plan view (that is, when viewed from an XY plane), the area of the upper surface of the thermally conductive interface material 150 is less than the area of the upper surface of the semiconductor package 20 Can have. Accordingly, the thermally conductive interface material 150 transfers heat generated from the semiconductor package 20 to only a portion of the cover 30 overlapping the semiconductor package 20 in a vertical direction.

The semiconductor device 1 according to the exemplary embodiment of the present disclosure may include the conductive label 100, so that the semiconductor package 20 is not vertically overlapped with the semiconductor package 20 by the conductive label 100. It may be thermally coupled to the second cover portion 30b of the uncovered cover 2, and the thermal coupling between the semiconductor package 20 and the cover 30 may be strengthened. Accordingly, heat generated from the semiconductor package 20 may be transferred to a portion of the cover 30 that does not overlap the semiconductor package 20 in a vertical direction, and may be rapidly radiated to the outside.

4 is a cross-sectional view of the conductive layer 120a of the semiconductor device 1 according to the exemplary embodiment of the present disclosure taken along line IV-IV' of FIG. 3.

Referring to FIG. 4 together with FIG. 3, a first hole H1 may be formed in the first conductive portion 120a. More specifically, a plurality of mesh-type first holes H1 may be formed in the conductive layer 120 overlapping the semiconductor package 20 in a vertical direction. A thermally conductive interface material 150 may be positioned in the first holes H1. That is, the thermally conductive interface material 150 may be filled in the first holes H1.

In addition, a second hole (not shown) overlapping the first hole H1 of the first conductive portion 120a in a vertical direction may be formed in the first adhesive layer 110. Since the thermally conductive interface material 150 may be positioned in the first hole H1 and the second hole, a part of the thermally conductive interface material 150 may contact the upper surface of the semiconductor package 20.

More specifically, the thermally conductive interface material 150 may include a phase change material as described above, and accordingly, the thermally conductive interface material 150 may be positioned in the first hole H1 and the second hole. I can. For example, the thermally conductive interface material 150 may flow into the first hole H1 and the second hole in a liquid state. After the thermally conductive interface material 150 is introduced into the first hole H1 and the second hole, the thermally conductive interface material 150 may be solidified to become a solid state.

Since a portion of the thermally conductive interface material 150 may directly contact the upper surface of the semiconductor package 20, heat generated from the semiconductor package 20 may be quickly transferred to the cover 30. Accordingly, the heat dissipation performance of the semiconductor device 1 may be improved.

5 is a cross-sectional view of a semiconductor device 2 according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 1 of FIG. 3 and the semiconductor device 2 of FIG. 5 will be omitted, and differences will be mainly described.

Referring to FIG. 5, the conductive label 100 of the semiconductor device 2 according to the exemplary embodiment of the present disclosure may further include a third adhesive layer 135 and an insulating layer 140.

In an exemplary embodiment, the third adhesive layer 135 may be configured to attach the insulating layer 140 to the third conductive portion 120c. The third adhesive layer 135 may be interposed between the third conductive portion 120c and the insulating layer 140.

The insulating layer 140 is attached to the lower portion of the third conductive portion 120c by the third adhesive layer 135 and may be a layer including an insulating material. The insulating layer 140 may be attached to a portion of the conductive layer 120 that does not overlap the semiconductor package 20 in a vertical direction.

In addition, the insulating layer 140 may be attached to a portion of the conductive layer 120 to face the system substrate 10. Accordingly, the insulating layer 140 prevents direct contact between the third conductive portion 120c of the conductive layer 120 and the system substrate 10, thereby suppressing the occurrence of a short defect.

6 is a cross-sectional view of a semiconductor device 3 according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 2 of FIG. 5 and the semiconductor device 3 of FIG. 6 will be omitted, and differences will be mainly described.

Referring to FIG. 6, the top surface of the semiconductor chip 200 of the semiconductor device 3 may be at substantially the same level as the top surface of the molding layer 230. In other words, the upper surface of the semiconductor chip 200 may be exposed from the molding layer 230, and the upper surface of the semiconductor chip 200 may directly contact the conductive label 100. Accordingly, heat generated from the semiconductor chip 200 can be quickly transferred to the conductive label 100, so that the heat dissipation performance of the semiconductor device 3 can be improved.

7 is a cross-sectional view of a semiconductor device 4 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7, the semiconductor device 4 according to the exemplary embodiment of the present disclosure may include a system substrate 10, a semiconductor package 20, a cover 30, and a conductive label 100. .

In an exemplary embodiment, the cover 30 may expose the upper surface of the semiconductor package 20 and surround the side surface of the semiconductor package 20. In an exemplary embodiment, the inner surface of the cover 30 may be at a higher level than the upper surface of the semiconductor package 20. Further, the outer surface of the cover 30 may be substantially at the same level as the upper surface of the semiconductor package 20. However, it is not limited thereto.

In an exemplary embodiment, the length C2 in the horizontal direction (X direction) of the conductive label 100 may have a value greater than the length P2 in the horizontal direction (X direction) of the semiconductor package 20. In addition, the conductive label 100 may be attached to the upper surface of the semiconductor package 20 and the outer surface of the cover 30.

More specifically, the conductive label 100 may include a first adhesive layer 110 and a conductive layer 120. In an exemplary embodiment, the first adhesive layer 110 may contact the upper surface of the semiconductor package 20 and the outer surface of the cover 30. In addition, the first adhesive layer 110 may be configured to attach the conductive layer 120 to the upper surface of the semiconductor package 20 and the outer surface of the cover 30.

In an exemplary embodiment, the conductive layer 120 may be configured to transfer heat generated from the semiconductor package 20 to the cover 30. The conductive layer 120 may be on the first adhesive layer 110 and may be exposed to the outside. The conductive layer 120 may dissipate heat transferred from the semiconductor package 20 to the outside.

Heat generated from the semiconductor package 20 may be transferred by the conductive layer 120 to a portion of the cover 30 that does not overlap the semiconductor package 20 in a vertical direction. Accordingly, the heat dissipation performance of the semiconductor device 4 can be improved.

In an exemplary embodiment, the semiconductor package 20 and the cover 30 are spaced apart from each other (i.e., a gap formed between the semiconductor package 20 and the cover 30) and a conductive label 100 overlapping in a vertical direction. A ventilation hole H2 may be formed in a portion of the. That is, a ventilation hole H2 may be formed in a portion of the conductive label 100 that does not overlap the semiconductor package 20 and the cover 30 in a vertical direction. Two or more ventilation holes H2 may be formed. The ventilation hole H2 may communicate with a space formed by spaced apart the semiconductor package 20 and the cover 30.

Air introduced into the semiconductor device 4 through the ventilation hole H2 of the conductive label 100 may be discharged to the outside through the ventilation hole H2 after circulating through the semiconductor package 20. Heat generated from the semiconductor package 20 may be rapidly discharged to the outside due to a thermal convection phenomenon caused by air. Accordingly, the heat dissipation performance of the semiconductor device 4 can be improved.

8 is a cross-sectional view of a semiconductor device 5 according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 4 of FIG. 7 and the semiconductor device 5 of FIG. 8 will be omitted, and differences will be mainly described.

Referring to FIG. 8, the conductive label 100 of the semiconductor device 5 according to the exemplary embodiment of the present disclosure may further include a second adhesive layer 130. The second adhesive layer 130 may be configured to attach the heat sink 310 on the conductive layer 120.

The heat sink 310 may be a heat dissipating member configured to receive heat generated from the semiconductor package 20 and dissipate the heat to the outside. The heat sink 310 may be attached to the conductive layer 120 by the second adhesive layer 130 and exposed to the outside.

In an exemplary embodiment, the length S1 of the heat sink 310 in the horizontal direction (X direction) may have a value greater than the length P2 of the semiconductor package 20 in the horizontal direction (X direction). For example, the length S1 in the horizontal direction (X direction) of the heat sink 310 is greater than the length P2 in the horizontal direction (X direction) of the semiconductor package 20, and the horizontal direction of the conductive layer 120 It may be smaller than the length of (X direction). However, the present invention is not limited thereto, and the length S1 in the horizontal direction (X direction) of the heat sink 310 is larger than the length P2 in the horizontal direction (X direction) of the semiconductor package 20, and It may be substantially the same as the length in the horizontal direction (X direction).

The heat sink 310 may include a material having excellent thermal conductivity. In an exemplary embodiment, the heat sink 310 may include a metal material having excellent thermal conductivity. For example, the heat sink 310 may include a metal material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), nickel (Ni), and the like.

In addition, the heat sink 310 may include a carbon-based material having excellent thermal conductivity. For example, the heat sink 310 may include graphite, diamond, carbon fiber, or the like. In addition, the heat sink 310 may include a polymer-based material having excellent thermal conductivity. However, the heat sink 310 is not limited to the above-described materials, and may include a combination of the above materials or other materials not shown.

In an exemplary embodiment, the heat sink 310 may have an uneven structure in order to increase a surface area exposed to the outside. Accordingly, the semiconductor device 5 can quickly dissipate heat generated from the semiconductor package 20 to the outside.

Also, information on the semiconductor package 20 may be marked on the surface of the heat sink 310. For example, information of the semiconductor package 20 such as the type, number, performance of the semiconductor chip 200, the name and/or logo of the manufacturer, the date of manufacture, the serial number, etc., will be marked on the surface of the heat sink 310. I can. For example, information on the semiconductor package 20 may be expressed on the surface of the heat sink 310 using a laser etching technique. However, the present invention is not limited thereto, and information on the semiconductor package 20 may be expressed on the surface of the heat sink 310 by using a pad printing technique.

9 is a cross-sectional view of a semiconductor device 6 according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 4 of FIG. 7 and the semiconductor device 6 of FIG. 9 will be omitted, and differences will be mainly described.

Referring to FIG. 9, the lower surface of the cover 30 may be at a lower level than the upper surface of the semiconductor package 20. Also, the upper surface of the semiconductor package 20 may be at a higher level than the upper surface of the cover 30. That is, the semiconductor package 20 may protrude from the outer surface of the cover 30.

The conductive label 100 may include a first adhesive layer 110a, a second adhesive layer 110b, a conductive layer 120, a third adhesive layer 137, and an insulating layer 140. In an exemplary embodiment, the first adhesive layer 110a may abut the upper surface of the semiconductor package 20. In addition, the first adhesive layer 110a may be configured to attach the conductive layer 120 to the upper surface of the semiconductor package 20. The first adhesive layer 110a may overlap the semiconductor package 20 in a vertical direction.

The second adhesive layer 110b may contact one surface of the conductive layer 120 that does not overlap the semiconductor package 20 in a vertical direction and the inner surface of the cover 30. The second adhesive layer 110b may be configured to attach the conductive layer 120 to the inner surface of the cover 30.

The length C3 of the conductive layer 120 in the horizontal direction (X direction) may be greater than the length P3 of the semiconductor package 20 in the horizontal direction (X direction). A portion of the conductive layer 120 may be on the top of the semiconductor package 20, and a portion of the conductive layer 120 may be on the bottom of the cover 30. Heat generated from the semiconductor package 20 may be transferred to the cover 30 by the conductive layer 120.

In an exemplary embodiment, the conductive layer 120 may include a first conductive portion 120d, a second conductive portion 120e, and a third conductive portion 120f. The first conductive portion 120d may be a portion of the conductive layer 120 attached to the upper surface of the semiconductor package 20 by the first adhesive layer 110a. Also, the first conductive portion 120d may be a portion of the conductive layer 120 overlapping the semiconductor package 20 in a vertical direction.

The second conductive portion 120e may be a portion of the conductive layer 120 that is bent downward from the first conductive portion 120d to cover the spaced space between the semiconductor package 20 and the cover 30. For example, the second conductive portion 120e may be inclined between the semiconductor package 20 and the cover 30.

The third conductive portion 120f may be a portion of the conductive layer 120 that extends laterally from the second conductive portion 120e and is attached to the inner surface of the cover 30 by the second adhesive layer 110b. . In addition, the third conductive portion 120f may be a portion of the conductive layer 120 that does not overlap the semiconductor package 20 in a vertical direction.

In an exemplary embodiment, the third adhesive layer 137 may be configured to attach the insulating layer 140 to a portion of the conductive layer 120 facing the system substrate 10. More specifically, the third adhesive layer 137 may contact the third conductive portion 120f and may be configured to attach the insulating layer 140 to the third conductive portion 120f.

In an exemplary embodiment, the insulating layer 140 may be a layer for suppressing the occurrence of a short defect by preventing direct contact between the conductive layer 120 and the system substrate 10. The insulating layer 140 may be attached to the third conductive portion 120f by the third adhesive layer 137. In addition, the insulating layer 140 may not overlap with the semiconductor package 20 in a vertical direction and may face the system substrate 10.

10 is a cross-sectional view of a semiconductor device 7 according to an exemplary embodiment of the present disclosure. 11 is a plan view of portion A of the semiconductor device 7 in FIG. 10.

10 and 11, the semiconductor device 7 of the present disclosure may further include a heat sink 310. The heat sink 310 may be a heat dissipating member configured to receive heat generated from the semiconductor package 20 and dissipate the heat to the outside.

In an exemplary embodiment, the fourth adhesive layer 320 may abut the upper surface of the first conductive portion 120d and may be configured to attach the heat sink 310 to the first conductive portion 120d. . The heat sink 310 may be attached to the first conductive portion 120d by the fourth adhesive layer 320 and may be exposed to the outside.

In an exemplary embodiment, the length S2 in the horizontal direction (X direction) of the heat sink 310 may be substantially the same as the length P4 in the horizontal direction (X direction) of the semiconductor package 20. However, the present invention is not limited thereto, and the length S2 of the heat sink 310 in the horizontal direction (X direction) may be smaller than the length P4 of the semiconductor package 20 in the horizontal direction (X direction).

Since the technical idea of the material and shape of the heat sink 310 overlaps with the content described with reference to FIG. 8, detailed information will be omitted.

In an exemplary embodiment, a ventilation hole H3 may be formed in the conductive layer 120 to allow air to flow into the semiconductor device 7 or to outflow air from the semiconductor device 7 to the outside. . A ventilation hole H3 may be formed in a portion of the conductive layer 120 vertically overlapping a space formed by spaced apart from the semiconductor package 20 and the cover 30. That is, the ventilation hole H3 may be formed in the second conductive portion 120e. Two or more ventilation holes H3 may be formed.

Air introduced into the semiconductor device 7 through the ventilation hole H3 of the conductive label 100 may be discharged to the outside through the ventilation hole H3 after circulating through the semiconductor package 20. Heat generated from the semiconductor package 20 may be rapidly discharged to the outside due to a thermal convection phenomenon caused by air. Accordingly, the heat dissipation performance of the semiconductor device 7 can be improved.

12 is a cross-sectional view of a semiconductor device 8a according to an exemplary embodiment of the present disclosure.

Referring to FIG. 12, a semiconductor device 8a according to an exemplary embodiment of the present disclosure includes a first system substrate 10a, a second system substrate 10b, a flexible substrate 11, and a first semiconductor package 20a. ), a second semiconductor package 20b, a cover 30, a first conductive label 100c, and a second conductive label 100d.

The first system substrate 10a may be a substrate on which the first semiconductor package 20a is mounted. The first system substrate 10a may include a first substrate pad 101a contacting the first package connection terminal 250a of the first semiconductor package 20a. In an exemplary embodiment, the first system substrate 10a may be a double-sided printed circuit board including substrate pads on both sides. However, the present invention is not limited thereto, and the first system substrate 10a may be a single-sided printed circuit board including the first substrate pad 101a on only one surface.

In an exemplary embodiment, the first system substrate 10a may include a first mounting surface 105 and a second mounting surface 107 opposite to the first mounting surface 105. The first mounting surface 105 may be one surface of the first system substrate 10a facing the inner surface of the cover 30, and the first semiconductor package 20a may be mounted on the first mounting surface 105. . In addition, the second mounting surface 107 may be one surface of the first system board 10a facing the second system board 10b, and a plurality of first electronic modules 410 are provided on the second mounting surface 107. ) Can be mounted. For example, the first electronic modules 410 may include a passive device, an active device, or the like.

In general, the amount of heat emitted from the first semiconductor package 20a mounted on the first mounting surface 105 of the first system substrate 10a is mounted on the second mounting surface 107 of the first system substrate 10a. It may be greater than the amount of heat emitted from the first electronic modules 410. Accordingly, when the first semiconductor package 20a is mounted on the first mounting surface 105, heat emitted from the first semiconductor package 20a may be rapidly discharged to the outside through the cover 30.

However, it is not limited to the above, and when the amount of heat emitted from the first electronic modules 410 is greater than the amount of heat emitted from the first semiconductor package 20a, the first electronic modules 410 It is mounted on the first mounting surface 105 of the substrate 10a, and the first semiconductor package 20a may be mounted on the second mounting surface 107.

The second system substrate 10b may be a substrate on which the second semiconductor package 20b is mounted. The second system substrate 10b may include a second substrate pad 101b contacting the second package connection terminal 250b of the second semiconductor package 20b. In an exemplary embodiment, the second system substrate 10b may be a double-sided printed circuit board including substrate pads on both sides. However, the present invention is not limited thereto, and the second system substrate 10b may be a single-sided printed circuit board including the second substrate pad 101b only on one side.

In an exemplary embodiment, the second system substrate 10b may include a third mounting surface 106 and a fourth mounting surface 108 opposite to the third mounting surface 106. The third mounting surface 106 may be one surface of the second system substrate 10b facing the inner surface of the cover 30, and the second semiconductor package 20b may be mounted on the third mounting surface 106. . In addition, the fourth mounting surface 108 may be one surface of the second system board 10b facing the first system board 10a, and a plurality of second electronic modules 420 are provided on the fourth mounting surface 108. ) Can be mounted. For example, the second electronic module 420 may include a passive device, an active device, or the like. In addition, the second mounting surface 107 of the first system substrate 10a and the fourth mounting surface 108 of the second system substrate 10b may face each other.

In general, the amount of heat emitted from the second semiconductor package 20b mounted on the third mounting surface 106 of the second system substrate 10b is mounted on the fourth mounting surface 108 of the second system substrate 10b. It may be greater than the amount of heat emitted from the second electronic modules 420. Accordingly, when the second semiconductor package 20b is mounted on the third mounting surface 106, the heat emitted from the second semiconductor package 20b may be rapidly discharged to the outside through the cover 30.

However, it is not limited to the above, and when the amount of heat emitted from the second electronic modules 420 is greater than the amount of heat emitted from the second semiconductor package 20b, the second electronic modules 420 It is mounted on the third mounting surface 106 of the substrate 10b, and the second semiconductor package 20b may be mounted on the fourth mounting surface 108.

In an exemplary embodiment, the flexible substrate 11 may be a substrate configured to physically and/or electrically connect the first system substrate 10a and the second system substrate 10b. In addition, the flexible substrate 11 may be a substrate having flexibility.

In an exemplary embodiment, the flexible substrate 11 may have a thickness of about 300 micrometers or less to ensure flexibility. However, the present invention is not limited thereto, and may have various thickness values. In addition, the flexible substrate 11 may be provided in a curved shape to connect the first system substrate 10a and the second system substrate 10b within a limited internal space provided by the cover 30.

In an exemplary embodiment, the flexible substrate 11 is polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), and polyetherether ketone (PEEK). , And at least one of a prepreg may be included.

The cover 30 protects the first system substrate 10a, the second system substrate 10b, the flexible substrate 11, the first semiconductor package 20a, and the second semiconductor package 20b from external impacts. For this purpose, the first system substrate 10a, the second system substrate 10b, the flexible substrate 11, the first semiconductor package 20a, and the second semiconductor package 20b may be surrounded.

In an exemplary embodiment, the cover 30 includes the first system substrate 10a, the second system substrate 10b, the flexible substrate 11, the first semiconductor package 20a, and the second semiconductor package 20b. It can be a case for packaging. However, the present invention is not limited thereto, and may be a heat dissipating member for dissipating heat generated from the first semiconductor package 20a and the second semiconductor package 20b.

In an exemplary embodiment, the cover 30 may include a material having excellent thermal conductivity in order to rapidly dissipate heat generated from the first semiconductor package 20a and the second semiconductor package 20b to the outside. For example, the cover 30 may include a metal material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), nickel (Ni), and the like. However, the present invention is not limited thereto, and the cover 30 may include a carbon-based material having excellent thermal conductivity, such as graphite, diamond, and carbon fiber.

The first semiconductor package 20a may be a package including a first semiconductor chip (not shown). For example, the first semiconductor package 20a may include two or more first semiconductor chips. The first semiconductor chips included in the first semiconductor package 20a may be of the same type or may be different types of semiconductor chips. In addition, the first semiconductor package 20a may include a first package connection terminal 250a in contact with the first system substrate 10a. In addition, the first semiconductor package 20a may have a first length P5 in a horizontal direction (X direction).

In an exemplary embodiment, the first semiconductor chip may include a first semiconductor device layer, and a plurality of individual devices of various types may be formed in the semiconductor device layer. The first semiconductor device layer may be connected to the first system substrate 10a through the first package connection terminal 250a.

The second semiconductor package 20b may be a package including a second semiconductor chip (not shown). For example, the second semiconductor package 20b may include two or more second semiconductor chips. The second semiconductor chips included in the second semiconductor package 20b may be of the same type or may be different types of semiconductor chips. In addition, the second semiconductor package 20b may include a second package connection terminal 250b in contact with the second system substrate 10b. In addition, the second semiconductor package 20b may have a second length P6 in the horizontal direction (X direction).

In an exemplary embodiment, the first semiconductor package 20a and the second semiconductor package 20b are electrically connected to each other to operate as one system. More specifically, the first semiconductor package 20a and the second semiconductor package 20b are electrically connected to each other through the first system substrate 10a, the second system substrate 10b, and the flexible substrate 11 It can operate as one system.

The first semiconductor chip included in the first semiconductor package 20a may be a semiconductor chip of a different type from the second semiconductor chip each included in the second semiconductor package 20b. For example, the first semiconductor chip may include a memory semiconductor chip. The first semiconductor chip may include, for example, a volatile memory semiconductor chip such as DRAM or SRAM, and may include a nonvolatile memory semiconductor chip such as PRAM, MRAM, FeRAM, or RRAM.

Also, the second semiconductor chip included in the second semiconductor package 20b may include a logic semiconductor chip. The second semiconductor chip may include, for example, a logic semiconductor chip such as a CPU, MPU, GPU, or AP.

In an exemplary embodiment, the first conductive label 100c may be interposed between the first semiconductor package 20a and the cover 30. In addition, the length C4 of the first conductive label 100c in the horizontal direction (X direction) may have a value greater than the first length P5 of the first semiconductor package 20a in the horizontal direction (X direction). . Accordingly, the first conductive label 100c may also be attached to the inner surface of the cover 30 that does not overlap the first semiconductor package 20a in a vertical direction.

The first conductive label 100c may include a first adhesive layer 110a, a first conductive layer 123, and a second adhesive layer 130a. The first adhesive layer 110a may abut the upper surface of the first semiconductor package 20a and may overlap the first semiconductor package 20a in a vertical direction. The first adhesive layer 110a may be configured to attach the first conductive layer 123 to the upper surface of the first semiconductor package 20a.

The first conductive layer 123 may be attached to the upper surface of the first semiconductor package 20a by the first adhesive layer 110a. The first conductive layer 123 may have a length C4 greater than the first length P5 of the first semiconductor package 20a in the horizontal direction.

In an exemplary embodiment, the first conductive layer 123 may be interposed between the first adhesive layer 110a and the second adhesive layer 130a. Heat generated from the first semiconductor package 20a may be transferred to the inner surface of the cover 30 that does not overlap the first semiconductor package 20a in a vertical direction by the first conductive layer 123.

The second adhesive layer 130a may be interposed between the cover 30 and the first conductive layer 123. The second adhesive layer 130a may be configured to attach the first conductive layer 123 to the inner surface of the cover 30.

In an exemplary embodiment, the second conductive label 100d may be interposed between the second semiconductor package 20b and the cover 30. In addition, the fourth length C5 in the horizontal direction (X direction) of the second conductive label 100d has a value greater than the second length P6 in the horizontal direction (X direction) of the second semiconductor package 20b. I can. Accordingly, the second conductive label 100d may also be attached to the inner surface of the cover 30 that does not overlap the second semiconductor package 20b in a vertical direction.

The second conductive label 100d may include a third adhesive layer 110b, a second conductive layer 125, and a fourth adhesive layer 130b. The third adhesive layer 110b may abut the upper surface of the second semiconductor package 20b and may overlap the second semiconductor package 20b in a vertical direction. The third adhesive layer 110b may be configured to attach the second conductive layer 125 to the upper surface of the second semiconductor package 20b.

The second conductive layer 125 may be attached to the upper surface of the second semiconductor package 20b by the third adhesive layer 110b. The second conductive layer 125 may have a length C5 greater than the second length P6 of the second semiconductor package 20b in the horizontal direction.

In an exemplary embodiment, the second conductive layer 125 may be interposed between the third adhesive layer 110b and the fourth adhesive layer 130b. Heat generated from the second semiconductor package 20b may be transferred to the inner surface of the cover 30 that does not overlap the second semiconductor package 20b in a vertical direction by the second conductive layer 125.

The fourth adhesive layer 130b may be interposed between the cover 30 and the second conductive layer 125. The fourth adhesive layer 130b may be configured to attach the second conductive layer 125 to the inner surface of the cover 30.

The semiconductor device 8a according to the exemplary embodiment of the present disclosure includes a first conductive label 100c and a second semiconductor package 20b and a cover 30 interposed between the first semiconductor package 20a and the cover 30. ), the second conductive label 100d may be interposed therebetween, so that heat emitted from the first semiconductor package 20a and the second semiconductor package 20b may be quickly transferred to the cover 30. Accordingly, the heat dissipation performance of the semiconductor device 8a can be improved.

13 is a cross-sectional view of a semiconductor device 8b according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 8a of FIG. 12 and the semiconductor device 8b of FIG. 13 will be omitted, and differences will be mainly described.

Referring to FIG. 13, a thermally conductive interface material 150 may be disposed on at least one of the first semiconductor package 20a and the second semiconductor package 20b. For example, as shown in FIG. 13, a thermally conductive interface material 150 may be present on the first semiconductor package 20a, and the thermally conductive interface material 150 may not be present on the second semiconductor package 20b. . However, the present invention is not limited thereto, and both the thermally conductive interface material 150 may be present on the first semiconductor package 20a and the second semiconductor package 20b.

In an exemplary embodiment, the thermally conductive interface material 150 may be interposed between the first conductive layer 123 and the cover 30. Since the technical idea of the thermally conductive interface material 150 overlaps with that described with reference to FIG. 3, detailed information will be omitted.

In an exemplary embodiment, the first conductive layer 123 may include a first conductive portion 123a, a second conductive portion 123b, and a third conductive portion 123c. The first conductive portion 123a overlaps the first semiconductor package 20a in a vertical direction and is interposed between the first adhesive layer 110a and the thermally conductive interface material 150. It can be part.

The second conductive portion 123b may be a portion of the first conductive layer 123 that is bent upward from the first conductive portion 123a and surrounds a side surface of the thermally conductive interface material 150. In addition, the third conductive portion 123c is laterally bent at the second conductive portion 123b, and the second adhesive layer 130a is formed on the inner surface of the cover 30 that does not overlap the first semiconductor package 20a in a vertical direction. It may be a part of the first conductive layer 123 attached by ).

In an exemplary embodiment, the first conductive label 100c may further include a first insulating layer 143 under the third conductive portion 123c. More specifically, the first conductive label 100c is attached to the third conductive portion 123c by the fifth adhesive layer 141 and the fifth adhesive layer 141 in contact with one surface of the third conductive portion 123c. It may further include a first insulating layer 143 to be attached. The first insulating layer 143 may be attached to the third conductive portion 123c to face the first mounting surface 105 of the first system substrate 10a.

In an exemplary embodiment, the second conductive label 100d may further include a second insulating layer 147 on the second conductive layer 125. More specifically, the second conductive label 100d includes a sixth adhesive layer 145 in contact with the second conductive layer 125 and a second conductive layer 125 attached to the second conductive layer 125 by the sixth adhesive layer 145. 2 Insulation layer 147 may be further included. The second insulating layer 147 may be attached to the second conductive layer 125 to face the third mounting surface 106 of the second system substrate 10b.

In an exemplary embodiment, the semiconductor device 8b may further include a third conductive label 100e. The third conductive label 100e may include a seventh adhesive layer 171, a third conductive layer 173, and an eighth adhesive layer 175. The third conductive label 100e may be attached to at least one of the first electronic module 410 and the second electronic module 420 described above.

In an exemplary embodiment, the seventh adhesive layer 171 may contact the upper surface of the first electronic module 410. The seventh adhesive layer 171 may be configured to attach the third conductive layer 173 to the upper surface of the first electronic module 410.

The third conductive layer 173 may be configured to transfer heat generated from the first electronic module 410 to the cover 30. For example, the third conductive layer 173 is bent in a vertical direction at the fourth conductive portion 173a extending in the horizontal direction and the fourth conductive portion 173a, and is attached to the inner surface of the cover 30. It may include 5 conductive parts 173b. More specifically, the fifth conductive portion 173b may be attached to the inner surface of the cover 30 by the eighth adhesive layer 175.

In an exemplary embodiment, the third conductive label 100e may further include a third insulating layer 177 and a fourth insulating layer 179. The third insulating layer 177 may be attached to one surface of the third conductive layer 173 facing the first system substrate 10a by the ninth adhesive layer 181. The third insulating layer 177 may suppress the occurrence of a short defect due to contact between the third conductive layer 173 and the first system substrate 10a.

In addition, the fourth insulating layer 179 may be attached to one surface of the third conductive layer 173 facing the second system substrate 10b by the tenth adhesive layer 183. The fourth insulating layer 179 may suppress the occurrence of a short defect due to contact between the third conductive layer 173 and the second system substrate 10b.

14 is a cross-sectional view of a semiconductor device 8c according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 8b of FIG. 13 and the semiconductor device 8c of FIG. 14 will be omitted, and differences will be mainly described.

Referring to FIG. 14, the first conductive label 100c and the second conductive label 100d may be interconnected and attached to the inner surface of the cover 30. In other words, the first conductive label 100c and the second conductive label 100d may be attached to the inner surface of the cover 30 in an integrated state.

In an exemplary embodiment, the second adhesive layer 130a, the first conductive layer 123, the fifth adhesive layer 141, and the first insulating layer 143 of the first conductive label 100c are each second The fourth adhesive layer 130b, the second conductive layer 125, the sixth adhesive layer 145, and the second insulating layer 147 of the conductive label 100d may be connected and integrated, respectively.

In an exemplary embodiment, the first conductive label 100c and the second conductive label 100d include the first conductive layer 123, the second conductive layer 125, the first system substrate 10a, and the second system. In order to prevent an electrical short circuit caused by contact between the substrate 10b and the flexible substrate 11, a first insulating layer 143 and a second insulating layer 147 may be provided.

However, the present invention is not limited to the above, and the first conductive label 100c and the second conductive label 100d include the fifth adhesive layer 141, the first insulating layer 143, the sixth adhesive layer 145, and the first conductive label 100c and the second conductive label 100d. 2 The insulating layer 147 may be omitted.

In an exemplary embodiment, the third conductive layer 173 of the third conductive label 100e is connected to the first conductive layer 123 of the first conductive label 100c, and is attached to the inner surface of the cover 30. I can.

More specifically, the eighth adhesive layer 175 and the third conductive layer 173 of the third conductive label 100e are each of the second adhesive layer 130a of the first conductive label 100c, and the first conductive layer. It is connected to the layer 123 and may be integrated.

In addition, the third conductive layer 173 of the third conductive label 100e is connected to the second conductive layer 125 of the second conductive label 100d and may be attached to the inner surface of the cover 30.

More specifically, the eighth adhesive layer 175 and the third conductive layer 173 of the third conductive label 100e are each of the fourth adhesive layer 130b and the second conductive layer of the second conductive label 100d. It is connected to 125 and can be integrated.

In an exemplary embodiment, the third conductive label 100e may be connected to at least one of the first conductive label 100c and the second conductive label 100d. As shown in FIG. 14, the third conductive label 100e may be connected to both the first conductive label 100c and the second conductive label 100d. However, the present invention is not limited to the above, and the third conductive label 100e may be connected to only one of the first conductive label 100c and the second conductive label 100d.

In an exemplary embodiment, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e are interconnected and may be attached to the entire inner surface of the cover 30. For example, the inner surface of the cover 30 may not be exposed by the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e.

By the above-described structure of the semiconductor device 8c of the present disclosure, heat generated by the operation of at least one of the first semiconductor package 20a, the second semiconductor package 20b, and the first electronic module 410 is It may be transmitted to the inner surface of the cover 30. Accordingly, the heat dissipation performance of the semiconductor device 8c of the present disclosure can be improved.

15 is a cross-sectional view of a semiconductor device 8d according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 8b of FIG. 13 and the semiconductor device 8d of FIG. 15 will be omitted, and differences will be mainly described.

Referring to FIG. 15, a first heat transfer hole H4 through which the first conductive label 100c can pass may be formed in the cover 30. In addition, a second heat transfer hole H5 through which the second conductive label 100d can pass may be formed in the cover 30.

In an exemplary embodiment, the second adhesive layer 130a of the first conductive label 100c may contact the inner surface of the cover 30 as described above. In addition, the second adhesive layer 130a may pass through the first heat transfer hole H4 and contact the outer surface of the cover 30.

In addition, the first conductive layer 123 passes through the first heat transfer hole H4 of the cover 30 by the second adhesive layer 130a as described above, and is covered by the second adhesive layer 130a. It can be extended and attached to the outer surface of (30).

In an exemplary embodiment, the fourth adhesive layer 130b of the second conductive label 100d may abut the inner surface of the cover 30 as described above. In addition, the fourth adhesive layer 130b may pass through the second heat transfer hole H5 and contact the outer surface of the cover 30.

In addition, the second conductive layer 125 passes through the second heat transfer hole H5 of the cover 30 by the fourth adhesive layer 130b as described above, and is covered by the fourth adhesive layer 130b. It can be attached to the outer surface of (30).

In an exemplary embodiment, the first conductive label 100c and the second conductive label 100d may cover a part of the outer surface of the cover 30 and expose a part of it. However, the present invention is not limited thereto, and the first conductive label 100c and the second conductive label 100d may cover the entire outer surface of the cover 30.

In an exemplary embodiment, a ventilation hole H6 may be formed in a portion of the cover 30 to which the first conductive label 100c and the second conductive label 100d are not attached. Air introduced into the semiconductor device 8c through the ventilation hole H6 of the cover 30 circulates through the first semiconductor package 20a and the second semiconductor package 20b, and then through the ventilation hole H6. It can be discharged to the outside. Heat generated from the first semiconductor package 20a and the second semiconductor package 20b may be rapidly discharged to the outside due to a thermal convection phenomenon caused by air. Accordingly, the heat dissipation performance of the semiconductor device 8d can be improved.

16 is a cross-sectional view of a semiconductor device 8e according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping contents of the semiconductor device 8d of FIG. 15 and the semiconductor device 8e of FIG. 16 will be omitted, and differences will be mainly described.

Referring to FIG. 16, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e are interconnected and may be attached to the inner surface of the cover 30. In other words, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e may be attached to the inner surface of the cover 30 in an integrated state. For example, the inner surface of the cover 30 may not be exposed by the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e.

In addition, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e are interconnected and may be attached to the outer surface of the cover 30. In other words, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e may be attached to the outer surface of the cover 30 in an integrated state. For example, the outer surface of the cover 30 may not be exposed by the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e.

By the above-described structure of the semiconductor device 8e of the present disclosure, heat generated by the operation of at least one of the first semiconductor package 20a, the second semiconductor package 20b, and the first electronic module 410 is It can be transmitted to both the inner surface and the outer surface of the cover 30. Accordingly, the heat dissipation performance of the semiconductor device 8e of the present disclosure can be improved.

As described above, exemplary embodiments have been disclosed in the drawings and specification. In the present specification, embodiments have been described using specific terms, but these are used only for the purpose of describing the technical idea of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

System substrate;
A semiconductor package mounted on the system substrate and having a first length in a horizontal direction;
A flexible conductive label on the semiconductor package, comprising: a first adhesive layer abutting on the semiconductor package; A conductive layer attached to the semiconductor package by the first adhesive layer and having a second length greater than the first length in a horizontal direction; And a second adhesive layer contacting a partial surface of the conductive layer not overlapping the semiconductor package in a vertical direction;
A thermal interface material (TIM) on the conductive layer to overlap the semiconductor package in a vertical direction; And
A first cover portion overlapping the semiconductor package in a vertical direction and contacting the thermally conductive interface material; And a second cover portion to which the conductive layer is attached by the second adhesive layer;
A semiconductor device comprising a. The method of claim 1,
The conductive layer,
A first conductive portion overlapping the semiconductor package in a vertical direction and interposed between the first adhesive layer and the thermally conductive interface material;
A second conductive portion bent upward at the first conductive portion and surrounding a side surface of the thermally conductive interface material; And
A third conductive portion that does not overlap with the semiconductor package in a vertical direction, is laterally bent at the second conductive portion, and is attached to the second cover portion by the second adhesive layer;
A semiconductor device comprising a. The method of claim 2,
The thermally conductive interface material,
A semiconductor device, characterized in that interposed between the first conductive portion and the first cover portion. The method of claim 2,
The conductive label,
A third adhesive layer in contact with a lower surface of the third conductive portion; And
An insulating layer attached to the third conductive portion by the third adhesive layer so as to face the system substrate;
The semiconductor device further comprising a. The method of claim 2,
Wherein the first conductive portion has a mesh-shaped first hole filled with the thermally conductive interface material. The method of claim 5,
In the first adhesive layer,
A second hole overlapping the first hole in a vertical direction is formed,
The thermally conductive interface material is positioned in the second hole and contacts an upper surface of the semiconductor package. The method of claim 1,
The thickness of the conductive label is,
A semiconductor device, characterized in that 0.10 millimeters to 0.50 millimeters. The method of claim 1,
The semiconductor package,
A semiconductor chip in direct contact with the conductive label;
A semiconductor device comprising a. System substrate;
A semiconductor package mounted on the system substrate and having a first length in a horizontal direction;
A cover exposing an upper surface of the semiconductor package and surrounding a side surface of the semiconductor package; And
A conductive label connecting the semiconductor package and the cover, comprising: a first adhesive layer contacting the semiconductor package; And a conductive layer on the first adhesive layer and having a second length greater than the first length in a horizontal direction;
A semiconductor device comprising a. The method of claim 9,
The conductive layer,
A semiconductor device, wherein the first adhesive layer is attached to an upper surface of the semiconductor package and an outer surface of the cover. The method of claim 10,
The conductive label,
And a ventilation hole penetrating the first adhesive layer and the conductive layer, wherein the ventilation hole communicates with a space formed by being spaced apart from the semiconductor package and the cover. The method of claim 9,
The inner surface of the cover is at a lower level than the upper surface of the semiconductor package,
The conductive label,
A second adhesive layer attached to an upper surface of the conductive layer that does not overlap the semiconductor package in a vertical direction;
Including more,
The conductive layer,
A first conductive portion overlapping the semiconductor package in a vertical direction and attached to an upper surface of the semiconductor package by the first adhesive layer;
A second conductive portion bent downward from the first conductive portion and covering a spaced space between the semiconductor package and the cover; And
A third conductive portion bent laterally from the second conductive portion and attached to an inner surface of the cover that is not vertically overlapped with the semiconductor package by the second adhesive layer;
A semiconductor device comprising a. The method of claim 12,
In the second conduction portion,
A semiconductor device, characterized in that a ventilation hole through the conductive layer is formed. The method of claim 12,
The conductive label,
A third adhesive layer in contact with a lower surface of the third conductive portion; And
An insulating layer attached to the third conductive portion by the third adhesive layer and facing the system substrate;
The semiconductor device further comprising a. A first system substrate;
A second system substrate spaced apart from the first system substrate in a vertical direction;
A flexible substrate connecting the first system substrate and the second system substrate;
A cover surrounding the first system substrate, the second system substrate, and the flexible substrate;
A first semiconductor package mounted on the first system substrate and having a first length in a horizontal direction;
A second semiconductor package mounted on the second system substrate and having a second length in a horizontal direction;
A first conductive label between the first semiconductor package and the cover, the first adhesive layer contacting the first semiconductor package; A first conductive layer on the first adhesive layer and having a third length greater than the first length in a horizontal direction; And a second adhesive layer abutting the cover on the first conductive layer and configured to attach the first conductive layer to the inner surface of the cover; And
A second conductive label between the second semiconductor package and the cover, the third adhesive layer contacting the second semiconductor package; A second conductive layer on the third adhesive layer and having a fourth length greater than the second length in a horizontal direction; And a fourth adhesive layer configured to abut the cover on the second conductive layer and attach the second conductive layer to the inner surface of the cover;
A semiconductor device comprising a. The method of claim 15,
A thermally conductive interface material interposed between the first conductive layer and the inner surface of the cover;
The semiconductor device further comprising a. The method of claim 16,
The first conductive layer,
A first conductive portion overlapping the first semiconductor package in a vertical direction and interposed between the first adhesive layer and the thermally conductive interface material;
A second conductive portion bent upward from the first conductive portion and surrounding a side surface of the thermally conductive interface material; And
A third conductive portion bent laterally at the second conductive portion and attached by the second adhesive layer to an inner surface of the cover that does not overlap in a vertical direction with the semiconductor package;
A semiconductor device comprising a. The method of claim 17,
The first conductive label,
A fifth adhesive layer in contact with the lower surface of the third conductive portion; And
A first insulating layer attached to the third conductive portion by the fifth adhesive layer and facing the first system substrate;
A semiconductor device further comprising a. The method of claim 17,
The second conductive label,
A sixth adhesive layer in contact with the upper surface of the second conductive layer; And
A second insulating layer attached to the second conductive layer by the sixth adhesive layer and facing the second system substrate;
A semiconductor device further comprising a. The method of claim 15,
Heat transfer holes are formed in the cover,
At least one of the first conductive label and the second conductive label,
A semiconductor device, characterized in that extending to an outer surface of the cover through the heat transfer hole of the cover.

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