KR102507541B1 - Semiconductor package and method of manufacturing semiconductor package - Google Patents

Abstract

The semiconductor package includes a package substrate, a first semiconductor device disposed on the package substrate, at least one second semiconductor device stacked on the first semiconductor device to partially cover the first semiconductor device, and the first and second semiconductor devices. 2 a heat dissipation insulation film coated on semiconductor devices, a first conductive heat dissipation member disposed on the heat dissipation insulation film over the first semiconductor device exposed by the second semiconductor device, and the first and second conductive heat dissipation members on the package substrate; 2 including a molding member covering the semiconductor devices.

Description

Semiconductor package and manufacturing method of semiconductor package {SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package and a method of manufacturing the semiconductor package. More specifically, the present invention relates to a system in package in which several chips are stacked in one package and a manufacturing method thereof.

In a system in package (SiP), a memory device may be affected by the invention of a logic device. Thus, it is very important to form a heat dissipation passage through which heat from the logic device is discharged to the outside. Metal materials are suitable for heat dissipation, but they do not have electrical insulation, so there are many limitations in using them inside the package.

According to related technologies, a method of simply improving the thermal conductivity of a package constituent material or dissipating heat by utilizing an adhesive member having high thermal conductivity such as a heat slug on the surface of the package is adopted. However, in this method, the heat is transferred from the logic device to the memory device and cannot effectively dissipate the heat to the outside. In addition, adhesives, encapsulants, etc. containing metal materials with high thermal conductivity lack electrical insulation, so there are limitations in direct application to the surface of the device.

One object of the present invention is to provide a semiconductor package having improved heat dissipation performance.

Another object of the present invention is to provide a method for manufacturing the above-described semiconductor package.

A semiconductor package according to example embodiments for achieving one object of the present invention includes a package substrate, a first semiconductor device disposed on the package substrate, and the first semiconductor device to partially cover the first semiconductor device. at least one second semiconductor device stacked on the first semiconductor device, a heat dissipation insulating film coated on the first and second semiconductor devices, and disposed on the heat dissipating insulating film over the first semiconductor device exposed by the second semiconductor device. and a molding member covering the first and second semiconductor devices on the package substrate.

An electronic device according to exemplary embodiments for achieving one object of the present invention includes a substrate, a first electronic component disposed on the substrate, and an upper surface of the first electronic component to partially cover the first electronic component. At least one second electronic component to be laminated, a heat dissipation insulating film coated on the substrate and the first and second electronic components, and on the heat dissipation insulating film over the first electronic component exposed by the second electronic component. A first conductive heat dissipation member disposed thereon, and a molding member covering the first and second electronic components on the substrate.

An electronic device according to exemplary embodiments for achieving one object of the present invention includes a substrate, a first electronic component disposed on the substrate, and an upper surface of the first electronic component to partially cover the first electronic component. at least one second electronic component that is stacked and consumes less power than the first electronic component, a heat dissipation insulating film coated on the substrate and the first and second electronic components, the exposed by the second electronic component and a first conductive heat dissipation member disposed on the heat dissipation insulating layer over the first electronic component, and a molding member covering the first and second electronic components on the substrate.

In the method of manufacturing a semiconductor package according to exemplary embodiments for achieving another object of the present invention, a first semiconductor device is stacked on a package substrate. At least one second semiconductor device is stacked on the first semiconductor device to partially cover the first semiconductor device. A heat dissipation insulating layer is coated on the first and second semiconductor devices. A first conductive heat dissipation member is formed on the heat dissipation insulating layer over the first semiconductor device exposed by the second semiconductor device. A molding member covering the first and second semiconductor devices is formed on the package substrate.

According to example embodiments, a semiconductor package includes first and second semiconductor devices sequentially stacked on a package substrate, a heat dissipation insulating layer coated on surfaces of the first and second semiconductor devices, and the heat dissipation insulation. A conductive heat dissipation member extending upward on the layer may be included. A heat dissipation member having electrical conductivity may be formed at a desired location and in a desired size by the heat dissipation insulating layer. Heat from the first semiconductor device may be emitted to the outside through the heat dissipation insulating layer and the conductive heat dissipation member. The conductive heat dissipation member may serve as a heat dissipation passage for dissipating heat from the first and second semiconductor devices to the outside.

Accordingly, high heat from the first semiconductor device consuming relatively high power may be quickly dissipated in a vertical direction through the conductive heat dissipation member made of a metal material and having high thermal conductivity. Accordingly, heat dissipation performance of the system-in-package may be improved.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously extended without departing from the spirit and scope of the present invention.

1 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
FIG. 2 is a plan view illustrating a part of the semiconductor package of FIG. 1 .
3 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.
8 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
9 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.
12 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
13 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
FIG. 14 is a perspective view illustrating a part of the semiconductor package of FIG. 13 .
15 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.
21 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
22 to 24 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.
25 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
26 and 27 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.
28 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
29 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
30 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
31 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail.

1 is a cross-sectional view illustrating a semiconductor package according to example embodiments. FIG. 2 is a plan view illustrating a part of the semiconductor package of FIG. 1 .

Referring to FIGS. 1 and 2 , the semiconductor package 10 includes a package substrate 100 , a first semiconductor device 110 , at least one second semiconductor device 120a or 120b , a heat dissipation insulating film 130 , and a conductive heat dissipation layer. A member 140 and a molding member 150 may be included. In addition, the semiconductor package 10 may further include external connection members 104 .

In example embodiments, the semiconductor package 10 may be an electronic device such as a System In Package (SIP). The first semiconductor device 110 may include a logic semiconductor device and a first electronic component, and the second semiconductor devices 120a and 120b may include a second electronic component such as a memory device. The first electronic component may be a first heat source consuming a first power, and the second electronic component may be a second heat source consuming a second power lower than the first power. Accordingly, the first semiconductor device 110 may emit higher heat than the second semiconductor devices 120a and 120b.

The package substrate 100 may be a substrate having upper and lower surfaces facing each other. For example, the package substrate 100 may be a printed circuit board (PCB). The printed circuit board may be a multilayer circuit board having vias and various circuits therein.

The first semiconductor device 110 may be stacked on the package substrate 100 . The first semiconductor device 110 may be mounted on the package substrate 100 using a flip chip bonding method. The first semiconductor device 110 may be electrically connected to the package substrate 100 through the conductive bumps 112 .

A plurality of conductive bumps 112 may be respectively disposed on a plurality of substrate pads on the top surface of the package substrate 100 to connect the first semiconductor device 110 and the package substrate 100 . When the first semiconductor device 110 is bonded to the package substrate 100 , an adhesive 114 may be underfilled between the first semiconductor device 110 and the package substrate 100 . The adhesive 114 may include an epoxy material to reinforce a gap between the first semiconductor device 110 and the package substrate 100 .

Alternatively, the first semiconductor device 110 may be electrically connected to the package substrate 100 through bonding wires. In this case, the first semiconductor device 110 may be stacked on the package substrate 100 via an adhesive layer.

In example embodiments, at least one second semiconductor device 120a or 120b may be stacked on the first semiconductor device 110 to partially cover the first semiconductor device 110 . The second semiconductor devices 120a and 120b may partially overlap the first semiconductor device 110 . A portion of the upper surface of the first semiconductor device 110 may be exposed by the second semiconductor devices 120a and 120b.

Specifically, two second semiconductor devices 120a and 120b may be stacked on the first semiconductor device 110 . The second semiconductor devices 120a and 120b may be spaced apart from each other on the first semiconductor device 110 . The second semiconductor devices 120a and 120b may be stacked on the first semiconductor device 110 via the adhesive layer 124 . The adhesive layer 124 may include a polymer material having excellent thermal conductivity. Examples of the polymer material include thermally conductive adhesive tape, thermally conductive grease, and thermally conductive adhesive. The second semiconductor devices 120a and 120b may be electrically connected to the package substrate 100 through bonding wires 122a and 122b.

For example, the second semiconductor devices 120a and 120b may include volatile memory devices such as DRAM and NAND flash memory. The second semiconductor device may include a plurality of stacked semiconductor chips. The number, size, arrangement, etc. of the stacked chips are provided as examples, and it will be understood that the present invention is not limited thereto.

In example embodiments, a heat dissipation insulating layer 130 may be coated on the first and second semiconductor devices 110 , 120a and 120b. The heat dissipation insulating layer 130 may be conformally coated on the exposed front surfaces of the package substrate 100 and the first and second semiconductor devices 110 , 120a and 120b. Accordingly, the top surface of the package substrate 100, the sidewall of the first semiconductor device 110, and the top surfaces and sidewalls of the second semiconductor devices 120a and 120b may be covered with the heat dissipation insulating layer 130.

The heat dissipation insulating layer 130 may include an insulating material having excellent thermal conductivity. The heat dissipation insulating film 130 has high thermal conductivity including silica (SiO2), aluminum oxide (Al2O3), boron nitride (BN), aluminum nitride (AlN), ceramics coated metal balls, etc. can have

In example embodiments, the conductive heat dissipation member 140 is disposed on the heat dissipation insulating layer 130 over the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. member 142. In addition, the conductive heat dissipation member 140 may further include a second conductive heat dissipation member 143 disposed on the heat dissipation insulating layer 130 above the second semiconductor devices 120a and 120b.

The conductive heat dissipation member 140 may include a metal such as gold (Au), silver (Ag), or copper (Cu), or a conductive material such as graphite or graphene, and may have high thermal conductivity.

The first conductive heat dissipation member 142 may have a pillar shape extending upward from the surface of the heat dissipation insulating layer 130 between the second semiconductor devices 120a and 120b. The first conductive heat dissipation member 142 may contact the heat dissipation insulating layer 130 on sidewalls of the second semiconductor devices 120a and 120b. Alternatively, the first conductive heat dissipation member 142 may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b.

The second conductive heat dissipation member 143 may extend laterally on the heat dissipation insulating layer 130 on the second semiconductor devices 120a and 120b. The second conductive heat dissipation member 143 may contact the sidewall of the first conductive heat dissipation member 142 . Alternatively, the second conductive heat dissipation member 143 may be spaced apart from the sidewall of the first conductive heat dissipation member 142 .

The second conductive heat dissipation member 142 may be integrally formed with the first conductive heat dissipation member 143 . The second conductive heat dissipation member 142 may have the same height as the height of the first conductive heat dissipation member 142 from the package substrate 100 .

In example embodiments, the molding member 150 is formed on the top surface of the package substrate 100 to cover at least a portion of the first and second semiconductor devices 110, 120a, and 120b to cover the first and second semiconductor devices 110, 120a, and 120b. The second semiconductor devices 110, 120a, and 120b may be protected from the outside. The molding member 150 may be formed to expose upper surfaces of the first and second conductive heat dissipation members 142 and 143 . The molding member 150 may have the same height as the heights of the first and second conductive heat dissipation members 142 and 143 from the package substrate 100 .

As described above, the semiconductor package 10 may include the first conductive heat dissipation member 142 that is thermally connected to the first semiconductor device 110 and may dissipate heat from the first semiconductor device 110 to the outside. can The semiconductor package 11 may include a second conductive heat dissipation member 143 that is thermally connected to the second semiconductor devices 120a and 120b to dissipate heat from the second semiconductor devices 120a and 120b to the outside. there is.

Heat from the first semiconductor device 110 may be emitted to the outside through the heat dissipation insulating layer 130 and the first conductive heat dissipation member 142 . Heat from the second semiconductor devices 120a and 120b may be dissipated to the outside through the heat dissipation insulating layer 130 and the second conductive heat dissipation member 143 . The first and second conductive heat dissipation members 142 and 143 may serve as a heat dissipation passage for dissipating heat from the first and second semiconductor devices 110 , 120a and 120b to the outside.

Accordingly, high heat from the first semiconductor device 110 consuming relatively high power may be rapidly dissipated in a vertical direction through the first conductive heat dissipation member 142 made of a metal material having high thermal conductivity. Accordingly, heat dissipation performance of the system-in-package may be improved.

Hereinafter, a method of manufacturing the semiconductor package of FIGS. 1 and 2 will be described.

3 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring to FIGS. 3 and 4 , a first semiconductor device 110 is stacked on a package substrate 100, and at least one semiconductor device 110 is stacked on the first semiconductor device 110 to partially cover the first semiconductor device 110. The second semiconductor devices 120a and 120b of may be stacked.

First, the first semiconductor device 110 may be stacked on the upper surface of the package substrate 100 . The package substrate 100 may include a printed circuit board (PCB), an organic substrate, a ceramic substrate, a module board, and the like.

The first semiconductor device 110 may be mounted on the package substrate 100 by flip chip bonding. The first semiconductor device 110 may be electrically connected to the package substrate 100 through the conductive bumps 112 . A plurality of conductive bumps 112 may be respectively disposed on a plurality of substrate pads on the top surface of the package substrate 100 to bond the first semiconductor device 110 to the package substrate 100 .

When the first semiconductor device 110 is bonded to the package substrate 100 , an adhesive 114 may be underfilled between the first semiconductor device 110 and the package substrate 100 . The adhesive may include an epoxy material to reinforce a gap between the first semiconductor device 110 and the package substrate 100 .

Subsequently, two second semiconductor devices 120a and 120b may be stacked on the first semiconductor device 110 to partially cover the first semiconductor device 110 . The second semiconductor devices 120a and 120b may partially overlap the first semiconductor device 110 . A portion of the upper surface of the first semiconductor device 110 may be exposed by the second semiconductor devices 120a and 120b.

The second semiconductor devices 120a and 120b may be spaced apart from each other on the first semiconductor device 110 . The second semiconductor devices 120a and 120b may be stacked on the first semiconductor device 110 via the adhesive layer 124 . The adhesive layer 124 may include a polymer material having excellent thermal conductivity. Examples of the polymer material include thermally conductive adhesive tape, thermally conductive grease, and thermally conductive adhesive.

Chip pads of the second semiconductor devices 120a and 120b may be connected to substrate pads on the upper surface of the package substrate 100 by performing a wire bonding process. The chip pads of the second semiconductor devices 120a and 120b may be electrically connected to the substrate pads of the package substrate 100 by bonding wires 122a and 122b.

5 and 6 , a heat dissipation insulating film 130 is coated on the first and second semiconductor devices 110, 120a, and 120b, and the first exposed by the second semiconductor devices 120a, 120b A first conductive heat dissipation member 142 may be formed on the heat dissipation insulating layer 130 above the first semiconductor device 110 . Second conductive heat dissipation members 143 may be formed on the heat dissipation insulating layer 130 over the second semiconductor devices 120a and 120b.

In example embodiments, the heat dissipation insulating film 130 is conformally applied on the exposed surfaces of the package substrate 100 and the first and second semiconductor devices 110, 120a, and 120b by a spray coating process. It can be. An insulating material may be sprayed on the exposed surfaces of the package substrate 100 and the first and second semiconductor devices 110, 120a, and 120b using a spray nozzle to form a heat dissipation insulating film 130 having a uniform thickness. can

The insulating material may have excellent thermal conductivity. The insulating material may have high thermal conductivity including silica (SiO2), aluminum oxide (Al2O3), boron nitride (BN), aluminum nitride (AlN), ceramics coated metal balls, etc. there is.

Subsequently, the first conductive heat dissipation member 142 may be formed by a dispensing process, a screen printing process, or the like. For example, the first conductive heat dissipation member 142 may be formed by dispensing a metal paste on the heat dissipation insulating layer 130 on the upper portion of the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. can In addition, the second conductive heat dissipation members 143 may be formed by dispensing the metal paste on the heat dissipation insulating layer 130 above the second semiconductor devices 120a and 120b.

By dispensing the metal paste a plurality of times using a dispenser, the first and second conductive heat dissipation members 142 and 143 may be formed at desired locations and in desired shapes. The metal paste may include a metal material such as gold (Au), silver (Ag), or copper (Cu) and may have high thermal conductivity.

The first conductive heat dissipation member 142 may be formed to have a pillar shape extending upward from the surface of the heat dissipation insulating layer 130 between the second semiconductor devices 120a and 120b. The first conductive heat dissipation member 142 may contact the heat dissipation insulating layer 130 on sidewalls of the second semiconductor devices 120a and 120b. Alternatively, the first conductive heat dissipation member 142 may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b.

The second conductive heat dissipation member 143 may be formed to extend laterally on the heat dissipation insulating layer 130 on the second semiconductor devices 120a and 120b. The second conductive heat dissipation member 143 may contact the sidewall of the first conductive heat dissipation member 142 . Alternatively, the second conductive heat dissipation member 143 may be spaced apart from the sidewall of the first conductive heat dissipation member 142 .

The second conductive heat dissipation member 142 may be integrally formed with the first conductive heat dissipation member 143 . The second conductive heat dissipation member 142 may have the same height as the height of the first conductive heat dissipation member 142 from the package substrate 100 .

Referring to FIG. 7 , a molding member 150 covering at least a portion of the first and second semiconductor devices 110 , 120a and 120b may be formed on the upper surface of the package substrate 100 . The molding member 150 may be formed to expose upper surfaces of the first and second conductive heat dissipation members 142 and 143 . An insulating material such as an epoxy molding compound is applied on the top surface of the package substrate 100 and the top of the applied insulating material is ground to expose the top surfaces of the first and second conductive heat dissipation members 142 and 143. can The molding member 150 may have the same height as the heights of the first and second conductive heat dissipation members 142 and 143 from the package substrate 100 .

Subsequently, the semiconductor package 10 may be completed by forming external connection members 104 on the external connection pads on the lower surface of the package substrate 100 .

8 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 1 except for a conductive heat dissipation member. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 8 , the conductive heat dissipation member 140 of the semiconductor package 11 is disposed on the heat dissipation insulating layer 130 over the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. The first conductive heat dissipation member 142 and the second conductive heat dissipation members 143 disposed on the heat dissipation insulating layer 130 above the second semiconductor devices 120a and 120b may be included.

In example embodiments, the molding member 150 may include through holes 151 exposing top surfaces of the heat dissipation insulating layer 130 on the first semiconductor device 110 and the second semiconductor devices 120a and 120b. can have A conductive heat dissipation member 140 may be filled in the through hole 151 .

The width of the through hole 151 may gradually decrease as it goes downward. Accordingly, the width of the conductive heat dissipation member 140 may gradually increase toward the top.

Hereinafter, a method of manufacturing the semiconductor package of FIG. 8 will be described.

9 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring to FIG. 9 , processes similar to those described with reference to FIGS. 3 to 5 are performed to dissipate heat on the first and second semiconductor devices 110 , 120a and 120b on the package substrate 100 . A molding member 150 may be formed on the upper surface of the package substrate 100 after coating the insulating layer 130 to cover the first and second semiconductor devices 110 , 120a and 120b.

10 and 11 , a conductive heat dissipation member 140 extending upward from the heat dissipation insulating film 300 on the first and second semiconductor devices 110, 120a, and 120b is formed in a molding member 150. can

First, the molding member 150 may be partially removed to form a through hole 151 exposing a portion of an upper surface of the heat dissipation insulating layer 300 . For example, the through hole 151 may be formed by an etching process, a laser drilling process, or the like.

Subsequently, a conductive material may be filled in the through hole 151 of the molding member 150 to form a conductive heat dissipation member 140 contacting the heat dissipation insulating layer 300 . The conductive material may be a metal paste including a metal material such as gold (Au), silver (Ag), or copper (Cu). The conductive heat dissipation member 140 may be exposed from the molding member 150 .

The conductive heat dissipation member 140 includes the first conductive heat dissipation member 142 and the second semiconductor disposed on the heat dissipation insulating layer 130 over the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. The devices 120a and 120b may include a second conductive heat dissipation member 143 disposed on the heat dissipation insulating layer 130 above.

12 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 1 except for the structure of the conductive heat dissipation member. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 12 , the conductive heat dissipation member 140 of the semiconductor package 12 is disposed on the heat dissipation insulating layer 130 over the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. The first conductive heat dissipation member 142 and the second conductive heat dissipation members 143 disposed on the heat dissipation insulating layer 130 over the second semiconductor devices 120a and 120b.

In example embodiments, the heat dissipation insulating layer 130 may cover the bonding wires 122a and 122b on the second semiconductor devices 120a and 120b. The second conductive heat dissipation member 143 may laterally extend to cover the front surfaces of the second semiconductor devices 120a and 120b. The second conductive heat dissipation member 143 may extend to an area where the bonding wires 122a and 122b on the second semiconductor devices 120a and 120b are disposed. The second conductive heat dissipation member 143 may cover the bonding wires 122a and 122b on the second semiconductor devices 120a and 120b. A heat dissipation insulation layer 130 may be interposed between the bonding wires 122a and 122b and the second conductive heat dissipation member 143 .

When the insulating material is sprayed on the exposed front surface of the package substrate 100 using a spray nozzle, the spray may cover surfaces of the bonding wires 122a and 122b on the second semiconductor devices 120a and 120b. there is. Accordingly, the bonding wires 122a and 122b may be coated with the heat dissipation insulating layer 130 .

Therefore, since the bonding wires 122a and 122b are electrically insulated by the heat dissipation insulating film 130, the second conductive heat dissipation member 143 can be formed in a wider area at a desired location. Accordingly, heat dissipation performance of the system-in-package may be improved.

13 is a cross-sectional view illustrating a semiconductor package according to example embodiments. FIG. 14 is a perspective view illustrating a part of the semiconductor package of FIG. 13 . The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 1 except for the second semiconductor device and the conductive heat dissipation member. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIGS. 13 and 14 , the second semiconductor devices 120a and 120b of the semiconductor package 13 may include a plurality of stacked semiconductor chips. The second semiconductor device may include a high bandwidth memory (HBM) device.

In example embodiments, the two second semiconductor devices 120a and 120b may be spaced apart from each other on the first semiconductor device 110 . The second semiconductor devices 120a and 120b may include sequentially stacked buffer dies 121a and first to third memory dies 121b, 121c, and 121d. The buffer die 121a and the first to third memory dies 121b, 121c, and 121d may be electrically connected by through-silicon vias (TSVs) 125 . The buffer die 121a and the first to third memory dies 121b, 121c, and 121d may communicate data signals and control signals through through-silicon vias 330 . The buffer die 121a may be electrically connected to the first semiconductor device 110 through the plurality of conductive bumps 123 . In this embodiment, it is illustrated as including four stacked dies (chips) as a high-bandwidth memory device. However, it will be appreciated that it is not limited thereto.

The heat dissipation insulating layer 130 may be conformally coated on the exposed front surfaces of the package substrate 100 and the first and second semiconductor devices 110 , 120a and 120b. Accordingly, the top surface of the package substrate 100, the sidewall of the first semiconductor device 110, and the top surfaces and sidewalls of the second semiconductor devices 120a and 120b may be covered with the heat dissipation insulating layer 130.

In example embodiments, the conductive heat dissipation member 140 is disposed on the heat dissipation insulating layer 130 over the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. A heat dissipation member 142 may be included. The first conductive heat dissipation member 142 includes a conductive plate 142a and a conductive plate 142a extending laterally to surround the second semiconductor devices 120a and 120b on the heat dissipation insulating layer 130 on the top of the first semiconductor device 110 . ) may include at least one conductive pillar 142b extending upwardly.

The conductive plate 142a may be spaced apart from sidewalls of the second semiconductor devices 120a and 120b. Alternatively, the conductive plate 142a may contact the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b.

The conductive pillar 142b may have the same height as the heights of the second semiconductor devices 120a and 120b from the package substrate 100 . The conductive posts 142b may have the same width along the vertical direction. The conductive pillar 142b may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b. Alternatively, the conductive pillar 142b may contact the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b.

One conductive pillar 142b may be disposed between the second semiconductor devices 120a and 120b. Two conductive pillars 142b may be disposed outward from the second semiconductor devices 120a and 120b. However, it will be appreciated that the number and shape of the conductive pillars are not limited thereto.

The molding member 150 may be formed on the upper surface of the package substrate 100 to cover at least a portion of the first and second semiconductor devices 110 , 120a and 120b. The molding member 150 may be formed to expose upper surfaces of the conductive pillars 142b. The molding member 150 may fill a space between the second semiconductor devices 120a and 120b and the first conductive heat dissipation members 140 .

Hereinafter, a method of manufacturing the semiconductor package of FIGS. 13 and 14 will be described.

15 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring to FIGS. 15 and 16 , processes similar to those described with reference to FIGS. 3 and 4 are performed to form first and second semiconductor devices 110 , 120a and 120b on the package substrate 100 . can form

In example embodiments, two second semiconductor devices 120a and 120b may be spaced apart from each other on the first semiconductor device 110 .

The second semiconductor devices 120a and 120b may include sequentially stacked buffer dies 121a and first to third memory dies 121b, 121c, and 121d. The buffer die 121a and the first to third memory dies 121b, 121c, and 121d may be electrically connected by through-silicon vias (TSVs) 125 . The buffer die 121a and the first to third memory dies 121b, 121c, and 121d may communicate data signals and control signals through through-silicon vias 330 . The buffer die 121a may be electrically connected to the first semiconductor device 110 through the plurality of conductive bumps 123 .

Referring to FIGS. 17 and 18 , processes similar to those described with reference to FIGS. 5 and 6 are performed to form a heat dissipation insulating film 130 on the first and second semiconductor devices 110 , 120a and 120b. coating, and a first conductive heat dissipation member 142 may be formed on the heat dissipation insulating layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b.

In example embodiments, as shown in FIG. 18 , the metal paste is dispensed on the heat dissipation insulating film 130 on the top of the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. Thus, the conductive plate 142a may be formed. The conductive plate 142a may laterally extend to surround the second semiconductor devices 120a and 120b on the heat dissipation insulating layer 130 on the first semiconductor device 110 .

The conductive plate 142a may be spaced apart from sidewalls of the second semiconductor devices 120a and 120b. Alternatively, the conductive plate 142a may contact the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b.

Subsequently, as shown in FIG. 19 , the conductive pillars 142b may be formed by dispensing a metal paste on the conductive plate 142a.

The conductive pillar 142b may have the same height as the heights of the second semiconductor devices 120a and 120b from the package substrate 100 . The conductive posts 142b may have the same width along the vertical direction. The conductive pillar 142b may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b. Alternatively, the conductive pillar 142b may contact the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a and 120b.

Referring to FIG. 20 , a molding member 150 covering at least a portion of the first and second semiconductor devices 110 , 120a , and 120b may be formed on the top surface of the package substrate 100 . The molding member 150 may be formed to expose upper surfaces of the conductive pillars 142b. The molding member 150 may fill a space between the second semiconductor devices 120a and 120b and the first conductive heat dissipation members 140 .

Subsequently, the semiconductor package 12 may be completed by forming external connection members 104 on the external connection pads on the lower surface of the package substrate 100 .

21 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 1 except for conductive pillars. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 21 , the first conductive heat dissipation member 142 of the semiconductor package 14 is provided on the heat dissipation insulating layer 130 on the upper portion of the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. It may include a conductive plate 142a extending laterally to surround the two semiconductor devices 120a and 120b and at least one conductive pillar 142b extending upward from the conductive plate 142a.

In example embodiments, the molding member 150 may have a through hole 151 exposing an upper surface of the conductive plate 142a. A conductive pillar 142b may be filled in the through hole 151 .

The width of the through hole 151 may gradually decrease as it goes downward. Accordingly, the width of the conductive pillar 142b may gradually increase toward the top.

Hereinafter, a method of manufacturing the semiconductor package of FIG. 21 will be described.

22 to 24 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring to FIG. 22 , processes similar to those described with reference to FIGS. 15 to 20 are performed to dissipate heat on the first and second semiconductor devices 110 , 120a and 120b on the package substrate 100 . The insulating layer 130 may be coated and the conductive plate 142a may be formed on the heat dissipating insulating layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. Subsequently, a molding member 150 may be formed on the upper surface of the package substrate 100 to cover at least a portion of the first and second semiconductor devices 110, 120a, and 120b and the conductive plate 142a. The molding member 150 may be formed to expose upper surfaces of the second semiconductor devices 120a and 120b.

Referring to FIGS. 23 and 24 , a conductive pillar 142b extending upward from the conductive plate 142a may be formed in the molding member 150 .

First, the molding member 150 may be partially removed to form a through hole 151 exposing a portion of the upper surface of the conductive plate 142a. For example, the through hole 151 may be formed by a laser drilling process.

Subsequently, a conductive material may be filled in the through hole 151 of the molding member 150 to form a conductive pillar 142b contacting the conductive plate 142a. The conductive material may be a metal paste including a metal material such as gold (Au), silver (Ag), or copper (Cu). The conductive pillar 142b may be exposed from the molding member 150 .

25 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 13 except for the first conductive heat dissipation member. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 25 , the semiconductor package 15 is a first conductive heat dissipation member (disposed on the heat dissipation insulating layer 130 above the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b). 142) may be included. The first conductive heat dissipation member 142 may be disposed to surround the second semiconductor devices 120a and 120b. The first conductive heat dissipation member 142 may contact the heat dissipation insulating layer 130 on sidewalls of the second semiconductor devices 120a and 120b.

In example embodiments, an upper surface of the package substrate 100 exposed by the first semiconductor device 110 may be coated with a heat dissipation insulating layer 130 . The first conductive heat dissipation member 142 may be disposed on the heat dissipation insulating layer 130 on the package substrate 100 exposed by the first semiconductor device 110 . The first conductive heat dissipation member 142 may not cover all of the exposed surface of the package substrate 100 . For example, the surface of the peripheral area of the package substrate 100 may not be covered by the first conductive heat dissipation member 142 .

Hereinafter, a method of manufacturing the semiconductor package of FIG. 25 will be described.

26 and 27 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring to FIG. 26 , processes similar to those described with reference to FIGS. 15 to 17 are performed to form a heat dissipation insulating film 130 on the first and second semiconductor devices 110 , 120a and 120b on the package substrate 100 . ) can be coated. Subsequently, a first conductive heat dissipation member 142a may be formed on the heat dissipation insulation layer 130 on the upper portion of the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b.

The first conductive heat dissipation member 142 may be disposed on the heat dissipation insulating layer 130 on the package substrate 100 exposed by the first semiconductor device 110 . The first conductive heat dissipation member 142 may not cover all of the exposed surface of the package substrate 100 . For example, the surface of the peripheral area of the package substrate 100 may not be covered by the first conductive heat dissipation member 142 .

Referring to FIG. 27 , a molding member 150 covering at least a portion of the first and second semiconductor devices 110 , 120a and 120b may be formed on an upper surface of the package substrate 100 . The molding member 150 may be formed on the heat dissipation insulating layer 130 on the package substrate 100 exposed by the first conductive heat dissipation member 142 .

28 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 13 except that a third conductive heat dissipation member is added. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 28 , the semiconductor package 16 may further include a third conductive heat dissipation member 144 disposed on the heat dissipation insulating layer 130 above the package substrate 100 .

In example embodiments, an upper surface of the package substrate 100 exposed by the first semiconductor device 110 may be coated with a heat dissipation insulating layer 130 . The third conductive heat dissipation member 144 may be disposed on the heat dissipation insulating layer 130 on the package substrate 100 exposed by the first semiconductor device 110 .

The third conductive heat dissipation member 144 may be formed together when forming the conductive pillar 142b of the first conductive heat dissipation member 142 . For example, the third conductive heat dissipation member 144 may be formed by dispensing a metal paste on the heat dissipation insulating layer 130 on the upper portion of the package substrate 100 exposed by the first semiconductor device 110 . The third conductive heat dissipation member 144 may have the same height as the heights of the second semiconductor devices 120a and 120b and the conductive pillar 122b from the package substrate 100 .

The molding member 150 may be formed to expose upper surfaces of the conductive pillars 142b and the third conductive heat dissipation member 144 . The molding member 150 may fill a space between the second semiconductor devices 120a and 120b, the first conductive heat dissipation members 140 and the third conductive heat dissipation members 144 .

29 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 13 except for the first conductive heat dissipation member and the third conductive heat dissipation member. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 29 , the semiconductor package 16 includes a first conductive heat dissipation member disposed on the heat dissipation insulating layer 130 over the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b, and A third conductive heat dissipation member 144 disposed on the heat dissipation insulating layer 130 above the package substrate 100 may be included.

The first conductive heat dissipation member extends laterally on the heat dissipation insulating film 130 over the first semiconductor device 110 and on the heat dissipation insulating film 130 over the package substrate 100 exposed by the first semiconductor device 110 . and a conductive plate 142c extending upwardly from the conductive plate 142c on the upper portion of the first semiconductor device 110 exposed by the second semiconductor devices 120a and 120b. .

The third conductive heat dissipation member 144 may extend upward from the conductive plate 142c on the upper portion of the package substrate 100 exposed by the first semiconductor device 110 .

The third conductive heat dissipation member 144 may be formed together when forming the conductive pillar 142b of the first conductive heat dissipation member 142 . For example, the third conductive heat dissipation member 144 may be formed by dispensing a metal paste on the heat dissipation insulating layer 130 on the upper portion of the package substrate 100 exposed by the first semiconductor device 110 . The third conductive heat dissipation member 144 may have the same height as the heights of the second semiconductor devices 120a and 120b and the conductive pillar 122b from the package substrate 100 .

30 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 25 except that a ground wire of the first conductive heat dissipation member is added. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 30 , the package substrate 100 of the semiconductor package 17 may include a ground wire 116 electrically connected to the first conductive heat dissipation member 142 .

In example embodiments, the first conductive heat dissipation member 142 may be disposed on the heat dissipation insulating layer 130 on the package substrate 100 exposed by the first semiconductor device 110 . The ground wiring 116 may be electrically connected to the first conductive heat dissipation member 142 on the package substrate 100 to ground the first conductive heat dissipation member 142 .

31 is a cross-sectional view illustrating a semiconductor package according to example embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to FIG. 25 except that a heat sink is added. Accordingly, the same reference numerals denote the same components, and repeated description of the same components is omitted.

Referring to FIG. 31 , the semiconductor package 18 may further include a heat sink 160 covering the first conductive heat dissipation member 142 . The heat sink 160 may include a conductive adhesive layer 162 and a heat dissipation plate 164 .

The heat sink 160 may be thermally connected to the first conductive heat dissipation member 142 exposed by the molding member 150 . The heat sink 160 may have a planar area corresponding to that of the package substrate 100 .

An electronic device including a semiconductor package according to example embodiments includes, for example, a logic element such as a central processing unit (CPU, MPU) or an application processor (AP), for example, an SRAM device, a DRAM ( Including volatile memory devices such as DRAM devices, high-bandwidth memory (HBM) devices, etc., and non-volatile memory devices such as, for example, flash memory devices, PRAM devices, MRAM devices, RRAM devices, etc. can do. The electronic device may be applied to a TV, computer, portable computer, laptop computer, personal portable terminal, tablet, mobile phone, digital music player, and the like.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand that you can.

10, 11, 12, 13, 14, 15, 16, 17, 18, 19: semiconductor package
100: package substrate 104: external connection member
110: first semiconductor device 112, 123: conductive bump
114: adhesive 116: ground wiring
120a, 120b: second semiconductor device 121a: buffer die
121b, 121c, 121d: memory die 122a, 122b: bonding wire
124: adhesive layer 130: heat dissipation insulating film
140: conductive heat dissipation member 142: first conductive heat dissipation member
142a, 124c: conductive plate 142b: conductive pillar
143: second conductive heat dissipation member 144: third conductive heat dissipation member
150: molding member 151: through hole
160: heat sink 162: conductive adhesive layer
164: heat dissipation plate

Claims (20)

package substrate;
a first semiconductor device disposed on the package substrate;
at least one second semiconductor device stacked on the first semiconductor device to partially cover the first semiconductor device;
a heat dissipation insulating film coated on the first and second semiconductor devices;
a first conductive heat dissipation member disposed on the heat dissipation insulating film over the first semiconductor device exposed by the second semiconductor device; and
a molding member covering the first and second semiconductor devices on the package substrate;
the molding member covers a first portion of an upper surface of the at least one second semiconductor device;
the first conductive heat dissipation member covers a second portion of an upper surface of the at least one second semiconductor device;
The semiconductor package of claim 1 , wherein the molding member is not formed between the first conductive heat dissipation member and a second portion of an upper surface of the at least one second semiconductor device. According to claim 1,
The semiconductor package further comprises a second conductive heat dissipation member disposed on the heat dissipation insulating layer over the second semiconductor device. The semiconductor package of claim 2 , wherein the second conductive heat dissipation member is integrally formed with the first conductive heat dissipation member. The semiconductor package of claim 2 , wherein the second conductive heat dissipation member has the same height as the first conductive heat dissipation member. The semiconductor package of claim 1 , wherein an upper surface of the first conductive heat dissipation member is exposed by the molding member. The semiconductor package of claim 1 , wherein the second semiconductor device is electrically connected to the package substrate by bonding wires. The semiconductor package of claim 6 , wherein the heat dissipation insulating layer covers the bonding wires. According to claim 7,
and a second conductive heat dissipation member disposed on the heat dissipation insulating film over the second semiconductor device and covering the bonding wires on the second semiconductor device. package substrate;
a first semiconductor device disposed on the package substrate;
at least one second semiconductor device stacked on the first semiconductor device to partially cover the first semiconductor device;
a heat dissipation insulating film coated on the first and second semiconductor devices;
a first conductive heat dissipation member disposed on the heat dissipation insulating film over the first semiconductor device exposed by the second semiconductor device; and
a molding member covering the first and second semiconductor devices on the package substrate;
The first conductive heat dissipation member
a conductive plate extending laterally on the heat dissipation insulating film to surround a sidewall of the second semiconductor device; and
at least one conductive pillar extending upwardly from the conductive plate;
A lower surface of the conductive plate is positioned equal to or higher than a lower surface of the second semiconductor device. 10. The semiconductor package of claim 9, wherein the conductive pillar gradually increases in width toward the top. 10. The semiconductor package of claim 9, wherein the conductive pillars have the same width along a vertical direction. 10. The method of claim 9, wherein the upper surface of the package substrate is coated with the heat dissipation insulating film,
The semiconductor package further includes a third conductive heat dissipation member disposed on the heat dissipation insulating layer over the package substrate. 10. The method of claim 9, wherein an upper surface of the package substrate is coated with the heat dissipation insulating film, and the conductive plate is formed on the heat dissipation insulating film over the package substrate,
The first conductive heat dissipation member further includes at least one second conductive pillar extending upward from the conductive plate on the package substrate. 14. The semiconductor package of claim 13, wherein the package substrate includes a ground wire electrically connected to the first conductive heat dissipation member. The semiconductor package of claim 1 , further comprising a heat sink covering the first conductive heat dissipation member. package substrate;
a first semiconductor device disposed on the package substrate;
at least one second semiconductor device stacked on the first semiconductor device to partially cover the first semiconductor device;
a heat dissipation insulating film coated on the package substrate and the first and second semiconductor devices;
a first conductive heat dissipation member disposed on the heat dissipation insulating film over the first semiconductor device exposed by the second semiconductor device; and
a molding member covering the first and second semiconductor devices on the package substrate;
The electronic device of claim 1 , wherein an upper surface of the package substrate exposed by the first semiconductor device is coated with the heat dissipation insulating film. 17. The electronic device of claim 16, wherein the second semiconductor device comprises a high bandwidth memory device. According to claim 16,
The electronic device further comprising a second conductive heat dissipation member disposed on the heat dissipation insulating layer over the second semiconductor device. The method of claim 16, wherein the first conductive heat dissipation member
a conductive plate extending laterally on the heat dissipation insulating film to surround a sidewall of the second semiconductor device; and
An electronic device comprising at least one conductive pillar extending upwardly from the conductive plate. According to claim 16,
The electronic device further comprising a third conductive heat dissipation member disposed on the heat dissipation insulating layer on the package substrate.

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