KR20210033057A - 메모리 디바이스와 연관된 수신기를 위한 트레이닝 절차 - Google Patents

메모리 디바이스와 연관된 수신기를 위한 트레이닝 절차 Download PDF

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Publication number
KR20210033057A
KR20210033057A KR1020217007438A KR20217007438A KR20210033057A KR 20210033057 A KR20210033057 A KR 20210033057A KR 1020217007438 A KR1020217007438 A KR 1020217007438A KR 20217007438 A KR20217007438 A KR 20217007438A KR 20210033057 A KR20210033057 A KR 20210033057A
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KR
South Korea
Prior art keywords
reference voltage
unit interval
offset
training
level
Prior art date
Application number
KR1020217007438A
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English (en)
Korean (ko)
Inventor
피터 메이어
토마스 하인
마틴 브록스
볼프강 안톤 스피어클
미카엘 디이터 리히터
Original Assignee
마이크론 테크놀로지, 인크
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Application filed by 마이크론 테크놀로지, 인크 filed Critical 마이크론 테크놀로지, 인크
Publication of KR20210033057A publication Critical patent/KR20210033057A/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Dram (AREA)
KR1020217007438A 2018-08-21 2019-08-13 메모리 디바이스와 연관된 수신기를 위한 트레이닝 절차 KR20210033057A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862720817P 2018-08-21 2018-08-21
US62/720,817 2018-08-21
US16/538,329 2019-08-12
US16/538,329 US10997095B2 (en) 2018-08-21 2019-08-12 Training procedure for receivers associated with a memory device
PCT/US2019/046398 WO2020041045A1 (fr) 2018-08-21 2019-08-13 Procédure d'apprentissage destinée à des récepteurs associés à un dispositif de mémoire

Publications (1)

Publication Number Publication Date
KR20210033057A true KR20210033057A (ko) 2021-03-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020217007438A KR20210033057A (ko) 2018-08-21 2019-08-13 메모리 디바이스와 연관된 수신기를 위한 트레이닝 절차

Country Status (5)

Country Link
US (2) US10997095B2 (fr)
EP (1) EP3841574A4 (fr)
KR (1) KR20210033057A (fr)
CN (1) CN112567461B (fr)
WO (1) WO2020041045A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10997095B2 (en) * 2018-08-21 2021-05-04 Micron Technology, Inc. Training procedure for receivers associated with a memory device
KR20220086948A (ko) 2020-12-17 2022-06-24 삼성전자주식회사 기준 전압 트레이닝을 수행하는 수신기 및 이를 포함하는 메모리 시스템
KR20230056315A (ko) 2021-10-20 2023-04-27 삼성전자주식회사 멀티 레벨 신호 수신을 위한 수신기 및 이를 포함하는 메모리 장치
KR20230064847A (ko) 2021-11-04 2023-05-11 삼성전자주식회사 메모리 장치, 호스트 장치 및 메모리 장치의 구동 방법

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DE60238602D1 (de) 2001-04-04 2011-01-27 Quellan Inc Verfahren und system zum decodieren von mehrpegelsignalen
US6920540B2 (en) 2001-10-22 2005-07-19 Rambus Inc. Timing calibration apparatus and method for a memory device signaling system
CN100583859C (zh) * 2003-04-14 2010-01-20 Nxp股份有限公司 无线通信系统中的脉冲检测
US7590175B2 (en) * 2003-05-20 2009-09-15 Rambus Inc. DFE margin test methods and circuits that decouple sample and feedback timing
US7158899B2 (en) 2003-09-25 2007-01-02 Logicvision, Inc. Circuit and method for measuring jitter of high speed signals
US7447971B2 (en) * 2004-05-14 2008-11-04 Hewlett-Packard Development Company, L.P. Data recovery systems and methods
US7991098B2 (en) * 2007-10-31 2011-08-02 Micron Technology, Inc. Method and apparatus for training the reference voltage level and data sample timing in a receiver
US20090219776A1 (en) * 2008-02-29 2009-09-03 Xian Liu Non-volatile memory device with plural reference cells, and method of setting the reference cells
KR101423052B1 (ko) * 2008-06-12 2014-07-25 삼성전자주식회사 메모리 장치 및 읽기 레벨 제어 방법
US8683164B2 (en) * 2009-02-04 2014-03-25 Micron Technology, Inc. Stacked-die memory systems and methods for training stacked-die memory systems
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US10997095B2 (en) * 2018-08-21 2021-05-04 Micron Technology, Inc. Training procedure for receivers associated with a memory device

Also Published As

Publication number Publication date
CN112567461B (zh) 2024-09-20
US20210318968A1 (en) 2021-10-14
EP3841574A4 (fr) 2022-04-20
US11500794B2 (en) 2022-11-15
US20200065267A1 (en) 2020-02-27
EP3841574A1 (fr) 2021-06-30
WO2020041045A1 (fr) 2020-02-27
CN112567461A (zh) 2021-03-26
US10997095B2 (en) 2021-05-04

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