KR20210024870A - Printed circuit board and package board - Google Patents

Abstract

According to an embodiment of the present invention, a printed circuit board includes: an insulating layer; a plurality of first pads disposed on an upper surface of the insulating layer; a plurality of second pads disposed on a lower surface of the insulating layer; a first device mounted on any one of the plurality of first pads; a second device mounted on one of the plurality of second pads; a first molding layer disposed on the upper surface of the insulating layer and molding the first device; a second molding layer disposed on the lower surface of the insulating layer and molding the second device; a first post bump disposed on any one of the plurality of second pads; and a second post bump disposed on any one of the plurality of first pads. The present invention provides the printed circuit board having a novel structure and a package board including the same.

Description

Printed circuit board and package board including the same

The embodiment relates to a printed circuit board and a package board including the same.

In general, the package substrate has a form in which a first substrate to which a memory chip is attached and a second substrate to which a processor chip is attached are connected into one.

Such a package substrate is advantageous in that a processor chip and a memory chip are manufactured as one package, thereby reducing a mounting area of a chip and enabling high-speed signal transmission through a short path.

Due to these advantages, the package substrate as described above has been widely applied to mobile devices and the like.

1 is a cross-sectional view showing a package substrate according to the prior art.

Referring to FIG. 1, the package substrate includes a first substrate 20 and a second substrate 30 attached to the first substrate 20.

In addition, the first substrate 20 includes a first insulating layer 1, a circuit pattern 2 formed on at least one surface of the first insulating layer 1, and a second insulating layer formed on the first insulating layer 1. Layer (2), a third insulating layer (3) formed under the first insulating layer (1), a circuit pattern (4) formed on at least one surface of the first insulating layer (1), a first insulating layer (1) And a conductive via 5 formed in at least one of the second insulating layer 2 and the second insulating layer 3, a pad 6 formed on the upper surface of the second insulating layer 2, and the pad ( 6) A plurality of adhesive pastes 7 formed thereon, a memory chip 8 formed on at least one of the plurality of adhesive pastes 7 and the second insulating layer 2, and the And a first passivation layer 10 exposing a partial upper surface of the pad 6 and a second passivation layer 9 formed on the passivation layer 10 to cover the memory chip 8.

In addition, the second substrate 30 includes a fourth insulating layer 11, a circuit pattern 12 formed on at least one surface of the fourth insulating layer 11, and a pad formed on at least one surface of the fourth insulating layer 11. (13), a conductive via (14) formed inside the fourth insulating layer (11), a processor chip (15) formed on the fourth insulating layer (11), the processor chip (15) and the pad (13) It includes a connecting member (S) to connect.

The package substrate according to the prior art shown in FIG. 1 is a schematic diagram of a package on package (PoP) to which TMV (Through Mold Via) technology is applied to which laser technology is applied.

In the TMV technology, after molding the first substrate 20 as described above, a conductive via connected to the pad is formed through a laser process, and accordingly, solder balls (adhesive paste) are printed in the conductive via.

In addition, the second substrate 30 is attached on the first substrate 20 by the printed solder balls 7.

However, the prior art as described above is a method of connecting the first substrate and the second substrate using the solder balls 7, and thus there is a problem in that there is a limitation in coping with the fine pitch.

In addition, since the prior art uses the solder balls 7 as described above, issues such as solder crack, bridge, and solder collapse may occur.

The embodiment provides a printed circuit board having a new structure and a package board including the same.

In addition, the embodiment provides a printed circuit board that is easy to respond to fine pitches and a package board including the same.

In addition, the embodiment provides a printed circuit board capable of minimizing the occurrence of warpage by maintaining the balance of the upper and lower parts, and a package substrate including the same.

In addition, the embodiment provides a printed circuit board capable of improving the reliability of a post bump and a package board including the same.

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks that are not mentioned are clear to those of ordinary skill in the technical field to which the proposed embodiment belongs from the following description. Will be able to understand

The printed circuit board according to the embodiment includes an insulating layer; A plurality of first pads disposed on an upper surface of the insulating layer; A plurality of second pads disposed on a lower surface of the insulating layer; A first element mounted on any one of the plurality of first pads; A second element mounted on any one of the plurality of second pads; A first molding layer disposed on an upper surface of the insulating layer and molding the first device; A second molding layer disposed on a lower surface of the insulating layer and molding the second device; A first post bump disposed on one of the second pads among the plurality of second pads; And a second post bump disposed on any one of the plurality of first pads.

In addition, the first post bump and the second post bump are disposed to have a mutually symmetrical structure with respect to the insulating layer.

In addition, the lower surface of the second molding layer is positioned on the same plane as the lower surface of the second device, and the upper surface of the first molding layer is positioned higher than the upper surface of the first device.

In addition, a first protective layer disposed between the upper surface of the insulating layer and the first molding layer; And a second protective layer disposed between the lower surface of the insulating layer and the second molding layer.

In addition, a lower surface of the first post bump is positioned higher than a lower surface of the second molding layer, and an upper surface of the second post bump is positioned lower than an upper surface of the first molding layer.

Further, an upper surface of the first post bump directly contacts a lower surface of the second pad, and a lower surface of the second post bump directly contacts an upper surface of the first pad.

In addition, the entire area of the side surface of the first post bump includes a first portion in direct contact with the second protective layer and a second portion in direct contact with the second molding layer, and The entire area of the side surface includes a third portion in direct contact with the first protective layer and a fourth portion in direct contact with the first molding layer.

Further, the entire area of the side surface of the first post bump directly contacts the second molding layer, and the entire area of the side surface of the second post bump directly contacts the first molding layer.

In addition, a first seed layer disposed between the lower surface of the insulating layer and the second pad; And a second seed layer disposed between the upper surface of the insulating layer and the first pad, wherein the first post bump is an electroplating layer formed using the first seed layer, and the second post bump, It is an electroplating layer formed by using the second seed layer.

In addition, the first seed layer may include a first region disposed between the lower surface of the insulating layer and the second pad, and extending from the first region, and disposed between the lower surface of the insulating layer and the second protective layer. A second region, wherein the second seed layer includes a third region disposed between an upper surface of the insulating layer and the first pad, and extending from the third region, and the upper surface of the insulating layer and the third region And a fourth region disposed between the first protective layer.

In addition, the first seed layer may include a first region disposed between the lower surface of the insulating layer and the second pad, and spaced apart from the first region, and disposed between the lower surface of the insulating layer and the second protective layer. A second region, wherein the second seed layer comprises a third region disposed between the upper surface of the insulating layer and the first pad, and spaced apart from the third region, and the upper surface of the insulating layer and the third region And a fourth region disposed between the first protective layer.

In addition, the first seed layer includes a fifth region connected between the first region and the second region and disposed between a lower surface of the insulating layer and the second molding layer, and the second seed layer And includes a sixth region connected between the third region and the fourth region and disposed between the upper surface of the insulating layer and the first molding layer.

In addition, the vertical width or height of each of the first and second post bumps has a range between 0.4 times and 0.7 times the horizontal width of each of the first and second post bumps.

Meanwhile, the package substrate according to the embodiment includes an insulating layer, a plurality of first pads disposed on an upper surface of the insulating layer, a plurality of second pads disposed on a lower surface of the insulating layer, and the plurality of first pads. A first device mounted on one of the first pads, a second device mounted on one of the plurality of second pads, and the first device disposed on the upper surface of the insulating layer. A first molding layer to be molded, a second molding layer disposed on a lower surface of the insulating layer to mold the second device, and a first post disposed on any one second pad of the plurality of second pads A printed circuit board including a bump and a second post bump disposed on one of the first pads among the plurality of first pads; A first solder ball disposed on a lower surface of the first post bump; A second solder ball disposed on an upper surface of the second post bump; A main board attached to the first post bump of the printed circuit board through the first solder ball; And an upper package attached to the second post bump of the printed circuit board through the second solder ball, wherein a lower surface of the second molding layer of the printed circuit board is flush with the lower surface of the second device. It is located on the upper surface, and the lower surface of the second element is disposed directly facing the upper surface of the main board.

In addition, the upper surface of the first post bump directly contacts the lower surface of the second pad, and the lower surface of the second post bump directly contacts the upper surface of the first pad, and the side surface of the first post bump The entire area is in direct contact with at least one of the second protective layer and the second molding layer, and the entire area of the side surface of the second post bump is at least one of the first protective layer and the first molding layer. Direct contact with Hana.

In addition, the printed circuit board may include a first seed layer disposed between a lower surface of the insulating layer and the second pad; And a second seed layer disposed between the upper surface of the insulating layer and the first pad, wherein the first post bump is an electroplating layer formed using the first seed layer, and the second post bump, It is an electroplating layer formed by using the second seed layer.

According to this embodiment, by forming a post bump on a printed circuit board and attaching an upper package or a main board using the post bump to manufacture a package substrate, it is possible to respond to a fine pitch, thereby increasing the productivity of the manufacturer. Can be maximized.

In addition, according to the present embodiment, by mounting the device on both sides of the printed circuit board, and disposing a molding part for molding the mounted device, it is possible to maintain the balance of the upper and lower parts of the printed circuit board compared to the conventional single-sided molding structure. As a result, the occurrence of warpage of the printed circuit board can be minimized.

In addition, according to the embodiment, by mounting the devices on both sides of the printed circuit board, both active or passive devices mounted on the existing upper package can be mounted on the printed circuit board, and accordingly, the total thickness of the package board Can be lowered.

In addition, according to the present embodiment, the lower surface of the lower molding part to which the main board is attached is placed on the same plane as the lower surface of the element mounted under the printed circuit board, thereby connecting the main board and the printed circuit board. Reliability can be improved.

In addition, according to the present embodiment, by disposing the post bumps on both sides of the printed circuit board, it is possible to improve the package balance compared to the conventional single-sided post bump arrangement structure, thereby minimizing occurrence of warpage.

In addition, according to the present embodiment, post bumps are disposed on both sides of the printed circuit board, so that heat dissipation can be made to both sides of the printed circuit board through the post bumps, and thus heat dissipation characteristics may be improved.

In addition, according to the present embodiment, it is possible to adjust the height of the post bump as much as the height of the device, thereby facilitating package design design.

In addition, according to the embodiment, a seed layer for electroplating is not separately formed under the post bump, and the post bump can be formed on the pad by using a seed layer located under the pad. Accordingly, it is not necessary to form a separate seed layer for the formation of the post bump, thereby simplifying the manufacturing process, solving the occurrence of cracks between the seed layers of the post bump, and thus reliability and durability of the product. Can improve. In addition, according to the embodiment, since the desmear process does not have to be separately performed on the solder resist, whitening of the solder resist due to the desmear solution can be prevented.

In addition, in the embodiment, the aspect ratio of the post bump is included in the range of 0.4 to 0.7, thereby improving the durability of the post bump.

1 is a cross-sectional view showing a package substrate according to the prior art.
2 is a view showing a printed circuit board according to the first embodiment.
3 is a diagram illustrating a structure of a second material included in an insulating layer of a circuit board according to an exemplary embodiment.
4 is a diagram illustrating an arrangement structure of a first material and a second material included in an insulating layer of a printed circuit board according to an exemplary embodiment.
5 is a diagram illustrating a structure of a post bump in a comparative example.
6 is a diagram illustrating a structure of a post bump according to the first embodiment.
7 is a diagram illustrating a structure of a post bump according to a second embodiment.
8 is a diagram illustrating a structure of a post bump according to a third embodiment.
9 to 15 are views illustrating a method of manufacturing a printed circuit board according to the first embodiment shown in FIG. 2 in order of processes.
16 is a diagram illustrating a package substrate according to the first embodiment.
17 is a diagram illustrating a printed circuit board according to a second embodiment.
18 is a diagram illustrating a package substrate according to a second embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical idea of the present invention is not limited to some of the embodiments to be described, but may be implemented in a variety of different forms, and within the scope of the technical idea of the present invention, one or more of the constituent elements may be selectively selected between the embodiments. It can be combined with and substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention are generally understood by those of ordinary skill in the art, unless explicitly defined and described. It can be interpreted as a meaning, and terms generally used, such as terms defined in a dictionary, may be interpreted in consideration of the meaning in the context of the related technology.

In addition, terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may also include the plural form unless specifically stated in the phrase, and when described as “at least one (or more than one) of A and (and) B and C”, it may be combined with A, B, and C. It may contain one or more of all possible combinations.

In addition, terms such as first, second, A, B, (a), and (b) may be used in describing the constituent elements of the embodiment of the present invention. These terms are only for distinguishing the component from other components, and are not limited to the nature, order, or order of the component by the term.

And, when a component is described as being'connected','coupled' or'connected' to another component, the component is not only directly connected, coupled, or connected to the other component, but also with the component. The case of being'connected','coupled', or'connected' due to another component between the other components may also be included.

In addition, when it is described as being formed or disposed on the “top (top) or bottom (bottom)” of each component, the top (top) or bottom (bottom) is one as well as when the two components are in direct contact with each other. It also includes the case where the above other component is formed or disposed between the two components.

In addition, when expressed as “up (up) or down (down)”, the meaning of not only an upward direction but also a downward direction based on one component may be included.

2 is a view showing a printed circuit board according to the first embodiment.

2, the printed circuit board 100 includes a first insulating layer 101, a circuit pattern 102, a via 103, a second insulating layer 103, a third insulating layer 104, and a first insulating layer. The pad 106, the second pad 107, the protective layer 108, the first molding layer 109, the second molding layer 110, the first connection part 111, the first element 112, the second A connection part 113, a second device 114, a third connection part 115, a third device 116 and a post bump 117 are included.

The first insulating layer 101 may be a core substrate.

The first insulating layer 101 may be a support substrate of a printed circuit board on which a single circuit pattern is formed, but may mean a region in which any one circuit pattern is formed among substrates having a plurality of stacked structures.

A second insulating layer 104 is formed on the first insulating layer 101, and a third insulating layer 105 is formed under the first insulating layer 101.

The first to third insulating layers 101, 104, and 105 form an insulating plate, and may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber-impregnated substrate. When included, may include epoxy-based insulating resins such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build-up Film), and otherly, polyimide-based resins may be included, but are specifically limited thereto. no.

The first to third insulating layers 101, 104, and 105 may be formed of different materials. For example, the first insulating layer 101 is an impregnated substrate including glass fibers, and the second and third insulating layers (104, 105) may be an insulating sheet formed of only resin.

The first insulating layer 101 is a central insulating layer and may be thicker than the second and third insulating layers 104 and 105.

An internal circuit pattern 102 is formed on at least one of the upper and lower portions of the first insulating layer 101.

The circuit pattern 102 is a conventional printed circuit board manufacturing process, such as additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process) method. It is possible, and detailed description is omitted here.

In addition, a via 103 is formed in the first insulating layer 101 to connect the internal circuit patterns 102 formed in different layers to each other.

An external circuit pattern (not shown) is also formed on the second insulating layer 104 formed on the first insulating layer 101 and the third insulating layer 105 formed on the lower side.

External circuit patterns (not shown) are also formed on the exposed surfaces of the second insulating layer 104 formed on the first insulating layer 101 and the third insulating layer 105 formed below the first insulating layer 101.

The external circuit pattern may mean the pads 106 and 107 shown in the drawings. That is, the external circuit pattern is formed by the same process as the pads 106 and 107, and is divided into a pattern and a pad according to their function.

That is, a circuit pattern is formed on the surfaces of the second insulating layer 104 and the third insulating layer 105, and depending on the function of the circuit pattern, some may be an external circuit pattern, and the rest may be chips or other substrates. It may be the pads 106 and 107 connected to each other.

In addition, vias are also formed inside the second insulating layer 104 and the third insulating layer 105.

The via 103 as described above forms a via hole that opens at least one of the first, second, and third insulating layers 101, 104, and 105 through a laser process, and the inside of the formed via hole is thus made of a metal paste. It can be formed by filling with.

At this time, the metal material forming the via 103 may be any one material selected from Cu, Ag, Sn, Au, Ni, and Pd, and the filling of the metal material is electroless plating, electrolytic plating, screen printing ( Screen Printing), sputtering, evaporation, ink jetting, and dispensing, any one of a combination of these may be used.

Meanwhile, the via hole may be formed by any one of mechanical, laser, and chemical processing.

When the via hole is formed by machining, methods such as milling, drilling, and routing may be used, and when formed by laser processing, a UV or CO ₂ laser method is used. In addition, when formed by chemical processing, the first, second and third insulating layers 101, 104, and 105 may be opened using a chemical containing aminosilane, ketones, or the like.

On the other hand, the laser processing is a cutting method that takes a desired shape by concentrating optical energy on the surface to melt and evaporate a part of the material. Even difficult composite materials can be processed.

In addition, the laser processing has a cutting diameter of at least 0.005mm, and has a wide range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. YAG laser is a laser that can process both copper foil layers and insulating layers, and CO ₂ laser is a laser that can process only insulating layers.

A protective layer 108 is formed on the surfaces of the second insulating layer 104 and the third insulating layer 105 (the surface exposed to the outside, the surface on which the pad is formed).

The protective layer 108 has an opening exposing an upper surface of the first pad 106.

That is, the protective layer 108 is to protect the surfaces of the second insulating layer 104 and the third insulating layer 105, and the front surface of the second insulating layer 104 and the third insulating layer 105 The first pad 106 and the second pad 107 are formed over and have an opening that opens the surface of the stacked structure.

The protective layer 108 may be formed of at least one or more layers using at least one of SR (Solder Resist), oxide, and Au. Preferably, the protective layer 108 may be a solder resist. In addition, the protective layer 108 may include an upper protective layer or a first protective layer disposed on the upper surface of the second insulating layer 104. In addition, the protective layer 108 may include a lower protective layer or a second protective layer disposed under the lower surface of the third insulating layer 105.

The first pad 106 exposed by the opening of the protective layer 108 is classified according to its function.

That is, the first pad 106 may include a pad connected to the first device 112 and a pad connected to the second device 114.

To this end, connection portions 111 and 113 may be disposed on the first pad 106. That is, the first connector 111 may be disposed on a pad on which the first element 112 is mounted among the first pads 106. In addition, a second connector 113 may be disposed on a pad on which the second element 114 is mounted among the first pads 106.

The first connection part 111 and the second connection part 113 may have a hexahedral shape. For example, cross-sections of the first connection part 111 and the second connection part 113 may have a rectangular shape. In more detail, cross-sections of the first connection part 111 and the second connection part 113 may have a rectangular or square shape. The first connection part 111 and the second connection part 113 may include gold (Au). For example, the first connection part 111 and the second connection part 113 may be gold bumps.

A first element 112 may be attached on the first connection part 111. In addition, a second element 114 may be attached on the second connection part 113.

The first device 112 and the second device 114 may be active devices and passive devices constituting a memory package. However, the embodiment is not limited thereto, and the first device 112 and the second device 114 may include other devices other than a memory package. For example, the first element 112 and the second element 114 are a drive IC chip, a diode chip, a power supply IC chip, a touch sensor IC chip, a multi-layer ceramic condencer (MLCC) chip, and a BGA. (Ball Grid Array) It may include at least one of a chip and a chip capacitor.

A first molding layer 109 is disposed on the upper protective layer or the first protective layer among the protective layers 108. The first molding layer 109 may be disposed on the upper protective layer or the first protective layer to cover the first element 112 and the second element 114. The first molding layer 109 may be formed of resin. The first molding layer 109 can protect the first element 112 and the second element 114 from an external environment by filling the first element 112 and the second element 114 therein. have. An upper surface of the first molding layer 109 may be positioned higher than an upper surface of the first element 112 and the second element 114. For example, a top surface of the first device 112 and a top surface of the second device 114 may be disposed to cover the top surface of the first molding layer 109.

Meanwhile, a second pad 107 is disposed on the lower surface of the third insulating layer 105. In addition, the second pad 107 may include a mounting pad on which the third element 116 is mounted, and a bump pad on which a post bump 117 for connection to an external main board is disposed.

A third connection part 115 may be disposed on the mounting pad of the second pad 107. In this case, the third connection part 115 may have a shape different from that of the first connection part 111 and the second connection part 113. For example, the third connection part 115 may have a spherical shape. Alternatively, the cross section of the third connection part 115 may have a circular shape. Alternatively, the third connection part 115 may have a wholly or partially rounded shape. As an example, the cross-sectional shape of the third connection part 115 may include a flat surface at one side and a curved surface at the other side opposite to the one side.

The third connection part 115 may have a size different from that of the first connection part 111 and the second connection part 113. For example, the third connection part 115 may be formed to have a size smaller than that of the first connection part 111 and the second connection part 113. The third connection part 115 is copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), bismuth (bi), silver ( At least one of Ag) and nickel (Ni) may be included. The third connection part 115 may be a solder bump. The third connection part 115 may be a solder ball, and accordingly, may be melted at the temperature of the reflow process.

The post bump 117 may be disposed under the lower surface of the second pad 107 or the bump pad exposed through the lower protective layer or the second protective layer.

The post bump 117 may protrude from the lower surface of the lower protective layer or the second protective layer. The post bump 117 may have the same upper and lower widths. In addition, the post bump 117 may have an upper width and a lower width different from each other. These post bumps 117 may have a column shape.

The post bump 117 may be composed of at least two or more. For example, the post bump 117 includes a first post bump 117 disposed on any one second pad formed on the left side of the second pad 107 and one of the first post bumps 117 formed on the right side. It may include a second post bump 117 disposed on the second pad.

In this case, the lower surface of the post bump 117 may be positioned higher than the lower surface of the third element 116. The post bump 117 may include a first part disposed in an opening of the lower protective layer or the second protective layer, and a second part protruding below a lower surface of the lower protective layer or the second protective layer.

In this case, the upper width and the lower width of the first part may be the same. In addition, the upper width and the lower width of the second part may be the same. Also, a width of the first part and a width of the second part may be the same. Also, differently, the width of the first part and the width of the second part may be different from each other. For example, the width of the second part may be larger than the width of the first part. Accordingly, the second part of the post bump 117 may be formed to extend to a lower surface of the lower protective layer or the second protective layer.

A surface treatment layer (not shown) may be disposed on the lower surface of the post bump 117. For example, a surface treatment layer for protecting the surface of the post bump 117 may be disposed on the lower surface of the post bump 117. The surface treatment layer may be formed by any one of a surface treatment method of OSP (Organic Solderability Preservative), electroless plating (ENEPIG), and EPIG (Thin-Nickel Electroless Palladium Immersion Gold). In addition, the surface treatment layer may be formed of soft gold composed of Ni/Au, and may have a thickness of 5 to 10 μm.

A second molding layer 110 is disposed under the lower protective layer or the second protective layer among the protective layers 108. The second molding layer 110 may be disposed on the lower protective layer or the second protective layer to cover the third device 116. The second molding layer 110 may be formed of resin. In this case, the second molding layer 110 may be disposed to cover the side of the third device 116. In addition, the second molding layer 110 may be disposed exposing the lower surface of the third device 116. In other words, the lower surface of the second molding layer 110 may be positioned on the same plane as the lower surface of the third element 116. This is, in a state in which the second molding layer 110 is formed to cover the lower surface of the third element 116, and the lower surface of the second molding layer 110 is the same as the lower surface of the third element 116. It may be formed by grinding the second molding layer 110 to be positioned on a plane.

As described above, the printed circuit board 100 in the first embodiment includes a first molding layer 109 for mounting a device on the insulating layers 101, 104, and 105, and molding the mounted device. do. In addition, the printed circuit board 100 according to the first embodiment includes a second molding layer 110 for mounting devices under the insulating layers 101, 104, and 105, and molding the mounted devices. In this way, the printed circuit board 100 may maintain the balance of both sides of the printed circuit board by not disposing the molding layer on only one side based on the insulating layer, but by disposing the molding layer on both sides, Accordingly, the occurrence of warpage can be minimized.

Meanwhile, the insulating layers 101, 104, and 105 in the embodiment may have a low dielectric constant.

That is, the first insulating layer 101 contains glass fibers. The glass fiber generally has a thickness of about 12 μm. Accordingly, the thickness of the first insulating layer 101 may have a thickness of 21 μm±2 μm including the thickness of the glass fiber. Specifically, the thickness of the first insulating layer 101 may range from 19 μm to 23 μm.

In contrast, glass fibers are not included in the second insulating layer 104 and the third insulating layer 105. Preferably, the second insulating layer 104 and the third insulating layer 105 may be composed of RCC. Accordingly, each thickness of the second insulating layer 104 and the third insulating layer 105 may have a thickness of 12 μm±2 μm. That is, each thickness of the second insulating layer 104 and the third insulating layer 105 may range from 10 μm to 14 μm.

In the embodiment, an insulating layer is formed using an RCC having a low dielectric constant, thereby reducing the thickness of the circuit board and providing a highly reliable circuit board in which signal loss is minimized even in a high frequency band. This can be achieved by the properties of the materials included in the second insulating layer 104 and the third insulating layer 105, which will be described in more detail below.

To this end, the second insulating layer 104 and the third insulating layer 105 may include a material capable of securing mechanical/chemical reliability with a low dielectric constant.

In detail, the second insulating layer 104 and the third insulating layer 105 may have a dielectric constant Dk of 3.0 or less. In more detail, the second insulating layer 104 and the third insulating layer 105 may have a dielectric constant of 2.03 to 2.7. Therefore, the second insulating layer 104 and the third insulating layer 105 may have a low dielectric constant, so when the insulating layer is applied to a circuit board for high frequency use, transmission loss according to the dielectric constant of the insulating layer is reduced. I can make it.

In addition, the second insulating layer 104 and the third insulating layer 105 may have a coefficient of thermal expansion of 50 ppm/°C or less. In detail, the second insulating layer 104 and the third insulating layer 105 may have a coefficient of thermal expansion of 15 ppm/°C to 50 ppm/°C.

Accordingly, the second insulating layer 104 and the third insulating layer 105 may have a low coefficient of thermal expansion, so that cracks in the insulating layer due to temperature changes may be minimized.

To this end, the second insulating layer 104 and the third insulating layer 105 may be formed of two materials. In detail, the second insulating layer 104 and the third insulating layer 105 may include a material in which two compounds are mixed. In detail, the second insulating layer 104 and the third insulating layer 105 may include a first compound and a second compound.

The first material and the second material may be included in a certain ratio range. In detail, the first material and the second material may be included in a ratio of 4:6 to 6:4.

In addition, the second insulating layer 104 and the third insulating layer 105 may further include inorganic particles. In detail, the second insulating layer 104 and the third insulating layer 105 may further include inorganic particles such as _{silicon dioxide (SiO 2 ).} The inorganic particles may be included in an amount of about 55% to 70% by weight with respect to the second insulating layer 104 and the third insulating layer 105 as a whole.

When the ratio of the inorganic particles is out of the above range, the coefficient of thermal expansion or the size of the dielectric constant is increased by the inorganic particles, so that the properties of the insulating layer may be deteriorated.

In addition, the first material and the second material may be chemically uncoupled with each other in the second insulating layer 104 and the third insulating layer 105. However, embodiments are not limited thereto, and the first material including the first compound and the second material including the second compound may be chemically bonded directly or by a separate linking group.

The first material may include a material having insulating properties. In addition, the first material may have high impact strength and thus improved mechanical properties. In detail, the first material may include a resin material. For example, the first material may include a first compound including polyphenyl ether (PPE) represented by Formula 1 below.

[Formula 1]

The first material may include a plurality of the first compounds, and the first compounds may be formed by chemically bonding to each other. In detail, as shown in Formula 2 below, the first compound may be linearly connected to each other by a covalent bond, that is, a pi-pi bond (π-π).

[Formula 2]

That is, the first compounds may be formed by chemically bonding with each other so that the first material has a molecular weight of about 300 to 500.

In addition, the second material may include a second compound. In detail, the second material may be formed by chemically bonding a plurality of second compounds to each other.

The second compound may include a material having a low dielectric constant and a coefficient of thermal expansion. In addition, the second compound may include a material having improved mechanical strength.

The second compound may include tricyclodecane and a terminal group connected to the tricyclodecane. The terminal group connected to the tricyclodecane may include various materials in which the second compounds may be connected to each other through a carbon double bond (C=C bonding). In detail, the terminal group connected to the tricyclodecane may include an acrylate group, an epoxide group, a carboxyl group, a hydroxyl group, and an isocyanate group.

The second compounds may be connected to each other with terminal groups connected to the tricyclodecane. Specifically, the second compounds are cross-linked with a double carbon bond (C = C bonding) between the terminal groups. To form a network structure.

3 is a diagram illustrating a structure of a second material included in an insulating layer of a circuit board according to an exemplary embodiment.

In detail, referring to FIG. 3, the second compounds may be cross-linked to form a network structure to be connected. That is, the second compounds may be an aggregate of bonds having a plurality of network structures.

Accordingly, the second material formed by the second compounds may have a low dielectric constant and a coefficient of thermal expansion according to material properties, and may have improved mechanical strength due to a network structure.

4 is a diagram for explaining an arrangement of the first material and the second material constituting the second insulating layer 104 and the third insulating layer 105.

The first material and the second material may be formed as a single phase in the insulating layer. Referring to FIG. 8, the first material connected by a covalent bond of the first compound may be disposed inside a second material formed by a second compound that is cross-linked with each other to form a network structure.

In detail, the first compound may be disposed inside the network structure of the second material formed by chemically bonding the second compound to prevent the first material and the second material from being separated.

That is, the second insulating layer 104 and the third insulating layer 105 may be formed as a single-phase structure without the first material and the second material being phase-separated and disposed in the insulating layer. Accordingly, the first material and the second material may have a low dielectric constant and a low coefficient of thermal expansion due to the material properties of the first material and the second material, and may be formed as a single phase, thereby having high mechanical strength.

Meanwhile, the post bump 117 in the embodiment may be formed using a plating seed layer (described later) used to form the second pad 107. Accordingly, in the printed circuit board 100 according to the embodiment, a separate seed layer for forming the post bump 117 may be omitted. In addition, the post bump 117 may be disposed in direct contact with the second pad 107. In addition, the post bump 117 may be disposed in direct contact with the lower protective layer or the second protective layer. That is, the upper surface of the post bump 117 may directly contact the lower surface of the second pad 107. In addition, a side surface of the post bump 117 may directly contact the lower protective layer or the second protective layer. That is, in the printed circuit board of the comparative example, a separate seed layer for electroplating the post bump was formed between the pads of the post bump. Accordingly, the printed circuit board of the comparative example has a structure in which the post bump and the pad do not directly contact each other.

That is, in the embodiment, a seed layer for electroplating is not separately formed under the post bump, and the post bump can be formed on the pad using a seed layer located under the pad. Accordingly, it is not necessary to form a separate seed layer for the formation of the post bump, thereby simplifying the manufacturing process, solving the occurrence of cracks between the seed layers of the post bump, and thus reliability and durability of the product. Can improve. In addition, according to the embodiment, since the desmear process does not have to be separately performed on the solder resist, whitening of the solder resist due to the desmear solution can be prevented.

Hereinafter, the structure of the post bump 117 will be described in more detail.

5 is a diagram illustrating a structure of a post bump in a comparative example, FIG. 6 is a diagram illustrating a structure of a post bump according to a first embodiment, and FIG. 7 is a diagram illustrating a structure of a post bump according to a second embodiment FIG. 8 is a diagram illustrating a structure of a post bump according to a third embodiment.

Referring to FIG. 5, the printed circuit board of the comparative example includes an insulating layer 41.

In addition, a pad 42 is disposed on the insulating layer 41. In this case, a first seed layer 43 for electroplating the pad 42 is disposed between the insulating layer 41 and the pad 42.

In addition, a protective layer 44 having an opening exposing at least a portion of an upper surface of the pad 42 is disposed on the insulating layer 41. In addition, a post bump 46 may be disposed on an upper surface of the pad 42 exposed through the opening of the protective layer 44. In this case, the post bump 46 may be formed through electroplating. That is, the post bump 46 has a predetermined height and is disposed on the pad 42 to have a protruding structure, and accordingly, the post bump 46 cannot be formed by non-electrolytic plating. Accordingly, the post bump 46 is formed by electroplating, and a second seed layer 45 is disposed on the pad 107 for this purpose. The second seed layer 45 may be disposed on an upper surface of the pad 42, an upper surface of the protective layer 44, and an inner wall of an opening of the protective layer 44, respectively.

That is, in the printed circuit board of the comparative example, the second seed layer 45 is disposed on the pad 42 to form the post bump 46. Accordingly, the printed circuit board of the comparative example had to perform an additional process of forming the second seed layer 45, and thus the manufacturing process was complicated or the manufacturing time was increased.

In addition, in the printed circuit board of the comparative example, whitening of the protective layer 44 occurs due to the solution during the desmear process of the second seed layer 45 formed by electroless plating. In addition, in the printed circuit board of the comparative example, the second seed layer 45 is disposed between the pad and the post bump, and the bump layer accordingly has a porous microstructure. In addition, this porous structure has a low density of metal, and accordingly, cracks are generated in the porous second seed layer 45 due to external impact or other physical force, and the post bump is destroyed accordingly, resulting in product reliability. However, there is a problem that the durability decreases rapidly.

In addition, the post bump of the comparative example had a width a and a vertical width b. At this time, the aspect ratio (b/a) of the post bump of the comparative example was included in the range of 0.8 to 2.0, and thus the durability of the post bump was low.

Referring to FIG. 6, the post bump of the first embodiment has a structure in which the second seed layer in the comparative example is omitted. In other words, the post bump of the first embodiment may be formed by electroplating on the pad 107 using the seed layer 107A used for electroplating the pad. 6 includes a SMD (Solder Mask Defined) type protective layer.

In the SMD type, a part of the upper surface of the pad 107 is exposed through the opening of the protective layer 108A, and the post bump 117A may be disposed on the exposed upper surface. In addition, the opening of the protective layer 108A in the SMD type has a width smaller than the width of the upper surface of the post bump 117A. Accordingly, at least a part of the upper surface of the post bump 117A is covered by the protective layer 108A.

At this time, the post bump 117A according to the first embodiment is disposed with its lower surface in direct contact with the upper surface of the pad 107. In addition, the side surface of the post bump 117A is disposed in direct contact with the protective layer 108A. Clearly, the side surface of the post bump 117A may be disposed in direct contact with the inner wall of the opening of the protective layer 108A.

Here, the seed layer 107A is disposed between the insulating layer 105 and the pad 107. At this time, the seed layer 107A is not removed immediately after the pad 107 is formed, but remains until the post bump 117A is formed. That is, in the first seed layer in the comparative example, after the pad is formed, all of the remaining areas except for the area disposed under the pad are removed.

In contrast, in the seed layer 107A in the embodiment, portions disposed in regions other than the lower portion of the pad 107 are not removed until all the post bumps 117A are formed. In addition, since the seed layer 107A is removed after the post bump 117A is formed as described above, it may have a different structure from the first seed layer of the comparative example.

That is, the first seed layer of the comparative example was disposed only in the area where the pad is disposed. That is, the first seed layer in the comparative example was disposed only under the pad.

In contrast, the seed layer 107A in the first embodiment may be disposed not only in the region where the pad 107 is disposed, but also extends therefrom and under the protective layer 108A.

That is, the seed layer 107A is formed between the first region disposed between the pad 107 and the insulating layer 105, and extending from the first region and between the protective layer 108A and the insulating layer 105. It may include a second area disposed in the.

Accordingly, a seed layer for electroplating is not separately formed under the post bump, and the post bump can be formed on the pad by using a seed layer located under the pad. Accordingly, it is not necessary to form a separate seed layer for the formation of the post bump, thereby simplifying the manufacturing process, solving the occurrence of cracks between the seed layers of the post bump, and thus reliability and durability of the product. Can improve. In addition, according to the embodiment, since the desmear process does not have to be separately performed on the solder resist, whitening of the solder resist due to the desmear solution can be prevented.

In addition, the post bump in the first embodiment may have a horizontal width of A and a vertical width of B. In addition, the aspect ratio (B/A) of the post bump 117A in the first embodiment is set to be within the range of 0.4 to 0.7, thereby improving the durability of the post bump 117A. In other words, the vertical width or height of the post bump is set to have a range between 0.4 times and 0.7 times the horizontal width of the post bump. At this time, when the aspect ratio (B/A) of the post bump 117A is less than 0.4, the height of the post bump 117A is not secured, so that the post bump 117A cannot perform its function normally. In addition, when the aspect ratio (B/A) of the post bump 117A is greater than 0.7, the post bump 117A easily collapses due to the too large vertical width compared to the horizontal width of the post bump 117A. You have a problem.

Further, a side surface of the post bump 117A having such a structure may include a first portion in direct contact with the protective layer 108 and a second portion in direct contact with the second molding layer 110. That is, the post bump in the comparative example has a structure that does not include the first portion of the post bump as a seed layer is additionally disposed between the protective layer and the post bump. It includes the first portion and a post bump may be disposed.

Referring to FIG. 7, the post bump of the second embodiment has a structure in which the second seed layer in the comparative example is omitted. In other words, the post bump of the second embodiment may be formed by electroplating on the pad 107 using the seed layer 107B used for electroplating the pad. 7 includes an NSMD (NonSolder Mask Defined) type of protective layer.

In the NSMD type, the entire upper surface of the pad 107 is exposed through the opening of the protective layer 108B, and the post bump 117B may be disposed on the exposed upper surface. In addition, the opening of the protective layer 108B in the NSMD type has a width greater than the width of the upper surface of the post bump 117B. Accordingly, the protective layer 108B may be disposed at a position spaced apart from the post bump 117B and the pad 107 at a predetermined interval.

At this time, the post bump 117B according to the second embodiment is disposed with a lower surface in direct contact with the upper surface of the pad 107. In addition, the side surface of the post bump 117B may be exposed. More specifically, the side surface of the post bump 117B may be disposed in direct contact with the second molding layer 110.

Here, the seed layer 107B is disposed between the insulating layer 105 and the pad 107. At this time, the seed layer 107B is not removed immediately after the pad 107 is formed, but remains until the post bump 117B is formed. That is, in the first seed layer in the comparative example, after the pad is formed, all of the remaining areas except for the area disposed under the pad are removed.

In contrast, the seed layer 107B in the second exemplary embodiment is not removed from a portion disposed in a region other than the lower portion of the pad 107 until all the post bumps 117B are formed. In addition, since the seed layer 107B is removed after the post bump 117B is formed as described above, it may have a different structure from the first seed layer of the comparative example.

That is, the first seed layer of the comparative example was disposed only in the area where the pad is disposed. That is, the first seed layer in the comparative example was disposed only under the pad.

In contrast, the seed layer 107B in the second exemplary embodiment may be disposed not only in the region where the pad 107 is disposed, but also extends therefrom and under the protective layer 108B.

That is, the seed layer 107B includes a first region disposed between the pad 107 and the insulating layer 105, and spaced apart from the first region, and between the protective layer 108B and the insulating layer 105. It may include a second area disposed in the.

Accordingly, a seed layer for electroplating is not separately formed under the post bump, and the post bump can be formed on the pad by using a seed layer located under the pad. Accordingly, it is not necessary to form a separate seed layer for the formation of the post bump, thereby simplifying the manufacturing process, solving the occurrence of cracks between the seed layers of the post bump, and thus reliability and durability of the product. Can improve. In addition, according to the embodiment, since the desmear process does not have to be separately performed on the solder resist, whitening of the solder resist due to the desmear solution can be prevented.

In addition, the post bump according to the second embodiment may have a horizontal width of A'and a vertical width of B'. In addition, the aspect ratio (B'/A') of the post bump 117B in the second embodiment is set to be within the range of 0.4 to 0.7, thereby improving the durability of the post bump 117B. When the aspect ratio (B'/A') of the post bump 117B is less than 0.4, the height of the post bump 117B is not secured, so that the post bump 117B cannot perform its function normally. In addition, when the aspect ratio (B'/A') of the post bump 117B is greater than 0.7, the post bump 117B easily collapses as the vertical width relative to the horizontal width of the post bump 117B is too large. There is a problem with durability.

In addition, the entire area of the side surface of the post bump 117 in the second embodiment may have a structure in direct contact with the second molding layer 110.

Referring to FIG. 8, the post bump of the third embodiment has a structure in which the second seed layer in the comparative example is omitted. In other words, the post bump of the third embodiment may be formed by electroplating on the pad 107 using the seed layer 107C used for electroplating the pad. 8 includes a NonSolder Mask Defined (NSMD) type protective layer.

In the NSMD type, the entire upper surface of the pad 107 is exposed through the opening of the protective layer 108C, and the post bump 117C may be disposed on the exposed upper surface. In addition, the opening of the protective layer 108C in the NSMD type has a width greater than the width of the upper surface of the post bump 117C. Accordingly, the protective layer 108C may be disposed at a position spaced apart from the post bump 117C and the pad 107 at a predetermined interval.

In this case, the post bump 117C according to the third embodiment is disposed with a lower surface in direct contact with the upper surface of the pad 107. In addition, the side surface of the post bump 117C may be exposed. More specifically, the side surface of the post bump 117C may be disposed in direct contact with the second molding layer 110.

Here, the seed layer 107C is disposed between the insulating layer 105 and the pad 107. At this time, the seed layer 107C is not removed immediately after the pad 107 is formed, but remains until the post bump 117C is formed. That is, in the first seed layer in the comparative example, after the pad is formed, all of the remaining areas except for the area disposed under the pad are removed.

In contrast, in the seed layer 107C in the third embodiment, portions disposed in regions other than the lower portion of the pad 107 are not removed until all the post bumps 117C are formed. In addition, since the seed layer 107C is removed after the post bump 117C is formed as described above, it may have a different structure from the first seed layer of the comparative example.

That is, the first seed layer of the comparative example was disposed only in the area where the pad is disposed. That is, the first seed layer in the comparative example was disposed only under the pad.

Alternatively, the seed layer 107C in the third embodiment may be disposed not only in the region in which the pad 107 is disposed, but also extends therefrom and under the protective layer 108C.

That is, the seed layer 107C includes a first region disposed between the pad 107 and the insulating layer 105, and spaced apart from the first region, and between the protective layer 108C and the insulating layer 105. A second region disposed in the first and second regions may include a third region disposed between the second molding layer 110 and the insulating layer 105 between the first and second regions.

Accordingly, a seed layer for electroplating is not separately formed under the post bump, and the post bump can be formed on the pad by using a seed layer located under the pad. Accordingly, it is not necessary to form a separate seed layer for the formation of the post bump, thereby simplifying the manufacturing process, solving the occurrence of cracks between the seed layers of the post bump, and thus reliability and durability of the product. Can improve. In addition, according to the embodiment, since the desmear process does not have to be separately performed on the solder resist, whitening of the solder resist due to the desmear solution can be prevented.

Hereinafter, a method of manufacturing the printed circuit board according to the first embodiment illustrated in FIG. 2 will be described in detail.

9 to 15 are views illustrating a method of manufacturing a printed circuit board according to the first embodiment shown in FIG. 2 in order of processes.

First, referring to FIG. 9, a first insulating layer 101 that is a basis for manufacturing the printed circuit board 100 is prepared.

The first insulating layer 101 is a basic material for forming a circuit pattern existing inside the printed circuit board 100.

The first insulating layer 101 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber-impregnated substrate, and if it contains a polymer resin, it may include an epoxy-based insulating resin. Alternatively, a polyimide-based resin may be included.

A metal layer (not shown) is formed on at least one surface of the first insulating layer 101. The metal layer (not shown) is used to form the internal circuit pattern 102.

The metal layer may be formed by subjecting the first insulating layer 101 to non-electrolytic plating. Alternatively, a copper clad laminate (CCL) may be used.

In this case, when the metal layer is formed by electroless plating, roughness may be applied to the upper surface of the first insulating layer 101 so that the plating is smoothly performed.

The metal layer may be formed of a conductive metal material such as copper (Cu), iron (Fe), and alloys thereof.

Thereafter, referring to FIG. 10, a circuit pattern 102 is formed by etching the metal layers on the upper and lower surfaces of the prepared first insulating layer 101, and a via hole (shown in the figure) is thus formed in the first insulating layer 101. Not) to form a conductive via 103 for electrically connecting the circuit patterns 102 formed on the upper and lower surfaces of the first insulating layer 101 to each other.

The circuit pattern 102 may be performed by applying a photoresist to the upper and lower surfaces of the metal layer, patterning them, and performing exposure and development processes to form a photoresist pattern.

That is, the circuit pattern 102 is an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are typical printed circuit board manufacturing processes. And the like, and detailed descriptions are omitted here.

The conductive via 103 is formed to conduct at least one or more regions of the one-layer circuit pattern and the two-layer circuit pattern. The via hole for forming the conductive via 103 may be formed through a process such as laser processing, and may be formed through a process of filling the formed via hole with a metal material.

At this time, the metallic material may be any one selected from Cu, Ag, Sn, Au, Ni, and Pd, and the filling of the metallic material is electroless plating, electroplating, screen printing, and sputtering. ), evaporation, ink jetting, and dispensing, or a combination thereof.

At this time, the order of formation of the circuit pattern 102 and the conductive via 103 is not very important, but for more efficient via hole processing, the conductive via 103 is first processed to form the conductive via 103 After that, the circuit pattern 102 is formed.

Thereafter, referring to FIG. 11, a second insulating layer 104 filling the circuit pattern 102 formed on the upper surface of the first insulating layer 101 is formed.

In this case, the second insulating layer 104 may be formed as a single layer, but may have a structure in which each is formed as a plurality of layers and is stacked with a plurality of layers. In this case, the second insulating layer 104 may be formed of a plurality of layers made of the same material by applying an epoxy, a phenol resin, a prepreg, a polyimide film, an ABF film, or the like. Preferably, the second insulating layer 104 may be formed of an RCC as described above.

Accordingly, a metal layer (not shown) may be formed on one surface of the second insulating layer 104.

The metal layer may be present to later form the first pad 106 or an external circuit pattern (not shown).

The metal layer serves to facilitate resin flow and spreadability during a pressing process by heat and pressure.

A third insulating layer 105 filling the circuit pattern 102 formed on the lower surface of the first insulating layer 101 is formed.

In this case, the third insulating layer 105 may be formed as a single layer, but may have a structure in which each is formed as a plurality of layers and is stacked as a plurality of layers. In this case, the third insulating layer 105 may be formed of a plurality of layers made of the same material by applying an epoxy, a phenol resin, a prepreg, a polyimide film, an ABF film, or the like. Preferably, the third insulating layer 105 may be formed of RCC.

Accordingly, a metal layer (not shown) may be formed on one surface of the third insulating layer 105.

The metal layer may be present to form the second pad 107 or an external circuit pattern (not shown) later. The metal layer serves to facilitate resin flow and spreadability during a pressing process by heat and pressure.

Next, the metal layer on the upper surface of the prepared second insulating layer 104 is etched to form a first pad 106, and a via hole (not shown) is formed in the second insulating layer 104 accordingly. , A conductive via for electrically connecting the circuit pattern 102 formed on the upper surface of the first insulating layer 101 and the first pad 106 to each other is formed.

That is, the first pad 106 is an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are typical printed circuit board manufacturing processes. It is possible by a construction method or the like, and detailed description is omitted here.

In addition, the metal layer on the lower surface of the prepared third insulating layer 105 is etched to form the second pad 107, and accordingly, a via hole (not shown) is formed in the third insulating layer 105, A conductive via for electrically connecting the circuit pattern 102 formed on the lower surface of the first insulating layer 101 and the second pad 107 to each other is formed.

Next, referring to FIG. 12, a first connection part 111 and a second connection part 113 are disposed on the first pad 106. In addition, the first element 112 is mounted on the first pad 106 using the first connection part 111.

In addition, the second element 114 is mounted on the first pad 106 by using the second connection part 113.

In addition, a third connection part 115 is formed on the second pad 108. In addition, the third element 116 is mounted on the second pad 108 using the third connection part 115.

Next, referring to FIG. 13, a protective layer 108 is formed on an upper surface of the second insulating layer 104 and a lower surface of the third insulating layer 105, respectively.

The protective layer 108 is for protecting the surface of the second insulating layer 104, the surface of the first pad 106, the surface of the third insulating layer 105, and the surface of the second pad 107, respectively. As such, it may be formed of at least one or more layers using at least one of a solder resist, an oxide, and Au.

Thereafter, the protective layer 108 is processed to expose the surface of the second pad 107 to the outside.

That is, the protective layer 108 is formed to include an opening (not shown) exposing a partial upper surface of the second pad 107, and the opening may have a diameter smaller than that of the second pad 107 (SMD type).

Accordingly, edge regions of the first and second pads 106 and 107 are protected by the protective layer 108.

Thereafter, a post bump 117 is formed on the second pad 108 exposed through the opening of the protective layer 108. In this case, as described above, the post bump 117 may be formed by performing electroplating using a seed layer formed for electroplating of the second pad 108.

Next, referring to FIG. 14, a first molding layer 109 filling the first element 112 and the second element 114 on the upper protective layer or the first protective layer of the protective layer 108 To form.

In addition, a second molding layer 110 filling the third device 116 is formed on the lower protective layer or the second protective layer of the protective layer 108. In this case, the lower surface of the second molding layer 110 may be positioned lower than the lower surface of the third element 116. In addition, an upper surface of the first molding layer 109 may be positioned higher than that of the first element 112 and the second element 114.

Next, referring to FIG. 15, the lower region of the second molding layer 110 is ground so that the lower surface of the third element 116 is exposed. That is, the lower region of the second molding layer 110 may be ground so that the lower surface of the second molding layer 110 is located on the same plane as the lower surface of the third device 116.

According to this embodiment, by forming a post bump on a printed circuit board and attaching an upper package or a main board using the post bump to manufacture a package substrate, it is possible to respond to a fine pitch. You can maximize your productivity.

In addition, according to the present embodiment, by mounting the device on both sides of the printed circuit board, and disposing a molding part for molding the mounted device, it is possible to maintain the balance of the upper and lower parts of the printed circuit board compared to the conventional single-sided molding structure. As a result, the occurrence of warpage of the printed circuit board can be minimized.

In addition, according to the embodiment, by mounting the devices on both sides of the printed circuit board, both active or passive devices mounted on the existing upper package can be mounted on the printed circuit board, and accordingly, the total thickness of the package board Can be lowered.

In addition, according to the present embodiment, the lower surface of the lower molding part to which the main board is attached is placed on the same plane as the lower surface of the element mounted under the printed circuit board, thereby connecting the main board and the printed circuit board. Reliability can be improved.

In addition, according to the present embodiment, post bumps are disposed on both sides of the printed circuit board, so that heat dissipation can be made to both sides of the printed circuit board through the post bumps, and thus heat dissipation characteristics may be improved.

In addition, according to the present embodiment, it is possible to adjust the height of the post bump as much as the height of the device, thereby facilitating package design design.

In addition, according to the embodiment, a seed layer for electroplating is not separately formed under the post bump, and the post bump can be formed on the pad by using a seed layer located under the pad. Accordingly, it is not necessary to form a separate seed layer for the formation of the post bump, thereby simplifying the manufacturing process, solving the occurrence of cracks between the seed layers of the post bump, and thus reliability and durability of the product. Can improve. In addition, according to the embodiment, since the desmear process does not have to be separately performed on the solder resist, whitening of the solder resist due to the desmear solution can be prevented.

In addition, in the embodiment, the aspect ratio of the post bump is included in the range of 0.4 to 0.7, thereby improving the durability of the post bump.

16 is a diagram illustrating a package substrate according to the first embodiment.

Referring to FIG. 16, the package substrate according to the first embodiment includes the printed circuit board 100 described in FIG. 2.

Further, a solder ball 210 may be disposed on a lower surface of the post bump 117 of the printed circuit board 100.

In addition, the main board 200 may be attached under the post bump 117 by the solder ball 210. That is, a pad (not shown) may be disposed on the upper surface of the main board 200 while being aligned with the post bump 117 and in contact with the solder ball 210. Accordingly, the upper surface of the main board 200 may be disposed to directly face the lower surface of the third element 116.

As described above, in the package substrate in the first embodiment, a post bump 117 connected to the main board 200 is formed under the printed circuit board, and the main board and the printing are performed using the post bump 117. Allows circuit boards to be electrically connected to each other. In addition, the lower surface of the second molding layer 110 disposed under the printed circuit board is positioned on the same plane as the lower surface of the third device 116, -contact can solve the problem.

17 is a diagram illustrating a printed circuit board according to a second embodiment.

The printed circuit board 300 of FIG. 17 is different from the printed circuit board of FIG. 2 in that the post bump has a vertical symmetrical structure.

That is, in the printed circuit board according to the first embodiment, the post bump 117 is disposed only under the printed circuit board.

Alternatively, in the printed circuit board according to the second embodiment, post bumps may be disposed on both sides of the printed circuit board.

Referring to FIG. 17, the printed circuit board 300 includes a first insulating layer 301, a circuit pattern 302, a via 303, a second insulating layer 303, a third insulating layer 304, and a first insulating layer. Pad 306, second pad 307, protective layer 308, first molding layer 309, second molding layer 310, first connection part 311, first element 312, second A connection part 313, a second device 314, a third connection part 315, a third device 316, and post bumps 317 and 318 are included.

The first insulating layer 301 may be a core substrate.

The first insulating layer 301 may be a support substrate of a printed circuit board on which a single circuit pattern is formed, but may mean a region in which any one circuit pattern is formed among substrates having a plurality of stacked structures.

A second insulating layer 304 is formed on the first insulating layer 301, and a third insulating layer 305 is formed under the first insulating layer 301.

The first to third insulating layers 301, 304, 305 form an insulating plate, and may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber impregnated substrate. When included, may include epoxy-based insulating resins such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build-up Film), and otherly, polyimide-based resins may be included, but specifically limited thereto no.

The first to third insulating layers 301, 304, 305 may be formed of different materials. For example, the first insulating layer 301 is an impregnated substrate including glass fibers, and the second and third insulating layers (304, 305) may be an insulating sheet formed of only resin.

An internal circuit pattern 302 is formed on at least one of an upper portion and a lower portion of the first insulating layer 301.

In addition, a via 303 is formed in the first insulating layer 301 to connect the internal circuit patterns 302 formed in different layers to each other.

An external circuit pattern (not shown) is also formed on the second insulating layer 304 formed on the first insulating layer 301 and the third insulating layer 305 formed on the lower side.

An external circuit pattern (not shown) is also formed on the exposed surfaces of the second insulating layer 304 formed on the first insulating layer 301 and the third insulating layer 305 formed below the first insulating layer 301.

The external circuit pattern may mean the pads 306 and 307 shown in the drawing. That is, the external circuit pattern is formed by the same process as the pads 306 and 307, and is divided into a pattern and a pad according to their function.

That is, a circuit pattern is formed on the surfaces of the second insulating layer 304 and the third insulating layer 305, and depending on the function of the circuit pattern, some may be an external circuit pattern, and the rest may be chips or other substrates. It may be the pads 306 and 307 connected to each other.

In addition, vias are also formed inside the second insulating layer 304 and the third insulating layer 305.

The via 303 as described above forms a via hole for opening at least one of the first, second, and third insulating layers 301, 304, 305 through a laser process, and thereby, a metal paste inside the formed via hole. It can be formed by filling with.

At this time, the metal material forming the via 303 may be any one material selected from Cu, Ag, Sn, Au, Ni, and Pd, and the filling of the metal material is electroless plating, electrolytic plating, screen printing ( Screen Printing), sputtering, evaporation, ink jetting, and dispensing, any one of a combination of these may be used.

A protective layer 108 is formed on the surfaces of the second insulating layer 304 and the third insulating layer 305 (the surface exposed to the outside, the surface where the pad is formed).

The protective layer 308 has openings exposing upper surfaces of the first and second pads 306 and 307.

That is, the protective layer 308 is to protect the surface of the second insulating layer 304 and the third insulating layer 305, the front surface of the second insulating layer 304 and the third insulating layer 305 The first pad 306 and the second pad 307 are formed over and have an opening to open the surface of the stacked structure.

The protective layer 308 may be formed of at least one or more layers using at least one of SR (Solder Resist), oxide, and Au. Preferably, the protective layer 308 may be a solder resist.

The first pad 306 exposed by the opening of the protective layer 308 is classified according to its function.

That is, the first pad 306 may include a pad connected to the first device 312, a pad connected to the second device 314, and a pad connected to the second post bump 318.

To this end, connection portions 311 and 313 may be disposed on the first pad 306. That is, the first connection part 311 may be disposed on a pad on which the first element 312 is mounted among the first pads 306. In addition, a second connector 313 may be disposed on a pad on which the second element 314 is mounted among the first pads 306.

A first element 312 may be attached on the first connection part 311. In addition, a second element 314 may be attached on the second connection part 313.

In addition, a second post bump 318 may be disposed on the first pad 306.

A first molding layer 309 is disposed on the upper protective layer or the first protective layer among the protective layers 308. The first molding layer 309 may be disposed on the upper protective layer or the first protective layer to cover the first element 312 and the second element 314. The first molding layer 309 may be formed of resin. The first molding layer 309 can protect the first element 312 and the second element 314 from an external environment by filling the first element 312 and the second element 314 therein. have. An upper surface of the first molding layer 309 may be positioned higher than an upper surface of the first element 312 and the second element 314. For example, a top surface of the first device 312 and a top surface of the second device 314 may be disposed to cover the top surface of the first molding layer 309.

The lower surface of the second post bump 318 may directly contact the upper surface of the first pad 306. In addition, a side surface of the second post bump 318 may include a first portion in direct contact with the first protective layer or an upper protective layer, and a second portion in direct contact with the first molding layer 309. have.

Meanwhile, a second pad 307 is disposed on the lower surface of the third insulating layer 305. In addition, the second pad 307 may include a mounting pad on which the third element 316 is mounted, and a bump pad on which a first post bump 317 for connection to an external main board is disposed.

A third connection part 315 may be disposed on the mounting pad of the second pad 307.

The first post bump 317 may be disposed under the lower surface of the second pad 307 or the bump pad exposed through the lower protective layer or the second protective layer.

The first post bump 317 may protrude from the lower surface of the lower protective layer or the second protective layer. The first post bump 317 may have the same upper and lower widths. In addition, the first post bump 317 may have an upper width and a lower width different from each other. The first post bump 317 may have a column shape.

In this case, a lower surface of the first post bump 317 may be positioned higher than a lower surface of the third element 316.

A second molding layer 310 is disposed under the lower protective layer or the second protective layer among the protective layers 308. The second molding layer 310 may be disposed on the lower protective layer or the second protective layer to cover the third device 316. The second molding layer 310 may be formed of resin. In this case, the second molding layer 310 may be disposed to cover the side of the third device 316. In addition, the second molding layer 310 may be disposed exposing the lower surface of the third device 316. In other words, the lower surface of the second molding layer 310 may be positioned on the same plane as the lower surface of the third element 316. This is, in a state in which the second molding layer 310 is formed to cover the lower surface of the third element 316, and the lower surface of the second molding layer 310 is the same as the lower surface of the third element 116. It may be formed by grinding the second molding layer 310 to be positioned on a plane.

As described above, the printed circuit board 300 in the second embodiment includes a first molding layer 309 for mounting a device on the insulating layers 301, 304, and 305, and molding the mounted device. do. In addition, the printed circuit board 300 in the second embodiment includes a second molding layer 310 for mounting a device under the insulating layers 301, 304, and 305 and molding the mounted device. In this way, the printed circuit board 300 may maintain the balance of both sides of the printed circuit board by not disposing the molding layer on only one side based on the insulating layer, but by disposing the molding layer on both sides, Accordingly, the occurrence of warpage can be minimized.

In addition, the printed circuit board 300 according to the second embodiment forms post bumps 318 and 317 disposed on the first pad 306 and the second pad 307 in a symmetrical structure. In this way, the post bumps are not disposed only on one side of the printed circuit board 300 based on the insulating layer, but the post bumps are disposed on both sides of the printed circuit board 300, so that the balance of both sides of the printed circuit board can be maintained. Accordingly, the occurrence of warpage can be minimized.

In addition, the first and second post bumps 317 and 318 may have the structures described with reference to FIGS. 5 to 7, thereby improving fracture resistance due to external physical and internal lamination pressure.

18 is a diagram illustrating a package substrate according to a second embodiment.

Referring to FIG. 18, the package substrate according to the second embodiment includes the printed circuit board 300 described in FIG. 17.

Further, a first solder ball 410 may be disposed on a lower surface of the first post bump 317 of the printed circuit board 300.

In addition, a second solder ball 510 may be disposed on an upper surface of the second post bump 318 of the printed circuit board 300.

In addition, the main board 400 may be attached under the first post bump 317 by the first solder ball 410. That is, a pad (not shown) in contact with the first solder ball 210 while being aligned with the first post bump 317 may be disposed on the upper surface of the main board 400.

As described above, in the package substrate in the second embodiment, a first post bump 317 connected to the main board 400 is formed under the printed circuit board, and the main The board and the printed circuit board may be electrically connected to each other. In addition, the lower surface of the second molding layer 310 disposed under the printed circuit board is positioned on the same plane as the lower surface of the third element 316, -contact can solve the problem.

In addition, the upper package 500 may be attached on the second post bump 318 by the second solder ball 510.

According to this embodiment, by forming a post bump on a printed circuit board and attaching an upper package or a main board using the post bump to manufacture a package substrate, it is possible to respond to a fine pitch, thereby increasing the productivity of the manufacturer. Can be maximized.

In addition, according to the present embodiment, by mounting the device on both sides of the printed circuit board, and disposing a molding part for molding the mounted device, it is possible to maintain the balance of the upper and lower parts of the printed circuit board compared to the conventional single-sided molding structure. As a result, the occurrence of warpage of the printed circuit board can be minimized.

In addition, according to the embodiment, by mounting the devices on both sides of the printed circuit board, both active or passive devices mounted on the existing upper package can be mounted on the printed circuit board, and accordingly, the total thickness of the package board Can be lowered.

In addition, according to the present embodiment, the lower surface of the lower molding part to which the main board is attached is placed on the same plane as the lower surface of the element mounted under the printed circuit board, thereby connecting the main board and the printed circuit board. Reliability can be improved.

In addition, according to the present embodiment, by disposing the post bumps on both sides of the printed circuit board, it is possible to improve the package balance compared to the conventional single-sided post bump arrangement structure, thereby minimizing occurrence of warpage.

In addition, according to the present embodiment, post bumps are disposed on both sides of the printed circuit board, so that heat dissipation can be made to both sides of the printed circuit board through the post bumps, and thus heat dissipation characteristics may be improved.

In addition, according to the present embodiment, it is possible to adjust the height of the post bump as much as the height of the device, thereby facilitating package design design.

In addition, according to the embodiment, a seed layer for electroplating is not separately formed under the post bump, and the post bump can be formed on the pad by using a seed layer located under the pad. Accordingly, it is not necessary to form a separate seed layer for the formation of the post bump, thereby simplifying the manufacturing process, solving the occurrence of cracks between the seed layers of the post bump, and thus reliability and durability of the product. Can improve. In addition, according to the embodiment, since the desmear process does not have to be separately performed on the solder resist, whitening of the solder resist due to the desmear solution can be prevented.

In addition, in the embodiment, the aspect ratio of the post bump is included in the range of 0.4 to 0.7, thereby improving the durability of the post bump.

Features, structures, effects, and the like described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified for other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

In addition, although the embodiments have been described above, these are only examples and do not limit the present invention, and those of ordinary skill in the field to which the present invention pertains are illustrated above within the scope not departing from the essential characteristics of the present embodiment. It will be seen that various modifications and applications that are not available are possible. For example, each component specifically shown in the embodiments can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

Claims (16)

Insulating layer;
A plurality of first pads disposed on an upper surface of the insulating layer;
A plurality of second pads disposed on a lower surface of the insulating layer;
A first element mounted on any one of the plurality of first pads;
A second element mounted on any one of the plurality of second pads;
A first molding layer disposed on an upper surface of the insulating layer and molding the first device;
A second molding layer disposed on a lower surface of the insulating layer and molding the second device;
A first post bump disposed on any one of the plurality of second pads; And
Including a second post bump disposed on any one of the plurality of first pads
Printed circuit board. The method of claim 1,
The first post bump and the second post bump,
It has a mutually symmetric structure based on the insulating layer and is arranged
Printed circuit board. The method of claim 1,
The lower surface of the second molding layer,
It is located on the same plane as the lower surface of the second element,
The upper surface of the first molding layer,
Positioned higher than the upper surface of the first element
Printed circuit board. The method of claim 1,
A first protective layer disposed between the upper surface of the insulating layer and the first molding layer; And
Including a second protective layer disposed between the lower surface of the insulating layer and the second molding layer
Printed circuit board. The method of claim 4,
The lower surface of the first post bump,
It is located higher than the lower surface of the second molding layer,
The upper surface of the second post bump,
Positioned lower than the upper surface of the first molding layer
Printed circuit board. The method of claim 4,
The top surface of the first post bump,
In direct contact with the lower surface of the second pad,
The lower surface of the second post bump,
In direct contact with the upper surface of the first pad
Printed circuit board. The method of claim 6,
The entire area of the side surface of the first post bump,
A first portion in direct contact with the second protective layer,
Including a second portion in direct contact with the second molding layer,
The entire area of the side surface of the second post bump,
A third portion in direct contact with the first protective layer,
Including a fourth portion in direct contact with the first molding layer
Printed circuit board. The method of claim 6,
The entire area of the side surface of the first post bump,
In direct contact with the second molding layer,
The entire area of the side surface of the second post bump,
In direct contact with the first molding layer
Printed circuit board. The method of claim 6,
A first seed layer disposed between the lower surface of the insulating layer and the second pad; And
A second seed layer disposed between the upper surface of the insulating layer and the first pad,
The first post bump,
It is an electroplating layer formed using the first seed layer,
The second post bump,
Which is an electroplating layer formed by using the second seed layer
Printed circuit board. The method of claim 9,
The first seed layer,
A first region disposed between the lower surface of the insulating layer and the second pad,
A second region extending from the first region and disposed between a lower surface of the insulating layer and the second protective layer,
The second seed layer,
A third region disposed between the upper surface of the insulating layer and the first pad,
Extending from the third region and including a fourth region disposed between the upper surface of the insulating layer and the first protective layer
Printed circuit board. The method of claim 9,
The first seed layer,
A first region disposed between the lower surface of the insulating layer and the second pad,
And a second region spaced apart from the first region and disposed between the lower surface of the insulating layer and the second protective layer,
The second seed layer,
A third region disposed between the upper surface of the insulating layer and the first pad,
And a fourth region spaced apart from the third region and disposed between the upper surface of the insulating layer and the first protective layer
Printed circuit board. The method of claim 11,
The first seed layer,
A fifth region connected between the first region and the second region and disposed between a lower surface of the insulating layer and the second molding layer,
The second seed layer,
And a sixth region connected between the third region and the fourth region and disposed between the upper surface of the insulating layer and the first molding layer.
Printed circuit board. The method of claim 4,
The vertical width or height of each of the first and second post bumps,
Having a range between 0.4 times and 0.7 times the horizontal width of each of the first and second post bumps
Printed circuit board. An insulating layer, a plurality of first pads disposed on an upper surface of the insulating layer, a plurality of second pads disposed on a lower surface of the insulating layer, and mounting on any one of the plurality of first pads A first element to be formed, a second element mounted on any one of the plurality of second pads, a first molding layer disposed on an upper surface of the insulating layer and molding the first element, and the A second molding layer disposed on a lower surface of the insulating layer and molding the second device; a first post bump disposed on one of the second pads among the plurality of second pads; and the plurality of first pads A printed circuit board including a second post bump disposed on one of the first pads;
A first solder ball disposed on a lower surface of the first post bump;
A second solder ball disposed on an upper surface of the second post bump;
A main board attached to the first post bump of the printed circuit board through the first solder ball; And
And an upper package attached to the second post bump of the printed circuit board through the second solder ball,
The lower surface of the second molding layer of the printed circuit board,
It is located on the same plane as the lower surface of the second element,
The lower surface of the second element,
Disposed facing the upper surface of the main board directly
Package substrate. The method of claim 14,
The top surface of the first post bump,
In direct contact with the lower surface of the second pad,
The lower surface of the second post bump,
In direct contact with the upper surface of the first pad,
The entire area of the side surface of the first post bump,
In direct contact with at least one of the second protective layer and the second molding layer,
The entire area of the side surface of the second post bump,
In direct contact with at least one of the first protective layer and the first molding layer
Package substrate.. The method of claim 15,
The printed circuit board,
A first seed layer disposed between the lower surface of the insulating layer and the second pad; And
A second seed layer disposed between the upper surface of the insulating layer and the first pad,
The first post bump,
It is an electroplating layer formed using the first seed layer,
The second post bump,
Which is an electroplating layer formed by using the second seed layer
Package substrate.

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