KR20210016779A - Semiconductor device - Google Patents

Abstract

Disclosed is a semiconductor device. The semiconductor device comprises: a semiconductor structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; an insulating layer disposed on the semiconductor structure; a first electrode disposed on the first conductivity type semiconductor layer; a second electrode disposed on the second conductivity type semiconductor layer; a first pad disposed on the first electrode; and a plurality of second pads disposed to be spaced apart from each other on the second electrode. The second pads overlap the active layer at least partially in a first direction. The first direction is a direction from the first conductivity type semiconductor layer toward the second conductivity type semiconductor layer. The insulating layer includes a groove disposed in a region between the first pad and the second pads and overlapping the second conductivity type semiconductor layer in the first direction. Accordingly, it is possible to provide a semiconductor device having improved heat dissipation characteristics.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device.

A semiconductor device including a compound such as GaN or AlGaN has many advantages, such as having a wide and easily adjustable band gap energy, and thus can be variously used as a light emitting device, a light receiving device, and various diodes.

In particular, light-emitting devices such as light emitting diodes and laser diodes using a group 3-5 or group 2-6 compound semiconductor material of semiconductors are red, green, and red due to the development of thin film growth technology and device materials. Various colors such as blue and ultraviolet light can be implemented, and efficient white light can be realized by using fluorescent materials or by combining colors. Low power consumption, semi-permanent life, and fast response speed compared to conventional light sources such as fluorescent lamps and incandescent lamps. , Has the advantages of safety and environmental friendliness.

In addition, when photo-receiving devices such as photodetectors and solar cells are also manufactured using compound semiconductor materials of groups 3-5 or 2-6 of semiconductors, the development of device materials generates photocurrent by absorbing light in various wavelength ranges. By doing so, light in various wavelength ranges from gamma rays to radio wavelength ranges can be used. In addition, it has the advantages of fast response speed, safety, environmental friendliness, and easy adjustment of device materials, so it can be easily used for power control or ultra-high frequency circuits or communication modules.

Therefore, the semiconductor device can replace the transmission module of the optical communication means, the light emitting diode backlight that replaces the cold cathode fluorescent lamp (CCFL) constituting the backlight of the LCD (Liquid Crystal Display) display device, and a fluorescent lamp or incandescent bulb. Applications are expanding to white light-emitting diode lighting devices, automobile headlights, traffic lights, and sensors that detect gas or fire. In addition, the application of the semiconductor device can be extended to high-frequency application circuits, other power control devices, and communication modules.

In particular, the light emitting device emitting light in the ultraviolet wavelength range can be used for curing, medical, and sterilization by performing a curing or sterilizing action.

Although research on ultraviolet light emitting devices is active in recent years, there is a problem that it is still difficult to implement ultraviolet light emitting devices with flip chips.

The embodiment provides a flip-chip type semiconductor device.

In addition, a semiconductor device having improved heat dissipation characteristics by increasing the pad area is provided.

In addition, a semiconductor device having improved light output due to light reflection is provided.

The problems to be solved in the examples are not limited thereto, and the objectives and effects that can be grasped from the solutions or embodiments of the problems described below are also included.

A semiconductor device according to an embodiment includes a semiconductor structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; An insulating layer disposed on the semiconductor structure; A first electrode disposed on the first conductivity type semiconductor layer; A second electrode disposed on the second conductivity type semiconductor layer; A first pad disposed on the first electrode; And a second pad on the second electrode, wherein the second pad overlaps at least partially with the active layer in a first direction, and the first direction is the second conductivity type in the first conductivity type semiconductor layer. A direction toward the semiconductor layer, the insulating layer is disposed in a region between the first pad and the second pad, and includes a groove overlapping the second conductivity type semiconductor layer in the first direction.

The groove, an inclined surface; And a lower surface disposed between adjacent inclined surfaces.

The inclined surface may be disposed to surround the lower surface.

The groove may penetrate the insulating layer.

The groove is disposed to penetrate to a partial area of the second electrode, the lower surface overlaps the second electrode in a second direction, the second direction is a direction perpendicular to the first direction, and the first pad May be in a direction toward the second pad.

The second pad may at least partially overlap the groove in a second direction, and the second direction may be a direction perpendicular to the first direction, and may be a direction from the first pad toward the second pad.

The ratio of the total width of the lower surface and the width in a second direction between the first pad and the second pad is 1:1.2 to 1:3, the second direction is a direction perpendicular to the first direction, and the second It may be a direction from the first pad toward the second pad.

The first electrode includes a first-first electrode region overlapping the first pad in the first direction, a first-second electrode region overlapping the second pad, and the first-first electrode region in the first direction And a 1-3 electrode region disposed between the first and second electrode regions, wherein the second electrode is a second electrode region overlapping the first pad in the first direction, and the first direction And a second electrode region overlapping the second pad and a second electrode region disposed between the second electrode region and the second electrode region, wherein the groove is the first It may be disposed between the -3 electrode region and the 2-3rd electrode region.

A second ohmic electrode disposed between the semiconductor structure and the second electrode may be further included, and the groove may be disposed to penetrate to a partial region of the second ohmic electrode.

A first ohmic electrode disposed between the semiconductor structure and the first electrode may be further included.

According to an embodiment, a semiconductor device may be implemented in the form of a flip chip.

In addition, a semiconductor device having improved heat dissipation characteristics can be manufactured by increasing the pad area.

In addition, even if the area of the pad is increased, it is possible to easily prevent an electrical short between the pads.

In addition, it is possible to manufacture a semiconductor device with improved light output by light reflection.

Various and beneficial advantages and effects of the present invention are not limited to the above-described contents, and may be more easily understood in the course of describing specific embodiments of the present invention.

1 is a plan view of a semiconductor device according to a first embodiment,
2 is a cross-sectional view taken along AA′ in FIG. 1,
3 is a cross-sectional view taken along BB′ in FIG. 1,
4 is a cross-sectional view taken along CC' in FIG. 1,
5 is a cross-sectional view taken along line DD′ in FIG. 1,
6A is an enlarged view of part K in FIG. 5,
6B is a modified example of FIG. 6A,
7 is a plan view specifically showing the semiconductor device according to the first embodiment,
FIG. 8 is a cross-sectional view illustrating a semiconductor structure cut by EE′ in FIG. 7,
9 is a modified example of FIG. 1,
10 is a cross-sectional view of a semiconductor device according to a second embodiment,
11 is an enlarged view of part L in FIG. 10,
12 is a cross-sectional view of a semiconductor device according to a third embodiment,
13 is an enlarged view of part M in FIG. 12,
14 is a plan view of a semiconductor device according to a fourth embodiment,
15 is a cross-sectional view taken along line FF′ in FIG. 14.
16 is a plan view of a semiconductor device for describing a pad according to an embodiment,
17 is a cross-sectional view taken along GG' in FIG. 16,
18 is a modified example of FIG. 16,
19 is a cross-sectional view of a semiconductor device package according to an embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical idea of the present invention is not limited to some embodiments to be described, but may be implemented in various different forms, and within the scope of the technical idea of the present invention, one or more of the constituent elements may be selectively selected between the embodiments. It can be combined with and substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention are generally understood by those of ordinary skill in the art, unless explicitly defined and described. It can be interpreted as a meaning, and terms generally used, such as terms defined in a dictionary, may be interpreted in consideration of the meaning in the context of the related technology.

In addition, terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In the present specification, the singular form may include the plural form unless specifically stated in the phrase, and when described as "at least one (or more than one) of A and (and) B and C", it is combined with A, B, and C. It may contain one or more of all possible combinations.

In addition, in describing the constituent elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

These terms are only for distinguishing the component from other components, and are not limited to the nature, order, or order of the component by the term.

And, when a component is described as being'connected','coupled' or'connected' to another component, the component is not only directly connected, coupled or connected to the other component, but also the component and It may also include the case of being'connected','coupled' or'connected' due to another component between the other components.

In addition, when it is described as being formed or disposed in the "top (top) or bottom (bottom)" of each component, the top (top) or bottom (bottom) is one as well as when the two components are in direct contact with each other. It also includes a case in which the above other component is formed or disposed between the two components. In addition, when expressed as "upper (upper) or lower (lower)", the meaning of not only an upward direction but also a downward direction based on one component may be included.

1 is a plan view of a semiconductor device according to a first embodiment, FIG. 2 is a cross-sectional view taken along AA′ in FIG. 1, FIG. 3 is a cross-sectional view taken along BB′ in FIG. 1, and FIG. 4 is a CC in FIG. It is a cross-sectional view cut with'.

1 to 4, the semiconductor device 10A according to the first embodiment of the present invention includes a substrate 110, a semiconductor structure 120 disposed on the substrate 110, and a semiconductor structure 120. A first insulating layer 171 disposed on, a first ohmic electrode 151 disposed on the first conductive type semiconductor layer 121, and a second ohmic electrode disposed on the second conductive type semiconductor layer 123 ( 161, a first electrode 152 disposed on the first ohmic electrode 151, a second electrode 162 disposed on the second ohmic electrode 161, and a first electrode 152 and a second electrode A second insulating layer 172 disposed on the 162, a first pad 153 electrically connected to the first electrode 152, and a second pad 163 electrically connected to the second electrode 162 It may include.

First, the semiconductor structure 120 according to an embodiment of the present invention may output light in an ultraviolet wavelength band. For example, the semiconductor structure 120 may output light (UV-A) in the near-ultraviolet wavelength band, may output light in the far-ultraviolet wavelength band (UV-B), and may output light in the deep ultraviolet wavelength band (UV-A). C) can be printed. The wavelength range may be determined by the composition ratio of Al in the semiconductor structure 120.

For example, light in the near ultraviolet wavelength band (UV-A) may have a wavelength band in the range of 320 nm to 420 nm as the center wavelength, and light in the far ultraviolet wavelength band (UV-B) is centered in the wavelength band in the range of 280 nm to 320 nm. It may have a wavelength, and the deep ultraviolet wavelength band (UV-C) may have a wavelength band ranging from 100 nm to 280 nm as a center wavelength.

Specifically, the substrate 110 may be formed of a material selected from sapphire (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge, but is not limited thereto. For example, the substrate 110 may be a light-transmitting substrate through which light in the ultraviolet wavelength band can be transmitted.

The buffer layer 111 may alleviate lattice mismatch between the substrate 110 and the semiconductor layers. The buffer layer 111 may be a combination of a group III and a group V element, or may include any one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. In the present embodiment, the buffer layer 111 may be AlN, but is not limited thereto. The buffer layer 111 may include a dopant, but is not limited thereto.

x1≤1, 0<y1≤1, 0≤x1+y1≤1)의 조성식을 갖는 반도체 재료, 예를 들어 AlGaN, AlN, InAlGaN 등에서 선택될 수 있다. 그리고, 제1 도펀트는 Si, Ge, Sn, Se, Te와 같은 n형 도펀트일 수 있다. 제1 도펀트가 n형 도펀트인 경우, 제1 도펀트가 도핑된 제1 도전형 반도체층(121)은 n형 반도체층일 수 있다.The first conductivity-type semiconductor layer 121 may be implemented as a compound semiconductor such as Group III-V or Group II-VI, and may be doped with a first dopant. The first conductivity type semiconductor layer 121 is In _x1 Al _y1 Ga _{1 -x1 -y1} N(0

A semiconductor material having a composition formula of x1≤1, 0<y1≤1, 0≤x1+y1≤1), for example, may be selected from AlGaN, AlN, InAlGaN, and the like. In addition, the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, and Te. When the first dopant is an n-type dopant, the first conductivity-type semiconductor layer 121 doped with the first dopant may be an n-type semiconductor layer.

The active layer 122 may be disposed between the first conductivity type semiconductor layer 121 and the second conductivity type semiconductor layer 123. The active layer 122 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 121 and holes (or electrons) injected through the second conductivity type semiconductor layer 123 meet. The active layer 122 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

The active layer 122 may have any one of a single well structure, a multiple well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 122 The structure of is not limited thereto.

x2≤1, 0<y2≤1, 0≤x2+y2≤1)의 조성식을 가질 수 있다. 우물층은 발광하는 파장에 따라 알루미늄 조성이 달라질 수 있다.The active layer 122 may include a plurality of well layers (not shown) and a barrier layer (not shown). The well layer and the barrier layer are In _x2 Al _y2 Ga _{1 -x2- y2} N(0

x2≤1, 0<y2≤1, 0≤x2+y2≤1) may have a composition formula. The composition of aluminum in the well layer may vary depending on the emission wavelength.

The second conductivity-type semiconductor layer 123 is formed on the active layer 122 and may be implemented as a compound semiconductor such as Group III-V or Group II-VI. Dopants can be doped.

x5≤1, 0<y2≤1, 0≤x5+y2≤1)의 조성식을 갖는 반도체 물질 또는 AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP 중 선택된 물질로 형성될 수 있다. The second conductivity-type semiconductor layer 123 is In _x5 Al _y2 Ga _{1 -x5- y2} N (0

It may be formed of a semiconductor material having a composition formula of x5≦1, 0<y2≦1, 0≦x5+y2≦1) or a material selected from AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP.

When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, Ba, or the like, the second conductivity-type semiconductor layer 123 doped with the second dopant may be a p-type semiconductor layer.

The first insulating layer 171 may be disposed between the first ohmic electrode 151 and the second ohmic electrode 161. In addition, the first insulating layer 171 may include a first hole 171a in which the first ohmic electrode 151 is disposed and a second hole 171b in which the second ohmic electrode 161 is disposed.

The first ohmic electrode 151 may be disposed on the first conductivity type semiconductor layer 121, and the second ohmic electrode 161 may be disposed on the second conductivity type semiconductor layer 123.

The first ohmic electrode 151 and the second ohmic electrode 161 are ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium). zinc oxide), IGTO(indium gallium tin oxide), AZO(aluminum zinc oxide), ATO(antimony tin oxide), GZO(gallium zinc oxide), IZON(IZO Nitride), AGZO(Al-Ga ZnO), IGZO(In -Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, It may be formed by including at least one of In, Ru, Mg, Zn, Pt, Au, and Hf, but is not limited to these materials. For example, the first ohmic electrode 151 may have a plurality of metal layers (eg, Cr/Al/Ni), and the second ohmic electrode 161 may be ITO.

The first electrode 152 may be disposed on the first ohmic electrode 151 to cover the first ohmic electrode 151. That is, the first electrode 152 may cover the side surface of the first ohmic electrode 151, but is not limited to this configuration.

In addition, the first electrode 152 may be electrically connected to the first ohmic electrode 151 through the first hole 171a to form an electrical channel with the first conductivity type semiconductor layer 121. In addition, the first electrode 152 may extend above the first insulating layer 171. Accordingly, the first electrode 152 may be positioned on a portion of the first insulating layer 171. Due to this configuration, since the total area of the first electrode 152 is increased, the operating voltage of the semiconductor device according to the embodiment may be decreased.

The second electrode 162 may be disposed on the second ohmic electrode 161 to cover the second ohmic electrode 161. Further, the second electrode 162 may cover a side surface of the second ohmic electrode 161, but is not limited thereto.

In addition, the second electrode 162 may be electrically connected to the second electrode 162 through the second hole 171b. Accordingly, the second electrode 162 may form an electrical channel with the second ohmic electrode 161 and the second conductivity type semiconductor layer 123 electrically. In addition, for example, the second electrode 162 may be disposed only on the second ohmic electrode 161.

The first electrode 152 and the second electrode 162 are Ni/Al/Au, or Ni/IrOx/Au, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg , Zn, Pt, Au, and may be formed to include at least one of Hf, but is not particularly limited. However, the outermost layer of the first electrode 152 and the second electrode 162 exposed to the outside may include gold (Au). Gold (Au) prevents corrosion of the electrode and improves electrical conductivity to facilitate electrical connection with the pad.

The second insulating layer 172 may be disposed on the first electrode 152, the second electrode 162, and the first insulating layer 171. The second insulating layer 172 may include a third hole 172a exposing the first electrode 152 and a fourth hole 172b exposing the second electrode 162. The third hole 172a and the fourth hole 172b may be spaced apart from each other.

The first insulating layer 171 and the second insulating layer 172 are formed by selecting at least one from the group consisting of SiO ₂ , SixOy, Si ₃ N ₄ , SixNy, SiOxNy, Al ₂ O ₃ , TiO ₂ , AlN, etc. Can be. In addition, the first insulating layer 171 and the second insulating layer 172 are partially formed at the boundary between the first insulating layer 171 and the second insulating layer 172 in the process of forming the second insulating layer 172. May be removed and exist integrally. In addition, the second insulating layer 172 may be a distributed Bragg reflector (DBR) having a multilayer structure including Si oxide or a Ti compound. However, the present invention is not necessarily limited thereto, and the insulating layer 171 may include various reflective structures.

In addition, the second insulating layer 172 may include a groove 173 disposed in a region between the first pad 153 and the second pad 163 to be described later. Specifically, the groove 173 may be located in the second insulating layer 172 between the first pad 153 and the second pad 163 in the second direction (Y-axis direction). The groove 173 may include a lower surface 173b disposed between the plurality of inclined surfaces 173a and adjacent inclined surfaces 173a. In this case, the lower surface 173b may be disposed to be surrounded by the inclined surface 173a. In addition, the groove 173 may have a pattern. For example, there are a plurality of grooves 173, and may be spaced apart from the adjacent grooves 173 by a predetermined distance in the second direction (Y-axis direction), and may be arranged side by side along the second direction on the second electrode 162. However, the present invention is not limited thereto, and the groove may have a pattern corresponding to a shape to be described later. Further, a plurality of patterns or a single pattern may be used.

In addition, the groove 173 may be disposed to overlap the second conductivity type semiconductor layer 123 in the first direction (X-axis direction). In addition, the groove 173 may be disposed on the first electrode 152 in a region between the first pad 153 and the second pad 163. Due to this configuration, the surface area increases in a region between the first pad 153 and the second pad 163. In this case, the heat dissipation characteristics of the semiconductor device may be improved. In addition, when a semiconductor device is disposed on a package substrate or a circuit board, the path through which the bonding metal (solder paste, etc.) is spread can be increased, so that even if the gap between the first pad 153 and the second pad 163 is reduced, Since it is possible to prevent the pad 153 and the second pad 163 from being short-circuited, the sizes of the first pad 153 and the second pad 163 can be easily increased. Although not shown in the drawing, for example, the groove 173 is in a region between the first pad 153 and the second pad 163 in the second conductive semiconductor layer 123 and the first direction (X-axis direction). In addition, it may be positioned to overlap the first conductivity-type semiconductor layer 121 in the first direction (X-axis direction). And in an embodiment, the groove 173 may penetrate the second insulating layer 172 to a partial area. In addition, the groove 173 may penetrate the second insulating layer 172 or may penetrate to a partial region of the second electrode 162 or the second ohmic electrode 161 under the second insulating layer 172. . Accordingly, a partial region of the second insulating layer 172 or a partial region of the second electrode 162 or a partial region of the second ohmic electrode 161 may be exposed by the groove 173.

Accordingly, the lower surface 173b overlaps the second insulating layer 172 or the second electrode 162 or the second ohmic electrode 161 in the second direction (Y-axis direction) or the third direction (Z-axis direction). Can be placed. In this embodiment, it will be described that the groove 173 penetrates the second insulating layer 172. And a specific embodiment for this will be described later. In addition, the first pad 153 may be disposed on the first electrode 152 to be electrically connected to the first electrode 152. In addition, the second pad 163 may be disposed on the second electrode 162 to be electrically connected to the second electrode 162. In this case, the first pad 153 and the second pad 163 may be eutectic bonding, but the present invention is not limited thereto.

In addition, the first pad 153 and the second pad 163 may be disposed to face each other on the semiconductor structure 120. In an embodiment, the first pad 153 may be spaced apart from the second pad 163 in a second direction (Y-axis direction) on a plane. In this specification, the first direction (X-axis direction) is a direction perpendicular to the second direction (Y-axis direction), and the third direction (Z-axis direction) is perpendicular to both the first and second directions, and the semiconductor structure 120 ) May be the same as the stacking direction of the first conductivity type semiconductor layer 121, the active layer 122, and the second conductivity type semiconductor layer 123.

In addition, the first pad 153 is electrically connected to the first electrode 152 through the third hole 172a of the second insulating layer 172, and the second pad 163 is a second insulating layer 172. ) May be electrically connected to the second electrode 162 through the fourth hole 162a. The third hole 172a may be one hole formed according to the shape of the first electrode 152, and there may be a plurality of fourth holes 162a, and the number of such holes may be variously changed.

In addition, the first pad 153 may be disposed on one side above the third hole 172a, and the second pad 163 may be disposed on the other side above the fourth hole 172b. In addition, the first pad 153 and the second pad 163 may be separated from each other on the semiconductor structure 120 to be electrically separated.

In addition, the first pad 153 and the second pad 163 may include a conductive material. For example, the first pad 153 and the second pad 163 are at least selected from the group including Ti, Cu, Ni, Au, Cr, Ta, Pt, Sn, Ag, P, Fe, Sn, Zn, and Al. It may contain one material or an alloy thereof. In addition, the first pad 153 and the second pad 163 may be provided as a single layer or multiple layers.

FIG. 5 is a cross-sectional view taken along line DD′ in FIG. 1, FIG. 6A is an enlarged view of part K in FIG. 5, and FIG. 6B is a modified example of FIG. 6A.

5 and 6A, as described above, the groove 173 is disposed between the first pad 153 and the second pad 163, and the second conductive semiconductor layer 123 and the first direction It can be arranged to overlap in the (X-axis direction).

In addition, there may be a plurality of grooves 173, and the plurality of grooves 173 may be spaced apart from each other. These grooves 173 are arranged to overlap in the first direction (X-axis direction) with the second electrode 162 positioned between the first pad 153 and the second pad 163 in the second direction (Y-axis direction). Can be.

According to the embodiment, the ratio of the width WB of the lower surface 173b and the width WL in the second direction (Y-axis direction) between the first pad 153 and the second pad 163 is 1:1.2 To 1:3. In this case, the width WB of the lower surface 173b may be a length in the second direction (Y-axis direction), and when a plurality of grooves 173 are present, it means the entire width of the lower surface 173b.

And since the ratio is 1:1.2 to 1:3, it is easy to block the occurrence of an electrical short between the first pad and the second pad, and improve the durability of the second insulating layer to improve the reliability of the semiconductor device. It can be improved. That is, when the ratio is less than 1:1.2, there may be a problem in that an electrical short occurs due to an area expansion limit of the first pad 153 and the second pad 163. In addition, when the ratio is greater than 1:3, the durability of the second insulating layer 172 partitioned by the groove 173 between the first pad 153 and the second pad 163 decreases, thereby reducing the reliability of the semiconductor device. There is a limit to this degrading.

In addition, the width WL between the first pad 153 and the second pad 163 in the second direction (Y-axis direction) may be 150 μm or less. Due to this configuration, even if there is a movement due to heat between the first pad 153 and the second pad 163, an electrical short between the first pad 153 and the second pad 163 does not occur and simultaneously The heat dissipation characteristics can be improved. Accordingly, in the semiconductor device according to the embodiment, an electrical short does not occur within the ratio, and reliability of the semiconductor device can be maintained. In addition, heat dissipation characteristics through the first pad 153 and the second pad 163 may be improved by the groove 173. In addition, since the areas of the first pad 153 and the second pad 163 are increased, current injection is facilitated therethrough, so that the optical speed of the semiconductor device can be improved. In addition, a substantial separation distance between the first pad 153 and the second pad 163 is reduced by the groove 173, so that the semiconductor device according to the embodiment may be used between the first pad 153 and the second pad 163. Electrical short can be easily prevented.

In addition, the second insulating layer 172 may have an insulating portion 174 partitioned by a plurality of grooves 173 between the first pad 153 and the second pad 163 as described above. In other words, the insulating part 174 may be the second insulating layer 172 exposed by the inclined surface 173a. In addition, the insulating portion 174 may overlap the second conductivity type semiconductor layer 123 in a first direction (X-axis direction) similarly to the groove 173. However, the insulating part 174 may be connected to the second insulating layer 172 disposed on the adjacent first electrode 152.

In addition, the width WT of the insulating part 174 in the second direction (Y-axis direction) may be the same as or different from the width WB of the lower surface 173b.

For example, the width WT of the insulating part 174 in the second direction (Y-axis direction) may be the same as the width WB of the lower surface 173b. When the width WT of the insulating portion 174 in the second direction (Y-axis direction) is the same as the width WB of the lower surface 173b, it is easy to form the groove 173 in the second insulating layer 172 can do. In addition, reliability in the insulating portion 174 may be improved.

In addition, the width WT of the insulating portion 174 in the second direction (Y-axis direction) may be different from the width WB of the lower surface 173b. When the width WT of the insulating part 174 in the second direction (Y-axis direction) is different from the width WB of the lower surface 173b, the heat dissipation effect of the first pad 153 and the second pad 163 Can be maximized.

In an embodiment, the width WT of the insulating portion 174 may increase in the second direction (Y-axis direction) as it is adjacent to the first pad 153 or the second pad 163. For example, the width of the insulating portion 174 located at the outermost side (which is most adjacent to the first pad 153 or the second pad 163 in the second direction (Y-axis direction)) is in the second direction (Y-axis direction) ) May be smaller than the width of the insulating portion 174 located at the center between the first pad 153 and the second pad 163.

With this configuration, the contact area between the first pad 153 or the second pad 163 and the second insulating layer 172 can be efficiently increased compared to the length in the second direction (Y-axis direction). That is, the area of the first pad 153 or the second pad 163 can be easily increased. Accordingly, the heat dissipation efficiency of the semiconductor device can be improved.

In addition, the semiconductor device according to the embodiment can easily scatter light emitted from the active layer 122 by increasing the area of the outer surface of the second insulating layer 172 through the groove 173 and the insulating portion 174. have. Accordingly, it is possible to improve the light output of the semiconductor device.

In addition, the lower surface 173b may be disposed so as to be surrounded by the inclined surface 173a, and may have various shapes.

Referring to FIG. 6B, as a modified example, the second insulating layer 172 may be present under the lower surface 173b of the groove 173 by etching unlike the above description. That is, the second insulating layer 172 may include the groove 173 and the lower surface 173b and the 2-1 insulating layer 172i overlapping in the first direction (X-axis direction). When the second insulating layer 172 is a single layer, the 2-1 insulating layer 172i may be a part of the second insulating layer 172. Alternatively, when the second insulating layer 172 is composed of a plurality of layers, the upper surface of the 2-1 insulating layer 172i coincides with the lower surface 173b of the groove, or the lower surface 137b of the groove is the second 1 It may be disposed lower than the upper surface of the insulating layer 172i. With this configuration, the first pad 153 and the second pad 163 may extend in the second direction (Y-axis direction) and partially overlap the groove 173 in the first direction (X-axis direction). In other words, the first pad 153 and the second pad 163 may be extended to a region between the first pad 153 and the second pad 163. In this case, the 2-1 insulating layer 172i prevents electrical connection between the first pad 153 and the second electrode 162, and finally, the electrical connection between the first pad 153 and the second pad 163 is prevented. Short circuit can be easily prevented.

FIG. 7 is a plan view specifically showing a semiconductor device according to the first embodiment, and FIG. 8 is a cross-sectional view illustrating a semiconductor structure cut by EE′ in FIG. 7.

Referring to FIGS. 7 and 8, the semiconductor structure 120 may include a light-emitting portion M1 protruding by etching and a non-light-emitting portion M2 to which the first conductivity-type semiconductor layer 121 is exposed by etching. have. The light emitting part M1 may include an active layer 122 and a second conductivity type semiconductor layer 123. In addition, the non-emission part M2 may include a first conductivity type semiconductor layer 121.

In this case, a ratio (P11/P12) of the maximum perimeter P11 of the light-emitting part M1 and the maximum area P12 of the light-emitting part may be 0.05 [1/um] or more and 0.10 [1/um] or less. Here, the maximum perimeter and maximum area of the light emitting part M1 may be the maximum perimeter and area of the second conductivity type semiconductor layer (or active layer). Hereinafter, the light-emitting portion M1 will be described with reference to the second conductivity-type semiconductor layer, and the non-light-emitting portion M2 will be described with reference to the first conductivity-type semiconductor layer 121.

When the ratio (P11/P12) is 0.05 or more, the circumference of the second conductivity type semiconductor layer is lengthened relative to the area, so that light output may be improved. For example, the probability that light can be emitted from the side is increased, so that light output may be improved. In addition, when the ratio P11/P12 is 0.10 or less, the circumference of the second conductivity-type semiconductor layer is too long relative to the area, thereby preventing a problem in that the light output is lowered.

In other words, when the circumference of the second conductivity-type semiconductor layer is excessively long within the same area, a very thin (length in the first direction) second conductivity-type semiconductor layer 123 may be continuously disposed. The second ohmic electrode disposed on the 2-conductivity semiconductor layer 123 is also very thin, so that resistance may increase. Accordingly, the operating voltage may increase. In addition, when the circumference of the second conductivity-type semiconductor layer 123 becomes very small within the same area, the area of the outer surface may decrease, and thus the light output may decrease.

Accordingly, the second conductivity-type semiconductor layer 123 extends in the first direction (X-axis direction) in order to have an appropriate circumference and area ratio. It may include a first branch portion 123b extending in the direction (Y-axis direction). In addition, a plurality of first branch portions 123b may be spaced apart from each other in the first direction (X-axis direction). In addition, the plurality of first branch portions 123b may be connected to the first body portion 123a at one end. However, as described above, it may also be interpreted that the light emitting portion M1 has a first body portion and a first branch portion.

More specifically, the first body portion 123a may be disposed adjacent to one side of the second conductivity type semiconductor layer 123. In addition, the first body portion 123a may be extended and disposed in the first direction (X-axis direction). In this case, the direction in which the first body part 123a is extended will be described as the direction in which the length in the first direction and the length in the second direction is larger. That is, in the embodiment, since the length La in the first direction (X-axis direction) is greater than the length L1 in the second direction (Y-axis direction), the first body part 123a ) May extend in the first direction. The description of this may be equally applied to the branch portions below.

In addition, the first body portion 123a has a first outer surface 123a-1 and a second outer surface 123a-2 disposed parallel to the first direction (X-axis direction), and the second direction (Y-axis direction). A direction) and a third outer surface 123a-3 and a fourth outer surface 123a-4 disposed in parallel with each other. At this time, as described above, the first outer surface 123a-1 and the second outer surface 123a-2 have a length L1 in the first direction (X-axis direction) of the third outer surface 123a-3 And a length La of the fourth outer surface 123a-4 in the second direction (Y-axis direction). And the first outer surface (123a-1) and the second outer surface (123a-2) are positioned to face each other, and the third outer surface (123a-3) and the fourth outer surface (123a-4) are positioned to face each other. can do. In addition, the length in the third direction (Z-axis direction), which is the stacking direction of the semiconductor structure, will be described.

The first branch portion 123b may be disposed to extend in a second direction (Y-axis direction) on the second outer surface 123a-2 of the first body portion 123a. In other words, as described above, the length Lb of the first branch portion 123b in the second direction (Y-axis direction) may be greater than the length L2 in the first direction (X-axis direction). In addition, each of the first branch portions 123b may be disposed to be spaced apart in the first direction (X-axis direction) on one outer surface (eg, the second outer surface 123a-2) of the first body portion 123a. have. In addition, the first branch portion 123b may be formed integrally with the first body portion 123a, and a boundary surface may not exist at a portion in contact with the first body portion 123a.

In addition, the first branch portion 123b is positioned to face the fifth outer surface 123b-1 and the fifth outer surface 123b-1 in contact with the first body portion 123a and is positioned in a first direction (X-axis direction) It may include a sixth outer surface (123b-2) parallel to. In addition, the first branch portion 123b includes the seventh outer surface 123b-3 and the eighth outer surface 123b-4 disposed between the fifth outer surface 123b-1 and the sixth outer surface 123b-2. ) Can be included.

The fifth outer surface 123b-1 may be disposed parallel to the first direction (X-axis direction) because it contacts a part of the second outer surface 123a-2, and the seventh outer surface 123-3 The and the eighth outer surfaces 123b-4 may face each other, and some may be disposed parallel to the second direction (Y-axis direction).

In addition, as described below, in another embodiment of the present invention, the seventh outer surface 123b-3 and the eighth outer surface 123b-4 may further include sub-branches extending in the first direction (X-axis direction). I can. However, in various embodiments of the present specification, the length Lb of the seventh outer surface 123b-3 and the eighth outer surface 123b-4 in the second direction (Y-axis direction) is the fifth outer surface 123b- 1) and may be maintained larger than the length L2 in the first direction (X-axis direction) of the sixth outer surface 123b-2. In this case, the second direction (Y-axis) of the first body part 123a In the direction), the length L1 may be larger than the length L2 in the first direction (X-axis direction) of the first branch portion 123b. Accordingly, even if the plurality of first branch portions 123b and the first body portion 123a become thinner due to an increase in the circumference of the second conductivity type semiconductor layer 123, the first body portion 123a is It is possible to easily support the plurality of first branch portions 123b connected to 123a). Accordingly, reliability of the semiconductor structure according to the embodiment may be improved.

In addition, the length L2 in the first direction (X-axis direction) of the first branch part 123b is 1 in the second direction (Y-axis direction) of the first body part 123a. :1.1 to 1:2.6.

When the length ratio is 1:1.1 or more, the first body portion easily supports the first branch, and the second ohmic electrode and the second electrode on the first body portion of the second conductivity type semiconductor layer also serve as a support, improving reliability. Can be. In addition, when the length ratio is 1:2.6 or less, the circumference of the second conductivity-type semiconductor layer may be improved to improve light output.

In addition, the exposed first conductivity-type semiconductor layer 121 may have a shape surrounding the second conductivity-type semiconductor layer 123 on a plane XY as described above.

Specifically, the exposed first conductivity-type semiconductor layer 121 includes a second body portion 121a extending in a first direction (X-axis direction) and a second branch portion extending in a second direction (Y-axis direction). 121b) may be included. A plurality of second body portions 121a may be positioned on both sides in the second direction (Y-axis direction). That is, the second body portion 121a may be positioned to surround the first body portion 123a and the first branch portion 123b on a plane XY.

In addition, the second branch portion 121b may be positioned between the first branch portions 123b. Alternatively, each of the plurality of first branch portions 123b may be positioned between the plurality of second branch portions 121b. With this configuration, the current injected through the first electrode disposed on the exposed first conductivity type semiconductor layer 121 may be uniformly distributed.

The length L3 of the second body portion 121a in the second direction (Y-axis direction) may be smaller than the length L1 in the second direction (Y-axis direction) of the first body portion 123a. The length ratio (L3:L1) of the length in the second direction of the second body portion 121a and the length in the second direction of the first body portion 123a may be 1:3 to 1:5. When the length ratio is 1:3 or more, the area of the second electrode is increased to improve hole injection efficiency, and when the width ratio is 1:5 or less, the area of the second body portion 121a is secured, so that the electron injection efficiency can be improved. have.

In addition, the second branch portion 121b is disposed between adjacent first branch portions 123b, and the length L4 in the first direction of the second branch portion 121b is the first branch portion 123b. It may be smaller than the length L2 in one direction. A length ratio of the length L4 in the first direction of the second branch portion 121b and the length L2 in the first direction of the first branch portion 123b may be 1:2 to 1:4. When the length ratio is greater than or equal to 1:2, the area of the second electrode may increase, thereby improving hole injection efficiency. In addition, when the length ratio is less than 1:4, the area of the first electrode can be secured, and thus electron injection efficiency can be improved.

In addition, an area of the second conductivity type semiconductor layer 123 may be larger than an area of the exposed first conductivity type semiconductor layer 121. The area R1 of the second conductivity type semiconductor layer 123 may have an area ratio of 1:0.5 to 1:0.8 to the area R2 of the exposed first conductivity type semiconductor layer. When the area ratio is 1:0.5 or more, the area of the first electrode may be secured to improve electron injection efficiency, and may be disposed to surround the second electrode of the first electrode. Accordingly, the current dispersion efficiency can also be improved. In addition, when the area ratio is 1:0.8 or less, the area of the second electrode is secured, thereby improving hole injection efficiency and improving light output.

In addition, the first body portion 123a may be positioned to overlap the second pad 163 in a third direction (Z-axis direction). That is, the first body part 123a may be located under the second pad 163.

In addition, a partial region of the first branch portion 123b may be positioned under each of the first pad 153 and the second pad 163. In other words, the end 123b-1 of the first branch part 123b may be located under the first pad. Unlike this, the end 121b-1 of the second branch portion 121b may be positioned under the second pad 163.

In addition, the first pad 153 includes a first side 153b and a second side 153a parallel to the first direction, and the second pad 163 is parallel to the first direction and a second side 153a A third side surface 163a close to and a fourth side surface 163b parallel to the third side surface 163a may be included.

At this time, the distance L5 in the second direction from the end 121b-1 of the second branch portion 121b to the fourth side surface 163b of the second pad 163 is the end of the first branch portion 123b ( 123b-1) to the first side surface 153b of the first pad 153 may be longer than the distance L6 in the second direction. Accordingly, the overlapping area of the first branch portion 123b and the first pad 153 may be larger than the overlapping area of the second branch portion 121b and the second pad 163.

Accordingly, the overlapping area of the first branch portion 123b and the first pad 153 is made larger than the overlapping area of the second branch portion 121b and the second pad 163, and thus the second pad ( The second insulating layer 172 positioned between the 163 and the second branch 121b is weakened to moisture between the second pad 163 and the second branch 121b, thereby preventing a problem of deteriorating reliability. have.

In addition, the exposed first conductivity type semiconductor layer 121 may be disposed to surround the second conductivity type semiconductor layer 123 on a plane (XY plane). In addition, a first electrode may be disposed on the exposed first conductivity type semiconductor layer 121. The first electrode may have a shape corresponding to the shape of the exposed first conductivity type semiconductor layer 121. In addition, since the first electrode corresponds to the shape of the exposed first conductivity type semiconductor layer 121 and the second electrode corresponds to the shape of the second conductivity type semiconductor layer 123, the first electrode is It may be arranged to surround the electrode.

In addition, according to the embodiment, the fourth hole 172b may be positioned to overlap the first body portion 123a and the first branch portion 123b in a third direction (Z-axis direction).

More specifically, in the embodiment, the fourth hole 172b is a body hole 172b-1 disposed on the first body part 123a and a branch hole 172b-2 disposed on the first branch part 123b. ) Can be included. In this case, the body hole 172b-1 may overlap the first body portion 123a in a third direction, and the branch hole 172b-2 may overlap the first branch portion 123b in a third direction. .

Accordingly, by arranging the fourth hole 172b on both the first body portion 123a and the first branch portion 123b, the circumference of the second conductivity type semiconductor layer 123 is brought into the above-described range. Reliability and light output can be improved by winding.

In addition, the main body hole 172b-1 and the branch hole 172b-2 are entirely located on one side of the semiconductor structure 120 along the first body part 123a and the first branch part 123b. The current spreading can be smoothly performed to the first body portion 123a and the first branch portion 123b through the second electrode 162.

In addition, when the second conductivity-type semiconductor layer 123 is made of, for example, AlGaN (but is not limited to this material), the second ohmic electrode 161 contacts the second conductivity-type semiconductor layer 123 If so, a large amount of heat may be generated due to high resistance. At this time, peeling of the second ohmic electrode 161 may occur due to the generated heat, but according to the embodiment, the first branch part 123b has a length in the second direction (Y-axis direction) of the first body part 123a. By taking it larger than the length in the first direction (X-axis direction) of, the above-described heat is evenly distributed, thereby preventing peeling and improving reliability. Furthermore, the fourth hole 172b may be disposed more adjacent to the first body part 123a on the semiconductor structure 120. In other words, the fourth hole 172b may be concentrated on one side of the second conductive type semiconductor layer 123 where the first branch portion 123b and the first body portion 123a are in contact. In addition, the above-described heat may be generated in an area in which a plurality of fourth holes 172b are disposed, so that the electrode may be peeled off, but as in the embodiment, the second direction (Y-axis direction) of the first body part 123a Since the length is larger than the length in the first direction (X-axis direction) of the first branch portion 123b, the heat distribution can be more evenly provided, thereby more effectively suppressing the peeling phenomenon.

In addition, the length of the first branch portion 123b in the first direction (X-axis direction) may increase as the distance increases from the first body portion 123a. In other words, the length of the first branch portion 123b may gradually increase in the first direction (X-axis direction) toward the second direction (Y-axis direction). With this configuration, the width of the second branch portion 121b may decrease in the first direction (X-axis direction) as the distance from the second body portion 121a increases. With this configuration, hole injection into the second conductivity-type semiconductor layer 123 can be smoothly performed not only on one side of the first branch portion 123b in contact with the first body portion 123a, but also on the other side of the opposite side.

In addition, the plurality of branch holes 172b-2 may be located on the first branch portion 123b. In particular, the plurality of branch holes 172b-2 may be positioned to overlap one first branch portion 123b in the second direction. With this configuration, the current injected into the first branch portion 123b through the branch hole 172b-2 is uniformly spread, so that the light output of the semiconductor device may be improved.

Also, the plurality of branch holes 172b-2 may be disposed to overlap in the first direction on the plurality of first branch portions 123b and the first body portion 123a. That is, the plurality of branch holes 172b-2 may be disposed side by side on the plurality of first branch portions 123b and the first body portion 123a. Thus, in the semiconductor device according to the embodiment, the first injected current through the branch hole 172b-2 is uniformly spread to the branch portion 123b and the first body portion 123a, thereby improving the light output of the semiconductor device. Can be.

In addition, at least one of the plurality of body holes 172b-1 may overlap the branch hole 172b-2 on the first branch portion 123b in the second direction. Accordingly, in the semiconductor device according to the embodiment, the body hole 172b-1 is disposed in the first body part 123a corresponding to the branch hole 172b-2 positioned on each of the first branch parts 123b. Current spreading can be further improved.

Also, the area of the first pad 153 may be larger than the area of the second pad 163. In an embodiment, the length of the first pad 153 in the first direction (X-axis direction) may be greater than the maximum length in the first direction (X-axis direction) of the plurality of second branch portions 121b. Accordingly, each of the second branch portions 121b may partially overlap the first pad 153 in the third direction. In addition, with this configuration, electron injection from the first pad 153 to the second branch portion 121b can be easily performed.

In addition, the length of the second pad 163 in the first direction (X-axis direction) may be greater than the length in the first direction (X-axis direction) of the plurality of first branch portions 123b. In addition, the length of the second pad 163 in the first direction (X-axis direction) may be greater than the length in the first direction (X-axis direction) of the first body part 123a. That is, each of the second branch portions 123b may partially overlap the second pad 163 in the third direction (Z-axis direction). As a result, holes can be easily injected from the second pad 163 to the first branch portion 123b.

In addition, the length of the second pad 163 in the first direction (X-axis direction) may be smaller than the maximum length in the first direction (X-axis direction) of the plurality of second branch portions 121b. That is, the second branch portions 121b positioned at the outermost side in the first direction (X-axis direction) may not overlap with the second pad 163 in the third direction (Z-axis direction). Accordingly, the overlapping area between the second pad 163 and the second branch portion 121b is reduced in the third direction (Z-axis direction), thereby reducing reliability according to the opposite polarity between the second pad 163 and the second branch portion 121b. It can prevent degradation.

In addition, as a modified example, the second pad 163 may have a shape corresponding to the shape of the second conductivity type semiconductor layer 123. For example, the second pad 163 is a body pad (not shown) positioned on the first body portion 123a of the second conductivity type semiconductor layer 123 and a branch positioned on the first branch portion 123b. It may include a pad (not shown). Accordingly, the second pad 163 may not overlap with the second branch portion 121b, the first ohmic electrode, and the first electrode in the third direction. Accordingly, the second branch portion 121b, the first ohmic electrode, and the first electrode can easily prevent a decrease in reliability due to the second pad 163.

9 is a modified example of FIG. 1.

Referring to FIG. 9, as described above, a groove 173 and an insulating portion 174 may be disposed between the first pad 153 and the second pad 163 in the second direction (Y-axis direction).

In this case, the groove 173 is a first groove region 173c extending in a second direction (Y-axis direction) between the first pad 153 and the second pad 163 in a second direction (Y-axis direction) And a second groove region 173d extending in a third direction (Z-axis direction) from the first groove region 173c. In addition, both the first groove region 173c and the second groove region 173d may be disposed to overlap the second conductivity type semiconductor layer 123 in the first direction (X-axis direction).

In addition, the length LK of the first groove region 173c in the second direction (Y-axis direction) may be greater than the length LM in the third direction (Z-axis direction) of the second groove region 173d.

In addition, the insulating portions 174 may be spaced apart in the second direction (Y-axis direction) and the third direction (Z-axis direction) and may be disposed on the second electrode 162. By this configuration. The areas of the first pad 153 and the second pad 163 may be more efficiently increased. Accordingly, heat dissipation efficiency through the first pad 153 and the second pad 163 and scattering of light emitted from the semiconductor structure may be improved.

In addition, configurations other than the configurations described in this embodiment can be applied in the same manner as configurations of other embodiments described above.

10 is a cross-sectional view of a semiconductor device according to the second embodiment, and FIG. 11 is an enlarged view of a portion L in FIG. 10.

10 and 11, in the semiconductor device 10B according to the second embodiment, the groove 173 penetrates the second insulating layer 172, and the second electrode under the second insulating layer 172 ( 162 or a partial region of the second ohmic electrode 161 may be penetrated. Here, it will be described that the groove 173 penetrates to the second electrode 162. Accordingly, a partial area of the second electrode 162 may be exposed by the groove 173.

In addition, the lower surface 173b of the groove 173 may be disposed to overlap the second electrode 162 in the second direction (Y-axis direction) or the third direction (Z-axis direction). Accordingly, the second electrode 162 acts as an etch stop layer, so that the groove 173 can be easily formed.

In addition, the inclined surface 173b of the groove 173 may include a first inclined area 173a-1 and a second inclined area 173a-2.

The first inclined region 173a-1 is an inclined surface to which the second insulating layer 172 is exposed, and the second inclined region 173a-2 is an inclined surface to which the second electrode 162 is exposed. Accordingly, the first inclined region 173a-1 may overlap with the second insulating layer 172 in the second direction (Y-axis direction) or the third direction (Z-axis direction). The second inclined region 173a-2 may overlap the second electrode 162 in a second direction (Y-axis direction) or a third direction (Z-axis direction).

In addition, the first pad 153 may be disposed to extend along the groove 173 to the lower second inclined region 173a-2. That is, the length of the groove 173 may be further increased in the first direction (X-axis direction). For example, the length of the groove 173 of the semiconductor device according to the present embodiment may increase in a first direction (X-axis direction) than the length in the first direction of the groove of the semiconductor device according to the first embodiment described above. have. As a result, the area efficiency of the first pad 153 may be further increased.

Likewise, the second pad 163 may be disposed to extend along the groove 173 to the lower second inclined region 173a-2. In addition, the length of the groove 173 may be further increased in the first direction (X-axis direction). As a result, the area efficiency of the second pad 163 may be further increased.

Accordingly, according to the groove 173 described above, the area efficiency of the first pad 153 and the second pad 163 is increased, so that the heat dissipation efficiency through the first pad 153 and the second pad 163 is increased. It can increase further.

In addition, the second pad 163 may extend to the second inclined region 173a-2 to contact the second electrode 162. Accordingly, since the second pad 163 is electrically connected to the second electrode 162, a contact area between the second pad 163 and the second electrode 162 may be further increased. As a result, current spreading may be improved and electrical characteristics of the semiconductor device may be improved.

In addition, as an additional modification, when the first pad 153 extends to the second inclined area 173a-2 in the area adjacent to the second inclined area 173a-2 and the first pad 153, an electrical short occurs. Therefore, only the first inclined area 173a-1 may exist without the second inclined area 173a-2 in the area adjacent to the first pad 153.

In an embodiment, the area S between the first pad 153 and the second pad 163 is a first area S1 and a second area adjacent to the first pad 153 in the second direction (Y-axis direction). It may be divided into a second area S2 adjacent to the pad 163. For example, the first area S1 is an area between the first pad 153 and the virtual line C1 based on the virtual line C1 obtained by dividing the area S in a second direction (Y-axis direction). . In addition, the second area S2 is an area between the virtual line C1 and the second pad 154.

In addition, the second inclined region 173a-2 may be disposed in the second region S2. With this configuration, the heat dissipation efficiency through the first pad 153 and the second pad 163 is improved, and current spreading is also improved by increasing the contact area between the second pad 163 and the second electrode 162 can do. In addition, configurations other than the configurations described in this embodiment can be applied in the same manner as configurations of other embodiments described above.

12 is a cross-sectional view of a semiconductor device according to the third embodiment, and FIG. 13 is an enlarged view of portion M in FIG. 12.

12 and 13, in the semiconductor device 10C according to the third embodiment, the second pad 163 may include a 2-1 pad region 163a and a 2-2 pad region 163b. I can.

The 2-1 pad area 163a may be an area that does not overlap with the groove 173 in the first direction (X-axis direction). In other words, the 2-1 th pad area 163a may be located outside the groove 173. In addition, the 2-2nd pad area 163b may be an area overlapping the groove 173 in the first direction (Y-axis direction). Accordingly, the 2-2nd pad region 163b may contact the inclined surface 173a of the groove 173 or may extend along the inclined surface 173a to contact the lower surface 173b.

With this configuration, the area of the second pad 163 can be efficiently increased compared to the length in the second direction (Y-axis direction). Accordingly, in the semiconductor device 10C according to the third exemplary embodiment, a heat dissipation effect through the second pad 163 may be improved, and an optical speed may be improved according to an increase in area.

In addition, configurations other than the configurations described in the present embodiment can be applied in the same manner as configurations of other embodiments described above.

14 is a plan view of a semiconductor device according to the fourth embodiment, and FIG. 15 is a cross-sectional view taken along line FF' in FIG. 14.

14 and 15, the semiconductor device 10D according to the fourth embodiment includes a substrate 110, a semiconductor structure 120 disposed on the substrate 110, and a semiconductor structure 120 disposed on the semiconductor structure 120. The insulating layer 172, the first electrode 152 disposed on the first conductivity type semiconductor layer 121, the second electrode 162 disposed on the second conductivity type semiconductor layer 123, the first electrode ( A first pad 153 electrically connected to 152 and a second pad 163 electrically connected to the second electrode 162 may be included. In addition, the second electrode 162 may be electrically connected to the second ohmic electrode 161 below. In addition, the second ohmic electrode 161 may include a 2-1 ohmic electrode 161a and a 2-2 ohmic electrode 161b covering the 2-1 ohmic electrode 161a. In this case, the 2-1 ohmic electrode 161a may be ITO. In addition, the 2-2nd ohmic electrode 161b may be formed of a plurality of metals described above. However, the present invention is not limited thereto and will be described as the second ohmic electrode 161.

Specifically, in the semiconductor device 10D according to the fourth embodiment, the second electrode 162 may be disposed to extend in the second direction (Y-axis direction). In addition, the first electrode 152 may be disposed to extend in the second direction (Y-axis direction). Accordingly, the first electrode 152 includes the first-first electrode region 152-1, the first-second electrode region 152-2, and the first-third electrode region 152-1 disposed along the second direction (Y-axis direction). The electrode region 152-3 may be included.

First, the first-first electrode region 152-1 may overlap the first pad 153 in a first direction (X-axis direction). In addition, the 1-2 th electrode region 152-2 may overlap the second pad 163 in the first direction (X-axis direction). In addition, the 1-3th electrode area 152-3 is disposed between the 1-1th electrode area 152-1 and the 1-2nd electrode area 152-2, so that the first pad 153 and the first pad 153 2 The pad 163 may not overlap in the first direction (X-axis direction). That is, the 1-3 electrode regions 152-3 may be positioned between the first pad 153 and the second pad 163 in the second direction (Y-axis direction).

In addition, the second electrode 162 includes the 2-1 electrode area 162-1, the 2-2 electrode area 162-2, and the 2-3rd electrode disposed along the second direction (Y-axis direction). It may include a region 162-3.

In addition, the 2-1 electrode region 162-1 may overlap the first pad 153 in a first direction (X-axis direction). In addition, the 2-2nd electrode region 162-2 may overlap the second pad 163 in the first direction (X-axis direction). In addition, the 2-3rd electrode area 162-3 is disposed between the 2-1st electrode area 162-1 and the 2-2nd electrode area 162-2, so that the first pad 153 and the 2 The pad 163 may not overlap in the first direction (X-axis direction). That is, the 2-3rd electrode region 162-3 may be positioned between the first pad 153 and the second pad 163 in the second direction (Y-axis direction).

At this time, the groove 173 according to the present embodiment is disposed between the first pad 153 and the second pad 163 in the second direction (Y-axis direction), and at the same time, the first-third electrode region 152- It may be spaced apart from 3) and the 2-3rd electrode regions 162-3 in a third direction (Z-axis direction). That is, the groove 173 overlaps with the 1-3 electrode regions 152-3 and 2-3 electrode regions 162-3 in the first direction (X-axis direction) and the second direction (Y-axis direction). And may overlap in the third direction (Z-axis direction).

For example, the groove 173 is disposed between the first pad 153 and the second pad 163 in the second direction (Y-axis direction), and at the same time, the first-third electrode region in the third direction (Z-axis direction). It may be disposed between the 152-3 and the 2-3rd electrode regions 162-3. Accordingly, the light emitted from the active layer 122 is not absorbed by the adjacent first electrode 152 and is reflected from the groove 173, thereby improving light output of the semiconductor device.

In addition, as described above, in the semiconductor device 10D according to the fourth exemplary embodiment, the first pad 153 and the second pad 163 through the groove 173 have an area compared to the length in the second direction (Y-axis direction). Can be increased efficiently. Accordingly, the heat dissipation effect through the first pad 9153 and the second pad 163 may be maximized. In addition, configurations other than the configurations described in the present embodiment can be applied in the same manner as configurations of other embodiments described above.

In addition, the groove 173 may be disposed to overlap the second conductivity type semiconductor layer 123 in the first direction (X-axis direction). In addition, the groove 173 may be disposed on the first electrode 152 in a region between the first pad 153 and the second pad 163. Due to this configuration, the surface area increases in a region between the first pad 153 and the second pad 163. In this case, the heat dissipation characteristics of the semiconductor device may be improved. In addition, when a semiconductor device is disposed on a package substrate or a circuit board, the path through which the bonding metal (solder paste, etc.) is spread can be increased, so that even if the gap between the first pad 153 and the second pad 163 is reduced, Since it is possible to prevent the pad 153 and the second pad 163 from being short-circuited, the sizes of the first pad 153 and the second pad 163 can be easily increased. Although not shown in the drawing, for example, the groove 173 is in a region between the first pad 153 and the second pad 163 in the second conductive semiconductor layer 123 and the first direction (X-axis direction). In addition, it may be positioned to overlap the first conductivity-type semiconductor layer 121 in the first direction (X-axis direction).

16 is a plan view of a semiconductor device for explaining a pad according to an embodiment, and FIG. 17 is a cross-sectional view taken along line GG' in FIG. 16.

Referring to FIGS. 16 and 17, as described above, the semiconductor device includes a substrate 110, a semiconductor structure 120 disposed on the substrate 110, and an insulating layer 172 disposed on the semiconductor structure 120. , The first electrode 152 disposed on the first conductivity type semiconductor layer 121, the second electrode 162 disposed on the second conductivity type semiconductor layer 123, and the first electrode 152 are electrically A first pad 153 to be connected and a second pad 163 electrically connected to the second electrode 162 may be included. In addition, the semiconductor device may further include a third pad 183.

More specifically, the first pad 153 may be spaced apart from the second pad 163 in a second direction (Y-axis direction) on a plane. As described above, in this specification, the first direction (X-axis direction) is a direction perpendicular to the second direction (Y-axis direction), and the third direction (Z-axis direction) is perpendicular to both the first direction and the second direction. In the semiconductor structure 120, the stacking direction of the first conductivity type semiconductor layer 121, the active layer 122, and the second conductivity type semiconductor layer 123 may be the same.

In addition, the first pad 153 is electrically connected to the first electrode 152 through a third hole of the second insulating layer 172, and the second pad 163 is a fourth pad of the second insulating layer 172. It may be electrically connected to the second electrode 162 through the hole. The third hole may be at least one hole formed according to the shape of the first electrode 152, and the fourth hole may be at least one hole, and the number of such holes may be variously changed.

Also, the third pad 183 may be disposed between the first pad 153 and the second pad 163. The third pad 183 may be positioned in a region between the first pad 153 and the second pad 163 in the second direction (Y-axis direction).

In addition, the third pad 183 may be disposed to be spaced apart from the first pad 153 and the second pad 163 in a second direction (Y-axis direction). In addition, the third pad 183 may be disposed in the groove 173 to contact the second ohmic electrode 161. That is, the third pad 183 may overlap at least some of the grooves 173 in the third direction (Z-axis direction) as described above. Accordingly, as described above, the surface area of the bottom surface of the third pad 183 is increased by the groove 173, so that heat dissipation characteristics may be improved. Accordingly, the performance and reliability of the semiconductor device can be improved and the life of each component can be extended.

In addition, the third pad 183 may include a conductive material like the first pad 153 and the second pad 163. For example, the third pad 183 contains at least one material selected from the group including Ti, Cu, Ni, Au, Cr, Ta, Pt, Sn, Ag, P, Fe, Sn, Zn, Al, or an alloy thereof. Can include. In addition, the third pad 183 may be formed of a single layer or multiple layers.

In addition, the length LP of the first pad 153 in the first direction (X-axis direction) may be the same as the length Lo in the first direction (X-axis direction) of the second pad 163. In response, the third pad 183 has a length Lg in the first direction (X-axis direction) of the first pad 153 in the first direction (X-axis direction). It may be the same as the length Lo in the first direction 163 (X-axis direction). With this configuration, heat is released in a balanced manner by the pads 153, 163, and 1830 in the first direction (X-axis direction), so that heat concentration due to imbalance can be prevented.

In addition, the length Lt of the first pad 153 in the second direction (Y-axis direction) may be the same as the length Lr of the second pad 163 in the second direction (Y-axis direction). However, the length Lr of the second pad 163 in the second direction (Y-axis direction) is the second direction of the first pad 153 to facilitate current injection into the second conductivity type semiconductor layer 123 It may be larger than the length Lt in (Y-axis direction).

In addition, the length Ls of the third pad 183 in the second direction (Y-axis direction) is the length Lt in the second direction (Y-axis direction) of the first pad 153 or of the second pad 163. It may be smaller than the length Lr in the second direction (Y-axis direction). While current injection through the first pad 153 and the second pad 163 is easily performed, additional heat can be easily dissipated from the third pad 183.

And the length ratio between the length Lt in the second direction (Y-axis direction) of the first pad 153 and the length LP in the first direction (X-axis direction) of the first pad 153 is from 1:1.1 to May be 1:1.8. By having the length ratio, it is possible to easily inject current into the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, and it is possible to easily prevent the concentration of current supply in a specific region. Also, like the first pad 153, the length Lr of the second pad 163 in the second direction (Y-axis direction) is the length Lo in the first direction (X-axis direction) of the second pad 163. It should be understood that the length ratio between) can be applied equally.

Further, the separation distance Lv between the first pad 153 and the third pad 183 in the second direction (Y-axis direction) and the length Ls in the second direction (Y-axis direction) of the third pad 183 ) The length ratio between them may be 1:3.3 to 1:5.1. Similarly, the separation distance Lu between the second pad 163 and the third pad 183 in the second direction (Y-axis direction) and the length Ls in the second direction (Y-axis direction) of the third pad 183 ) The length ratio between them may be 1:3.3 to 1:5.1.

When the length ratio is greater than 1:5.1, there is a problem that it is difficult to optimize current injection and heat dissipation due to a reduction in the pad area, and when the length ratio is less than 1:3.3, the connection between the first pad and the third pad Alternatively, there is a limit in which an electrical short may occur due to the connection between the second pad and the third pad.

In addition, in another embodiment, the semiconductor device includes a substrate 110, a semiconductor structure 120 disposed on the substrate 110, an insulating layer 172 disposed on the semiconductor structure 120, and a first conductivity type semiconductor layer. A first electrode 152 disposed on the 121, a second electrode 162 disposed on the second conductivity type semiconductor layer 123, and a first pad 153 electrically connected to the first electrode 152 ), a second pad 163 and a third pad 183 electrically connected to the second electrode 162.

In addition, the third pad 183 may be disposed in a region between the first pad 153 and the second pad 163. In this case, the third pad 183 may be disposed in a region between the first pad 153 and the second pad 163 even if the groove 173 does not exist or does not exist.

18 is a modified example of FIG. 16.

Referring to FIG. 18, the contents described in FIGS. 16 and 17 may be applied in the same manner except for the contents described below.

First, in a modified example, the first pad 153 may include a 1-1 pad part 153-1 and a 1-2 pad part 153-2. In addition, the second pad 163 may include a 2-1 pad part 163-1 and a 2-2 pad part 163-2.

The first-first pad portion 153-1 and the second-first pad portion 163-1 may be disposed on the outermost side in the second direction (Y-axis direction). In addition, the first-first pad portion 153-1 and the second-first pad portion 163-1 may have a rectangular shape. However, the shape is not limited thereto.

In addition, the 1-2 th pad part 153-2 may be disposed to extend from the 1-1 th pad part 153-1 toward the second pad part 163. The 1-2 th pad part 153-2 may be a part protruding from the 1-1 th pad part 153-1 toward the second pad part 163. Conversely, the 2-2 pad part 163-2 may be disposed extending from the 2-1 pad part 163-1 toward the first pad part 153. That is, the 2-2nd pad portion 163-2 may be a portion protruding from the 2-1 pad portion 163-1 toward the first pad portion 153.

In addition, the third pad part 183 may include a 3-1 pad part 183-1, a 3-2 pad part 183-2, and a 3-3 pad part 183-3. The 3-1 pad portion 183-1 may be disposed between the 3-2 pad portion 183-2 and the 3-3 pad portion 183-3. In addition, the 3-1 pad part 183-1 is disposed to be spaced apart from the 1-2 pad part 153-2 and the 2-2 pad part 163-2, and the 1-2 pad part 153 -2) and the 2-2 pad part 163-2 may not overlap in the first direction (X-axis direction).

The 3-2nd pad portion 183-2 may be disposed to extend from the 3-1th pad portion 183-1 toward the first pad 153. In other words, the 3-2th pad portion 183-2 may be a portion protruding from the 3-1th pad portion 183-1 toward the first pad 153. In addition, the 3-2nd pad part 183-2 may overlap with the 1-2nd pad part 153-2 in a part of the first direction (X-axis direction).

In addition, the 3-3 pad portion 183-3 may be disposed to extend from the 3-1 pad portion 183-1 toward the second pad 163. In other words, the 3-3 pad portion 183-3 may be a portion protruding from the 3-1 pad portion 183-1 toward the second pad 163. In addition, the 3-3 pad part 183-3 may partially overlap the 2-2 pad part 163-2 in the first direction (X-axis direction). With this configuration, the area of the first pad 153 and the second pad 163 where current injection occurs may be substantially increased, so that heat dissipation through the pad may be further improved. In addition, since the third pad 183 is added and positioned so that heat is radiated in a region between the first pad and the second pad, heat emission and reliability of the semiconductor device may be improved.

In addition, the 3-2 pad part 183-2 is spaced apart from the 1-2 pad part 153-2, and the 3-3 pad part 183-3 is the 2-2 pad part 163 -2) and can be spaced apart. In addition, the above-described information may be applied to the distance between the third pad 183 and the first pad 153 or the distance between the third pad 183 and the second pad 163. With this configuration, the electrical connection between the first pad 153 and the second pad 163 may be blocked.

19 is a cross-sectional view of a semiconductor device package according to an embodiment.

Referring to FIG. 19, a semiconductor device package according to an embodiment includes a body BD including a cavity CV, a first substrate electrode 31 and a second substrate electrode 32 disposed on the body BD, The first substrate electrode 31 and the semiconductor device disposed in the cavity CV, the substrate pads 41, 42, 43 disposed under the body BD, and the light-transmitting member 50 disposed on the cavity CV. Can include.

First, the body BD may include a cavity CV, and may include a substrate 10 and a sidewall 20. In this case, the cavity CV may be defined by the package substrate 10 and the sidewall 20. That is, the cavity CV may include an air gap when the light transmitting member 50 is disposed thereon. The air gap may mean a space filled with air, and one air gap may be formed over the entire area of the cavity CV. However, the present invention is not limited thereto, and various gases other than air (eg, nitrogen) may be filled in the cavity CV, and a polymer or the like may be filled.

The package substrate 10 may be located under the body BD. The package substrate 10 may include a conductive material or an insulating material. The package substrate 10 may include a metal material such as aluminum (Al) or copper (Cu), or may include an insulating material such as ceramic. The ceramic material may include low temperature co-fired ceramic (LTCC) or high temperature co-fired ceramic (HTCC). As an example, the package substrate 10 may include a ceramic material such as AlN. However, the present invention is not limited thereto, and the package substrate 10 may include other ceramic materials such as SiO2, SixOy, Si3N4, SixNy, SiOxNy, Al2O3, and the like.

When the package substrate 10 includes an insulating material, the first substrate electrode 31 and the second substrate electrode 32 may be disposed on the package substrate 10. The first substrate electrode 31 and the second substrate electrode 32 may have the same area, but are not limited thereto.

In addition, the dummy portion 35 may be disposed between the first substrate electrode 31 and the second substrate electrode 32. The dummy part 35 may be made of a thermally conductive and non-electrically conductive material. For example, it may include a Si paste. Accordingly, the dummy part 35 may contact the above-described third pad to receive heat through the third pad and provide it to the outside. The dummy part 35 may be connected to a third substrate pad 43 to be described later through a hole to perform heat transfer and emission.

In addition, the package substrate 10 may include a plurality of via holes VH. The plurality of via holes VH are disposed under the first substrate electrode 31 and the second substrate electrode 32 to be described later, and the first through electrode 33 and the second through electrode 34 to be described later are inside. Can be placed.

In addition, the sidewall 20 may be disposed outside the package substrate 10. In an embodiment, the sidewall 20 may be disposed along the edge of the package substrate 10.

In addition, the sidewall 20 may be made of various materials. For example, the sidewall 20 may be made of an insulating material, and may be made of a material similar to that of the package substrate 10. However, the present invention is not limited thereto, and may be made of an insulating material having a similar thermal expansion coefficient to that of the package substrate 10. In addition, the sidewall 20 may be formed of a conductive material such as metal. For example, the sidewall 20 may efficiently reflect light emitted from an internal semiconductor device including Cu and Al toward the top. In this case, when the sidewall 20 includes a conductive material, it may be disposed to be spaced apart from the first substrate electrode 31 and the second substrate electrode 32 to be described later.

More specifically, the sidewall 20 may include a first wall portion 21 positioned below and a second wall portion 22 positioned on the first wall portion 21.

The first wall part 21 may be located on the side of the package substrate 10. In addition, the first wall portion 21 may be disposed to be in contact with the upper surface of the package substrate 10. The first wall part 21 may have a plurality of layers according to a manufacturing method, but is not limited thereto.

The second wall portion 22 may be positioned above the side wall 20. Specifically, the second wall portion 22 may be disposed on the first wall portion 21 and may be disposed on the side of the first wall portion 21. In an embodiment, the second wall portion 22 may be disposed outside the upper surface of the first wall portion 21.

The first substrate electrode 31 and the second substrate electrode 32 may be disposed on the first package substrate 10. The first substrate electrode 31 and the second substrate electrode 32 may be spaced apart by a predetermined distance. That is, the first substrate electrode 31 and the second substrate electrode 32 may be electrically separated.

In addition, the first substrate electrode 31 and the second substrate electrode 32 may be electrically connected to the semiconductor device. For example, the first electrode pad 153 of the semiconductor device may be disposed on the first substrate electrode 31 and electrically connected to the first electrode pad 153. Further, the second electrode pad 163 of the semiconductor device may be disposed on the second substrate electrode 32 and electrically connected to the second electrode pad 163.

The first through electrode 33 and the second through electrode 34 may be disposed inside the package substrate 10. More specifically, the first through electrode 33 and the second through electrode 34 may be disposed in the via hole VH in the package substrate 10.

In addition, the first through electrode 33 may be located under the first substrate electrode 31 and may be electrically connected to the first substrate electrode 31. In addition, corresponding to the first through electrode 33, the second through electrode 34 may be positioned under the second substrate electrode 32 and may be electrically connected to the second substrate electrode 32. Accordingly, the first through electrode 33 and the second through electrode 34 may have electrical channels and thermal channels of the first and second substrate electrodes 31 and 32, respectively. Accordingly, current and heat from the semiconductor device may be provided to the lower portion of the package substrate 10 through the first through electrode 33 and the second through electrode 34.

In addition, the semiconductor device may be positioned on the first substrate electrode 31 and the second substrate electrode 32. In addition, the semiconductor device is electrically connected to the first substrate electrode 31 and the second substrate electrode 32 through the first electrode pad 153 and the second electrode pad 163 as described above to receive current. have. In addition, it should be understood that the semiconductor device according to the various embodiments described above can be applied to the semiconductor device.

The first substrate pad 41, the second substrate pad 42, and the third substrate pad 43 may be positioned under the package substrate 10.

The first substrate pad 41 and the second substrate pad 42 may be disposed under the package substrate 10 to be spaced apart from each other. Accordingly, the first substrate pad 41 and the second substrate pad 42 may be electrically insulated. In addition, the third substrate pad 43 may be positioned between the first substrate pad 41 and the second substrate pad 42.

In addition, the first substrate pad 41 may be electrically connected to the first through electrode 33 disposed in the via hole VH of the package substrate 10. Accordingly, the first substrate pad 41 may form an electrical channel with the first through electrode 33 and the first substrate electrode 31.

In addition, the second substrate pad 42 may be electrically connected to the second through electrode 34 disposed in the via hole VH of the package substrate 10. Accordingly, the second substrate pad 42 may form an electrical channel with the second through electrode 34 and the second substrate electrode 32.

The third substrate pad 43 may be disposed to be spaced apart from the first substrate pad 41 and the second substrate pad 42. That is, the third substrate pad 43 may not be electrically connected to the first substrate electrode 31 and the second substrate electrode 32. Accordingly, the third substrate pad 43 may be a dummy pad. However, as described above, heat radiation may be performed by being connected to the dummy part 35 through a hole. Accordingly, the third substrate pad 43 can easily dissipate heat generated by driving of the semiconductor device to the outside. That is, the third substrate pad 43 may improve reliability of the semiconductor device package according to the embodiment.

The light transmitting member 50 may be located in or on the body BD. That is, the light-transmitting member 50 may be positioned on the first wall part 21 of the side wall 20 or the second wall part 22. The light-transmitting member 50 may be made of a light-transmitting material. In particular, it may be made of a material having high light transmittance for a wavelength band of light emitted from a semiconductor device. For example, when the semiconductor device emits light having an ultraviolet wavelength band as a center wavelength, the light-transmitting member 50 may also be made of a material having a high transmittance for light having an ultraviolet wavelength band as the center wavelength.

The semiconductor device can be applied to various types of light source devices. For example, the light source device may be a concept including a sterilization device, a curing device, a lighting device, and a display device and a vehicle lamp. That is, the semiconductor device can be applied to various electronic devices that are disposed in a case to provide light.

The sterilization device may sterilize a desired area by including the semiconductor device according to the embodiment. The sterilization device may be applied to household appliances such as water purifiers, air conditioners, and refrigerators, but is not limited thereto. That is, the sterilization device can be applied to all products (eg, medical devices) that require sterilization.

Exemplarily, the water purifier may include a sterilization device according to an embodiment to sterilize circulating water. The sterilization device is disposed in a nozzle or outlet through which water circulates to irradiate ultraviolet rays. In this case, the sterilization device may include a waterproof structure.

The curing apparatus may cure various types of liquids by including the semiconductor device according to the embodiment. The liquid may be the broadest concept including all of the various materials that are cured when irradiated with ultraviolet rays. Exemplarily, the curing device can cure various types of resins. Alternatively, the curing device may be applied to cure cosmetic products such as manicure.

The lighting device may include a light source module including a substrate and the semiconductor device of the embodiment, a heat dissipation unit for dissipating heat from the light source module, and a power supply unit for processing or converting an electrical signal received from the outside to provide the light source module. In addition, the lighting device may include a lamp, a head lamp, or a street light.

The display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may constitute a backlight unit.

The reflector is disposed on the bottom cover, and the light emitting module may emit light. The light guide plate is disposed in front of the reflective plate to guide light emitted from the light emitting module to the front, and the optical sheet may include a prism sheet and the like, and may be disposed in front of the light guide plate. A display panel may be disposed in front of the optical sheet, an image signal output circuit supplies an image signal to the display panel, and a color filter may be disposed in front of the display panel.

When the semiconductor device is used as a backlight unit of a display device, it may be used as an edge type backlight unit or a direct type backlight unit.

In addition to the above-described light emitting diode, the semiconductor device may be a laser diode.

Like the light emitting device, the laser diode may include a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer having the above-described structure. In addition, the p-type first conductivity type semiconductor and the n-type second conductivity type semiconductor are bonded to each other and use the electro-luminescence phenomenon in which light is emitted when current is passed, but the direction of the emitted light There are differences in and phase. In other words, in the laser diode, light having a specific wavelength (monochrome light, monochromatic beam) can be emitted in the same direction with the same phase by using a phenomenon of stimulated emission and constructive interference. Therefore, it can be used for optical communication, medical equipment, and semiconductor processing equipment.

As an example of the light-receiving element, a photodetector, which is a kind of transducer that detects light and converts its intensity into an electric signal, is exemplified. As such photodetectors, photovoltaic cells (silicon, selenium), photoelectric devices (cadmium sulfide, cadmium selenide), photodiodes (for example, PD with a peak wavelength in the visible blind spectral region or true blind spectral region), Transistors, photomultiplier tubes, photoelectric tubes (vacuum, gas encapsulated), IR (Infra-Red) detectors, etc. are provided, but embodiments are not limited thereto.

In addition, semiconductor devices such as photodetectors may be generally manufactured using a direct bandgap semiconductor having excellent light conversion efficiency. Alternatively, photodetectors have various structures, and the most common structures include a pin-type photodetector using a pn junction, a Schottky photodetector using a Schottky junction, and a metal semiconductor metal (MSM) photodetector. have.

The photodiode may include a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer having the above-described structure, as in the light emitting device, and has a pn junction or a pin structure. The photodiode operates by applying a reverse bias or a zero bias, and when light is incident on the photodiode, electrons and holes are generated and a current flows. At this time, the magnitude of the current may be substantially proportional to the intensity of light incident on the photodiode.

A photovoltaic cell or a solar cell is a type of photodiode and can convert light into electric current. The solar cell may include a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer having the above-described structure, similarly to the light emitting device.

In addition, it may be used as a rectifier of an electronic circuit through the rectification characteristic of a general diode using a p-n junction, and may be applied to an ultra-high frequency circuit and applied to an oscillation circuit.

In addition, the above-described semiconductor device is not necessarily implemented as a semiconductor, and may further include a metallic material in some cases. For example, a semiconductor device such as a light receiving device may be implemented using at least one of Ag, Al, Au, In, Ga, N, Zn, Se, P, or As, and may be implemented by a p-type or n-type dopant. It may be implemented using a doped semiconductor material or an intrinsic semiconductor material.

Claims (10)

A semiconductor structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
An insulating layer disposed on the semiconductor structure;
A first electrode disposed on the first conductivity type semiconductor layer;
A second electrode disposed on the second conductivity type semiconductor layer;
A first pad disposed on the first electrode; And
Including; a second pad disposed on the second electrode,
The second pad at least partially overlaps the active layer in a first direction,
The first direction is a direction from the first conductivity type semiconductor layer toward the second conductivity type semiconductor layer,
The insulating layer is disposed in a region between the first pad and the second pad and includes a groove overlapping the second conductivity type semiconductor layer in the first direction.
The method of claim 1,
The groove, an inclined surface; And a lower surface disposed between adjacent inclined surfaces.
The method of claim 2,
The inclined surface is a semiconductor device disposed to surround the lower surface.
The method of claim 2,
The groove penetrates the insulating layer.
The method of claim 3,
The groove is disposed to penetrate to a partial region of the second electrode,
The lower surface overlaps the second electrode in a second direction,
The second direction is a direction perpendicular to the first direction, and a direction from the first pad toward the second pad.
The method of claim 2,
The second pad at least partially overlaps the groove in a first direction.
The method of claim 2,
The ratio of the overall width of the lower surface and the width in the second direction between the first pad and the second pad is 1:1.2 to 1:3,
The second direction is a direction perpendicular to the first direction, and a direction from the first pad toward the second pad.
The method of claim 2,
The first electrode includes a first-first electrode region overlapping the first pad in the first direction, a first-second electrode region overlapping the second pad, and the first-first electrode region in the first direction And a 1-3 electrode region disposed between the first and second electrode regions,
The second electrode is a 2-1 electrode area overlapping the first pad in the first direction, a 2-2 electrode area overlapping the second pad, and the 2-1 electrode area in the first direction And a 2-3rd electrode region disposed between the 2-2nd electrode region,
The groove is a semiconductor device disposed between the first-third electrode region and the second-third electrode region.
The method of claim 1,
A second ohmic electrode disposed between the semiconductor structure and the second electrode; further comprising,
The groove is disposed to penetrate to a partial region of the second ohmic electrode.
The method of claim 9,
A semiconductor device further comprising a first ohmic electrode disposed between the semiconductor structure and the first electrode.

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