KR20210007410A - Buck converter recycling gate charge of power transistor - Google Patents

Abstract

The present invention relates to a buck converter capable of recycling a power transistor gate charge. According to the present invention, the buck converter capable of recycling a power transistor gate charge comprises: a PWM controller for alternately outputting PWM control signals SW_P and SW_N; a three-phase buffer BF_1 and a three-phase buffer BF_2; a PMOS transistor M_P and an NMOS transistor M_N; a capacitor C_(GP) and a capacitor C_(GN); a switch M_1 and a switch M_2; and a capacitor C_(OUT). According to the present invention, it is possible to dramatically improve power efficiency.

Description

Buck converter recycling gate charge of power transistor {BUCK CONVERTER RECYCLING GATE CHARGE OF POWER TRANSISTOR}

The present invention relates to a buck converter, and more particularly, to a buck converter that recycles charge of a power transistor gate.

1 is a circuit diagram of a buck converter according to the prior art, and FIG. 2 is a timing diagram of a buck converter according to the prior art.

The buck converter of FIG. 1 uses two power transistors M _P and M _N that are turned on opposite to each other and an inductor L that stores charging energy to store charging energy in the inductor L or load (load) It is configured to operate by repeating the steps of discharging energy with I _LOAD . At this time, it is configured to supply a constant output voltage V _OUT from the input voltage V _IN by adjusting the inductor current I _L according to the load current I _LOAD .

Here, the switch signals SW _P and SW _N generated by the PWM controller are transmitted to the power transistors M _P and M _N through a gate driver.

However, as the switch signals SW _P and SW _N are charged and discharged at the gates of the power transistors M _P and M _N , there is a problem that gate charge loss occurs. Specifically, if another switch is operated before one power transistor is turned off, a short-circuit condition is caused, and a short-circuit current rapidly increases current consumption.

Accordingly, as shown in the timing diagram of FIG. 2, the switch signals SW _P and SW _N are controlled to form a dead time in which both power transistors M _P and M _N are turned off, thereby preventing the occurrence of a short-circuit current.

Registered Patent Publication 10-1310092 Registered Patent Publication 10-1631677

It is an object of the present invention to provide a buck converter that recycles power transistor gate charge.

The buck converter for recycling the power transistor gate charge according to the object of the present invention described above is a PWM controller that alternately outputs PWM control signals SW _P and SW _N having opposite values (1 or 0) to each other. modulation controller); A three-phase buffer BF ₁ and a three-phase buffer BF ₂ respectively receiving and outputting the PWM control signals SW _P and SW _N output from the PWM controller; PMOS transistors M _P and NMOS transistors M _{N for} receiving PWM control signals SW _P and SW _N output from the three-phase buffer BF ₁ and the three-phase buffer BF ₂ to the gate G _P and the gate G _N , respectively; A capacitor C _GP and a capacitor C _GN each having one end connected to the gate G _P and the gate G _N and the other end connected to the ground; A switch M ₁ and a switch M _{2 having one} end connected to the gate G _P and the gate G _N , respectively, each other end being connected to each other, and outputting an output voltage V _OUT to a load through the other end; It may be configured to include a capacitor C _OUT whose one end is connected to the other end of the switch M ₁ and the switch M _{2 and} the other end is connected to the ground.

Here, the PMOS transistor M _P has one end connected to the input voltage V _IN and the other end connected to the NMOS transistor M _N , and the NMOS transistor M _N has one end connected to the PMOS transistor M _P and the other end connected to the ground. It can be configured to be connected.

In addition, the three-phase buffer BF ₁ and the three-phase buffer BF _{2 each} have terminals CR _P and CR _N indicating a state signal of a high impedance state at an output terminal, and the terminals CR _P and CR _N are the It may be configured to be connected to each gate terminal of the switch M ₁ and the switch M ₂ , respectively.

Meanwhile, when the PWM control signal SW _P is changed from 1 to 0, the terminal CR _P becomes 0, and the three-phase buffer BF ₁ is configured to be in a high impedance state, and the 0 of the terminal CR _P is The switch M ₁ may be configured to be turned on while being input to the gate of the switch M ₁ .

At this time, when the signal of the gate G _P of the PMOS transistor M _P changes from 1 to 0, the charge charged in the capacitor C _GP is transferred to the three-phase buffer BF ₁ connected to the PMOS transistor M _P and the turn-on. ) Can be configured to charge the capacitor C _OUT through the switched M ₁ .

And when the PWM control signal SW _N is changed from 0 to 1, the terminal CR _N becomes 0 and the three-phase buffer BF ₂ is configured to be in a high impedance state, and the 0 of the terminal CR _N is The switch M ₂ may be configured to be turned on while being input to the gate of the switch M ₂ .

Here, when the signal of the gate G _N of the NMOS transistor M _N changes from 0 to 1, the charge charged in the capacitor C _OUT is transferred to the NMOS through a three-phase buffer BF ₂ and a switch M ₂ connected to the NMOS transistor M _N. by passing the gate G of the transistor M _{N N} it may be configured to recycle the charge.

According to the buck converter that recycles the gate charge of the power transistor described above, the charge lost from the gate of the PMOS transistor is stored in the capacitor connected to the gate of the PMOS transistor and then recycled in the capacitor connected to the gate of the NMOS transistor. And dramatically improve the power efficiency of the existing buck converter.

1 is a circuit diagram of a buck converter according to the prior art.
2 is a timing diagram of a buck converter according to the prior art.
3 is a circuit diagram of a buck converter recycling power transistor gate charge according to an embodiment of the present invention.
4 is a timing diagram of a buck converter recycling power transistor gate charges according to an embodiment of the present invention.

In the present invention, various modifications may be made and various embodiments may be provided, and specific embodiments will be illustrated in the drawings and will be described in detail in specific details for carrying out the invention. However, this is not intended to limit the present invention to a specific embodiment, it is to be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention. In describing each drawing, similar reference numerals have been used for similar elements.

Terms such as first, second, A, and B may be used to describe various elements, but the elements should not be limited by the terms. These terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. Does not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a buck converter recycling power transistor gate charges according to an embodiment of the present invention, and FIG. 4 is a timing diagram of a buck converter recycling power transistor gate charges according to an embodiment of the present invention.

First, referring to FIG. 3, a buck converter for recycling the power transistor gate charge according to an embodiment of the present invention includes a pulse width modulation controller, a three-phase buffer BF _1, and a three-phase buffer BF ₂ , respectively. It may be configured to include a gate driver 1 and a gate driver 2, a PMOS transistor M _P and an NMOS transistor M _N , a capacitor C _GP and a capacitor C _GN , a switch M ₁ and a switch M ₂ , and a capacitor C _OUT .

In contrast to the conventional buck converter, the buck converter that recycles the power transistor gate charge further includes a three-phase buffer BF ₁ and a three-phase buffer BF ₂ at each gate terminal of the PMOS transistor M _P and NMOS transistor M _N. A switch M ₁ and a switch M ₂ are added to the output of the transistor M _P and the NMOS transistor M _N.

In addition, a capacitor C _GP and a capacitor C _GN are further provided at each gate terminal of the PMOS transistor M _P and the NMOS transistor M _N.

These configurations are configured to recycle the charge lost in the gate of the PMOS transistor in the gate of the NMOS transistor.

Hereinafter, a detailed configuration will be described.

The PWM controller may be configured to output to the gate driving circuit 1 and the gate driving circuit 2 respectively alternately the PWM control signals SW _P and SW _N having mutually opposite values (1 or 0).

The gate driving circuit 1 and the gate driving circuit 2 may be configured to receive PWM control signals SW _P and SW _N and input them to respective gate terminals of the PMOS transistor M _P and the NMOS transistor M _N.

Here, the gate driving circuit 1 and the gate driving circuit 2 may be configured to include a three-phase buffer BF ₁ and a three-phase buffer BF ₂ .

The three-phase buffer BF ₁ and the three-phase buffer BF ₂ have three terminals, and if the values of terminals CR _P and CR _N of each three-phase buffer are 1, normal buffering is performed, but if the values of terminals CR _P and CR _N are 0 The three-phase buffer BF ₁ and the three-phase buffer BF ₂ are in a high impedance state and are turned off.

The PMOS transistor M _P and the NMOS transistor M _N may be configured to perform an on/off operation as a power transistor.

The PMOS transistor M _P and the NMOS transistor M _N may be configured to receive PWM control signals SW _P and SW _N output from the three-phase buffer BF ₁ and the three-phase buffer BF ₂ to the gate G _P and the gate G _N , respectively.

Here, the PMOS transistor M _P may be configured such that one end is connected to the input voltage V _IN and the other end is connected to the NMOS transistor M _N.

In addition, the NMOS transistor M _N may be configured such that one end is connected to the other end of the PMOS transistor M _{P and} the other end is connected to the ground.

The capacitor C _GP and the capacitor C _GN are configured such that one end of each is connected to the gates of the PMOS transistor M _P and the NMOS transistor M _N , respectively, and each other end may be configured to be connected to the ground.

The switch M ₁ and the switch M ₂ may be provided between the PMOS transistor M _P and the NMOS transistor M _N and V _OUT of the output terminal.

Switch M ₁ and switch M ₂ have one end connected to the gate G _P and gate G _N of the PMOS transistor M _P and NMOS transistor M _N , respectively, and the other end of the switch M ₁ and switch M ₂ It can be configured to be interconnected. In addition, the output voltage V _OUT is output at each other end of the switch M ₁ and the switch M ₂ and can be configured to be connected to a load.

Each gate of the switch M ₁ and the switch M ₂ may be configured to be connected to terminals CR _P and CR _N of the three-phase buffer BF ₁ and the three-phase buffer BF ₂ , respectively.

The capacitor C _OUT may be provided between the other ends of the switch M ₁ and the switch M ₂ from which the output voltage V _OUT is output and the ground.

In addition, an inductor L may be provided between the connection terminal of the PMOS transistor M _P and the NMOS transistor M _N and the connection terminal of the switch M ₁ and the switch M ₂ .

Hereinafter, the operation of the buck converter will be described in more detail.

First, when the PWM control signal SW _P output from the PWM controller changes from 1 to 0, the terminal CR _P becomes 0, and the 3-phase buffer BF ₁ becomes high impedance.

At this time, 3-phase buffers BF ₁ is a three-phase buffer terminal BF ₁ is off (off) from a high-impedance state, the switch M ₁ is turned on (turn-on) while the 0 CR _P input to the gate of the switch M _1.

And when the signal of the gate G _P of the PMOS transistor M _P changes from 1 to 0, the charge already charged in the capacitor C _GP is transferred to the capacitor C through the three-phase buffer BF ₁ connected to the PMOS transistor M _P and the turned-on switch M ₁ Can be configured to charge _OUT .

Through the above operation, the charging operation of capacitor C _OUT is completed.

On the other hand, when the PWM control signal SW _N output from the PWM controller is changed from 0 to 1, the terminal CR _N becomes 0 and the 3-phase buffer BF ₂ is in a high impedance state.

At this time, the terminal switch M ₂ is turned on (turn-on) while the CR 0 _N is input to the gate of the switch M _2.

And when the signal of the gate G _N of the NMOS transistor M _N changes from 0 to 1, the charge previously charged in the capacitor C _OUT is transferred to the NMOS transistor M _N through the three-phase buffer BF ₂ and the switch M _{2 connected} to the NMOS transistor M _N. It is passed to the gate G _N.

That is, PMOS transistors M _P in the operation of the charge loss in the gate _GP C and charged in the capacitor C _OUT, is recycled is input to a gate at the time of operation of the NMOS transistor M _N charges charged in the capacitor C _OUT.

Accordingly, it is possible to reduce the gate loss of charge as much as possible, and to recycle it, thereby having an effect of one move.

Recycling of such charge is preferably operated only within a dead time so as not to affect the duty ratio of the PWM control signal.

Although described with reference to the above embodiments, those skilled in the art can understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention described in the following claims. There will be.

Claims (7)

A PWM controller (pulse width modulation controller) for alternately outputting PWM control signals SW _P and SW _N having opposite values (1 or 0) to each other;
A three-phase buffer BF ₁ and a three-phase buffer BF ₂ respectively receiving and outputting the PWM control signals SW _P and SW _N output from the PWM controller;
PMOS transistors M _P and NMOS transistors M _{N for} receiving PWM control signals SW _P and SW _N output from the three-phase buffer BF ₁ and the three-phase buffer BF ₂ to the gate G _P and the gate G _N , respectively;
A capacitor C _GP and a capacitor C _GN each having one end connected to the gate G _P and the gate G _N and the other end connected to the ground;
A switch M ₁ and a switch M _{2 having one} end connected to the gate G _P and the gate G _N , respectively, each other end being connected to each other, and outputting an output voltage V _OUT to a load through the other end;
A buck converter for recycling a power transistor gate charge comprising a capacitor C _OUT whose one end is connected to the other end of the switch M ₁ and the switch M _{2 and} the other end is connected to the ground.
The method of claim 1,
The PMOS transistor M _P is,
One end is connected to the input voltage V _IN and the other end is connected to the NMOS transistor M _N ,
The NMOS transistor M _N is,
A power transistor gate charge recycling buck converter, characterized in that one end is connected to the PMOS transistor M _P and the other end is configured to be connected to the ground.
The method of claim 2,
The three-phase buffer BF ₁ and the three-phase buffer BF ₂ ,
The output terminal is provided with terminals CR _P and CR _N respectively representing a state signal in a high impedance state,
The terminals CR _P and CR _N are,
The buck converter for recycling the power transistor gate charge, characterized in that configured to be connected to each of the gate terminals of the switch M ₁ and the switch M ₂ , respectively.
The method of claim 3,
When the PWM control signal SW _P is changed from 1 to 0, the terminal CR _P becomes 0, and the three-phase buffer BF ₁ is configured to be in a high impedance state, and 0 of the terminal CR _P is the switch. a buck converter to charge recycle power transistor gate being configured such that the switch M ₁ turns on (turn-on) as input to the gate of M _1.
The method of claim 4,
When the signal of the gate G _P of the PMOS transistor M _P changes from 1 to 0, the charge charged in the capacitor C _GP is turned on with the three-phase buffer BF ₁ connected to the PMOS transistor M _P. A power transistor gate charge recycling buck converter configured to charge capacitor C _OUT through switch M ₁ .
The method of claim 5,
When the PWM control signal SW _N is changed from 0 to 1, the terminal CR _N becomes 0, and the three-phase buffer BF ₂ is configured to be in a high impedance state, and 0 of the terminal CR _N is the switch. a buck converter to charge recycle power transistor gate being configured such that the switch M ₂ turns on (turn-on) as input to the gate of M _2.
The method of claim 6,
When the signal of the gate G _N of the NMOS transistor M _N changes from 0 to 1, the charge charged in the capacitor C _OUT is transferred to the NMOS transistor M through a three-phase buffer BF ₂ and a switch M ₂ connected to the NMOS transistor M _N. by passing the gate G of the _{N N} buck converter to charge recycle power transistor gate being configured so as to recycle the charge.

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