KR101310092B1 - Buck converter enhancing response characteristic - Google Patents

Abstract

PURPOSE: A buck converter improving response characteristics is provided to improve response characteristics of output voltage by increasing a crossover frequency of buck converter using a compensating circuit. CONSTITUTION: A clock control part(10) applies a clock signal according to a control signal as an input signal. A control signal increases switching frequency using the change of output voltage. The above-mentioned applied input signal is charged or discharged through a filter (20). A compensation part(30) increases crossover frequency showing the spot in which the converter gain becomes 0. A buck converter(500) improves the response characteristics and noise reduction effect of output voltage at the same time through the clock control part and the compensation part. [Reference numerals] (10) Clock control part; (20) Charge/discharge; (30) Compensation part; (AA) Input voltage; (BB) Output voltage

Description

Buck converter enhancing response characteristic

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buck converter, which is a DC-DC converter for reducing and outputting an input voltage. In particular, the present invention relates to a buck converter that improves response characteristics and also improves noise attenuation performance.

Voltage regulation uses batteries, such as cellular phones, notebook computers and consumer products, especially in various micro devices such as digital ICs, semiconductor memories, display modules, hard disk drives, RF circuits, microprocessors, digital signal processors and analog ICs. It is often required to prevent variations in supply voltage in such applications.

This regulator is called a DC-DC converter because the battery or DC input voltage of the product is often forced to step up to a higher DC voltage or to a lower DC voltage. A boost converter, commonly referred to as a boost converter, is needed when the battery voltage is lower than the voltage needed to power the load. The boost converter may include an inductive switching regulator or a capacitive charge pump. In contrast, pressure reducing converters, commonly referred to as buck converters, are used when the battery voltage is higher than the desired load voltage. Step-down converters may include inductive switching regulators, capacitive charge pumps, and linear regulators.

Various attempts have been made to improve the response characteristics in the above buck converter. Non-patent literature cited below introduces the general structure of a buck converter.

 R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell, MA: Kluwer, 2001.

The technical problem to be solved by the present invention is to meet the technical requirements to improve the response characteristics in the buck converter to reduce the input voltage, and to control the crossover frequency only to satisfy the technical requirements, the attenuation effect of the switching noise By reducing the problem, the problem of being relatively vulnerable to the influence of noise is solved, and it is intended to prevent a sudden change in the output voltage occurring when returning from the increased frequency to the original switching frequency.

In order to solve the above technical problem, a buck converter for reducing and outputting an input voltage according to an embodiment of the present invention, a clock according to a control signal for increasing the switching frequency by using a change in the output voltage A clock control unit which applies a signal as an input signal; And a compensator for increasing a crossover frequency indicating a point where the converter gain becomes zero, wherein the clock controller is configured to increase the crossover using a clock signal based on a control signal for increasing the switching frequency. Increase the width of noise attenuation by frequency.

In the buck converter according to an embodiment, when the output voltage is out of the reference voltage range according to the change of the load current, the clock controller generates a clock signal having a frequency higher than the current frequency.

In the buck converter according to an embodiment, the clock controller may operate at the original switching frequency by decreasing the increased switching frequency after a predetermined time elapses from the time of increasing the switching frequency.

In the buck converter according to an embodiment, the compensator may receive an feedback voltage defined from an output voltage, generate an error voltage, and increase a crossover frequency based on the control signal.

In order to solve the above technical problem, a buck converter for reducing and outputting an input voltage according to another embodiment of the present invention, a clock signal according to a control signal for increasing the switching frequency by using a change in the output voltage is applied as an input signal. A clock control unit; A latch receiving the clock signal and a reset signal to generate pulse width modulation (PWM); A dead time buffer receiving the PWM and generating a first voltage and a second voltage for operating two power transistors, respectively; A filter unit connected to one end of the power transistor to generate an output voltage by having an inductor for charging and discharging; A compensator configured to receive the control signal and increase a crossover frequency indicating a point where a converter gain becomes zero; And receiving a sum SUM of the sensed voltage sensed by the filter unit and a ramp voltage generated from the ramp RAMP generator, receiving an error voltage of the compensating unit, comparing the two, and generating a reset signal and supplying the reset signal to the latch. And a comparator, wherein the clock controller increases a noise attenuation width due to the increased crossover frequency by using a clock signal based on a control signal that increases a switching frequency by using a change in the output voltage.

In the buck converter according to another embodiment, the clock control unit, the first comparator for receiving a first reference voltage which is the upper limit of the output voltage and the reference voltage range; A second comparator receiving a second reference voltage which is a lower limit of the output voltage and the reference voltage range; And a clock generator configured to generate a clock signal based on a result of performing an OR operation on the outputs of the first comparator and the second comparator.

In the buck converter according to another embodiment, the clock control unit further includes a counter for operating at the original switching frequency by decreasing the increased switching frequency after a predetermined time elapses from the time of increasing the switching frequency. can do.

In the buck converter according to another embodiment, the compensation unit includes an error amplifier (error amplifier) for generating an error voltage by receiving a feedback voltage defined from the output voltage, and includes the at least one resistor and capacitor It is possible to increase the crossover frequency based on the control signal.

Embodiments of the present invention can improve the response characteristics of the output voltage by increasing the crossover frequency of the buck converter using a compensation circuit, and can also improve the attenuation effect of the switching noise by increasing the switching frequency, buffer and ramp generator The output voltage can be minimized when returning from the increased frequency to the original switching frequency by using.

1 is a block diagram showing the basic structure of a buck converter.
FIG. 2 is a diagram for describing a compensation method of a buck converter having a closed loop structure.
3 is a view for explaining a method for improving the response characteristics of the output voltage in the buck converter of the closed loop structure of FIG.
4 is a view for explaining a problem of noise reduction effect degradation caused by the response characteristic improving method of FIG.
5 is a block diagram illustrating a structure for simultaneously improving a response characteristic and a noise attenuation effect in a buck converter adopted by embodiments of the present invention.
6 is a circuit diagram illustrating the clock control unit in a buck converter according to an embodiment of the present invention in more detail.
FIG. 7 is a diagram illustrating a change of an output voltage and a clock according to a load current appearing in the clock controller of FIG. 6.
8 is a circuit diagram illustrating in detail the compensator in the buck converter according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a change in output voltage according to a load current when there is no buffer proposed by the compensator of FIG. 8.
FIG. 10 is a circuit diagram illustrating the operation of the compensator of FIG. 8 according to a switching frequency. FIG.
FIG. 11 illustrates a change in duty of the PWM according to the change of the clock when the ramp voltage is constant in the buck converter.
12 is a circuit diagram illustrating in more detail a lamp generator in a buck converter according to an embodiment of the present invention.
FIG. 13 is a circuit diagram illustrating the operation of the lamp generator of FIG. 12 according to a load current.
14 is a diagram illustrating a simulation waveform for an output voltage, a clock, and a ramp voltage according to a load current using a buck converter according to an embodiment of the present invention.
FIG. 15 is a diagram illustrating an output voltage simulation waveform for a load current in comparison with a conventional buck converter and a buck converter proposed by embodiments of the present invention.

Prior to describing the embodiments of the present invention, the buck converter, which is a DC-DC converter for reducing the output voltage and outputting the input voltage, is briefly described with reference to FIGS. 1 and 2. Structural problems that may occur in an environment where they are implemented are presented through FIGS. 3 and 4.

FIG. 1 is a block diagram illustrating a basic structure of a buck converter. The buck converter of FIG. 1 includes a filter including an SR latch 110, a dead time buffer 120, a power transistor (PMOS, NMOS), an inductor, and a capacitor. 130, a compensation circuit composed of an error amplifier 140 and resistors R _C , capacitors C _C1 and C _C2 , a current sensing circuit 150, a ramp (RAMP) generator 160, and a comparator 170. Include.

In filter 130, ESR is a parasitic resistance component of the filter capacitor. The feedback voltage FB and the reference voltage V _REF defined by the output voltage V _OUT and the two feedback resistors R1 and R2 are input to the error amplifier 140, and the error voltage COMP is output to the output of the error amplifier 140. Is generated. The sum SUM of the voltage consisting of the ramp voltage RAMP by the lamp generator 160 and the sensing voltage SENSE of the current sensing circuit 150 by sensing the SW node is an error voltage COMP through the comparator 170. And reset signal is generated. Then, the clock signal CLOCK and the reset signal are input to the SR latch 110, and a pulse width modulation (PWM) is generated as an output. The dead time buffer 120 is used to prevent the shoot-through current of the power transistor, and finally PD and ND voltages for operating the PMOS and NMOS power transistors are generated. The control loop of the buck converter is operated by negative feedback, and a compensation circuit is required to ensure stability.

FIG. 2 is a diagram illustrating a compensation method of a buck converter having a closed loop structure by type II compensation.

In general, current mode buck converters use type II compensation to ensure the stability of the feedback loop. f _LC denotes a double pole by the inductor and capacitor of the filter, and f _P and f _Z denote the pole (f) by the resistor R _C of the compensation circuit and the capacitors C _C1 and C _C2 . _P ) and zero (f _Z ), f _ESR is zero due to the filter's capacitor and parasitic resistance component ESR, and f _C is the crossover frequency. The closed loop system consists of the filter gain by the filter, the compensation gain by the resistors (R _C ) and capacitors (C _C1 , C _C2 ) of the error amplifier and compensation circuit, and the converter gain by two gains. The filter gain is reduced to -40dB / dec slope by f _LC and then to -20dB / dec slope by f _ESR . The compensation gain decreases with a slope of -20 dB / dec at the origin, then has a constant gain by f _Z , and then decreases again with a slope of -20 dB / dec by f _P. The converter gain decreases with a slope of -20 dB / dec at the origin, has a constant gain by f _Z , a slope of -40 dB / dec by f _LC , and a slope of -20 dB / dec again by f _ESR . f will pass _C. After that, we have a slope of -40 dB / dec by f _P.

3 is a view for explaining a method for improving the response characteristics of the output voltage in the buck converter of the closed loop structure of FIG.

In the closed loop system, the response of the buck converter is related to the crossover frequency. f _P1 , f _P2 and f _Z are the output impedance of the error amplifier, the resistance of the compensation circuit (R _C ), and the poles (f _P1 , f _P2 ) and zero (f _Z ) by the capacitors (C _C1 , C _C2 ). Here, by adjusting the _Z f _P1 and f by increasing the cross-over frequency from f to f _{C1 C2,} it is possible to improve the response characteristic of the output voltage. In other words, the crossover frequency is changed from f _C1 to f _C2 .

4 is a view for explaining a problem of noise reduction effect degradation caused by the response characteristic improving method of FIG.

When the method described above with reference to FIG. 3 (change in crossover frequency) is performed, the response characteristic of the output voltage may be improved. However, if only the crossover frequency is increased (f _C1 ? F _C2 ), as shown in FIG. As the width changes from attenuation 1 to attenuation 2, the noise is more affected. In other words, the noise attenuation effect is reduced.

As described above, when only the crossover frequency is changed in order to improve the response characteristic of the output voltage according to the change of the load current in the conventional buck converter, a side effect of reducing the attenuation effect of noise due to the switching frequency appears.

Embodiments of the present invention to be described below have been devised to solve the problems described above, and embodiments of the present invention provide noise in the case of increasing the crossover frequency to improve the response characteristic of the output voltage in a buck converter. In order to solve the problem that the attenuation effect is lowered, a technical means for improving the attenuation effect due to noise by increasing the switching frequency is also proposed. In particular, embodiments of the present invention improve the response characteristics by increasing the crossover frequency when the load current of the buck converter changes, and at the same time improve the noise attenuation effect by increasing the switching frequency, after which the original Return to the switching frequency and operate again. In other words, the proposed buck converter operates at the original switching frequency by increasing the crossover frequency, increasing the switching frequency and decreasing the switching frequency after a certain time when the load current increases or decreases.

In addition, the buck converter proposed through the embodiments of the present invention uses a buffer and a RAMP generator to provide a technical means for minimizing a sudden change in the output voltage at the instant of the change from the high switching frequency to the original switching frequency. It may be provided additionally.

Hereinafter, with reference to the drawings will be described embodiments of the present invention in more detail.

FIG. 5 is a block diagram illustrating a structure for simultaneously improving a response characteristic and a noise attenuation effect in a buck converter 500 adopted by embodiments of the present invention. FIG. The description is omitted about the structure. In FIG. 5, the operation will be described based on a configuration that is differentiated in terms of improving the response characteristic of the output voltage and improving the noise attenuation effect.

The clock controller 10 applies a clock signal corresponding to a control signal that increases the switching frequency by using a change in the output voltage as an input signal. In addition, when the output voltage is out of the reference voltage range according to the change of the load current, the clock controller 10 generates a clock signal having a frequency higher than the current frequency.

On the other hand, the clock control unit 10, after a predetermined time elapses from the time of increasing the switching frequency, it is preferable to reduce the increased switching frequency to operate at the original switching frequency. In other words, once the switching frequency is increased, the high frequency is not maintained continuously, but is returned to the original clock signal by decreasing the frequency after a certain time has elapsed. In this case, the constant time may be determined in consideration of the time of change of the load current and the degree of change of the output voltage, and the determination of the constant time is flexible through an experimental method by those skilled in the art to which the present invention pertains. Can be chosen.

The input signal thus applied can now be charged or discharged through the filter 20 through a series of processes. In particular, the filter 20 may generate an output voltage by repeating a process of storing energy input from a transistor (not shown) for switching the input signal and discharging it to a load by including an inductor.

The compensator 30 increases the crossover frequency indicating the point where the converter gain becomes zero.

Here, the clock control unit 10 increases the noise attenuation width due to the increased crossover frequency by using a clock signal based on the increased switching frequency. Through the one clock controller 10 and the compensator 30, the buck converter 500 may simultaneously improve the response characteristic of the output voltage and the noise attenuation effect.

In addition, the compensation unit 30 may receive an input feedback voltage defined from an output voltage, generate an error voltage, and increase a crossover frequency based on the control signal of the clock controller 10. In particular, the compensator 30 may reduce the variation in the undershoot phenomenon in which the output voltage is greatly reduced in the switching process according to the change of the crossover frequency.

In addition, the buck converter 500 of FIG. 5 may include a ramp generator (not shown) for generating a ramp (RAMP) voltage, and the ramp generator may include a slope of the ramp (RAMP) voltage according to a change in switching frequency. By adjusting, it is preferable to reduce the variation width of the undershoot phenomenon in which the variation width of the error voltage and the output voltage are greatly reduced.

In the above configuration, at least one of the compensation unit 30 and the lamp generator (not shown), which are two configurations for reducing the variation of the undershoot phenomenon, may be selectively provided or modified, but to achieve the sufficient effect. It is desirable for both to be adopted at the same time.

Hereinafter, a detailed circuit configuration devised in consideration of the actual implementation from the function-oriented configuration of the buck converter 500 introduced through FIG. 5 will be presented. The buck converter, which reduces the output voltage and outputs it, has the following configuration.

The clock control unit applies, as an input signal, a clock signal corresponding to a control signal that increases the switching frequency by using a change in the output voltage. The latch receives the clock signal and the reset signal applied from the clock control unit to generate a pulse width modulation (PWM), and the dead time buffer receives the PWM to operate a first voltage for operating two power transistors, and Generate a second voltage. In this case, the power transistors may be PMOS transistors and NMOS transistors, respectively. For convenience, a voltage for operating each power transistor is called a PD voltage and an ND voltage.

Next, the filter unit includes an inductor connected to one end of the power transistor to perform charging and discharging to generate an output voltage. In addition, the compensator receives the output voltage through a negative feedback loop and increases a crossover frequency indicating a point where the converter gain becomes zero. Now, the comparator receives the sum SUM of the sensed voltage sensed from the filter unit and the ramp voltage generated from the ramp RAMP generator, receives an error voltage of the compensating unit, compares them, and generates a reset signal. Supply to the latch.

Through the above configuration, the clock controller increases the noise attenuation width due to the increased crossover frequency by using a clock signal based on a control signal that increases the switching frequency by using the change of the output voltage.

Below, each structure is demonstrated more concretely.

FIG. 6 is a circuit diagram illustrating the clock control unit 10 in a buck converter according to an embodiment of the present invention. In detail, two comparators 11 and 12, an OR logic circuit 13, an SR latch 15, A clock generator 17 and a counter 19. In FIG. 6, V _REF1 represents a first reference voltage, V _REF2 represents a second reference voltage, V _OUT represents an output voltage, and CLOCK _REF represents a reference clock for counter operation.

That is, the first comparator 11 receives and compares the first reference voltage which is the upper limit of the output voltage and the reference voltage range, and the second comparator 12 receives the second reference voltage which is the lower limit of the output voltage and the reference voltage range. The clock generator 17 generates a clock signal based on a result of ORing the outputs of the first comparator 11 and the second comparator 12 through the OR logic circuit 13.

In the clock control unit 10, if the output voltage is lower than the first reference voltage according to a change in load current, the clock generator 17 generates a clock signal having a frequency higher than a current frequency. do. In addition, when the output voltage is higher than the second reference voltage in response to a change in the load current, the clock control unit 10 receives a clock signal having a frequency higher than the current frequency through the clock generator 17. Will be created.

On the other hand, the clock control unit 10, after a predetermined time elapses from the time of increasing the switching frequency, it is preferable to further include a counter (counter) for operating at the original switching frequency by reducing the increased switching frequency. Do. The counter 19 causes the clock generator 17 to start counting from the time of increasing the switching frequency and output a clear signal to the SR latch 15 after a preset reference time has elapsed. Control to operate at a switching frequency of.

FIG. 7 is a diagram illustrating a change in an output voltage and a clock according to a load current appearing in the clock control unit of FIG. 6, and particularly, sections 710 and 720 in which the frequency is increased are markedly displayed.

As can be seen from FIGS. 6 and 7, when the load current I _LOAD increases from I _L to I _H , the output voltage is compared by the first reference voltage and the first comparator, and if the output voltage is the first When the voltage is lower than the reference voltage, the control signal CLK_CON of the clock controller 10 becomes high. This signal is transmitted to the clock generator 17, which generates a relatively high frequency clock and simultaneously operates the counter 19. Then, after a predetermined time, the counter 19 generates a clear signal, and the control signal CLK_CON becomes low to generate a clock signal of the previous frequency through the clock generator 17.

On the other hand, when the load current decreases from I _H to I _L , the output voltage is compared by the second reference voltage and the second comparator. When the load current is higher than the second reference voltage, the control signal CLK_CON becomes high. The clock generator 17 generates a high frequency clock and simultaneously operates the counter 19. After a certain time, the counter 19 generates a clear signal, and the control signal CLK_CON becomes low, and the clock generator 17 generates a clock of a previous frequency.

FIG. 8 is a circuit diagram illustrating the compensator 30 in a buck converter according to an embodiment of the present invention in detail. The compensator 30 generates an error voltage by receiving a feedback voltage defined from an output voltage. An error amplifier 31 may be included. In addition, the at least one resistor and the capacitor may increase the crossover frequency based on the control signal of the clock controller as described above.

More specifically, the compensation unit 30, the first switch unit 33, one end of which controls the resistance connected to the output terminal of the error amplifier, the other end of the resistance is connected in the switching process according to the change in the crossover frequency A second switch unit 35 for controlling the buffer and a third switch unit 37 for controlling a capacitor connected to the other end of the resistor; It may include.

Here, the first switch unit 33 and the third switch unit 37 are simultaneously turned on (off) by the first control signal CLK_CON generated from the clock controller (not shown). The second switch unit 35 is the first switch unit 33 and the third switch unit by a second control signal (the phase may be opposite to the first control signal) generated from the clock control unit. Contrary to (37), it is preferable to be turned on and off.

In FIG. 8, V _OUT represents an output voltage, FB voltage represents an output voltage and a feedback voltage defined by R ₁ and R ₂ , V _REF3 represents a third reference voltage, and COMP voltage represents an error amplifier 31. Indicates an error voltage that is an output of. To adjust the crossover frequency, R ₄ resistors, C ₁ capacitors, and S ₁ and S ₃ switches were added. Under normal conditions, the S ₁ and S ₃ switches are on and the crossover frequency is determined by the R ₃ resistors and the C ₁ and C ₂ capacitors. When the load current increases, the switches S ₁ and S _{3 are} turned off by the control signal CLK_CON generated by the clock controller 30, and the crossover frequencies are determined by R ₃ , R _4, and C ₂ . Then, when the counter (not shown) returns to the original crossover frequency after a predetermined time, the S ₁ and S ₃ switches are turned on again.

FIG. 9 is a diagram illustrating a change in output voltage according to a load current when there is no buffer proposed by the compensator of FIG. 8.

As shown in FIG. 9, when the voltage of the P ₃ node is smaller than the voltage of the P ₂ node and the S ₃ switch is turned on, the voltage of the P ₂ node decreases momentarily and the S ₁ switch is turned on. As the P ₁ node and the P ₂ node are connected, the voltage of the P ₁ node is also reduced, thereby reducing the error voltage COMP. As a result, the duty is reduced, and insufficient current is supplied to the output terminal, causing an undershoot of the output voltage. In addition, when the undershoot occurs, the output voltage is lower than the first reference voltage, and the counter is operated again.In the event of undershoot even though the load current does not change when the counter stops operating after a predetermined time. This happens repeatedly. In order to minimize this undershoot phenomenon, an S ₂ switch and a buffer are added in the embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating the operation of the compensator of FIG. 8 according to a switching frequency. FIG.

As shown in FIG. 10A, the S ₂ switch is turned off at a low switching frequency (which means the original switching frequency), and as shown in FIG. 10B, a high switching frequency (increased switching frequency). and.) in the can to reduce the change of the COMP voltage switch S ₂ is on / off time of the switch S ₃ by matching the voltage at the node P ₂ and P ₃ by the node buffer as a whole.

In summary, the compensator of the buck converter according to an embodiment of the present invention turns on the first switch unit and the third switch unit at the original switching frequency and simultaneously turns off the second switch unit. It is preferable. On the other hand, the compensator reduces the error voltage by the buffer by turning off the first switch unit and the third switch unit at the increased switching frequency and simultaneously turning on the second switch unit. It is desirable to prevent.

FIG. 11 illustrates a change in duty of the PWM according to the change of the clock when the ramp voltage is constant in the buck converter.

As can be seen in FIG. 11, when the switching frequency decreases, the duty of the PWM decreases. As a result, undershoot of the output voltage occurs while the inductor current supplied to the output stage decreases, so that the COMP voltage is increased to increase the duty. Will increase.

In order to minimize the undershoot of the output voltage, the lamp generator 50 of FIG. 12 is proposed.

The voltage-current relationship in the capacitor of FIG. 12 is expressed by Equation 1 below.

Where I is the current, C is the capacitance, t is the time, and V is the voltage. As can be seen in Equation 1, when the current is constant, the amount of change in voltage per unit time is changed by the change in capacitance. The lamp generator 50 may adjust the slope of the lamp voltage according to the switching frequency by adding a C ₃ capacitor and an S ₄ switch in the conventional buck converter structure shown in FIG. 1.

12 is a circuit diagram illustrating in detail a lamp generator 50 in a buck converter according to an embodiment of the present invention, wherein the lamp generator 50 includes two capacitors connected in parallel and one of the capacitors. It may include a switch for controlling.

In FIG. 12, the switch is turned on and off by a control signal CLK_CON generated by a clock controller to adjust an inclination of a ramp voltage according to a change in a switching frequency. It will reduce the change of phenomenon.

FIG. 13 is a circuit diagram illustrating the operation of the lamp generator of FIG. 12 according to the load current, and shows the operation of the switch at a low frequency and a high frequency, respectively.

In Fig. 13A, the ramp generator sets the capacitance to the sum of the two capacitors (C ₃ + C ₄ ) by turning on the S ₄ switch at its original switching frequency (corresponding to a low frequency). You decide.

On the other hand, in FIG. 13B, the ramp generator turns off the switch at the increased switching frequency (corresponding to a high frequency) to determine capacitance by using only the capacitor to which the switch is not connected to the lamp voltage. This increases the slope of. More specifically, when the switching frequency is increased, the S ₄ switch is turned off, the capacitance decreases to C ₄ and the ramp voltage slope increases, and the COMP voltage level at this time is COMP when the ramp voltage slope does not increase. Increases above the voltage level. Thus, even if the switching frequency is lowered, the variation of the COMP voltage becomes smaller and the undershoot of the output voltage is minimized. An S ₅ switch was added to reduce the discharge time of the capacitor when the clock was high.

FIG. 14 is a diagram illustrating a simulation waveform of an output voltage, a clock, and a ramp voltage according to a load current using a buck converter according to an embodiment of the present invention, and illustrates the HSPICE simulation result of the proposed buck converter.

In FIG. 14, the section ① is a section in which the switching frequency is increased by operating the counter, and the section ② is a section in which the output voltage V _OUT changes when returning to the original switching frequency after a predetermined time. As shown in FIG. 14, when the load current I _LOAD increases or decreases, the frequency of the clock increases and the slope of the lamp also increases, thereby minimizing the output voltage change after a certain time.

FIG. 15 is a diagram illustrating an output voltage V _OUT simulation waveform for a load current I _LOAD comparing a conventional buck converter with a buck converter proposed by embodiments of the present invention.

In Fig. 15, ① denotes an output voltage of the proposed structure, and ② denotes an output voltage of a conventional structure. As can be seen from FIG. 15, it can be seen that the output voltage response of the proposed buck converter is relatively faster than in the conventional case.

According to the embodiments of the present invention described above, the response characteristics of the output voltage can be improved by increasing the crossover frequency of the buck converter using a compensation circuit, and the attenuation effect of switching noise can be improved by increasing the switching frequency. Using a buffer and ramp generator, the output voltage change can be minimized when returning from the increased frequency to the original switching frequency.

The present invention has been described above with reference to various embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

110: latch 120: dead time buffer
130 filter 140 error amplifier
150: current sensing circuit 160: lamp generator
170: comparator
500: Buck Converter
10: clock control unit
11: first comparator 12: second comparator
13: OR logic circuit 15: latch
17: clock generator 19: counter
20: filter (charge / discharge part)
30: compensation unit
31 error amplifier 33 first switch unit
35: second switch part 37: third switch part
50: lamp generator

Claims (19)

In the buck converter for reducing the input voltage to output
A clock control unit which applies a clock signal corresponding to a control signal for increasing a switching frequency using a change in an output voltage as an input signal; And
A compensator for increasing a crossover frequency representing a point at which the converter gain becomes zero;
And the clock control unit increases a noise attenuation width due to the increased crossover frequency by using a clock signal based on a control signal for increasing the switching frequency. The method of claim 1,
Wherein the clock control unit comprises:
If the output voltage is out of the reference voltage range in accordance with the change in the load current, the buck converter characterized in that for generating a clock signal of a frequency higher than the current frequency. The method of claim 1,
Wherein the clock control unit comprises:
And after a predetermined time elapses from the time of increasing the switching frequency, the buck converter reduces the increased switching frequency to operate at the original switching frequency. The method of claim 1,
Wherein the compensation unit comprises:
And a feedback voltage defined from an output voltage to generate an error voltage, and increase a crossover frequency based on the control signal. 5. The method of claim 4,
Wherein the compensation unit comprises:
A buck converter, characterized in that for reducing the variation of the undershoot phenomenon that the output voltage is greatly reduced in the switching process according to the change of the crossover frequency. 5. The method of claim 4,
A ramp generator for generating a ramp (RAMP) voltage,
The lamp generator,
The buck converter characterized by reducing the variation of the undershoot phenomenon in which the variation of the error voltage and the output voltage is greatly reduced by adjusting the slope of the ramp (RAMP) voltage according to the change in the switching frequency. In the buck converter for reducing the input voltage to output
A clock control unit which applies a clock signal according to a control signal for increasing a switching frequency using a change in an output voltage as an input signal;
A latch receiving the clock signal and a reset signal to generate pulse width modulation (PWM);
A dead time buffer receiving the PWM and generating a first voltage and a second voltage for operating two power transistors, respectively;
A filter unit connected to one end of the power transistor to generate an output voltage by having an inductor for charging and discharging;
A compensator configured to receive the control signal and increase a crossover frequency indicating a point where a converter gain becomes zero; And
By receiving the sum (SUM) of the sense voltage sensed from the filter unit and the ramp voltage generated from the ramp (RAMP) generator, and receiving the error voltage of the compensation unit to compare the two, generating a reset signal to supply to the latch Comparators; including,
And the clock controller increases a noise attenuation width due to the increased crossover frequency by using a clock signal based on a control signal that increases a switching frequency by using the change of the output voltage. The method of claim 7, wherein
Wherein the clock control unit comprises:
A first comparator receiving a first reference voltage which is an upper limit of the output voltage and a reference voltage range;
A second comparator receiving a second reference voltage which is a lower limit of the output voltage and the reference voltage range; And
And a clock generator configured to generate a clock signal based on an OR operation of the outputs of the first and second comparators. The method of claim 8,
Wherein the clock control unit comprises:
When the output voltage is higher than the first reference voltage according to the change of the load current, the buck converter, characterized in that for generating a clock signal of a frequency higher than the current frequency through the clock generator. The method of claim 8,
Wherein the clock control unit comprises:
If the output voltage is lower than the second reference voltage according to the change of the load current, the buck converter, characterized in that for generating a clock signal of a frequency higher than the current frequency through the clock generator. The method of claim 7, wherein
Wherein the clock control unit comprises:
And a counter for decreasing the increased switching frequency to operate at the original switching frequency after a predetermined time elapses from the time of increasing the switching frequency. The method of claim 11,
The above-
And starting the counting from an increase of the switching frequency and outputting a clear signal after a predetermined reference time has elapsed, thereby controlling the clock generator to operate at the original switching frequency. The method of claim 7, wherein
Wherein the compensation unit comprises:
And an error amplifier receiving an feedback voltage defined from the output voltage and generating an error voltage.
And having at least one resistor and capacitor to increase the crossover frequency based on the control signal. The method of claim 13,
Wherein the compensation unit comprises:
A first switch unit having one end controlling a resistance connected to an output terminal of the error amplifier;
A second switch unit connected to the other end of the resistor to reduce a change width of an undershoot phenomenon in which an output voltage is greatly reduced during a switching process according to a change of a crossover frequency, and a second switch unit controlling the buffer; And
And a third switch unit controlling a capacitor connected to the other end of the resistor.
The first switch unit and the third switch unit are simultaneously turned on (off) by the first control signal generated from the clock control unit,
And the second switch unit is turned on and off in opposition to the first switch unit and the third switch unit by a second control signal generated from the clock controller. 15. The method of claim 14,
Wherein the compensation unit comprises:
A buck converter, characterized in that the first switch portion and the third switch portion on at the original switching frequency, and at the same time turn off the second switch portion. 15. The method of claim 14,
Wherein the compensation unit comprises:
Reducing the error voltage by the buffer by turning off the first switch portion and the third switch portion at the increased switching frequency and simultaneously turning on the second switch portion. Buck converter. The method of claim 13,
The lamp generator,
Two capacitors connected in parallel; And
Including; switch to control one of the capacitors,
The switch is turned on and off by a control signal generated by the clock controller to adjust the slope of the ramp voltage according to the change of the switching frequency, thereby changing the variation of the undershoot phenomenon in which the variation of the error voltage and the output voltage are greatly reduced. Buck converter, characterized in that for reducing. The method of claim 17,
The lamp generator,
A buck converter, characterized in that the capacitance is determined by the sum of the two capacitors by turning on the switch at its original switching frequency. The method of claim 17,
The lamp generator,
Turning off the switch at the increased switching frequency to determine capacitance with only the capacitor to which the switch is not connected, thereby increasing the slope of the ramp voltage.

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