CN107888070B - buck converter - Google Patents
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- CN107888070B CN107888070B CN201610872765.3A CN201610872765A CN107888070B CN 107888070 B CN107888070 B CN 107888070B CN 201610872765 A CN201610872765 A CN 201610872765A CN 107888070 B CN107888070 B CN 107888070B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Abstract
The invention provides a buck converter, which comprises a first power transistor, a second power transistor, a third power transistor and a buck mode control unit. The voltage reduction mode control unit comprises a voltage comparison unit, a logic concurrent unit and a signal transmission unit, the voltage comparison unit compares the control voltage with a preset threshold voltage and outputs a disconnection signal when the control voltage is lower than the threshold voltage, the logic concurrence unit outputs a conduction signal when receiving the disconnection signal and the voltage reduction signal, the signal transmission unit inputs a first driving signal and a second driving signal, and when the signal transmission unit does not receive the turn-off signal and the turn-on signal, the first driving signal is output to the grid electrode of the first power transistor, the second driving signal is output to the grid electrodes of the second power transistor and the third power transistor, when the signal transmission unit receives the turn-off signal and the turn-on signal, the power supply potential is provided to the gates of the first power transistor and the third power transistor and the ground potential is provided to the gate of the second power transistor, thereby discharging the output capacitor connected to the voltage output terminal to ground through the third power transistor.
Description
Technical Field
The present invention relates to power management circuits, and more particularly to a buck converter.
background
Fig. 1 is a circuit diagram of a conventional BUCK (BUCK) converter, and referring to fig. 1, a BUCK converter 10 mainly adopts a peak current mode, which makes a V out terminal reach a preset voltage through a principle of common feedback of a voltage loop and a current loop, and specifically, a V out terminal divides a voltage by a voltage dividing circuit 12 composed of resistors R fh and R fl to obtain a voltage V fb, and then, the voltage V fb is used as an input of an operational amplifier (EA)14 together with an output voltage V ref of a reference Voltage (VREF) module 13, an output V c of the EA 14 is used as an input of a comparator (e.g., a PWM comparator) 15, another input terminal of the comparator 15 is a V r output by a ramp and current sampling signal unit 16, V c and V r are compared by the comparator 16 to generate a comparator output signal R, the comparator output signal R is input to a control logic unit 18 together with an output clock S of an Oscillator (OSC)17, and finally, a power gate control signal NGATE and PGATE are determined through logic operation, so that a high-low output voltage of the BUCK converter 10 is obtained through a preset duty ratio output of an inductor SW 25 and a voltage SW filter composed of the output of the voltage SW 5.
In the conventional operating mode, when the current output voltage of the system is lower than the preset target output voltage of the system, a quick response can be performed, the waveform of the SW output is controlled to reach a duty ratio close to 100%, the output capacitor C out is charged to the maximum extent, so that V out is rapidly increased and finally reaches the preset voltage, but when the current output voltage of the system is lower than the current output voltage of the system, the system control can only adjust the duty ratio of the waveform of the SW output to 0%, namely the buck conversion circuit does not charge the output capacitor C out any more, but the buck converter 10 cannot discharge the output capacitor C out, and can only discharge the output capacitor C out by means of the load resistor R out, the internal feedback resistors R fl and R fh, so that the output voltage V out is reduced.
Disclosure of Invention
The present invention provides a buck converter, which can rapidly reduce the current output voltage of a system to a target output voltage when the output voltage is adjusted from a high voltage to a low voltage.
In order to solve the above technical problem, the present invention provides a buck converter, which includes a first power transistor, a second power transistor, a third power transistor, and a buck mode control unit. The first power transistor is provided with a first source electrode, a first drain electrode and a first grid electrode, wherein the first source electrode is connected with a power supply, and the first drain electrode is connected with the voltage output end. The second power transistor is provided with a second source stage, a second drain stage and a second grid electrode, the second source stage is grounded, and the second drain stage is connected with the voltage output end. The third power transistor has a third source, a third drain and a third gate, the third source is grounded, and the third drain is connected to the voltage output terminal. The voltage reduction mode control unit comprises a voltage comparison unit, a logic concurrent unit and a signal transmission unit, the voltage comparison unit compares a control voltage with a preset threshold voltage and outputs a turn-off signal when the control voltage is lower than the threshold voltage, the logic concurrent unit outputs a conducting signal when receiving the disconnection signal and the voltage reduction signal, the signal transmission unit inputs a first driving signal and a second driving signal, and when the signal transmission unit does not receive the turn-off signal and the turn-on signal, the first driving signal is output to the first gate, the second driving signal is output to the second gate and the third gate, when the signal transmission unit receives the turn-off signal and the turn-on signal, a power supply potential is provided to the first grid and the third grid and a ground potential is provided to the second grid, thereby discharging an output capacitor connected to the voltage output terminal to ground through the third power transistor.
In an embodiment of the invention, the buck converter further includes an output voltage control unit, which provides the buck signal.
In an embodiment of the invention, the output voltage control unit is a digital circuit.
In an embodiment of the invention, the buck converter further includes an operation comparator for comparing a reference voltage with a feedback voltage related to the output voltage, thereby outputting the control voltage.
In an embodiment of the invention, the signal transmission unit has a first input end for inputting the first driving signal, a second input end for inputting the second driving signal, a first output end connected to the first gate, a second output end connected to the second gate, and a third output end connected to the third gate, when the signal transmission unit does not receive the turn-off signal and the turn-on signal, the first input end is connected to the first output end, the second input end is connected to the second output end and the third output end, when the signal transmission unit receives the turn-off signal and the turn-on signal, the first output end is disconnected from the first input end and connected to a power supply, the second output end is disconnected from the second input end and grounded, and the third output end is disconnected from the second input end and connected to the power supply.
In an embodiment of the invention, the first power transistor and the second power transistor are complementary transistors, and the second power transistor and the third power transistor are of the same type.
In an embodiment of the invention, the second power transistor and the third power transistor have a predetermined size ratio.
The invention provides a rapid voltage reduction method of a buck converter, which comprises the following steps: comparing the control voltage with a preset threshold voltage, and outputting a disconnection signal when the control voltage is lower than the threshold voltage; outputting a turn-on signal upon receiving the turn-off signal and the step-down signal; determining first to third gate control signals respectively supplied to the first to third power transistors according to the turn-off signal and the turn-on signal, the first power transistor has a first source, a first drain and a first gate, the first source is connected to a power source, the first drain is connected with the voltage output end, the second power transistor is provided with a second source, a second drain and a second grid, the second source is grounded, the second drain is connected with the voltage output end, the third power transistor is provided with a third source, a third drain and a third grid, the third source is grounded, the third drain is connected with the voltage output end, wherein when receiving the turn-off signal and the turn-on signal, a power supply potential is provided to the first gate and the third gate and a ground potential is provided to the second gate, thereby discharging an output capacitor connected to the voltage output terminal to ground through the third power transistor.
The invention provides a power management chip which comprises the buck converter.
Compared with the prior art, the invention adopts a rapid voltage reduction mode, and can rapidly reduce the output voltage when the target voltage of the system is lower than the current voltage of the system.
Drawings
Fig. 1 is a circuit diagram of a conventional buck converter.
Fig. 2 is a circuit diagram of a buck converter according to an embodiment of the present invention.
Fig. 3 is an internal structure of a buck mode control unit of the buck converter shown in fig. 2.
Fig. 4A and 4B are circuit diagrams of the signal transfer unit shown in fig. 3.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
Fig. 2 is a circuit diagram of a buck converter according to an embodiment of the present invention, referring to fig. 2, a buck converter 20 according to an embodiment of the present invention includes an output voltage control unit 21, a voltage dividing circuit 22, a reference Voltage (VREF) module 23, an operational amplifier (EA)24, a comparator (e.g., PWM comparator) 25, a ramp and current sampling signal unit 26, an Oscillator (OSC)27, a control logic unit 28, and a buck mode control unit 29. the buck converter 20 further includes a first power transistor MP, a second power transistor MN1, and a second power transistor mn2. the output voltage control unit 21, the voltage dividing circuit 22, the reference Voltage (VREF) module 23, the operational amplifier (EA)24, the comparator (e.g., comparator) 25, a ramp and current sampling signal unit 26, an oscillator (3527, and the control logic unit 28 of this embodiment are respectively the same as units shown in fig. 1. the operation principle of the buck converter 20 is that a V out terminal is divided by resistors R fh and R7 to obtain an output voltage signal, which is output as a signal after comparing with a PWM signal inputted from a voltage V5631V 24, the output voltage of the output voltage control signal of the output voltage control unit 21, a ramp and a voltage sampling signal of the output voltage sampling unit 27, and a feedback signal of the output voltage sampling unit 27, which are determined by a PWM signal of the operational amplifier 36493 2, and a PWM signal of the operational amplifier 27, which are input of the operational amplifier 3625, and a PWM signal of the operational amplifier 27, and a PWM signal generator are connected to a PWM signal generator, which are connected to a circuit, and a circuit 24, and a circuit 3627, and a feedback signal of the circuit 36.
The feature of this embodiment is that a buck mode control unit 29 is added between the control logic unit 28 and the power transistors, and two power transistors MN1 and MN2 of N-type will be used. Specifically, the first power transistor MP has a first source connected to the power source VIN, a first drain connected to the voltage output terminal SW, and a first gate. The second power transistor MN1 has a second source connected to the ground GND, a second drain connected to the voltage output terminal SW, and a second gate. And the third power transistor MN2 is provided with a third source stage, a third drain stage and a third grid electrode, wherein the third source stage is grounded GND, and the third drain stage is connected with the voltage output end.
In this embodiment, the first power transistor MP and the second power transistor MN1 are complementary transistors, i.e., one is a P-type transistor and the other is an N-type transistor. The second power transistor and the third power transistor are of the same type and are both N-type transistors.
The buck mode control unit 29 has a first input terminal pgatepe and a second input terminal ngatpepe, and inputs the first driving signal PGATE and the second driving signal NGATE, respectively, the buck mode control unit 29 further has a first control terminal VC and a second control terminal OVSHL, and inputs the control voltage V c and the buck signal shovl, respectively, from the output voltage control unit 21, indicating that the system is configured from a high voltage to a low voltage, the output voltage control unit 21 is typically a digital circuit, the buck mode control unit 29 further has a first output terminal pgatefe, a second output terminal ngatable, and a third output terminal FAST DOWN, and outputs the first control signals PAGTE1, NGATE1, and NGATE2, respectively, under the control of the control voltage V c and the buck signal OVSHL, the buck mode control unit selects signals to be supplied to the first output terminal pgatefe, the second output terminal ngatfe, and the third output terminal FAST DOWN.
Referring to fig. 3, the buck mode control unit 29 may include a voltage comparison unit 31, a logic concurrency unit 32, and a signal transfer unit 33, the voltage comparison unit 31 compares a control voltage V c with a preset threshold voltage V TH, and outputs an off signal OPEN when the control voltage V c is lower than the threshold voltage V TH, when this condition is not satisfied, the voltage comparison unit 31 does not output an off signal, one input terminal of the logic concurrency unit 32 is connected to the voltage comparison unit 31, and the other input terminal is connected to a second control terminal OVSHL of the buck mode control unit 29, when the logic concurrency unit 32 receives the off signal OPEN and the buck signal ovshshl, the signal transfer unit 33 outputs a first driving signal pgpgpgpggate, outputs a second driving signal ngt, and outputs a first driving signal atpgpgpgate to the first output terminal, outputs a second driving signal NGATE to the second driving signal nggate when the off signal OPEN and the turn-on signal is not received by the signal transfer unit 33, and further outputs a third driving signal atpgate to a third gate terminal of a second driving signal DOWN, and a third driving signal fasfaasfaasfaasfaat, and a third driving signal fasfaasfaat is further provided to the third gate terminal 2, and a third gate terminal of the second driving signal fasfaasfaat.
out outThus, when the signal transfer unit 33 does not receive the OPEN signal OPEN and the close signal SHORT, the first power transistor MP is controlled by the first driving signal PGATE, the second power transistor MN1 and the third power transistor MN2 are controlled by the second driving signal, and the system operates normally.
When the signal transfer unit 33 receives the OPEN signal OPEN and the on signal SHORT, the second output NGATEAFT is connected to ground potential, while the first output PGATEAFT and the third output FAST DOWN are connected to the supply potential, the first power transistor MP stops operating and no longer charges the capacitor C out, while the second power transistor MN1 is disconnected, the third power transistor MN2 operates to discharge the capacitor C out to ground, so that V out rapidly decreases, here, MN1 and MN2 have a preset ratio, which depends on the requirement of the discharge speed.
When the system output voltage V out reaches the system target voltage, V c is greater than V TH, the voltage comparing unit 31 of fig. 3 clears the OPEN signal and simultaneously clears the SHORT signal through the logic concurrent unit 32, so that the system returns to the conventional control loop.
fig. 4A and 4B are circuit diagrams of the signal transfer unit shown in fig. 3. Referring to fig. 4A, the signal transfer unit 33 has a first input terminal pgatepe to which the first driving signal is input, a second input terminal ngatpere to which the second driving signal is input, a first output terminal connected to the first gate, a second output terminal ngatheaft connected to the second gate, and a third output terminal FAST DOWN connected to the third gate. The signal transmission unit 33 includes a plurality of switches controlled by an off signal OPEN and an on signal SHORT. When the signal pass unit 33 does not receive the turn-off signal and the turn-on signal, as shown in fig. 4A, the first input terminal pgatepe is connected to the first output terminal PGATEAFT, and the second input terminal ngatpepe is connected to the second output terminal ngateeft and the third output terminal FAST DOWN. When the signal transmitting unit 33 receives the OPEN signal OPEN and the on signal SHORT, as shown in fig. 4B, the first output terminal pgateaf is disconnected from the first input terminal pgatepe and connected to the power supply VDD, the second output terminal ngateft is disconnected from the second input terminal ngatpepe and connected to the ground GND, and the third output terminal FAST DOWN is disconnected from the second input terminal ngatpepe and connected to the power supply VDD.
The embodiment of the invention adopts analog control for the voltage reduction mode, namely when a system self-regulation mechanism V c is lower than V TH, a traditional loop is disconnected, and adopts digital control, namely, NGATEAFT is connected to the ground potential after a digital control signal OVSHL is detected, and FAST DOWN and PGATEAFT are connected to the power supply potential.
From another perspective, the present invention provides a fast step-down method of a buck converter, as shown in fig. 2, which compares a control voltage V c with a preset threshold voltage V TH, and outputs an off signal OPEN when the control voltage V c is lower than the threshold voltage V TH, outputs an on signal SHORT when receiving the off signal OPEN and a step-down signal SHORT, determines first to third gate control signals to be respectively supplied to first to third power transistors according to the off signal OPEN and the on signal SHORT, wherein when receiving the off signal OPEN and the on signal SHORT, a power potential is supplied to the first gate and the third gate and a ground potential is supplied to the second gate, thereby discharging an output capacitor C out connected to a voltage output terminal SW to ground through a third power transistor MN 2.
the embodiment of the invention adopts a rapid voltage reduction mode, and can rapidly reduce the output voltage when the target voltage of the system is lower than the current voltage of the system. In addition, the embodiment of the invention adopts digital-analog hybrid control, avoids hard switching of a system and enables the voltage to be stable and continuous.
the circuit and method of the above embodiments of the present invention can be applied to a power management chip. For example, the power management chip may be a portable electronic device such as a cell phone. This circuit may be used to drive a radio frequency power amplifier.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (8)
1. A buck converter comprising:
The first power transistor is provided with a first source electrode, a first drain electrode and a first grid electrode, wherein the first source electrode is connected with a power supply, and the first drain electrode is connected with the voltage output end;
A second power transistor having a second source, a second drain and a second gate, the second source being grounded, the second drain being connected to the voltage output terminal;
A third power transistor having a third source, a third drain and a third gate, the third source being grounded, the third drain being connected to the voltage output terminal;
A voltage-reducing mode control unit including a voltage comparison unit, a logic concurrency unit and a signal transmission unit, wherein the voltage comparison unit compares a control voltage with a preset threshold voltage and outputs a disconnection signal when the control voltage is lower than the threshold voltage, the logic concurrency unit outputs a conduction signal when receiving the disconnection signal and a voltage-reducing signal, the signal transmission unit inputs a first driving signal and a second driving signal, the signal transmission unit has a first input terminal for inputting the first driving signal, a second input terminal for inputting the second driving signal, a first output terminal connected to the first gate, a second output terminal connected to the second gate and a third output terminal connected to the third gate, and when the signal transmission unit does not receive the disconnection signal and the conduction signal, the first input terminal is connected to the first output terminal, and the second input terminal is connected to the second output terminal and the third output terminal, when the signal transmission unit receives the disconnection signal and the conduction signal, the first output end and the first input end are disconnected and connected with a power supply, the second output end and the second input end are disconnected and grounded, and the third output end and the second input end are disconnected and connected with the power supply.
2. The buck converter according to claim 1, further comprising an output voltage control unit providing the buck signal.
3. A buck converter according to claim 2, wherein the output voltage control unit is a digital circuit.
4. The buck converter according to claim 1, further comprising an operation comparator comparing a reference voltage with a feedback voltage with respect to the output voltage, thereby outputting the control voltage.
5. A buck converter according to claim 1, wherein the first and second power transistors are complementary transistors, the second and third power transistors being of the same type.
6. The buck converter according to claim 1, wherein the second power transistor and the third power transistor have a predetermined size ratio.
7. a method of fast buck for a buck converter as claimed in claim 1, said method comprising the steps of:
Comparing the control voltage with a preset threshold voltage, and outputting a disconnection signal when the control voltage is lower than the threshold voltage;
Outputting a turn-on signal upon receiving the turn-off signal and the step-down signal; the first input end of the signal transmission unit inputs the first driving signal, the second input end of the signal transmission unit inputs the second driving signal, the signal transmission unit determines to respectively provide connection relations from the first input end to the first output end and from the second input end to the third output end according to the disconnection signal and the conduction signal, when the disconnection signal and the conduction signal are received, the first output end is disconnected from the first input end and connected with a power supply, the second output end is disconnected from the second input end and grounded, and the third output end is disconnected from the second input end and connected with the power supply, so that an output capacitor connected to the voltage output end discharges to the ground through the third power transistor.
8. A power management chip comprising a buck converter as claimed in any one of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610872765.3A CN107888070B (en) | 2016-09-29 | 2016-09-29 | buck converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610872765.3A CN107888070B (en) | 2016-09-29 | 2016-09-29 | buck converter |
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| CN107888070A CN107888070A (en) | 2018-04-06 |
| CN107888070B true CN107888070B (en) | 2019-12-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2007244156A (en) * | 2006-03-10 | 2007-09-20 | Fuji Electric Device Technology Co Ltd | Switching regulator |
| CN102594146A (en) * | 2011-01-06 | 2012-07-18 | 原景科技股份有限公司 | Buck circuit having fast transient response mechanism and operating method thereof |
| US8461815B1 (en) * | 2009-10-05 | 2013-06-11 | Huy X Ngo | Fast transient buck regulator with dynamic charge/discharge capability |
| CN104753318A (en) * | 2013-12-27 | 2015-07-01 | 展讯通信（上海）有限公司 | BNB (Buck Negative Boost) switching power supply |
-
2016
- 2016-09-29 CN CN201610872765.3A patent/CN107888070B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007244156A (en) * | 2006-03-10 | 2007-09-20 | Fuji Electric Device Technology Co Ltd | Switching regulator |
| US8461815B1 (en) * | 2009-10-05 | 2013-06-11 | Huy X Ngo | Fast transient buck regulator with dynamic charge/discharge capability |
| CN102594146A (en) * | 2011-01-06 | 2012-07-18 | 原景科技股份有限公司 | Buck circuit having fast transient response mechanism and operating method thereof |
| CN104753318A (en) * | 2013-12-27 | 2015-07-01 | 展讯通信（上海）有限公司 | BNB (Buck Negative Boost) switching power supply |
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| CN107888070A (en) | 2018-04-06 |
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