KR20200132809A - Display apparatus and organic luminescense display apparatus - Google Patents

Abstract

The present invention provides a display device which provides a structure of pads to improve bonding failure. The display device comprises: a substrate; a first wiring formed on the substrate; a first pad electrically connected to the first wiring and formed on the same layer as the first wiring; a second wiring formed on another layer with the first wiring and an insulating layer interposed therebetween; a second pad formed on the same layer as the first pad; and a connection unit electrically connecting the second wiring and the second pad.

Description

Display and organic light-emitting display {DISPLAY APPARATUS AND ORGANIC LUMINESCENSE DISPLAY APPARATUS}

The present invention relates to a display device and an organic light emitting diode display including pads disposed in a non-display area around a display area in which an image is displayed.

Recently, display devices are being replaced with portable thin flat panel display devices. Flat panel displays include a liquid crystal display device as a light-receiving display device, and an organic light-emitting display device and a plasma display device as an emissive display device.

Such a flat panel display device is divided into a display area in which an image is displayed on a substrate and a non-display area around the display area. In the non-display area, pads connecting to the driver IC and wirings connecting the display area and the pads are provided.

The driver IC is bonded to the pads using an adhesive containing a conductive material. However, when the thickness of the insulating film formed under the pads is different, there is a problem in that a difference in height occurs between the pads and a bonding failure occurs between the driver IC and the pads.

The present invention relates to a display device and an organic light emitting diode display that disclose a structure of pads for improving the bonding defects described above.

According to an embodiment of the present invention for solving the above problems, a substrate; A first wiring formed on the substrate; A first pad electrically connected to the first wiring and formed on the same layer as the first wiring; A second wiring formed on another layer with the first wiring and an insulating layer therebetween; A second pad formed on the same layer as the first pad; And a connection part electrically connecting the second wiring and the second pad. Disclosed is a display device including.

The plurality of first wirings and the plurality of second wirings are alternately arranged with each other.

* The plurality of first pads and the plurality of second pads are alternately arranged to be alternately arranged.

The first wiring and the first pad are integrally formed.

First and second insulating layers including first openings exposing a portion of the first pad; And a first protective layer covering the first pad exposed through the first opening. It includes more.

First and second insulating layers including second openings exposing a portion of the second pad; And a second protective layer covering the second pad exposed through the second opening. It includes more.

The second insulating layer covers the second wiring and includes a contact hole for connecting the second wiring and the connecting portion, and the connecting portion is integrally formed with the second protective layer.

A first insulating layer including a first opening exposing a portion of the first pad; And a first protective layer covering the first pad exposed through the first opening. It includes more.

A first insulating layer including a second opening exposing a portion of the second pad; And a second protective layer covering the second pad exposed through the second opening. It includes more.

A second insulating layer and the first insulating layer are formed on the second wiring, the first and second insulating layers include contact holes for connecting the second wiring and the connection portion, and the connection portion It is formed integrally with the second protective layer.

One end of the first wiring and the second wiring is connected to a display area for displaying an image.

According to an embodiment of the present invention for solving the above-described problems, there is provided a substrate partitioned into a display area in which an image is displayed and a non-display area around the display area; A plurality of first gate lines formed in the display area and extending in a first direction; A plurality of second gate lines formed in the display area, insulated by the first gate line and a first insulating layer, and extending in a second direction; A plurality of data lines formed in the display area, insulated by the second gate line and a second insulating layer, and extending in a second direction crossing the first direction; A pixel including a driving circuit part electrically connected to the first gate line or the second gate line and the data line; An organic light-emitting device included in the pixel and electrically connected to the driving circuit to emit light; Pads disposed in the non-display area; And wires connecting the pads and the display area. Wherein the wirings include first wirings and second wirings formed on another layer with the first wirings and the insulating layer interposed therebetween, and the pads are electrically connected to the first wirings, and the first wirings And first pads formed on the same layer as the first pad and second pads formed on the same layer as the first pad, wherein: a connection portion electrically connecting the second wiring and the second pad; Disclosed is an organic light emitting display device further comprising a.

The plurality of first wirings and the plurality of second wirings are alternately arranged with each other.

The plurality of first pads and the plurality of second pads are alternately disposed to be alternately arranged with each other.

The first wiring and the first pad are integrally formed.

The first pad is formed on the same layer as the first gate line, the first and second insulating layers include a first opening exposing a part of the first pad, and the first pad exposed through the first opening A first protective layer covering the first pad; It includes more.

The second pad is formed on the same layer as the first gate line, the first and second insulating layers include a second opening exposing a part of the second pad, and the exposed through the second opening A second protective layer covering the second pad; It includes more.

The second wiring is formed on the same layer as the second gate line, the second insulating layer covers the second wiring and includes a contact hole for connecting the second wiring and the connection portion, and the connection portion It is formed integrally with the second protective layer.

The first pad is formed on the same layer as the second gate line, the second insulating layer includes a first opening exposing a part of the first pad, and the first pad exposed through the first opening A first protective layer covering; It includes more.

The second pad is formed on the same layer as the second gate line, the second insulating layer includes a second opening exposing a part of the second pad, and includes the second pad exposed through the second opening. A second protective layer covering; It includes more.

The second wiring is formed on the same layer as the first gate line, the first and second insulating layers include contact holes for connecting the second wiring and the connection part, and the connection part is the second protective layer Is formed integrally with

According to an embodiment of the present invention, bonding failures between the pads and the driver IC are improved by forming even pads connected to wirings formed on different layers on the same layer through a connection portion.

Meanwhile, according to an embodiment of the present invention, wirings arranged in the non-display area are alternately arranged on different layers, thereby minimizing dead space by reducing the spacing between the wirings, and easy fan-out in a small panel or high-resolution display device. Sub-design is possible.

1 is a schematic diagram of a display substrate 100 of an organic light emitting diode display according to an exemplary embodiment of the present invention.
FIG. 2 is a surface of FIG. 1 taken along line II-II.
3 is an enlarged view of a pixel portion of FIG. 1.
4 is an enlarged view of A of FIG. 1.
5 is a surface of FIG. 4 cut along the line V-V.
6 is a surface cut along the line VI-VI of FIG. 4.
7 is a surface cut along the line VII-VII in FIG. 4.
8 is a view showing A of FIG. 1 according to another embodiment of the present invention.
FIG. 9 is a surface of FIG. 8 cut along the line IX-IX.
10 is a surface cut along line X-X in FIG. 8.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art may easily implement the present invention. The present invention may be implemented in various different forms and is not limited to the embodiments described herein.

In order to clearly describe the present invention, parts irrelevant to the description have been omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

Terms such as first and second may be used to describe various components, but the components should not be limited by terms. The terms are only used for the purpose of distinguishing one component from another component. For example, the first pad, the second pad, the first wiring, and the second wiring prepared in claims 8 to 10 are the pads 2a, pads 1a and 2 fan-outs of FIGS. 8 to 10, respectively. , May refer to a first fan-out wiring.

In the present specification, when a part such as a layer, a film, a region, or a plate is said to be on or on another part, this includes not only the case directly above the other part, but also the case where there is another part in the middle.

In the drawings, the thicknesses are enlarged to clearly express various layers and regions. In addition, in the drawings, the thicknesses of some layers and regions are exaggerated for convenience of description.

Hereinafter, a display device according to an exemplary embodiment will be described in detail with reference to the drawings. In the present embodiment, it is described that the display device is an organic light emitting display device as an example, but this is only exemplary, and an embodiment of the present invention is a display device including pads in a non-display area such as a liquid crystal display device and a plasma display device Is applicable to all.

1 is a schematic diagram of a display substrate 100 of an organic light emitting diode display according to an exemplary embodiment of the present invention. FIG. 2 is a surface of FIG. 1 cut along the line II-II. 3 is an enlarged view of a pixel portion of FIG. 1. 4 is an enlarged view of A of FIG. 1. 5 is a surface of FIG. 4 cut along the line V-V. 6 is a surface cut along the line VI-VI of FIG. 4. 7 is a surface cut along the line VII-VII in FIG. 4.

Referring to FIG. 1, an organic light emitting display device according to an exemplary embodiment of the present invention includes a display substrate 100 and a sealing substrate (not shown). The display substrate 100 is divided into a display area DA in which an image is displayed and a non-display area NDA around the display area DA. Although not shown, a sealing member is disposed in the non-display area NDA so as to surround the display area DA to bond a sealing substrate that seals the display area DA from outside air. However, when the sealing substrate is a thin film encapsulation type, the sealing member may be omitted. The sealing substrate is disposed so as to face the display substrate 100 with the sealing member therebetween, but the sealing substrate is not shown in FIG. 1. Hereinafter, the display substrate 100 including the features of the present invention will be described in detail.

First, the display area DA of the display substrate 100 will be described in detail with reference to FIGS. 1 to 3. 1 to 3 illustrate one first gate line GL1, a second gate line GL2, a data line DL, and one pixel P, but these are exemplary and the entire display area DA is A plurality of wires and pixels may be disposed.

1 to 3, the display area DA is an area in which an image is displayed, and is an area in which various signal lines and pixels P connected to the various signal lines are disposed. The signal wires include first gate wires GL1 and second gate wires GL2 extending in a first direction, and data wires DL extending in a second direction, and the first gate wires GL1 ) And the pixel P is disposed in a region where the second gate lines GL2 and the data lines DL cross each other.

The first gate wirings GL1 are provided on the first gate insulating layer 113 and extend in the first direction X. The first gate wirings GL1 may include a previous scan line and a light emission control line, but are not limited thereto. The first gate wirings GL1 may be connected to a gate driver (not shown) or a light emission control driver (not shown) to receive a scan signal or a light emission control signal, but are not limited thereto.

The second gate wirings GL2 are insulated from the first gate wirings GL1 with the second gate insulating layer 123 therebetween, and extend in the first direction X. The second gate wirings GL2 may include a scan line and an initialization power line, but are not limited thereto. The second gate wirings GL2 may be connected to a gate driver (not shown) or an initialization power driver (not shown) to receive a scan signal or initialization power, but is not limited thereto.

The first gate wirings GL1 and the second gate wirings GL2 are non-overlapping with each other. That is, the first gate lines GL1 and the second gate lines GL2 do not overlap each other. As described above, in the display substrate 100 according to an exemplary embodiment of the present invention, each of the first gate wirings GL1 and the second gate wirings GL2, which are gate wirings, has the second gate insulating layer 123 therebetween. By being positioned in different layers, since the distance W1 between neighboring gate wirings positioned in different layers can be formed narrow, more pixels P can be formed in the same area. That is, a high-resolution display device can be formed.

The types of signal wires constituted by the above-described first and second gate wires GL1 and GL2, the types of signals transmitted by the signal wires, and the type, number, and location of drivers to which the signal wires are connected It is not limited to the contents described and illustrated, and may be variously applied and changed according to the design contents.

The data lines DL are insulated from the gate lines GL1 and GL2 with the interlayer insulating layer 105 interposed therebetween, and extend in a second direction Y crossing the first direction X. The data lines DL are connected to a driver IC (not shown) mounted in the non-display area NDA through pads and fan-out lines. The data line DL receives a data signal from a driver IC (not shown) through fan-out lines.

A plurality of pixels P are disposed in the crossing regions of the first gate lines GL1, the second gate lines GL2, and the data lines DL. The pixel may emit red, green, or blue light, but is not limited thereto and may emit white light.

The pixel P includes an organic light-emitting device OLED that emits light with a luminance corresponding to a driving current corresponding to a data signal, and a pixel circuit (or driving circuit) for controlling a driving current flowing through the organic light-emitting device OLED. do. The pixel circuit is connected to each of the first gate lines GL1, the second gate lines GL2, and the data lines DL, and the organic light emitting device OLED is connected to the pixel circuit. The pixel circuit may include a plurality of thin film transistors Ta and Tb and at least one capacitor (not shown).

Referring to FIG. 3, the structure of the pixel P including the pixel circuit and the organic light emitting device will be described in detail.

Meanwhile, FIG. 3 shows two thin film transistors and an organic light emitting device included in the pixel P, but the pixel P may further include an additional thin film transistor and a capacitor in addition to the illustrated device.

The pixel P is formed on the substrate 10. The substrate 10 may be formed of a glass material, a plastic material, or a metal material. In order to implement a flexible display device that can be folded or bent freely, the substrate 10 may be formed of a flexible material, for example, a polyimide film.

On the substrate 10, a buffer layer 101 containing an insulating material is formed to provide a flat surface on the upper portion of the substrate 10 and prevent moisture and foreign matter from penetrating in the direction of the substrate 10.

On the buffer layer 101, a pixel circuit including a thin film transistor (Ta, Tb (TFT: thin film transistor)) and a capacitor (not shown) (not shown) and an organic light emitting device (OLED) connected to the pixel circuit are disposed on the buffer layer 101. Is formed. The thin film transistors Ta and Tb largely include active layers 102a and b, gate electrodes 104a and b, and source/drain electrodes 106sa, da, sb, and db. The two thin film transistors Ta and Tb are characterized in that the gate electrodes 104a and b are formed on different layers.

Specifically, in the case of the first thin film transistor Ta, an active layer 102a formed in a predetermined pattern is disposed on the upper surface of the buffer layer 101. The active layer 102a is formed of an inorganic semiconductor material such as silicon, an organic semiconductor material, or an oxide semiconductor material including oxides such as indium (In), gallium (Ga), tin (Sn), hafnium (Hf), and zinc (Zn). It may contain. In addition, a p-type or n-type dopant may be injected as needed. A first gate insulating layer 113 is formed on the active layer 102a. A first gate electrode 104a is formed on the first gate insulating layer 113 to correspond to the active layer 102a. The second gate insulating layer 123 and the interlayer insulating layer 105 are formed to cover the first gate electrode 104a, and the source/drain electrodes 106sa and da are formed on the interlayer insulating layer 105. The active layer ( It is formed so as to contact a predetermined area of 102a).

Next, in the case of the second thin film transistor Tb, the active layer 102b formed in a predetermined pattern is disposed on the upper surface of the buffer layer 101, and the first gate insulating film 113 and the second gate insulating film are disposed on the active layer 102b. 123 is formed. A second gate electrode 104b is formed on the second gate insulating layer 123 to correspond to the active layer 102b. An interlayer insulating film 105 is formed to cover the second gate electrode 104b, and source/drain electrodes 106sb and db are formed on the interlayer insulating film 105 to contact the active layer 102b.

Here, the first gate insulating layer 113 and the second gate insulating layer 123 may be formed of a single layer or multiple layers of an inorganic material such as silicon oxide or silicon nitride. In addition, the interlayer insulating layer 105 may be formed of a single layer or multiple layers of an inorganic material such as silicon oxide or silicon nitride. The thickness d3 of the interlayer insulating layer 105 is formed to be thicker than the thickness d1 of the first gate insulating layer 113 or the thickness d2 of the second gate insulating layer 123 to planarize the surface, and source/drain electrodes It prevents the generation of parasitic capacitance between (106sa,sb,da,db) and the lower conductive layer.

Meanwhile, as described above, by varying the thickness (d1, d1 + d2) of the gate insulating film between the gate electrode 104a, b and the active layer 102a, b for each thin film transistor (Ta, Tb), the following effects can be obtained. I can. First, when the thin film transistor used as the driving thin film transistor is formed to have a thick gate insulating film, the driving range of the gate voltage (Vgs) is widened and the size of the gate voltage (Vgs) applied to the gate electrode of the driving thin film transistor By differently, it is possible to control the light emitted from the organic light emitting device to have a richer gradation. On the other hand, the thin film transistor used as the switching thin film transistor can be formed to have a thin gate insulating layer, so it has a feature that can perform turn-on and turn-off at a high speed, and can reduce parasitic capacitance generated between the gate electrode and the active layer. . Accordingly, there is a feature of implementing a pixel circuit structure that is optimal for an organic light emitting display device.

The passivation layer 107 is formed to cover the source/drain electrodes 106sa, sb, da, db of the thin film transistors Ta and Tb. A separate insulating layer may be further formed on the passivation layer 107 for planarization.

An organic light emitting diode (OLED) is formed on the passivation layer 107. The organic light emitting diode OLED includes a first electrode 111, a second electrode 112, and an intermediate layer 114.

A first electrode 111 is formed on the passivation layer 107. The first electrode 111 is formed to be electrically connected to any one of the source/drain electrodes 106sa, sb, da, and db. In addition, the pixel defining layer 109 is formed to cover the first electrode 111. After forming a predetermined opening in the pixel defining film 109, an intermediate layer 114 including an organic light emitting layer is formed in a region defined by the opening. A second electrode 112 is formed on the intermediate layer 114.

Meanwhile, when the organic light-emitting device (OLED) is a full-color organic light-emitting device (OLED), the organic light-emitting layer may be patterned into a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, respectively, according to a red sub-pixel, a green sub-pixel, and a blue sub-pixel. have.

Meanwhile, the organic emission layer may have a multilayer structure in which a red emission layer, a green emission layer, and a blue emission layer are stacked to emit white light, or may have a single-layer structure including a red emission material, a green emission material, and a blue emission material. The organic light-emitting device (OLED) having such an organic light-emitting layer may emit full color by additionally including a red color filter, a green color filter, and a blue color filter. The organic light-emitting display device is in the direction of the substrate 10. In the case of a bottom emission type that emits light, the first electrode 111 becomes a transparent electrode, and the second electrode 112 becomes a reflective electrode. On the other hand, in the case of a top emission type emitting light in a direction opposite to the substrate 10, the first electrode 111 becomes a reflective electrode and the second electrode 112 becomes a transflective electrode. In the case of a dual emission type, the first electrode 111 becomes a transparent electrode and the second electrode 112 becomes a transflective electrode.

Meanwhile, although not shown, each pixel may have a transparent window structure capable of transmitting external light, thereby implementing a transparent display device.

Next, a non-display area NDA of the display substrate 100 will be described in detail with reference to FIGS. 1 and 4 to 7.

1 and 4 to 7, the non-display area NDA is an area in which an image is not displayed and various members for driving the display area DA and other modules are mounted. In the non-display area NDA, a driver IC (not shown), pads 300 connecting the driver IC (not shown) and the display area DA, and a fan-out part 200 are formed.

The driver IC (not shown) may include a data driver for supplying a data signal, and may include various functional units required for driving the display area DA. A driver IC (not shown) is mounted on the display substrate 100 in a COG (chip on glass) type. One side of the driver IC (not shown) includes a connection terminal (not shown) electrically connected to the pads 300 formed on the display substrate 100. The pads 300 and the connection terminal (not shown) may be bonded between the pads 300 and the connection terminal (not shown) by interposing an adhesive material capable of conducting electricity including a conductive ball. As such an adhesive material, for example, an anisotropic conductive film, a self-organizing conductive film, or the like may be used.

The pads 300 are formed on the display substrate 100 and are electrically connected to a connection terminal of a driver IC (not shown). The pads 200 extend from the fan-out wirings 210 and 220, respectively.

The pads 300 include first pads 311 and second pads 312. The first pad 311 and the second pad 312 are classified according to a layer of the connected fan-out wires 210 and 220. That is, the first pad 311 is a pad extended from the first fan-out wiring 210 to be described later, and the second pad 312 is a pad extended from the second fan-out wiring 220 to be described later. The first pads 311 and the second pads 312 are alternately disposed.

The first pad 311 is formed at a first position in the non-display area NDA. The second pad 312 is formed at a second position in the non-display area NDA, and the second position is not on the same line as the first position in the X direction. Accordingly, the first pads 311 and the second pads 312 are not arranged in a line, but are arranged alternately. In this way, when the first pads 311 and the second pads 312 are alternately disposed, the two pads overlap by regions V1, V2, and V3 shown in FIG. 4. Accordingly, according to an embodiment of the present invention, many pads 300 can be arranged even in a space having a narrow width in the X direction, and as a result, a dead space of the non-display area NDA can be reduced. .

Fan-out wirings 210 and 220 connecting them are disposed between the pads 300 and the display area DA. The fan-out wires 210 and 220 include first fan-out wires 210 and second fan-out wires 220 according to a formed layer. The plurality of first fan-out wires 210 and the plurality of second fan-out wires 220 are disposed alternately with each other.

The first fan-out wiring 210 is formed on the first gate insulating layer 113 and is formed of the same material on the same layer as the first gate wiring GL1. One side of the first fan-out line 210 is connected to the first pad 311 and the other side is connected to the display area DA, for example, the data line DL of the display area. The first fan-out wiring 210 may transmit a data signal from a driver IC (not shown) to the data line DL.

The second fan-out wiring 220 is formed on the second gate insulating layer 123 and is formed of the same material on the same layer as the second gate wiring GL2. One side of the second fan-out line 220 is connected to the second pad 312 and the other side is connected to the display area DA, for example, the data line DL of the display area. The second fan-out wiring 220 may transmit a data signal from a driver IC (not shown) to the data line DL.

The first fan-out wiring 210 and the second fan-out wiring 220 are insulated with the second gate insulating layer 123 therebetween, and are formed in different layers. The first fan-out wiring 210 and the second fan-out wiring 220 are non-overlapping with each other. Because, the thickness d2 of the second gate insulating layer 123 formed between the first fan-out wiring 210 and the second fan-out wiring 220 is a relatively thin layer, the first fan-out wiring 210 This is because the parasitic capacitance of the wiring region increases when the and the second fan-out wiring 220 overlap.

6 is a cross-sectional view illustrating a first fan-out wire 210 and a first pad 311 electrically connected to the first fan-out wire 210.

The first pad 311 is formed on the first gate insulating layer 113. Since the first fan-out wiring 210 is also formed on the first gate insulating layer 113, the first pad 311 and the first fan-out wiring 210 may be integrally formed. A second gate insulating layer 123 and an interlayer insulating layer 105 are formed on the first pad 311 and the first fan-out wiring 201. Since the first pad 311 must be in contact with the driver IC (not shown), a first opening 321 is formed in the second gate insulating layer 123 and the interlayer insulating layer 105 formed on the first pad 311. The first pad 311 is exposed. Accordingly, the second gate insulating layer 123 and the interlayer insulating layer 105 may cover an edge of the first pad 311, and the first opening 321 may expose the center of the first pad 311. However, since the first fan-out wiring 210 must be insulated from the outside, an opening is not formed in the insulating layers formed on the first fan-out wiring 210.

The first fan-out wiring 210 and the first pad 311 may be formed of the same material. For example, the first fan-out wiring 210 and the first pad 311 include at least one selected from molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti). It may be formed as a single layer or multiple layers of a low resistance metal material. However, a portion exposed to the outside, such as the first pad 311, is formed of a metallic material and is easily corroded or damaged. Accordingly, the first protective layer 331 is formed on the first pad 311 exposed by the first opening 321.

The first protective layer 331 is formed to cover a portion of the first pad 311, the second gate insulating layer 123, and the interlayer insulating layer 105 exposed through the first opening 321. The first protective layer 331 serves to prevent corrosion of the first pad 311 and prevent lift between the first pad 311 and the insulating layers, thereby improving pad reliability. The first protective layer 331 is at least one material selected from a low-resistance metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti), and a transparent conductive oxide (TCO). It may be made of a single layer and multiple layers including. Here, the transparent conductive oxide is indium tin oxide (ITO), indium zink oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (indium). It may include at least one or more selected from the group including galium oxide: IGO), and aluminum zink oxide (AZO).

Next, FIG. 7 is a cross-sectional view illustrating a second fan-out wire 220 and a second pad 312 electrically connected to the second fan-out wire 220.

The second pad 312 is formed on the first gate insulating layer 113 in the same manner as the first pad 311. However, since the second fan-out wiring 220 is formed on the second gate insulating layer 123, a structure for connecting to the second pads 312 formed on different layers is required. Accordingly, in the present invention, a connection part 333 is provided to connect the second pad 312 and the second fan-out wiring 220.

A second gate insulating layer 123 and an interlayer insulating layer 105 are formed on the second pad 312 in the same manner as the first pad 311. Since the second pad 312 must be in contact with the driver IC (not shown), a second opening 322 is formed in the second gate insulating layer 123 and the interlayer insulating layer 105 formed on the second pad 312. The second pad 312 is exposed. Accordingly, the second gate insulating layer 123 and the interlayer insulating layer 105 may cover the edge of the second pad 312, and the second opening 322 may expose the center of the second pad 312. Meanwhile, an interlayer insulating layer 105 is formed on the second fan-out wiring 220. Since the second fan-out wiring 220 must be protected from the outside, the second fan-out wiring 220 is covered with the interlayer insulating layer 105. However, since the second fan-out wiring 220 must be electrically connected to the second pad 312, a contact hole for connecting the second fan-out wiring 220 and the connection part 333 to the interlayer insulating layer 105 323) can be formed. Here, the number, arrangement, shape, etc. of the contact holes 323 are not limited to the illustrated bars and may be variously implemented.

The second fan-out wiring 220 and the second pad 312 may be formed of different materials. For example, the second fan-out wiring 220 and the second pad 312 include at least one selected from molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti). It may be formed as a single layer or multiple layers of a low resistance metal material. However, the present invention is not limited thereto, and the second fan-out wiring 220 and the second pad 312 may be formed of the same material. However, a portion exposed to the outside, such as the second pad 312, is formed of a metallic material and is easily corroded or damaged. Accordingly, a second protective layer 332 is formed on the second pad 312 exposed by the second opening 322.

The second protective layer 332 is formed to cover a portion of the second pad 312 exposed through the second opening 322, the second gate insulating layer 123, and the interlayer insulating layer 105. The second protective layer 332 serves to prevent corrosion of the second pad 312 and prevent lift between the second pad 312 and the insulating layers, thereby improving pad reliability. The second protective layer 332 is at least one material selected from a low-resistance metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti), and a transparent conductive oxide (TCO). It may be made of a single layer and multiple layers including. Here, the transparent conductive oxide is indium tin oxide (ITO), indium zink oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), as the transparent conductive material. It may include at least one or more selected from the group including indium galium oxide (IGO), and aluminum zink oxide (AZO).

Meanwhile, the above-described connection part 333 may be integrally formed with the second protective layer 332. Accordingly, the connection part 333 is the second fan-out wire 220 and the second protective layer 332 through the contact hole 323 formed in the interlayer insulating film 105 disposed on the second fan-out wire 220. Connect. The second protective layer 332 directly contacts the second pad 312. Since the second protective layer 332 is made of the above-described conductive material, as a result, the second pad 312 may be electrically connected to the second fan-out wiring 220.

According to an embodiment of the present invention, by forming all the pads 300 on the same layer, bonding failure between the driver IC (not shown) and the pads 300 due to the difference in height of the pads 300 The problem that occurred was solved. In detail, the buffer layer 101 and the first gate insulating layer 113 are present under the first pads 311, and the buffer layer 101 and the first gate insulating layer 113 are also present under the second pads 312. . Accordingly, the first pads 311 and the second pads 312 are all positioned at a height equal to the thickness of the buffer layer 101 and the first gate insulating layer 113 from the substrate 10. That is, the pads 300 are all disposed at a constant height from the substrate 10. In this case, when bonding the driver IC (not shown) and the pads 300 with an adhesive material, bonding failure does not occur.

However, as a comparative example, when the second pad is formed on the same layer as the second fan-out wiring, a buffer layer, a first gate insulating layer, and a second gate insulating layer are present under the second pad. Accordingly, a height difference equal to the thickness of the second gate insulating layer is generated compared to the first pad. In this case, a floating part occurs between the driver IC terminal and the pad surface, and there is a problem in that close bonding is difficult because there is a space for air, moisture, and futon to penetrate during bonding, and it is difficult to maintain reliability even after bonding. However, as in the exemplary embodiment of the present invention, the difference in height of the pads is eliminated through the connection part, thereby solving the problem and improving reliability.

Meanwhile, according to an embodiment of the present invention, the connection part 333 is formed together when the first and second protective layers 331 and 332 are formed, thereby simplifying a process and improving contact reliability.

In addition, according to an embodiment of the present invention, fan-out wirings, which have been conventionally formed on the same layer, are formed by distributing them to different layers, thereby reducing the size of the fan-out portion. This reduces dead space and allows a larger number of wires to be placed in the fan-out part. Accordingly, more wirings can be formed in the same area, and a high-resolution display device can be formed. In addition, there is an advantage of realizing high resolution even in a small panel.

8 is a view showing A of FIG. 1 according to another embodiment of the present invention. FIG. 9 is a surface of FIG. 8 cut along the line IX-IX. 10 is a surface cut along line X-X in FIG. 8.

According to another exemplary embodiment of the present invention illustrated in FIGS. 8 to 10, the pads 300 are formed on the second gate insulating layer 123 compared to the previous exemplary embodiment. Among the reference numerals shown in FIGS. 8 to 10, the same reference numerals as those of FIGS. 1 to 7 have the same function and the same function, and thus redundant descriptions thereof will be omitted. Hereinafter, it will be described based on features peculiar to FIGS. 8 to 10.

8 and 9, the first pad 311a is formed on the second gate insulating layer 123. However, since the first fan-out wiring 210 is formed on the first gate insulating layer 113, a structure for connecting the first a pad 311a formed on different layers and the first fan-out wiring 210 is required. Accordingly, in the present invention, a connection part 333a is provided to connect the first a pad 311a and the first fan-out wiring 210.

An interlayer insulating film 105 is formed on the first a pad 311a. Since the 1a pad 311a needs to be in contact with the driver IC (not shown), a 1a opening 321a is formed in the interlayer insulating layer 105 formed on the 1a pad 311a to expose the 1a pad 311a. do. Meanwhile, since the first fan-out wiring 210 must be insulated from the outside, the first fan-out wiring 210 is covered with the second gate insulating layer 123 and the interlayer insulating layer 105. However, since the first fan-out wiring 210 must be electrically connected to the first a pad 311a, the second gate insulating layer 123 and the interlayer insulating layer 105 have the first fan-out wiring 210 and the connection part 333a. A contact hole 323a for connecting) may be formed.

The 1a pad 311a may be made of the above-described metal material, and since it is exposed to the outside, the 1a pad 311a is easily corroded or damaged. Accordingly, the 1a protective layer 331a is formed on the 1a pad 311a exposed by the 1a opening 321a.

The 1a protective layer 331a is formed to cover a portion of the 1a pad 311a and the interlayer insulating layer 105 exposed through the 1a opening 321a. The 1a protective layer 331a serves to prevent corrosion of the first a pad 311a and prevent lift between the first a pad 311a and the insulating layers, thereby improving pad reliability.

Meanwhile, the above-described connection part 333a may be integrally formed with the first protective layer 331a. Accordingly, the connection part 333a is the first fan-out wiring 210 through the second gate insulating layer 123 disposed on the first fan-out wiring 210 and the contact hole 323a formed in the interlayer insulating layer 105. And the 1a protective layer 331a are connected. The 1a protective layer 331a directly contacts the 1a pad 311a. Since the 1a protective layer 331a is made of the above-described conductive material, as a result, the 1a pad 311a may be electrically connected to the first fan-out wiring 210.

Next, referring to FIGS. 8 and 10, the second a pad 312a is formed on the second gate insulating layer 123 in the same manner as the first a pad 311a. Since the second fan-out wiring 220 is also formed on the second gate insulating layer 123, the second a pad 312a and the second fan-out wiring 220 may be integrally formed. An interlayer insulating layer 105 is formed on the 2a pad 312a and the second fan-out wiring 220. Since the 2a pad 312a must be in contact with the driver IC (not shown), a 2a opening 322a is formed in the interlayer insulating layer 105 formed on the 2a pad 312a to expose the 2a pad 312a. do.

Since the 2a pad 312a may be formed of a metallic material, it is easily corroded or damaged when exposed. Accordingly, the 2a protective layer 332a is formed on the 2a pad 312a exposed by the 2a opening 322a.

The 2a protective layer 332a is formed to cover a part of the 2a pad 312a and the interlayer insulating layer 105 exposed through the 2a opening 322a. The 2a protective layer 332a serves to prevent corrosion of the 2a pad 312a and prevent lifting between the 2a pad 312a and the insulating layers, thereby improving pad reliability.

In the case of the other embodiment of the present invention, as in the previous embodiment, the bonding reliability between the pad and the driver IC is improved.

Meanwhile, the first protective layer 331, the 1a protective layer 331a, the second protective layer 332, the second protective layer 332a, and the connection portions 333 and 333a are connected to the data line ( DL) may be formed at the same time, and thus may be formed of the same material on the same layer as the data line DL.

On the other hand, an additional protective layer may be further formed on the first and second protective layers 331, 332, 331a, 332a shown in FIGS. 6, 7, 9, and 10 of the present invention, and this additional protective layer is To prevent corrosion, indium tin oxide (ITO), indium zink oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium galium oxide oxide: IGO), and aluminum zink oxide (AZO) may be formed of a transparent conductive oxide selected from the group.

Meanwhile, although not shown in FIGS. 5 to 7, 9, and 10, a passivation layer (107 in FIG. 2) is further formed on the fan-out wirings 210 and 220 to planarize the surface and protect the lower wirings. . Here, the passivation layer (107 in FIG. 2) may include an inorganic material such as silicon oxide or silicon nitride, or may include at least one organic material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. .

Although the present invention has been described through preferred embodiments as described above, the present invention is not limited thereto, and various modifications and variations are possible without departing from the concept and scope of the following claims. Those in the field of technology to which it belongs will understand easily.

210,220: fan out wiring
310,320: pad

Claims (13)

A substrate including a display area in which an image is displayed and a non-display area around the display area;
A buffer layer disposed on the substrate;
An active layer disposed on the buffer layer;
A first insulating layer disposed on the active layer;
A first metal layer disposed on the first insulating layer;
A second insulating layer disposed on the first metal layer;
A second metal layer disposed on the second insulating layer;
A third insulating layer disposed on the second metal layer;
A third metal layer disposed on the third insulating layer;
A display device disposed on the third metal layer and including a first electrode, an intermediate layer, and a second electrode;
A first wiring disposed in the non-display area and formed of the same material as the first metal layer;
A second wiring disposed with the first wiring and the second insulating layer therebetween;
A first pad connected to the first wiring;
A second pad connected to the second wiring;
The first wiring and the second wiring extend in a first direction, and the first wiring is disposed adjacent to the second wiring in a second direction crossing the first direction,
The display device, wherein a center of the first pad and a center of the second pad are alternately disposed. The method of claim 1,
A first protective layer disposed on the first pad and electrically connected to the first pad; And
The display device further comprising a second protective layer disposed on the second pad and electrically connected to the second pad. The method of claim 2,
The second wiring is connected to the second protective layer through a first opening provided in the second insulating layer. The method of claim 2,
The first passivation layer and the second passivation layer are formed of the same material as the third metal layer. The method of claim 2,
The first protective layer and the second protective layer are formed of the same material as the first electrode. The method of claim 2,
A connection portion disposed on the second insulating layer and connecting the second wiring and the second pad;
The second insulating layer includes a contact hole for connecting the second wiring and the connection part, and the connection part is integrally provided with the second protective layer. The method of claim 1,
The first pad and the second pad are disposed to overlap in the second direction. The method of claim 1,
The first wiring and the first pad are integrally provided. The method of claim 1,
One end of the first wiring and the second wiring is connected to the display area. The method of claim 1,
The display device, wherein the second wiring does not overlap with the second pad in cross section. The method of claim 1,
The first wiring and the second wiring are provided in plurality,
The plurality of first wirings and the plurality of second wirings are alternately disposed along the second direction. The method of claim 1,
The first pad and the second pad are provided in plurality,
The plurality of first pads and the plurality of second pads are alternately disposed along the second direction. The method of claim 1,
A display device, wherein a center of the first pad and a center of the second pad are alternately disposed with respect to the first direction and the second direction.

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