KR20200108230A - Source driver and display device including the same - Google Patents

Abstract

The present invention relates to a source driver capable of reducing noise generated in data lines, and a display device including the same. The source driver comprises: a gamma voltage generation part that generates gamma voltages having different voltage levels from each other; a digital-analog conversion part that generates data voltage corresponding to a gray level value by using the gamma voltages; an output buffer part that outputs the data voltage to the outside; and a chopping control part that generates a chopping control signal and provides the same to the output buffer part. The output buffer part comprises: an amplifier connected between the digital-analog conversion part and a data line; and a chopping circuit that periodically changes the polarity of the offset of the amplifier in response to the chopping control signal, wherein the chopping control part varies the slew rate of the chopping control signal.

Description

Source driver and display device including the same {SOURCE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME}

An embodiment of the present invention relates to a source driver and a display device including the same.

The display device includes a display panel and a driver. The display panel includes scan lines, data lines, and pixels. The driver includes a scan driver that sequentially provides scan signals to the scan lines and a source driver that provides data signals to the data lines. Each of the pixels may emit light with a luminance corresponding to a data signal provided through a corresponding data line in response to a scanning signal provided through a corresponding scan line.

The source driver generates a data signal corresponding to a gray level value of the image data, and provides the data signal to the data lines through an output buffer. Since the amplifier constituting the output buffer has an offset, the quality of an image (ie, an image displayed in response to a data signal) may be degraded by the offset. Accordingly, the source driver may include a chopping function that periodically changes the polarity of the offset of the amplifier.

Noise is generated in the data lines due to the operation of the chopping circuit, and the noise may affect other components adjacent to the data lines.

An object of the present invention is to provide a source driver capable of reducing noise generated in data lines and a display device including the same.

In order to achieve an object of the present invention, a source driver according to embodiments of the present invention includes: a gamma voltage generator for generating gamma voltages having different voltage levels; A digital-analog converter that generates a data voltage corresponding to a gradation value by using the gamma voltages; An output buffer for outputting the data voltage to the outside; And a chopping control unit generating a chopping control signal and providing it to the output buffer unit. Here, the output buffer unit, an amplifier connected to the output terminal of the digital-analog conversion unit; And a chopping circuit for periodically changing a polarity of an offset of the amplifier in response to the chopping control signal, wherein the chopping control unit varies a slew of the chopping control signal.

According to an embodiment, the chopping circuit comprises: a first switch connected between an input node and a first input terminal of the amplifier, a second switch connected between the input node and a second input terminal of the amplifier, and the amplifier A third switch connected between the first input terminal of the amplifier and the output terminal of the amplifier, and a fourth switch connected between the second input terminal of the amplifier and the output terminal of the amplifier, and the first The fourth to fourth switches may operate in response to the chopping control signal.

According to an embodiment, a parasitic capacitor may be formed between an output node to which the output terminal of the amplifier is connected and a control line that transmits the chopping control signal to the third switch.

According to an embodiment, the chopping control unit includes: a logic control circuit for generating a first control signal including a pulse, a level shifter for generating a second control signal by shifting up a level of the first control signal, and 2 A control signal may be output as the chopping control signal, but may include a buffer circuit for varying a buffer size.

According to an embodiment, the slew rate may be a rate at which the chopping control signal follows the second control signal.

According to an embodiment, the buffer circuit may include sub buffers connected in parallel to the chopping circuit; And sub switches respectively connecting the sub buffers to an output terminal of the level shifter, and at least one of the sub switches may be turned on in response to a preset selection signal.

According to an embodiment, the sub-buffers may have the same buffer size.

According to an embodiment, the sub buffers may have different buffer sizes.

According to an embodiment, as the buffer size of the buffer circuit decreases, the slew rate of the chopping control signal may decrease.

According to an embodiment, the chopping control unit includes: a logic control circuit for generating a first control signal in the form of a square wave, a level shifter for generating a second control signal by shifting up the level of the first control signal, and the second control A buffer circuit for outputting a signal as the chopping control signal, and an analog filter connected between the output terminal of the buffer circuit and the chopping circuit to variably filter a high frequency component of the chopping control signal.

According to an embodiment, the analog filter may include a variable resistor connected between the buffer circuit and the chopping circuit, and a variable capacitor connected between the chopping circuit and a reference voltage line.

According to an embodiment, the chopping control unit includes: a logic control circuit for generating a first control signal in the form of a square wave, a level shifter for generating a second control signal by shifting up the level of the first control signal, and the second control A buffer circuit that outputs a signal as the chopping control signal, and a delay element connected between the output terminal of the buffer circuit and the chopping circuit.

According to an embodiment, the delay element may include a resistor connected between the buffer circuit and the chopping circuit, and a switch and a diode connected in parallel to the resistor but connected in series with each other.

In order to achieve an object of the present invention, a display device according to example embodiments includes: a display panel including a data line and a pixel connected to the data line; And a source driver providing a data voltage to the data line. Here, the source driver includes: a digital-analog converter generating the data voltage; An output buffer unit outputting the data voltage to the data line; And a chopping control unit generating a chopping control signal and providing it to the output buffer unit. The output buffer unit may include an amplifier connected between the digital-analog converter and the data line; And a chopping circuit for periodically changing the polarity of the offset of the amplifier in response to a chopping control signal. The chopping control unit varies a slew of the chopping control signal.

According to an embodiment, the chopping circuit comprises: a first switch connected between an input node and a first input terminal of the amplifier, a second switch connected between the input node and a second input terminal of the amplifier, and the amplifier A third switch connected between the first input terminal of the amplifier and the output terminal of the amplifier, and a fourth switch connected between the second input terminal of the amplifier and the output terminal of the amplifier, and the first The fourth to fourth switches may operate in response to the chopping control signal.

According to an embodiment, the chopping control unit includes: a logic control circuit for generating a first control signal including a pulse, a level shifter for generating a second control signal by shifting up a level of the first control signal, and 2 A control signal may be output as the chopping control signal, but may include a buffer circuit for varying a buffer size.

According to an embodiment, the display device further includes a touch sensing unit including touch electrodes, and the buffer size of the buffer circuit is adjusted based on noise of the touch electrodes caused by the chopping control signal. I can.

According to an embodiment, as the noise increases, the buffer size of the buffer circuit may decrease.

According to an embodiment, the buffer size of the buffer circuit may be set to be the largest within a range in which the noise does not occur.

According to an embodiment, the buffer circuit may include sub buffers connected in parallel to the chopping circuit; And sub switches respectively connecting the sub buffers to an output terminal of the level shifter, and at least one of the sub switches may be turned on in response to a preset selection signal.

A source driver and a display device according to embodiments of the present invention include a slew rate of a chopping control signal that controls a chopping circuit that periodically changes the polarity of an offset of a source amplifier (ie, a source amplifier that outputs a data signal). ), it is possible to reduce noise generated in the data lines and other components adjacent thereto.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1.
3 is a block diagram illustrating an example of a source driver included in the display device of FIG. 1.
4 is a circuit diagram illustrating an example of an output buffer included in the source driver of FIG. 3.
5 is a circuit diagram illustrating an example of the output buffer of FIG. 4.
6 is a waveform diagram illustrating an example of signals measured in the output buffer of FIG. 5.
7 is a block diagram illustrating an example of a chopping controller included in the source driver of FIG. 3.
8 is a circuit diagram illustrating an example of a buffer circuit included in the chopping controller of FIG. 7.
9 is a waveform diagram illustrating an example of a chopping control signal output from the buffer of FIG. 8.
10 is a block diagram illustrating another example of a chopping controller included in the source driver of FIG. 3.
11 is a block diagram illustrating another example of a chopping controller included in the source driver of FIG. 3.
12 is a diagram illustrating a display device according to another exemplary embodiment of the present invention.
13 is a cross-sectional view illustrating an example of the display device of FIG. 12.
14 is a plan view illustrating an example of a touch sensing layer included in the display device of FIG. 13.
15 is a cross-sectional view illustrating an example of the display device of FIG. 13.
16 is a diagram illustrating an example of a sensing signal measured by the touch sensing layer of FIG. 14.

In the present invention, various modifications can be made and various forms can be applied, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, the present invention is not limited to the embodiments disclosed below, and may be changed in various forms and implemented.

Meanwhile, in the drawings, some constituent elements not directly related to the features of the present invention may be omitted in order to clearly illustrate the present invention. In addition, some of the components in the drawings may have their size or ratio somewhat exaggerated. Throughout the drawings, the same or similar components are assigned the same reference numerals and reference numerals as much as possible even though they are displayed on different drawings, and redundant descriptions will be omitted.

1 is a block diagram illustrating a display device according to example embodiments.

Referring to FIG. 1, the display device 100 includes a display unit 110 (or a display panel), a scan driver 120 (or a scan driver, a gate driver), and a source driver 130 (or a source driver, data driver), and a timing controller 140 (or, a timing controller). Also, the display device 100 may further include a light emission driver 150 (or an emission driver).

The display unit 110 includes scan lines SL1 to SLn, where n is a positive integer (or gate lines), data lines DL1 to DLm, where m is a positive integer, and emission control lines EL1 to ELn. ), and a pixel PXL. The pixel PXL may be disposed in a region (eg, a pixel region) partitioned by the scan lines SL1 to SLn, the data lines DL1 to DLm, and the emission control lines EL1 to ELn.

The pixel PXL may be connected to at least one of the scan lines SL1 to SLn, one of the data lines DL1 to DLm, and at least one of the emission control lines EL1 to ELn. For example, the pixel PXL may be connected to the scan line SLi, the previous scan line SLi-1 adjacent to the scan line SLi, the data line DLj, and the emission control line ELi (however, i and j each is a positive integer).

The pixel PXL is initialized in response to a scan signal (or a scan signal provided at a previous time point, a previous gate signal) provided through the previous scan line SLi-1, and a scan signal provided through the scan line SLi (or , In response to a scanning signal and a gate signal provided at the present time), a data signal provided through the data line DLj is stored or recorded, and a data signal stored in response to a light emission control signal provided through the emission control line ELi It can emit light with a luminance corresponding to.

First and second power voltages VDD and VSS may be provided to the display unit 110. The first and second power voltages VDD and VSS are voltages required for the operation of the pixel PXL, and the first power voltage VDD may have a voltage level higher than the voltage level of the second power voltage VSS. have. Also, an initialization power voltage Vint may be provided to the display unit 110. The first and second power voltages VDD and VSS, and the initialization power voltage Vint may be provided to the display unit 110 from a separate power supply.

The scan driver 120 may generate a scan signal based on the scan control signal SCS and sequentially provide the scan signal to the scan lines SL1 to SLn. Here, the scan control signal SCS includes a start signal, clock signals, and the like, and may be provided from the timing controller 140. For example, the scan driver 120 may include a shift register (or stage) that sequentially generates and outputs a pulse type scan signal corresponding to a pulse type start signal using clock signals. have.

The light emission driver 150 may generate a light emission control signal based on the light emission drive control signal ECS, and may sequentially or simultaneously provide the light emission control signal to the light emission control lines EL1 to ELn. Here, the emission driving control signal ECS includes an emission start signal, emission clock signals, and the like, and may be provided from the timing controller 140. For example, the light emission driver 150 may include a shift register that sequentially generates and outputs a pulse type light emission control signal corresponding to a pulse type light emission start signal using light emission clock signals.

The source driver 130 generates data signals based on the image data DATA2 and the data control signal DCS provided from the timing controller 140, and converts the data signals to the display unit 110 (or the pixel PXL). Can be provided. Here, the data control signal DCS is a signal that controls the operation of the source driver 130 and may include a load signal (or a data enable signal) instructing the output of a valid data signal.

In embodiments, the source driver 130 outputs a data signal (or data voltage) to the data lines DL1 to DLm through source amplifiers (or source amplifiers), respectively, in response to a chopping control signal. A chopping circuit for periodically changing the polarities of the source amplifiers, and a chopping controller for generating a square wave chopping control signal but varying a slew rate or a transition speed of the chopping control signal may be included. Here, the slew rate may represent a rate at which an output signal (ie, a chopping control signal) follows an input signal or a rate of change of the chopping control signal over time. In consideration of noise generated by the data lines DL1 to DLm by the chopping control signal, the slew rate of the chopping control signal may be set or adjusted during the manufacturing process of the display device 100.

A specific configuration of the source driver 130 (and a specific configuration of a chopping circuit and a chopping controller) will be described later with reference to FIGS. 3 to 11.

The timing controller 140 receives input image data DATA1 and a control signal CS from an external (for example, a graphic processor), and based on the control signal CS, a scan control signal SCS and a data control signal (DCS) is generated, and the image data DATA2 may be generated by converting the input image data DATA1. Here, the control signal CS may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock CLK. For example, the timing controller 140 may convert the input image data DATA1 in the RGB format into the image data DATA2 in the RGBG format corresponding to the pixel arrangement in the display unit 110.

Meanwhile, at least one of the scan driver 120, the source driver 130, the timing controller 140, and the light emitting driver 150 is formed on the display unit 110 or implemented as an IC to form a tape carrier package. ) Can be connected. In addition, at least two of the scan driver 120, the source driver 130, the timing controller 140, and the light emission driver 150 may be implemented with one IC.

2 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1.

Referring to FIG. 2, the pixel PXL may include first to seventh transistors T1 to T7, a storage capacitor Cst, and a light emitting device LD.

Each of the first to seventh transistors T1 to T7 may be implemented as a P-type transistor, but is not limited thereto. For example, at least some of the first to seventh transistors T1 to T7 may be implemented as an N-type transistor.

The first electrode of the first transistor T1 (driving transistor) is connected to the second node N2, or via the fifth transistor T5, to which the first power line (ie, the first power voltage VDD) is applied. Power line). The second electrode of the first transistor T1 may be connected to the first node N1 or may be connected to the anode of the light emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 is a power line that transmits a second power line (that is, a second power voltage VSS) from the first power line through the light emitting element LD in response to the voltage of the third node N3. The amount of current flowing through) can be controlled.

The second transistor T2 (switching transistor) may be connected between the data line DLj and the second node N2. The gate electrode of the second transistor T2 may be connected to the scan line SLi. The second transistor T2 is turned on when a scan signal is supplied to the scan line SLi to electrically connect the data line DLj to the first electrode of the first transistor T1.

The third transistor T3 may be connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be connected to the scan line SLi. The third transistor T3 is turned on when a scan signal is supplied to the scan line SLi to electrically connect the first node N1 and the third node N3. Accordingly, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

The storage capacitor Cst may be connected between the first power line and the third node N3. The storage capacitor Cst may store a data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

The fourth transistor T4 may be connected between the third node N3 and an initialization power line (ie, a power line that transfers the initialization power voltage Vint). The gate electrode of the fourth transistor T4 may be connected to the previous scan line SLi-1. The fourth transistor T4 is turned on when a scan signal is supplied to the previous scan line SLi-1 to supply the initialization power voltage Vint to the first node N1. Here, the initialization power voltage Vint may be set to have a voltage level lower than that of the data signal.

The fifth transistor T5 may be connected between the first power line and the second node N2. The gate electrode of the fifth transistor T5 may be connected to the emission control line ELi. The fifth transistor T5 may be turned off when a light emission control signal is supplied to the light emission control line ELi, and may be turned on in other cases.

The sixth transistor T6 may be connected between the first node N1 and the light emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the emission control line ELi. The sixth transistor T6 may be turned off when the emission control signal is supplied to the emission control line ELi, and may be turned on in other cases.

The seventh transistor T7 may be connected between the initialization power line and the anode of the light emitting device LD. The gate electrode of the seventh transistor T7 may be connected to the scan line SLi. The seventh transistor T7 is turned on when a scan signal is supplied to the scan line SLi to supply the initialization power voltage Vint to the anode of the light emitting element LD.

The anode of the light emitting element LD may be connected to the first transistor T1 via the sixth transistor T6, and the cathode may be connected to the second power line. The light-emitting device LD may generate light of a predetermined luminance in response to the current supplied from the first transistor T1. The first power voltage VDD may be set to have a higher voltage level than the second power voltage VSS so that current flows through the light emitting device LD.

3 is a block diagram illustrating an example of a source driver included in the display device of FIG. 1.

1 and 3, the source driver 130 (or source driver) includes a controller 310 (or a controller), a chopping controller 320 (or a chopping controller), and a gamma voltage generator 330 ( Alternatively, a gamma voltage generator), a shift register 340, a latch 350, a decoder 360 (or a digital-analog converter, a digital-analog converter), and an output buffer 370 (or an output buffer unit) ) Can be included.

The controller 310 may receive a data control signal DCS from the timing controller 140.

The controller 310 may generate the first control signal CCCS based on the data control signal DCS. The first control signal CCCS includes a pulse and may be used to periodically change the polarity of an offset of source amplifiers (or source amplifiers) constituting the output buffer 370. have.

Also, the controller 310 may generate a bias control signal based on the data control signal DCS. The bias control signal may be used to adjust the bias voltage Vbias applied to the output buffer 370 (or source amplifiers).

The controller 310 may generate a gamma enable signal G_EN. The gamma enable signal G_EN may control the gamma voltage generator 330 so that the gamma voltage generator 330 generates the gamma voltages VG0 to VG2047. Here, the gamma voltages VG0 to VG2047 may be used to convert the data DATA (ie, the image data DATA2 described with reference to FIG. 1) into a data voltage (ie, a gray scale voltage). . Meanwhile, the gamma voltages VG0 to V2047 may include 2048 gamma voltages corresponding to 11-bit data, but this is exemplary and is not limited thereto.

The controller 310 may change the serialized data received from the timing controller 140 into parallelized data DATA. The controller 310 may provide parallelized data DATA to the shift register 340 (or the latch 350).

The chopping controller 320 may generate a chopping control signal CCS based on the first control signal CCCS and provide the chopping control signal CCS to the output buffer 370.

Further, the chopping controller 320 may generate bias voltages having various voltage levels in response to the bias control signal. The configuration for generating the bias voltage may be implemented as a separate bias voltage generator independently of the chopping controller 320.

In embodiments, the chopping controller 320 may adjust the slew rate of the chopping control signal CCS or change the transition speed. For example, when the chopping control signal CCS is a square wave or includes pulses, the chopping controller 320 may vary the speed at which the voltage level of the chopping control signal CCS changes.

As will be described later, components (eg, a touch panel) provided in the display device 100 or included in a product together with the display device 100 and their arrangement may be variously changed, and accordingly, Components affected by the display device 100 (or the data lines DL1 to DLm, see FIG. 1) may also be various. Therefore, the slew rate or transition speed of the chopping control signal CCS is determined by the arrangement (for example, data) of the components in the manufacturing process of the display device 100 (or a product including the display device 100). It is set in consideration of the lines (DL1 to DLm) and the arrangement and distance between electrodes in the touch panel, etc. ) Can be set in consideration of the measurement result.

The gamma voltage generator 330 may receive the gamma enable signal G_EN and generate gamma voltages VG0 to VG2047 having various voltage levels.

The shift register 340 may provide parallelized data DATA to the latch 350. The shift register 340 may generate a latch clock signal and provide it to the latch 350, and the latch clock signal may be used to control timing at which parallelized data DATA is output.

The latch 350 may latch or temporarily store data sequentially received from the shift register 340 and transmit it to the decoder 360.

The decoder 360 may convert digital data (ie, a gray scale value of parallelized data DATA) into an analog data signal (or data voltage) using gamma voltages VG0 to VG2047. .

The output buffer 370 may receive the data signal and output it to the data lines DLs (that is, the data lines DL1 to DLm of the display unit 110 described with reference to FIG. 1 ). The output buffer 370 may include source amplifiers connected to the data lines DLs.

Meanwhile, in FIG. 3, the chopping controller 320 is illustrated as being independent of the controller 310 and the output buffer 370, but is not limited thereto. For example, the chopping controller 320 may be included in the controller 310 or the output buffer 370 (or the output buffer unit).

4 is a circuit diagram illustrating an example of an output buffer included in the source driver of FIG. 3. In FIG. 4, the output buffer 370 is schematically illustrated with the center of the circuit (or source amplifier) corresponding to the data line DLj shown in FIG. 1.

3 and 4, the output buffer 370 may include an amplifier (AMP) (or a source amplifier) and a chopping circuit (SW).

The amplifier AMP may be connected to an output terminal of the decoder 360 or between the decoder 360 and the data line DLj.

The chopping circuit SW may periodically change the polarity of the offset of the amplifier AMP in response to the chopping control signal CCS. Here, the chopping control signal CCS is provided from the chopping controller 320 (or the chopping controller), and may include a pulse having a turn-on voltage level.

The chopping circuit SW may include first to fourth switches SW1 to SW4.

The first switch SW1 may be connected between the input node N_IN and the first input terminal (or the first input node N_P) of the amplifier AMP. The second switch SW2 may be connected between the input node N_IN and the second input terminal (or the second input node N_N) of the amplifier AMP. The third switch SW3 may be connected between the first input terminal (or the first input node N_P) of the amplifier AMP and the output terminal (or the output node N_OUT) of the amplifier AMP. The fourth switch SW4 may be connected between the second input terminal (or the second input node N_N) of the amplifier AMP and the output terminal of the amplifier AMP.

The first to fourth switches SW1 to SW4 may operate in response to the chopping control signal CCS or may be turned on. For example, the first switch SW1 is turned on in response to the first chopping control signal CCS1 having a turn-on voltage level, and the second switch SW2 is a second switch SW2 having a turn-on voltage level. The third switch SW3 is turned on in response to the chopping control signal CCS2, and the third switch SW3 is turned on in response to the third chopping control signal CCS3 having a turn-on voltage level, and the fourth switch SW4 May be turned on in response to the fourth chopping control signal CCS4 having a turn-on voltage level.

In response to the first and fourth chopping control signals CCS1 and CCS4 of the turn-on voltage level in the first time (or the first period), the first switch SW1 and the fourth switch SW4 are turned- Can be turned on. In response to the second and third chopping control signals CCS2 and CCS3 of the turn-on voltage level at a second time (or a second period) different from the first time, the second switch SW2 and the third switch ( SW3) can be turned on. Here, the first time and the second time may be alternated for each frame period (ie, for each frame period in which the display device 100 (see FIG. 1) displays one frame image), but is limited thereto. It is not.

For example, at a first time, a data signal is output with an offset of a first polarity through a first input terminal of the amplifier AMP, and at a second time, the data signal is output through a second input terminal of the amplifier It may be output with an offset of the second polarity (ie, an offset having the same size as the offset of the first polarity, but having a different polarity).

5 is a circuit diagram illustrating an example of the output buffer of FIG. 4. In FIG. 5, the output buffer 370 is schematically illustrated with the center of the third switch SW3 shown in FIG. 4.

4 and 5, the third switch SW3 may be an N-type transistor (or, an NMOS transistor or an oxide semiconductor transistor), but this is exemplary and is not limited thereto. For example, the third switch SW3 may be a P-type transistor.

A first parasitic capacitor Cpar1 is formed between the output node N_OUT to which the output terminal of the amplifier AMP is connected and the control line CL that transmits the third chopping control signal CCS3 to the third switch SW3. Can be. For example, while the wiring connected to the output node N_OUT and the control line CL overlap or are adjacent, a first parasitic capacitor Cpar1 may be formed therebetween.

The high frequency component of the third chopping control signal CCS3 is transmitted to the output node N_OUT through the first parasitic capacitor Cpar1 and may appear as noise for the data signal transmitted through the data line DLj.

Meanwhile, in FIG. 5, it has been described that the first parasitic capacitor Cpar1 is formed in the third switch SW3, but the present invention is not limited thereto. For example, parasitic capacitors may be formed in the fourth switch SW4 shown in FIG. 4, and parasitic capacitors may be formed in the first switch SW1 and the second switch SW2, respectively, and accordingly, A high frequency component of each of the first, second, and fourth chopping control signals (CCS1, CCS2, CCS4, see FIG. 4) may appear as noise for the data signal.

6 is a waveform diagram illustrating an example of signals measured in the output buffer of FIG. 5.

5 and 6, the third chopping control signal CCS3 is a turn-on voltage level (or a logic low level, a gate-off voltage level) at a turn-off voltage level at a first time point t1. , A logic high level, a gate-on voltage level), and a turn-off voltage level at a second time point t2. Here, the turn-off voltage level may be a voltage level for turning off the transistor shown in FIG. 5, and the turn-on voltage level may be a voltage level for turning on the transistor.

A data signal transmitted through the data line DLj in response to a change in the third chopping control signal CCS3 (ie, a transition from the turn-off voltage level to the turn-on voltage level) at the first time point t1 Impulse-type noise may occur in (DATAj).

Similarly, in response to a change in the third chopping control signal CCS3 (i.e., transition from the turn-on voltage level to the turn-off voltage level) at the second time point t2, transmission through the data line DLj Noise in the form of an impulse may be generated in the data signal DATAj.

The effect of such noise on the data signal stored in the pixel may be insignificant. As described with reference to FIG. 2, the data signal DATAj is stored in the storage capacitor Cst of the pixel PXL for a specific time in response to the scan signal transmitted through the scan line SLi, or the storage capacitor Cst is Since it is charged, the transition point of the data signal DATAj (that is, the first point of time t1 and the second point of time t2) is non-overlapping with the scan signal of the turn-on voltage level, thereby Effects may be ruled out.

However, other components (for example, a touch panel that is not synchronized with the source driver 130) provided in the display device 100 or provided in a product together with the display device 100 are generated in the data line DLj. It is affected by noise and may malfunction. This will be described later with reference to FIGS. 12 to 15.

Accordingly, the chopping controller 320 (refer to FIG. 4) according to embodiments of the present invention may vary the slew rate or transition speed of the chopping control signal CCS (or the third chopping control signal CCS3). For example, when the slew rate or transition speed of the chopping control signal CCS is lowered, a high frequency component of the chopping control signal CCS may be reduced, and noise of the data signal DATAj may be reduced. However, as the slew rate or transition speed of the chopping control signal CCS decreases, time for stabilization of the output buffer 370 may be additionally required or increased. Accordingly, the slew rate or transition speed of the chopping control signal CCS may be set to the highest or the fastest within a range in which noise is not generated by other components (eg, a touch panel).

7 is a block diagram illustrating an example of a chopping controller included in the source driver of FIG. 3.

3, 4 and 7, the chopping controller 320 includes a logic control circuit 710 (or a logic control block), a level shifter 720, and a buffer circuit 730 (or a buffer block). It may include.

The logic control circuit 710 may generate a first control signal including a pulse. Here, the first control signal may be substantially the same as the first control signal CCCS described with reference to FIG. 3, and the logic control circuit 710 may be included in the controller 310.

The level shifter 720 may generate a second control signal by shifting up the level of the first control signal.

The buffer circuit 730 outputs the second control signal as a chopping control signal CCS, but may change the slew rate of the chopping control signal. Here, the slew rate may represent a rate at which the chopping control signal CCS follows the second control signal, or a change rate of the chopping control signal CCS over time. The chopping control signal CCS output from the buffer circuit 730 may be provided to the chopping circuit SW.

In embodiments, the buffer circuit 730 may include sub-buffers connected in parallel to the chopping circuit SW and sub-switches for serially connecting the sub-buffers to the level shifter 720, respectively.

8 is a circuit diagram illustrating an example of a buffer circuit included in the chopping controller of FIG. 7.

Referring to FIG. 8, the buffer circuit 730 may include first to fourth sub buffers BUF_S1 to BUF_S4 and first to fourth sub switches SW_S1 to SW_S4.

The first sub buffer BUF_S1 and the first sub switch SW_S1 may be connected in series between the level shifter 720 and the chopping circuit SW. Similarly, the second sub buffer BUF_S2 and the second sub switch SW_S2 are connected in series between the level shifter 720 and the chopping circuit SW, and the third sub buffer BUF_S3 and the third sub switch SW_S3 ) Is connected in series between the level shifter 720 and the chopping circuit SW, and the fourth sub buffer BUF_S4 and the fourth sub switch SW_S4 are connected in series between the level shifter 720 and the chopping circuit SW. I can.

Each of the first to fourth sub-buffs BUF_S1 to BUF_S4 is connected in series between the first driving voltage V_TOP and the second driving voltage GND, and the gate electrode is connected to the input terminal IN. M1) and a P-type transistor M2, the input terminal IN may be connected to a corresponding sub-switch, and the output terminal OUT may be connected to the chopping circuit SW. The first to fourth sub-buffers BUF_S1 to BUF_S4 may have the same buffer size, but are not limited thereto. For example, the first to fourth sub-buffers BUF_S1 to BUF_S4 may have different buffer sizes.

Each of the first to fourth sub switches SW_S1 to SW_S4 may be implemented as an N-type transistor, but is not limited thereto. At least one of the first to fourth sub switches SW_S1 to SW_S4 may be turned on based on the selection signal CHOP_SLOPE_CON[1:0]. Here, the selection signal CHOP_SLOPE_CON[1:0] is preset and may be provided from the controller 310 or the like.

Meanwhile, in FIG. 8, the buffer circuit 730 is shown to include four pairs of sub buffers and sub switches, but this is exemplary and the buffer circuit 730 is not limited thereto. For example, the buffer circuit 730 may include 2 pairs, 3 pairs, or 5 or more pairs of sub buffers and sub switches.

9 is a waveform diagram illustrating an example of a chopping control signal output from the buffer of FIG. 8.

8 and 9, when the selection signal CHOP_SLOPE_CON[1:0] has a first value (for example, 00), all of the first to fourth sub switches SW_S1 to SW_S4 are turned. -Can be on.

In this case, the chopping control signal CCS rapidly transitions from the turn-off voltage level to the turn-on voltage level at the first time point t1, as described with reference to FIG. 6, and further, the second time point t2 ) Can quickly transition from the turn-on voltage level to the turn-off voltage level.

When the selection signal CHOP_SLOPE_CON[1:0] has a second value (for example, 01), three of the first to fourth sub-switches SW_S1 to SW_S4 (for example, the first to the first The three sub switches SW_S1 to SW_S3 may be turned on.

In this case, the chopping control signal CCS transitions from the turn-off voltage level to the turn-on voltage level in the section between the first time point t1 and the third time point t3, and further, the second time point t2 ) And the sixth time point t6 may transition from the turn-on voltage level to the turn-off voltage level.

When the selection signal (CHOP_SLOPE_CON[1:0]) has a second value, the slope of the chopping control signal CCS (or, the rising edge and/or the falling edge of the pulse). The slope) may be smoother than the slope of the chopping control signal CCS when the selection signal CHOP_SLOPE_CON[1:0] has a first value.

Similarly, when the selection signal CHOP_SLOPE_CON[1:0] has a third value (for example, 10), two of the first to fourth sub-switches SW_S1 to SW_S4 (for example, the first The first and second sub switches SW_S1 and SW_S2 may be turned on. In this case, the chopping control signal CCS transitions from the turn-off voltage level to the turn-on voltage level in the section between the first time point t1 and the fourth time point t4, and further, the second time point t2 ) And the seventh time point t7 may transition from the turn-on voltage level to the turn-off voltage level. The slope of the chopping control signal CCS when the selection signal CHOP_SLOPE_CON[1:0] has a third value is the chopping control signal CCS when the selection signal CHOP_SLOPE_CON[1:0] has a second value. It can be smoother than the slope of ).

When the selection signal CHOP_SLOPE_CON[1:0] has a fourth value (eg, 11), one of the first to fourth sub switches SW_S1 to SW_S4 (eg, the first sub switch ( SW_S1)) may be turned on. In this case, the chopping control signal CCS transitions from the turn-off voltage level to the turn-on voltage level in the period between the first time point t1 and the fifth time point t5, and further, the second time point t2 ) And the eighth time point t8 may transition from the turn-on voltage level to the turn-off voltage level. The slope of the chopping control signal CCS when the selection signal CHOP_SLOPE_CON[1:0] has a fourth value is the chopping control signal CCS when the selection signal CHOP_SLOPE_CON[1:0] has a third value. It can be smoother than the slope of ).

That is, the buffer size of the buffer circuit 730 is varied according to the selection signal CHOP_SLOPE_CON[1:0], and the slew rate (or transition speed, or the transition speed) of the chopping control signal CCS output through the buffer circuit 730 Tilt) can be adjusted. For example, as the buffer size of the buffer circuit 730 decreases, the slew rate of the chopping control signal CSS may decrease.

During the manufacturing process of the display device 100 (FIG. 1 ), noise generated from other components may be measured while changing a value of the selection signal CHOP_SLOPE_CON[1:0]. An optimum value (eg, a value that causes the chopping control signal CCS to have the largest slope without generating noise) may be selected or set according to the measurement result of noise. That is, within a range in which noise is not generated, the buffer size of the buffer circuit 730 may be set to be the largest.

Meanwhile, in FIG. 9, the description is made on the assumption that the first to fourth sub-buffers BUF_S1 to BUF_S4 have the same size (or buffer size), but the present disclosure is not limited thereto. For example, the second sub-buffer BUF_S2 has a size that is twice the size of the first sub-buffer BUF_S1, and the third sub-buffer BUF_S3 has a size that is twice the size of the second sub-buffer BUF_S2. Can have. In this case, only the first sub-switch SW_S1 corresponding to the first sub-buffer BUF_S1 is turned on corresponding to the fourth value (eg, 11), and the third value (eg, 10) is Correspondingly, only the second sub switch SW_S2 corresponding to the second sub buffer BUF_S2 is turned on, and the first and second sub buffers BUF_S1 and BUF_S2 corresponding to the second value (eg, 01) ) May be turned on, and only the third sub-buffer BUF_S3 may be turned on corresponding to the first value (eg, 00).

10 is a block diagram illustrating another example of a chopping controller included in the source driver of FIG. 3.

7 and 10, the chopping controller 320 of FIG. 10 is different from the chopping controller 320 of FIG. 7 in that it further includes an analog filter 740 (or a low-pass filter).

The buffer circuit 730 may output a second control signal provided from the level shifter 720 as a chopping control signal CCS. Unlike the buffer circuit 730 described with reference to FIG. 7, the buffer circuit 730 illustrated in FIG. 10 may not change the slew rate of the chopping control signal CCS, but is not limited thereto.

The analog filter 740 is connected between the output terminal of the buffer circuit 730 and the chopping circuit SW, and may variably filter the high frequency component of the chopping control signal CCS. That is, the analog filter 740 may adjust a cut-off frequency, and accordingly, the slope of the chopping control signal CCS may be varied.

The analog filter 740 may include a variable resistor R1 and a variable capacitor C1. The variable resistor R1 may be connected between the buffer circuit 730 and the chopping circuit SW, and the variable capacitor C1 may be connected between the chopping circuit SW and the reference voltage line VREF (eg, ground). have. The variable resistor R1 is implemented with a plurality of resistors and switching elements, and similarly, the variable capacitor C1 may be implemented with a plurality of capacitors and switching elements.

At least one of the resistance of the variable resistor R1 and the capacitance of the variable capacitor C1 may be varied based on the selection signal CHOP_SLOPE_CON[1:0]. Referring to FIG. 9, for example, when the selection signal CHOP_SLOPE_CON[1:0] has a first value (for example, 00), the resistance of the variable resistor R1 and the capacitance of the variable capacitor C1 are respectively It can be the smallest. As another example, when the selection signal CHOP_SLOPE_CON[1:0] has a fourth value (eg, 11), each of the resistance of the variable resistor R1 and the capacitance of the variable capacitor C1 may be the largest.

11 is a block diagram illustrating another example of a chopping controller included in the source driver of FIG. 3.

7 and 11, the chopping controller 320 of FIG. 11 is different from the chopping controller 320 of FIG. 7 in that it further includes a delay element 750 instead of the analog filter 740. Do.

The delay element 750 may be connected between the buffer circuit 730 and the chopping circuit SW.

The delay element 750 may include a resistor R, diodes D1 and D2, and delay switching elements SW_D1 and SW_D2. The resistor R is connected between the buffer circuit 730 and the chopping circuit SW, and a first diode D1 and a first delay switching element SW_D1 connected in series are connected in parallel to the resistor R. Thus, the second diode D2 and the second delay switching element SW_D2 connected in series with each other may be connected in parallel to the resistor R. The first and second delay switching elements SW_D1 and SW_D2 may be turned on or turned off in response to a preset selection signal.

The resistor R may be composed of a variable resistor, and a chopping control signal (or a rising edge and a falling edge of the chopping control signal) provided from the buffer circuit 730 may be delayed and transmitted by the resistor R. . Instead of the resistor R, the analog filter 740 described with reference to FIG. 10 may be applied.

The first diode D1 and the second diode D2 may be connected in different directions (or different polarities). The first diode D1 may transmit the rising edge of the chopping control signal provided from the buffer circuit 730 without delay, and similarly, the second diode D2 may transmit the falling edge of the chopping control signal without delay. .

That is, the delay element 750 delays the chopping control signal using the resistor R or adjusts the slew rate of the chopping control signal, but controls the chopping using the first diode D1 and the second diode D2. It is also possible to adjust the slew rate for at least one of the rising edge and the falling edge of the signal.

12 is a diagram illustrating a display device according to another exemplary embodiment of the present invention. 13 is a cross-sectional view illustrating an example of the display device of FIG. 12.

12 and 13, the display device 1 may display an image. The display device 1 may be a portable terminal such as a tablet PC, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a game machine, and a wrist watch type electronic device. However, the display device 1 is not limited thereto. For example, the display device 1 may be a large electronic device such as a television or an external billboard, or may be a personal computer, a notebook computer, a car navigation device, and a small and medium-sized electronic device such as a camera.

The display device 1 may include a display area DA and a non-display area NDA. The display area DA is a part that displays an image, and the non-display area NDA may be defined as a part that does not display an image.

The display area DA is located in the center of the display device 1 and may have a relatively larger area than the non-display area NDA. The display unit 110 described with reference to FIG. 1 may be provided in the display area DA, or the display area DA may correspond to the display unit 110.

The non-display area NDA may be located on or around at least one side of the display area DA. The non-display area NDA may be an area from the outer boundary of the display area DA to the edge (or edge) of the display device 1. In the non-display area NDA, the scan driver 120, the source driver 130, the timing controller 140, and the light emission driver 150 described with reference to FIG. 1 may be provided.

The display device 1 may include a base layer SUB (or a substrate), a display layer DISP (or a display panel), and a touch sensing layer TSP (or a touch panel).

The base layer SUB may be made of an insulating material such as glass or resin. The base layer SUB may be formed of a material having flexibility so as to be bent or folded, and may have a single layer structure or a multilayer structure.

The display layer DISP may be formed on the base layer SUB (that is, in the third direction DR3 based on the base layer SUB). Since the display layer DISP may be substantially the same as the display device 100 described with reference to FIG. 1, overlapping descriptions will not be repeated.

The touch sensing layer TSP is disposed on the display layer DISP, and is provided in the touch electrode and non-display area NDA (or non-sensing area) provided in the display area DA (or sensing area). A sensing wire connected to the touch electrode may be included.

The touch sensing layer TSP may be formed integrally or directly with the display layer DISP. However, the present invention is not limited thereto, and the touch sensing layer TSP is manufactured as a separate touch panel independent of the display layer DISP (or display panel), and includes an adhesive layer (eg, OCR, OCA, etc.). It may be coupled to the display layer DISP.

14 is a plan view illustrating an example of a touch sensing layer included in the display device of FIG. 13.

13 and 14, the touch sensing layer TSP may include a sensing area SA and a non-sensing area NSA. The sensing area SA may correspond to the display area DA of the display device 1, and the non-sensing area NSA may correspond to the non-display area NDA of the display device 1.

The touch electrode TE may be provided in the sensing area SA, and the sensing line SSL and the pad part PD may be provided in the non-sensing area NSA.

The touch electrode TE may include a first touch electrode TE1 and a second touch electrode TE2. The first and second touch electrodes TE1 and TE2 are alternately disposed (or alternately), and may be connected along different directions.

The first touch electrodes TE1 are arranged in a matrix form, are electrically connected to each other along the second traveling direction DR2, and may constitute touch electrode rows parallel to each other. In one row of touch electrodes, the first touch electrode TE1 may be electrically connected to an adjacent touch electrode through a first connection pattern CNP1 (or a bridge pattern).

The second touch electrodes TE2 are arranged in a matrix form, are electrically connected to each other along the first direction DR1, and may form touch electrode rows parallel to each other. In one row of touch electrodes, the second touch electrode TE2 may be electrically connected to an adjacent touch electrode through the second connection pattern CNP2.

Each of the first touch electrode TE1 (or touch electrode rows) and the second touch electrode TE2 (or touch electrode columns) is electrically connected to a sensing pad included in the pad unit PD through a sensing line SSL. Can be connected to.

In an embodiment, each of the touch electrode TE and the connection patterns CNP1 and CNP2 may include a plurality of thin conductive wires. For example, as shown enlarged in the touch area EA, each of the touch electrode TE and the connection patterns CNP1 and CNP2 extends in one direction and includes a plurality of first conductive thin lines parallel to each other, and A plurality of second conductive thin wires extending in a direction crossing the first conductive thin wires and parallel to each other may be included. That is, each of the touch electrode TE and the connection patterns CNP1 and CNP2 may have a mesh structure.

However, the touch electrode TE and the connection patterns CNP1 and CNP2 are not limited thereto. For example, the touch electrode TE and the connection patterns CNP1 and CNP2 are transparent conductive materials such as ITO and IZO. It may also include.

The sensing line SSL may electrically connect the touch electrode TE and a driving circuit (not shown). The sensing line SSL may transmit a sensing input signal from the driving circuit to the touch electrode TE, or may transmit a sensing output signal from the touch electrode TE to the driving circuit.

15 is a cross-sectional view illustrating an example of the display device of FIG. 13. In FIG. 15, a portion (eg, a pixel) in the display area DA of the display device 1 is enlarged and illustrated.

13 to 15, the display layer DISP is disposed on the base layer SUB, and may include a pixel circuit layer PCL and a light emitting device layer LDL (or a display device layer). .

The pixel circuit layer PCL is disposed on the base layer SUB, and is provided on the display area DA of the base layer SUB. A data line DL corresponding to one of the data lines DL1 to DLm described with reference may be included.

The pixel circuit layer PCL includes a buffer layer BUF, a semiconductor layer, a first insulating layer INS1, a first conductive layer GAT, a second insulating layer INS2, a second conductive layer SD, and a third insulating layer. A layer INS3 may be included.

The buffer layer BUF may be disposed on the entire surface of the base layer SUB. The buffer layer BUF may prevent diffusion of impurity ions, prevent penetration of moisture or outside air, and may perform a surface planarization function. The buffer layer BUF may include silicon nitride, silicon oxide, or silicon oxynitride. The buffer layer BUF may be omitted depending on the type of the base layer SUB or process conditions.

The semiconductor layer may be disposed on the buffer layer BUF (or the base layer SUB). The semiconductor layer may be an active layer forming a channel of the transistor TR. The semiconductor layer may include a source region and a drain region in contact with the source electrode SE and the drain electrode DE, which will be described later. A region between the source region and the drain region may be a channel region ACT.

The semiconductor layer may include polysilicon, amorphous silicon, oxide semiconductor, or the like. The channel region ACT of the semiconductor pattern is a semiconductor pattern that is not doped with impurities, and may be an intrinsic semiconductor. The source region and the drain region may be semiconductor patterns doped with impurities. Impurities such as n-type impurities, p-type impurities, and other metals may be used as impurities.

The first insulating layer INS1 (or the gate insulating layer) may be disposed on the semiconductor layer and the buffer layer BUF (or the base layer SUB). The first insulating layer INS1 may be disposed over the entire surface of the base layer SUB. The first insulating layer INS1 may be a gate insulating layer having a gate insulating function.

The first insulating layer INS1 may include an inorganic insulating material such as a silicon compound and a metal oxide. For example, the first insulating layer INS1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. The first insulating layer INS1 may be a single layer or a multilayer layer formed of a stacked layer of different materials.

The first conductive layer GAT may be disposed on the first insulating layer INS1. The first conductive layer GAT may include a gate electrode GE. The gate electrode GE may be disposed to overlap the semiconductor layer (or the channel region ACT of the semiconductor layer).

The first conductive layer (GAT) is molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), may include at least one metal selected from copper (Cu). The first conductive layer GAT may have a single layer structure or a multilayer structure.

The second insulating layer INS2 (or interlayer insulating layer) may be disposed on the first conductive layer GAT and may be disposed over the entire surface of the base layer SUB. The second insulating layer INS2 serves to insulate the first conductive layer GAT and the second conductive layer SD, and may be an interlayer insulating film.

The second insulating layer INS2 may include an inorganic insulating material or an organic insulating material. The second insulating layer INS2 may be a single layer or a multilayer layer formed of a stacked layer of different materials.

The second conductive layer SD may be disposed on the second insulating layer INS2. The second conductive layer SD may include a source electrode SE (or a first transistor electrode), a drain electrode DE (or a second transistor electrode), and a data line DL.

Each of the source electrode SE and the drain electrode DE may contact the source region and the drain region of the semiconductor pattern through a contact hole penetrating through the second insulating layer INS2 and the first insulating layer INS1.

Similar to the first conductive layer GAT, the second conductive layer SD is molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), Gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu) Can include. The second conductive layer SD may have a single layer or a multilayer structure.

The third insulating layer INS3 (or the protective layer) may be positioned on the second conductive layer SD.

The light emitting device layer LDL may be disposed on the pixel circuit layer PCL. The light emitting device layer LDL is provided in the display area DA and may include at least one light emitting device EL and an encapsulation layer TFE connected to the at least one transistor TR.

The light emitting device EL may be disposed on the third insulating layer INS3.

The light emitting element EL (or, the light emitting element layer LDL) includes a first electrode LE (or a lower electrode), a second electrode UE (or an upper electrode), and a light emitting layer IL (or, An intermediate layer). In addition, the light emitting device EL may further include a pixel defining layer PDL. One of the first electrode LE and the second electrode UE may be an anode electrode, and the other may be a cathode electrode. For example, the first electrode LE may be an anode electrode, and the second electrode CE may be a cathode electrode.

The first electrode LE may be electrically connected to the drain electrode DE of the transistor TR through a contact hole penetrating the third insulating layer INS3.

The pixel defining layer PDL is disposed along the edge of the first electrode LE, and the pixel defining layer PDL may include an organic insulating material.

The emission layer IL may be disposed on the first electrode LE exposed by the pixel defining layer PDL. The light emitting layer IL may include a low molecular weight material or a high molecular weight material.

The second electrode UE may be disposed on the emission layer IL. The second electrode UE may be a common electrode formed entirely on the emission layer IL and the pixel definition layer PDL. The second electrode UE may be a transparent or translucent electrode.

The encapsulation layer TFE may be disposed on the second electrode UE. The encapsulation layer TFE may prevent moisture and air that may be introduced from the outside from penetrating into the light emitting element EL. The encapsulation layer TFE may be formed as a thin film encapsulation, and may include one or more organic layers and one or more inorganic layers.

Meanwhile, in FIG. 15, the light-emitting device layer LDL is illustrated as including an organic light-emitting device, but is not limited thereto. For example, the light-emitting device layer LDL may include an inorganic light-emitting device or the like.

The touch sensing layer TSP may be disposed on the light emitting device layer LDL. The touch sensing layer TSP may include a touch electrode TE provided in the display area DA (or the sensing area SA).

The touch sensing layer TSP may include a third conductive layer YTML1, a fourth insulating layer INS4, a fourth conductive layer YTML2, and a fifth insulating layer INS5.

The third conductive layer YTML1 is disposed on the encapsulation layer TFE and may include a first connection pattern CNP1.

The fourth insulating layer INS4 may be disposed on the third conductive layer YTML1. Further, the fourth insulating layer INS4 may be disposed on the encapsulation layer TFE partially exposed by the third conductive layer YTML1 and the third conductive layer YTML1.

The fourth conductive layer YTML2 is disposed on the fourth insulating layer INS4 and includes a first touch electrode TE1, a second connection pattern CNP2, and a second touch electrode TE2 (see FIG. 14). can do. The first touch electrode TE1 may contact or be connected to the first connection pattern CNP1 through a contact hole penetrating the fourth insulating layer INS4.

The fifth insulating layer INS5 may be disposed on the fourth conductive layer YTML2 and may be disposed over the entire surface of the encapsulation layer TFE.

Meanwhile, a second parasitic capacitor Cpar2 may be formed between the data line DL and the touch electrode TE. For example, the data line DL, the touch electrode TE overlapping therewith, and at least one insulating layer disposed therebetween (for example, the third insulating layer INS3, the pixel defining layer PDL, etc.) ) May constitute a second parasitic capacitor Cpar2.

As described with reference to FIG. 5, by the operation of the chopping controller 320 (refer to FIG. 3) of the source driver 130, the data line DL (or the data line) through the output buffer 370 (refer to FIG. 3). When noise occurs in the data signal transmitted through (DL)), the noise affects the second parasitic capacitor Cpar2 on the touch electrode TE (or a driving signal flowing through the touch electrode TE, a sensing signal) Or can act as touch noise.

The touch sensing layer TSP is driven independently of the display layer DISP, and, for example, a period of scanning the touch sensing layer TSP (or timing points at which sensing signals are output) of the display layer DISP It may not be synchronized with the driving period (or timing points at which the chopping control signal transitions). In this case, it may be difficult to exclude touch noise caused by noise of the data line DL.

Meanwhile, the structure of the display layer DISP, the arrangement of the data lines DL in the display layer DISP, the structure of the touch sensing layer TSP, the combination structure of the touch sensing layer TSP with the display layer DISP, etc. Accordingly, the size of the touch noise may vary for each display device, and the touch noise may not occur.

Accordingly, the display device 1 according to the exemplary embodiment of the present invention, as described with reference to FIGS. 7 to 11, is a chopping controller 320 capable of varying the slew rate or transition speed of the chopping control signal CCS. ), and the slew rate of the chopping control signal CCS (or the value of the selection signal CHOP_SLOPE_CON[1:0], refer to FIG. 9) that determines the value of the touch noise in the manufacturing process of the display device 1 It is set in consideration of occurrence and size, and the chopping controller 320 may operate based on a set slew rate (or a value of a set selection signal CHOP_SLOPE_CON[1:0]). The larger the touch noise, the lower the slew rate.

16 is a diagram illustrating an example of a sensing signal measured by the touch sensing layer of FIG. 14. FIG. 16 illustrates a sensing signal flowing through the touch electrode TE (or touch electrode rows composed of the second touch electrode TE2) described with reference to FIG. 14. The sensing signals may be sequentially transmitted along the touch electrode columns.

15 and 16, when noise is generated in the data line DL by the operation of the chopping controller 320 (FIG. 7), output through the touch electrode column overlapping the data line DL at the time point Touch noise may occur in the sensed signal.

Accordingly, the display device 1 according to embodiments of the present invention may reduce or remove touch noise by varying the slew rate or transition speed of the chopping control signal CCS (refer to FIG. 7 ).

The scope of the present invention is not limited to the content described in the detailed description of the specification, but should be defined by the claims. In addition, the meaning and scope of the claims, and all changes or modified forms derived from the concept of equivalents thereof should be construed as being included in the scope of the present invention.

1, 100: display device 110: display unit
120: scan driver 130: source driver
140: timing control unit 150: light emitting driver
310: controller 320: chopping controller
330: gamma voltage generator 340: shift register
350: latch 360: decoder
370: output buffer 710: logic control circuit
720: level shifter 730: buffer circuit
740: analog filter 750: delay element
AMP: amplifier
BUF_S1, BUF_S2, BUF_S3, BUF_S4: sub buffers
Cpar1: first parasitic capacitor Cpar2: second parasitic capacitor
SW: Chopping circuit
SW1, SW2, SW3, SW4: first to fourth switches
SW_S1, SW_S2, SW_S3, SW_S4: first to fourth sub switches
TE: touch electrode TSP: touch sensing layer

Claims (20)

A gamma voltage generator for generating gamma voltages having different voltage levels;
A digital-analog converter that generates a data voltage corresponding to a gradation value by using the gamma voltages;
An output buffer for outputting the data voltage to the outside; And
And a chopping control unit that generates a chopping control signal and provides it to the output buffer unit,
The output buffer unit,
An amplifier connected to an output terminal of the digital-analog converter; And
And a chopping circuit for periodically changing the polarity of the offset of the amplifier in response to the chopping control signal,
The chopping control unit varies a slew rate of the chopping control signal. The method of claim 1, wherein the chopping circuit,
A first switch connected between the input node and the first input terminal of the amplifier,
A second switch connected between the input node and a second input terminal of the amplifier,
A third switch connected between the first input terminal of the amplifier and the output terminal of the amplifier, and
A fourth switch connected between the second input terminal of the amplifier and the output terminal of the amplifier,
The first to fourth switches operate in response to the chopping control signal. The source driver of claim 2, wherein a parasitic capacitor is formed between an output node to which the output terminal of the amplifier is connected and a control line for transmitting the chopping control signal to the third switch. The method of claim 1, wherein the chopping control unit,
A logic control circuit for generating a first control signal including a pulse,
A level shifter for generating a second control signal by shifting up the level of the first control signal, and
And a buffer circuit that outputs the second control signal as the chopping control signal and varies a buffer size. The source driver of claim 4, wherein the slew rate is a rate at which the chopping control signal follows the second control signal. The method of claim 4, wherein the buffer circuit,
Sub buffers connected in parallel to the chopping circuit; And
And sub switches respectively connecting the sub buffers to an output terminal of the level shifter,
At least one of the sub switches is turned on in response to a preset selection signal. The source driver of claim 6, wherein the sub-buffers have the same buffer size. The source driver of claim 6, wherein the sub-buffers have different buffer sizes. The source driver of claim 4, wherein the slew rate of the chopping control signal decreases as the buffer size of the buffer circuit decreases. The method of claim 1, wherein the chopping control unit,
A logic control circuit for generating a first control signal in the form of a square wave,
A level shifter for generating a second control signal by shifting up the level of the first control signal,
A buffer circuit for outputting the second control signal as the chopping control signal, and
And an analog filter connected between the output terminal of the buffer circuit and the chopping circuit to variably filter a high frequency component of the chopping control signal. The method of claim 10, wherein the analog filter,
A variable resistor connected between the buffer circuit and the chopping circuit, and
A source driver comprising a variable capacitor connected between the chopping circuit and a reference voltage line. The method of claim 1, wherein the chopping control unit,
A logic control circuit for generating a first control signal in the form of a square wave,
A level shifter for generating a second control signal by shifting up the level of the first control signal,
A buffer circuit for outputting the second control signal as the chopping control signal, and
And a delay element connected between the output terminal of the buffer circuit and the chopping circuit. The method of claim 12, wherein the delay element,
A resistor connected between the buffer circuit and the chopping circuit, and
A source driver connected in parallel to the resistor and including a switch and a diode connected in series with each other. A display panel including a data line and a pixel connected to the data line; And
Includes a source driver providing a data voltage to the data line,
The source driver,
A digital-analog converter for generating the data voltage;
An output buffer unit outputting the data voltage to the data line; And
And a chopping control unit generating a chopping control signal and providing it to the output buffer unit,
The output buffer unit,
An amplifier connected between the digital-analog converter and the data line; And
In response to a chopping control signal comprising a chopping circuit for periodically changing the polarity of the offset of the amplifier,
The chopping control unit varies a slew rate of the chopping control signal. The method of claim 14, wherein the chopping circuit,
A first switch connected between the input node and the first input terminal of the amplifier,
A second switch connected between the input node and a second input terminal of the amplifier,
A third switch connected between the first input terminal of the amplifier and the output terminal of the amplifier, and
A fourth switch connected between the second input terminal of the amplifier and the output terminal of the amplifier,
The first to fourth switches operate in response to the chopping control signal. The method of claim 14, wherein the chopping control unit,
A logic control circuit for generating a first control signal including a pulse,
A level shifter for generating a second control signal by shifting up the level of the first control signal, and
And a buffer circuit that outputs the second control signal as the chopping control signal and varies a buffer size. The method of claim 16,
Further comprising a touch sensing unit including touch electrodes,
The display device, wherein the buffer size of the buffer circuit is adjusted based on noise of the touch electrodes caused by the chopping control signal. The display device according to claim 17, wherein the larger the noise, the smaller the buffer size of the buffer circuit. The display device according to claim 18, wherein the buffer size of the buffer circuit is set to be the largest within a range in which the noise does not occur. The method of claim 16, wherein the buffer circuit,
Sub buffers connected in parallel to the chopping circuit; And
And sub switches respectively connecting the sub buffers to an output terminal of the level shifter,
At least one of the sub switches is turned on in response to a preset selection signal.

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