KR20200079738A - Driving circuit of the display device - Google Patents

Abstract

The present invention relates to a driving circuit of a display device and, more specifically, includes: a plurality of source buffers for controlling a slew rate by a bias current and outputting a data voltage corresponding to displayed image data to each of the plurality of source lines; and a power controller for controlling the bias current based on a transition degree that is a difference between image data sequentially provided to the source buffer.

Description

Driving circuit of the display device {Driving circuit of the display device}

The present invention relates to a driving circuit of a display device, more specifically, a slew rate is controlled by a bias current, and a plurality of sources for outputting data voltages corresponding to displayed image data to each of the plurality of source lines And a power control unit controlling the bias current based on a transition degree, which is a difference between image data sequentially provided to the buffer and the source buffer.

In general, a display device includes a display panel for displaying an image and a driver for supplying a plurality of signals to the display panel. The driving unit includes a timing controller for generating image data and multiple control signals, a gate driver for generating gate signals using image data and multiple control signals, and a source driver for generating data signals.

As the display device becomes high-resolution and large-sized, it is required that the source driver to display a high-quality image has a fast slew rate characteristic and is driven at low power.

The problem to be solved by the present invention is to reduce power consumption of a display device by controlling a bias current of a source buffer based on a transition degree, which is a difference between input image data.

As a means for solving the above-described problems, the present invention has an embodiment with the following features.

The present invention, the slew rate (slew rate) is controlled by the bias current, a plurality of source buffers for outputting a data voltage corresponding to the displayed image data to each of the plurality of source lines; And a power control unit controlling the bias current based on a transition degree that is a difference between image data sequentially provided to the source buffer. It characterized in that it comprises.

The power control unit includes an analysis module that calculates an average transition degree of a transition degree, which is a difference between image data sequentially provided to the source buffer, and generates a power control signal that controls the bias current based on the average transition degree. It is characterized by.

The period for generating the control signal is a constant multiple of the horizontal synchronization signal (Hsync) period, and the average transition degree calculation period is characterized in that it coincides with the period for generating the control signal.

The constant multiple is characterized in that it is one multiple.

The period for generating the control signal is a constant multiple of the Long-H period, the average transition degree calculation period coincides with the control signal generation period, and the Long-H period is a display period using a time division method. In order to divide the touch sensing section and drive the in-cell touch screen integrated display, it is characterized in that it is a touch sensing section.

An analysis module for calculating a maximum transition degree of a transition degree, which is a difference between image data sequentially provided to the source buffer, and generating a power control signal for controlling the bias current based on the maximum transition degree; It characterized in that it comprises a.

The power control unit may include a receiving module that receives the temperature of the source buffer; An analysis module that calculates a transition degree, which is a difference between image data sequentially provided to the source buffer, and generates a power control signal that controls the bias current based on the transition degree; And a compensation module that compensates for a power control signal generated by the analysis module when the temperature received by the receiving module is greater than a preset value. It characterized in that it comprises a.

The power control unit includes: a receiving module that receives output voltage information of the source buffer; An analysis module that calculates a transition degree, which is a difference between image data sequentially provided to the source buffer, and generates a power control signal that controls the bias current based on the transition degree; And a compensation module that compensates for a power control signal generated by the analysis module by measuring a rise/fall time from the output voltage information received by the receiving module. It characterized in that it comprises a.

The analysis module, it characterized in that it comprises a counter for measuring the rise / fall time of the output voltage.

According to the present invention, an optimal source buffer is provided for an image that is different or complex in only one part by segmenting and analyzing image data by synchronizing a control signal generation cycle for controlling a bias current with a horizontal synchronization signal (Hsync) or a Long-H cycle. It has the effect of adjusting the bias current.

In addition, the present invention has the effect of adjusting the optimal source buffer bias current even in a high temperature environment by compensating for a signal that controls the source buffer bias current when the temperature of the source buffer is measured and the temperature is higher than a set value. have.

In addition, the present invention provides an optimal source buffer bias current by compensating for the signal controlling the source buffer bias current by measuring the rise/fall time by measuring the output voltage of the source buffer even if the panel load is changed according to the panel deviation. It has the effect of controlling.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention
2 is a block diagram of a source driver according to an embodiment of the present invention
3 is a block diagram of a power control unit according to an embodiment of the present invention
FIG. 4 is a diagram showing the waveform of the source voltage output from the source buffer during one gate driving pulse time.
5A is a general pattern (PTN) image and a transitional analysis graph for the image data.
Figure 5b is a RED pattern (PTN) image and a transitional analysis graph for the image data
6A is a diagram illustrating a case where the entire display screen is a 1 dot pattern image
FIG. 6B is a diagram illustrating a case where a display top screen is a 1 dot pattern and a bottom screen is a white pattern.
7 is a diagram for driving an in-cell touch screen integrated display by dividing a display section and a touch sensing section using a time division method.
8 is a diagram related to analyzing image data and generating a control signal (PCS) in a time or space division method;
9 is a view showing a reduction in power consumption of a display device according to a result of controlling a source buffer bias current in a time or space division method.

Hereinafter, with reference to the accompanying drawings, specific details for the practice of the present invention will be described.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

The driving circuit of the present invention display device includes an image display panel 100, a timing controller 200, a gate driver 300, a source driver 400, and a power control unit 500.

The image display panel 100 includes a plurality of pixels P and displays an image (image) according to the input image data. The pixel P is composed of R, G, and B sub-pixels SP. The arrangement of the sub-pixels SP includes a stripe arrangement method, a mosaic arrangement method, a delta arrangement method, and the like. In the present invention, it is assumed that the sub-pixels SP are arranged in a stripe arrangement method for convenience of description.

Each of the sub-pixels SP is connected to the gate line GL and the source line SL. One sub-pixel SP receives a gate signal from the gate driver 300 through the gate line GL, and receives a data signal from the source driver 400 through the source line SL.

The timing controller 200 controls timing of driving signals input to the image display panel 100 and receives image data RGB and control signals from an image source (not shown) external to the display device. The control signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an enable signal (DE), and a clock signal (CLK).

The horizontal synchronization signal (Hsync) represents the time it takes to display one line of the screen. The vertical synchronization signal (Vsync) represents the time it takes to display the screen of one frame. The enable signal DE represents a period during which data is supplied to the sub-pixel SP. The clock signal CLK represents a signal that serves as a reference for generating various signals in synchronization with a gate driver, a source driver, and a timing controller.

The timing controller 200 converts the data format of the image data RGB to meet the interface specification of the source driver 400 to generate input image data, and the input image data is supplied to the source driver 400. to provide. In addition, the timing controller 400 generates a data control signal DCS and a gate control signal GCS based on the control signal. The timing controller 400 provides the data control signal DCS to the source driver 400 and the gate control signal GCS to the gate driver 300.

The gate control signal GCS includes a scan start signal indicating a scan start, the clock signal CLK controlling an output period of the gate on voltage, and an output enable (DE) signal limiting the duration of the gate on voltage. It can contain.

The data control signal DCS may include, for example, a horizontal start signal STH, a load signal MS, an inversion signal POL, and the start of an input image data being transmitted to the data driver 300. It may include a clock signal (CLK).

The gate driver 300 outputs a gate signal while shifting the level of the gate voltage in response to the gate control signal GCS supplied from the timing controller 200. The gate driver 300 supplies gate signals to sub-pixels SP included in the image display panel 100 through a plurality of gate lines GL. The gate driver 300 may be formed in the form of an integrated circuit (IC) or a gate in panel method on the image display panel 100.

The source driver 400 samples and latches image data in response to a data timing control signal supplied from the timing controller 200 and converts the gamma reference voltage to output. The source driver 400 supplies image data to sub-pixels SP included in the image display panel 100 through the source line SL. The source driver 400 may be formed in the form of an integrated circuit (IC).

The power control unit 500 analyzes image data supplied to the source driver 400 to output a power control signal PCS, and the power control signal PCS controls power consumption of the source driver 400. .

2 is a block diagram of a source driver according to an embodiment of the present invention.

The source driver 400 converts the digital circuit 410 for receiving and storing image data RGB in the form of digital signals and the grayscale voltage in the form of analog signals to convert the image data RGB into an image signal panel 100. And an analog circuit 420 output to the source line SL.

The digital circuit 410 includes a shift register unit 411 and a data latch unit 412.

The shift register unit 411 controls timing at which image data RGB is sequentially stored in the data latch unit 412. The shift register unit 411 sequentially shifts the vertical synchronization start signal STH to provide shifted clock signals to the data latch unit 412.

The data latch unit 412 is composed of a plurality of latch circuits, and based on clock signals output from the shift register unit 411, image data RGB corresponding to one horizontal line is applied at one end of the latch circuit. Save sequentially to the other end. When the storage of the image data RGB is completed, the data latch unit 412 outputs the image data RGB in response to the load signal TP.

The analog circuit 420 includes a D/A converter 421 and a source buffer 422.

The D/A converter 421 receives the image data RGB output from the data latch unit 412, and outputs an analog grayscale voltage corresponding to the image data RGB among the grayscale voltages. For example, a gamma decoder, which is a kind of D/A converter 421, decodes N-bit image data (RGB), selects one grayscale voltage among 2 ^N grayscale voltages in response to the decoding result, and selects the selected grayscale voltage. The gradation voltage is output to the source buffer 422. Furthermore, the D/A converter 421 may select one of the 2 ^N high grayscale voltages and 2 ^N low grayscale voltages based on the polarity control signal, and output the selected grayscale voltage.

The source buffer 422 buffers and outputs the analog gradation voltage output from the D/A converter 421. The source buffer 422 may include a plurality of output amplifiers AMP and an output amplifier bias circuit BC that controls the bias of the plurality of output amplifiers AMP.

The output amplifier bias circuit BC receives the power control signal PCS from the power control unit 500 to control the bias current I _B of the output amplifier AMP.

The output amplifier AMP receives grayscale voltages selected in response to image data as input signals, buffers them, and outputs them to the source line SL of the video display panel. At this time, the slew rate of the output amplifier AMP may be adjusted according to the level of the bias signal VB, for example, the level of the bias current I _B. In addition, the source buffer 422 may be connected 1:1 with the source line SL, but a mux (not shown) between the source buffer 422 and the source line SL as a method for reducing the number of source buffers 422. It may be connected to 1:N through.

3 is a block diagram of a power control unit according to an embodiment of the present invention.

The power control unit 500 controls the bias current I _B based on a transition, which is a difference between image data sequentially provided to the source buffer 400, and receives module 510 and storage module 520 ), an analysis module 530, a compensation module 540, and an output module 550.

The receiving module 510 receives and receives image data RGB from an image source (not shown) external to the display device. Also, the receiving module 510 may receive and receive temperature information of the source buffer 422. Also, the reception module 510 may receive output voltage information of the source buffer 422. In addition, the received image data (RGB), temperature information, and output voltage information may be stored in the storage module 520.

The analysis module 530 may analyze the image data RGB stored in the storage module 520 to calculate a transition degree, which is a difference between image data sequentially provided to the source buffer. In addition, an average of the transition diagrams may be calculated, or a maximum value may be calculated. Then, a power control signal PCS for controlling the bias current I _B is generated based on the average or maximum transition.

The compensation module 540 compensates for the power control signal (PCS) generated by the analysis module 530 when the temperature of the source buffer 422 is greater than a preset value. The source buffer 422 is composed of an output amplifier. Since the characteristics of the output amplifier vary depending on the temperature, when the temperature of the source buffer 422 is higher than a set value, the power control signal PCS is compensated. It needs to be changed.

In addition, the compensation module 540 compensates for the power control signal generated by the analysis module by measuring the rise/fall time from the output voltage information of the source buffer 422.

The image display panel 100 in which the source buffer 422 supplies voltage may be modeled as a resistor and a capacitor. Therefore, the output voltage supplied from the source buffer causes a rise/fall time delay due to the response of the RC circuit. In order to compensate for this, the bias current of the source buffer 422 is conventionally set in a manual manner. However, due to manufacturing technology limitations, the image display panels 100 do not all have the same characteristic value, but have a certain value deviation. Therefore, setting the conventional bias current in a manual manner has a problem in that it is impossible to apply an optimal bias current value because it does not reflect the deviation between the panels. The present invention has an effect of automatically setting the optimum bias current value by compensating for the power control signal generated by the analysis module by measuring the rise/fall time from the output voltage information of the source buffer 422.

The output module 550 is generated by the analysis module and transmits a power control signal (PCS) compensated by the compensation module to a source buffer 422. The output amplifier bias circuit BC receiving the power control signal PCS controls the bias current I _B of the output amplifier AMP.

4 is a diagram showing a waveform of a source voltage output from a source buffer during one gate driving pulse time. 4, the transition diagram will be described.

The embodiment illustrated in FIG. 4 illustrates a case in which the source buffer 422 and the source line SL are connected 1:3 through a 1:3 mux (not shown). The transition degree refers to the degree of change in the voltage waveform output from the source buffer 422. In other words, when the source buffer 422 and the source line SL are connected 1:1, the transition degree is a difference between grayscale values between adjacent pixels P in the vertical line direction. The example shown in FIG. 4 is a case where the source buffer 422 and the source line SL are connected 1:3, and since the gradation values do not differ according to red, green, and blue sections, in this case, the transition value is 0. It becomes. Since the voltage waveform output from the source buffer 422 is determined according to the input image data, it is possible to obtain a transition diagram by analyzing the image data.

On the other hand, when this is described based on the image displayed on the display device, the image between the adjacent sub-pixels SP in the vertical direction in the vertical direction based on the case where the source buffer 422 and the source line SL are 1:1 connected. It can be viewed as information. However, it is not accurate to determine the degree of transition based on the image displayed on the display device. Because, even when the same image is displayed on the display device, the actual transition value may be different depending on the connection method of the source buffer 422 and the source line SL or the color arrangement method of the sub-pixel SP.

The RED pattern in which the entire screen is RED will be described again as an example. The output voltage of the source buffer 420 will be described on the assumption that the voltage for turning on the sub-pixel is 1 and the voltage for turning off is 0. If the source buffer 422 and the source line SL are 1:1 connected, the voltage output from the source buffer 422 connected to the source line SL of the R sub-pixel can be expressed as 111 being repeated. In this case, the transition degree becomes 0, and the voltage output from the source buffer 422 connected to the source line SL of the G or B subpixel can be expressed as 000 repetition, and in this case, the transition degree also becomes 0. However, if it is connected 1:3 through MUX, the voltage output from the source buffer can be expressed as 100100100 repeated, and in this case, the transition is not zero. Even in the case where the same image is seen, the transition value may vary depending on the connection method.

FIG. 5A is a graph of transition analysis of a general pattern (PTN) image and its image data, and FIG. 5B is a graph of transition diagram analysis of a RED pattern (PTN) image and its image data. The X-axis of the graph is the transition, and the Y-axis is the frequency. Although FIG. 5B is a RED pattern, it can be seen that the transition degree is high. This is because, as described above, the connection between the source buffer 422 and the source line SL is not 1:1, but is connected 1:3 through mux.

6A is a diagram illustrating a case where the entire display screen is a 1dot pattern image, and FIG. 6B is a diagram illustrating a case where the display top screen is a 1dot pattern and the bottom screen is a White pattern.

The 1-dot pattern has a very high transition value because on/off is repeated vertically and horizontally for each pixel P as shown in the enlarged portion of FIG. 6A.

On the other hand, in the white pattern, since all the pixels P are turned on vertically, left and right, the transition value becomes 0.

As illustrated in FIG. 6A, when the entire screen is a 1-dot pattern, there is no problem even if the bias current I _B of the source buffer 420 is determined to be a large value to correspond to the transition value in the entire section of one frame.

However, as illustrated in FIG. 6B, when a part of the screen is a 1 dot pattern and the other part is a white pattern, it is not efficient to determine the bias current I _B in the entire section of one frame. If a bias current I _B having a large value to match a 1 dot pattern is applied, waste of power is generated in the source buffer 420, and if a bias current I _B with a small value to match a white pattern is applied. , The slew rate of the source buffer 420 is deteriorated, so that a screen in a 1-dot area with a large transition cannot be properly displayed.

Therefore, in order to efficiently determine the bias current, the bias current of the source buffer is analyzed by dividing and analyzing the image of one frame for each time period or space (one or more horizontal lines) instead of determining the bias current (I _B ) in the entire section of one frame. It is desirable to determine the current I _B.

FIG. 7 is a diagram for driving an in-cell touch screen integrated display by dividing a display section and a touch sensing section using a time division method, and FIG. 8 is a time or space division method. This diagram is about analyzing and generating control signals (PCS).

Referring to FIGS. 7 to 8, division by time section or space is performed by the power control unit in order to synchronize the power control signal controlling the bias current of the source buffer 420 with the output voltage of the source buffer 420. It is preferable to determine the synchronization signal (Hsync) period or a constant multiple of the Long-H period.

When the control signal (PCS) is calculated by a multiple of the Hsync period, the division rate is highest for each time section or space. Therefore, from the viewpoint of minimizing the power consumption of the source buffer, it is most efficient to calculate the control signal PCS at a multiple of the Hsync period. However, during 1 Hsync, since the image data is analyzed, the control signal (PCS) is calculated, and the control signal is transmitted to control the bias current of the source buffer 420, the time margin is short in us. .

The in-cell type touch screen integrated display is divided into a display section DS and a touch section TS according to the touch control signal Tsync and is driven. The Long-H period divides the display section DS and the touch sensing section TS using a time division method to drive an in-cell touch screen integrated display, and the touch sensing section TS is used. Speak. The Long-H period generally has a time of several ms. Therefore, in this case, there is no problem in securing the time margin required to control the bias current I _B of the source buffer.

9 is a view showing a degree of power consumption reduction of a display device according to a result of controlling a source buffer bias current I _B in a time or space division method. As shown in FIG. 9, there is no significant difference in the frame method, the long-H method, and the Hsync method in the white, black, and red patterns, in which the entire screen is the same pattern. However, when a part of the screen is a pattern with a high transition (RED in the drawing), it can be seen that there is a difference in power consumption reduction in the Frame method, Long-H method, and Hsync method. In addition, it can be seen that the case of calculating the control signal PCS at a multiple of the Hsync period is the most efficient in terms of minimizing the power consumption of the source buffer, since the division rate is highest for each time period.

It should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included in the claims of the present invention. .

100: panel
200: timing controller
300: gate driver
400: source driver
410: digital circuit
411: shift register unit
412: data latch unit
420: analog circuit
421: D/A converter
422: source buffer
500: power control
510: receiving module
520: storage module
530: analysis module
540: compensation module
550: output module

Claims (11)

A slew rate is controlled by a bias current, and a plurality of source buffers outputting data voltages corresponding to the displayed image data to each of the plurality of source lines; And
A power control unit controlling the bias current based on a transition degree that is a difference between image data sequentially provided to the source buffer; A driving circuit of the display device comprising a. According to claim 1,
The power control unit
An analysis module for calculating an average transition of transitions, which is a difference between image data sequentially provided to the source buffer, and generating a power control signal for controlling the bias current based on the average transition; A driving circuit of the display device comprising a. According to claim 2,
The period for generating the control signal is a constant multiple of the horizontal synchronization signal (Hsync) period,
The average transition degree calculation section, the driving circuit of the display device, characterized in that coincides with the control signal generation cycle. According to claim 2,
The period for generating the control signal is a constant multiple of the Long-H period,
The average transition diagram calculation section is identical to the control signal generation period,
The long-H period is a display device and a touch sensing section using a time division method to drive an in-cell (in-cell) touch screen-integrated display, and is a touch sensing section of the display device characterized in that it is a touch sensing section. in. According to claim 1,
The power control unit,
An analysis module for calculating a maximum transition degree of a transition degree, which is a difference between image data sequentially provided to the source buffer, and generating a power control signal for controlling the bias current based on the maximum transition degree; A driving circuit of the display device comprising a. The method of claim 5,
The period for generating the control signal is a constant multiple of the horizontal synchronization signal (Hsync) period,
The maximum transition degree calculation section, the driving circuit of the display device, characterized in that coincides with the control signal generation cycle. The method of claim 5,
The period for generating the control signal is a constant multiple of the Long-H period,
The maximum transition degree calculation section is identical to the control signal generation period,
The long-H period is a display device and a touch sensing section using a time division method to drive an in-cell (in-cell) touch screen-integrated display, and is a touch sensing section of the display device characterized in that it is a touch sensing section. in. According to claim 1,
The power control unit,
A receiving module that receives the temperature of the source buffer;
An analysis module that calculates a transition degree, which is a difference between image data sequentially provided to the source buffer, and generates a power control signal that controls the bias current based on the transition degree; And
A compensation module that compensates for a power control signal generated by the analysis module when the temperature received by the receiving module is greater than a preset value; A driving circuit of the display device comprising a. According to claim 1,
The power control unit,
A receiving module for receiving output voltage information of the source buffer;
An analysis module that calculates a transition degree, which is a difference between image data sequentially provided to the source buffer, and generates a power control signal that controls the bias current based on the transition degree; And
A compensation module that compensates for a power control signal generated by the analysis module by measuring a rise/fall time from the output voltage information received by the receiving module; A driving circuit of the display device comprising a. The method of claim 9,
The analysis module, the driving circuit of the display device including a counter for measuring the rise / fall time of the output voltage. An image display panel including a plurality of pixels and displaying an image according to the input image data; And
A driving circuit for driving the video display panel; Including,
The driving circuit includes a plurality of source buffers in which a slew rate is controlled by a bias current, and a data voltage corresponding to the displayed image data is output to each of the plurality of source lines; And a power control unit controlling the bias current based on a transition degree that is a difference between image data sequentially provided to the source buffer. Video display device comprising a.

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