KR101857813B1 - Gamma voltage generation circuit and organic light emitting diode display device including the same - Google Patents

Abstract

The present invention relates to a gamma voltage generating circuit and an organic light emitting diode display device including the same. A gamma voltage generating circuit according to an embodiment of the present invention includes a reference luminance controller for controlling a maximum luminance voltage and a minimum luminance voltage to adjust a maximum luminance and a minimum luminance of a display panel; A minimum and a maximum gradation gamma voltage selector for dividing the maximum luminance voltage and the minimum luminance voltage and selecting and outputting the lowest gradation gamma voltage and the maximum gradation gamma voltage; And a voltage dividing circuit for dividing the lowest gradation gamma voltage and the highest gradation gamma voltage to output a plurality of gamma voltages.

Description

TECHNICAL FIELD [0001] The present invention relates to a gamma voltage generating circuit and an organic light emitting diode (OLED) display device including the same. BACKGROUND ART [0002]

The present invention relates to a gamma voltage generating circuit and an organic light emitting diode display device including the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been used . Among the flat panel display devices, the organic light emitting diode display device is low-voltage driven, thin, has excellent viewing angle, and has a high response speed. An active matrix type organic light emitting diode display device in which a plurality of pixels are arranged in a matrix form to display an image is widely used in organic light emitting diode display devices.

A display panel of the organic light emitting diode display device receives a scan signal from a scan driving circuit, receives a data voltage from a data driving circuit, and displays an image. At this time, the data driving circuit converts the digital video data inputted from the timing controller into the analog data voltage by using the gamma voltage outputted from the gamma voltage generating circuit.

On the other hand, since the conventional gamma voltage generating circuit can not vary the maximum luminance voltage and the minimum luminance voltage outputted from the reference luminance control section, the module maker manufacturing the display panel is required to design a TV, a monitor, a notebook, It is inconvenient to set the maximum luminance voltage and the minimum luminance voltage of the reference luminance control unit after setting the maximum luminance and minimum luminance of the display panel through preset tuning with the set supplier assembling the information device. In addition, since the conventional gamma voltage generating circuit can not vary the maximum luminance voltage and the minimum luminance voltage output from the reference luminance controller, it is necessary to change the design of the driving TFT (Thin Film Transistor) of the organic light emitting diode display device, And the inconvenience of changing the minimum luminance.

The present invention provides a gamma voltage generating circuit capable of varying a maximum luminance voltage and a minimum luminance voltage output from a reference luminance controller and a display device including the same.

A gamma voltage generating circuit according to an embodiment of the present invention includes a reference luminance controller for controlling a maximum luminance voltage and a minimum luminance voltage to adjust a maximum luminance and a minimum luminance of a display panel; A minimum and a maximum gradation gamma voltage selector for dividing the maximum luminance voltage and the minimum luminance voltage and selecting and outputting the lowest gradation gamma voltage and the maximum gradation gamma voltage; And a voltage dividing circuit for dividing the lowest gradation gamma voltage and the highest gradation gamma voltage to output a plurality of gamma voltages.

A display device according to an embodiment of the present invention includes a display panel on which data lines and scan lines are formed; A data driving circuit for converting the digital video data into an analog data voltage using a gamma voltage and supplying the data voltage to the data lines; A gate driving circuit sequentially supplying a scan pulse synchronized with the data voltage to the scan lines; And a gamma voltage generating circuit for supplying the gamma voltage to the data driving circuit, wherein the gamma voltage generating circuit controls the maximum luminance voltage and the minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel A reference luminance controller; A minimum and a maximum gradation gamma voltage selector for dividing the maximum luminance voltage and the minimum luminance voltage and selecting and outputting the lowest gradation gamma voltage and the maximum gradation gamma voltage; And a voltage divider circuit for dividing the lowest gradation gamma voltage and the highest gradation gamma voltage to output a plurality of gamma voltages.

The present invention can vary the maximum luminance voltage and the minimum luminance voltage output from the reference luminance controller of the gamma voltage generator circuit. As a result, according to the present invention, the set maker can adjust the maximum luminance and the minimum luminance by changing the maximum luminance voltage and the minimum luminance voltage of the reference luminance controller.

Further, the present invention can analyze the average picture level every one frame period and vary the maximum luminance voltage according to the average picture level. As a result, the present invention can reduce power consumption.

Furthermore, the present invention can control gamma voltages of R pixels, G pixels, and B pixels having different luminous efficiency differently. As a result, the present invention can adjust the color coordinates of the light generated by the light emission of the R pixel, the G pixel, and the B pixel.

1 is a block diagram schematically showing an organic light emitting diode display device as an example of a display device according to an embodiment of the present invention.
2 is a block diagram showing a source drive IC;
3 is a block diagram schematically showing a gamma voltage generating circuit.
4 is a diagram showing the maximum luminance and the minimum luminance of a display device according to an embodiment of the present invention.
5 is a block diagram schematically showing an average picture level analyzing unit;
FIG. 6 is a view showing luminous efficiency according to gradations of R organic light emitting diodes, G organic light emitting diodes, and B organic light emitting diodes. FIG.
7 is a circuit diagram showing a gamma voltage generating circuit in detail.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

1 is a block diagram schematically showing an organic light emitting diode display device as an example of a display device according to an embodiment of the present invention. Referring to FIG. 1, an organic light emitting diode display device according to an embodiment of the present invention includes a display panel 10, a data driving circuit 20, a gamma voltage generating circuit 30, a scan driving circuit 40, a timing controller 50, a host system 60, and the like. The display panel 10 according to the embodiment of the present invention may be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) And a flat panel display device such as an organic light emitting diode (OLED). Although the present invention has been described with reference to the embodiment in which the display panel 10 is embodied as an organic light emitting diode device, it should be noted that the present invention is not limited thereto.

The display panel 10 displays an image under the control of the timing controller 50. The display panel 10 includes upper and lower substrates. The upper substrate of the display panel 10 serves as an encapsulating substrate. In the lower substrate of the display panel 10, a pixel array in which pixels are arranged in a matrix form in cell regions defined by data lines and scan lines is formed. Each of the pixels of the pixel array of the display panel 10 includes at least one switching TFT (Thin Film Transistor), a driving TFT, an organic light emitting diode device, and at least one capacitor. Each of the pixels controls an electric current flowing in the organic light emitting diode element using a switching TFT and a driving TFT to display an image. It should be noted that the switching TFT and the driving TFT are formed of a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in the following description. The display panel 10 may display an image in the form of bottom emission and top emission depending on the pixel structure.

The data driving circuit 20 includes a plurality of source drive ICs. The source drive ICs receive the data timing control signal DCS and digital video data (DATA) from the timing controller 50. In addition, the source drive ICs are supplied with the gamma voltage supplied from the gamma voltage generating circuit 30. Source drive ICs convert digital video data (DATA) to analog data voltages using gamma voltages. The source drive ICs supply the data voltages to the data lines of the display panel 10. [ A detailed description of the source drive IC will be given later with reference to FIG. 2, and a detailed description of the gamma voltage generating circuit 30 will be given later with reference to FIG.

The scan driver circuit 40 sequentially supplies scan pulses synchronized with the data voltage to the scan lines of the display panel 10 under the control of the timing controller 50. The scan driving circuit 40 is a shift register for sequentially shifting and outputting a gate start pulse (Gate Start Pulse) supplied from the timing controller 50 according to a gate shift clock, A level shifter for converting into a swing width suitable for driving the TFT, and an output buffer.

The timing controller 50 receives digital video data (DATA) from the host system 60 through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 50 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal (Data Enable), and a dot clock (Dot Clock). The timing controller 50 generates timing control signals for controlling the operation timings of the data driving circuit 20 and the scan driving circuit 40 based on the timing signals. The timing control signals include a scan timing control signal GCS for controlling the operation timing of the scan driving circuit 40 and a data timing control signal DCS for controlling the operation timing of the data driving circuit 20. [ The timing controller 50 outputs the scan timing control signal GCS to the scan drive circuit 40 and the data timing control signal DCS to the data drive circuit 20. [

The scan timing control signal GCS includes a gate start pulse, a gate shift clock, and a gate output enable signal (Gate Output Enable). The gate start pulse controls the timing of the first gate pulse. The gate shift clock is a clock signal for shifting the gate start pulse. The gate output enable signal controls the output timing of the scan driving circuit 40.

The data timing control signal DCS includes a source start pulse, a source sampling clock, a source output enable signal, and the like. The source start pulse controls the starting point of data sampling of the source drive ICs. The source sampling clock is a clock signal that controls the sampling operation of the source drive ICs based on the rising or falling edge. If digital video data (DATA) to be input to the source drive ICs is transmitted in the mini LVDS (Low Voltage Differential Signaling) interface specification, the source start pulse and the source sampling clock may be omitted. The source output enable signal controls the output timing of the source drive ICs.

2 is a block diagram showing the source drive IC. 2, the source driver IC includes a data register 121, a shift register 122, a two-line latch 123, a digital-to-analog converter (DAC) 124, an output circuit 125, .

The data register 121 converts the digital video data (DATA) received from the timing controller 50 into parallel data and supplies the parallel data to the 2-line latch 123. The shift register 122 sequentially shifts the sampling clock by shifting the source start pulse SSP to match the source sampling clock SSC. The 2-line latch 123 samples the digital video data DATA input from the data register 121 on the basis of the sampling clocks sequentially input from the shift register 122 and outputs the low logic of the source output enable signal SOE And outputs the latched data simultaneously with the two-line latch of the other source drive ICs in response to the voltage. The DAC 124 receives the gamma voltage from the gamma voltage generating circuit 30 and converts the digital video data DATA input from the two-line latch 123 into an analog data voltage using the gamma voltage. For example, when 8 bits of digital video data (DATA) are supplied, the digital video data (DATA) is represented by 256 data having the 0th to 255th gray levels (G0 to G255) . In this case, the DAC 124 receives the 0th to 255th gamma voltages (V0 to V255) from the gamma voltage generating circuit 30 and receives 256 gamma voltages V0 to V255 corresponding to the values of the digital video data DATA, V255). The output circuit 125 provides a data voltage to the data lines via an output buffer in response to the low logic voltage of the source output enable signal SOE.

3 is a block diagram schematically showing a gamma voltage generating circuit. 3, the gamma voltage generating circuit 30 includes a reference luminance controller 131, a maximum luminance controller 132, a minimum and a maximum gradation gamma voltage selector 133, a tap voltage output unit 134, Circuit 135. [

The reference luminance controller 131 controls the maximum luminance voltage and the minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel 10. [ For example, the set maker can control the maximum luminance voltage using the reference luminance controller 131 to adjust the maximum luminance of the display panel 10 from 600 nits to 400 nits as shown in Fig. In addition, the set maker can control the minimum luminance voltage using the reference luminance controller 131 to adjust the minimum luminance of the display panel 10 to 0 nit. Since the driving TFT of the pixel of the present invention is formed of a P-type MOSFET, power consumption can be reduced as the minimum luminance voltage is lowered. Accordingly, the present invention is advantageous in that power consumption can be reduced by adjusting the minimum luminance voltage to a minimum by using the reference luminance controller 131. [

The maximum luminance controller 132 analyzes the average picture level (APL) per one frame period and controls the maximum luminance voltage according to the analyzed average picture level APL. The average image level APL can be calculated from the average image level analyzing unit 70 as shown in FIG. The average picture level analyzing unit 70 receives the digital video data DATA from the host system 60 and calculates the luminance and color difference information YCbCr from the digital video data DATA and then outputs the luminance information Y To calculate an average image level APL. The average picture level analyzing unit 70 outputs the average picture level APL to the maximum luminance control unit 132 of the gamma voltage generating circuit 30. [

Referring to FIG. 5, the average image level analyzing unit 70 includes a luminance and chrominance information calculating unit 171 and an average image level calculating unit 172. The luminance and chrominance information calculation unit 171 calculates luminance and chrominance information YCbCr from the digital video data (DATA) as shown in Equations (1) to (3).

In Equations (1) to (3), R means red data, G means green data, and B means blue data. The red data R, the green data G and the blue data B are represented by the 0 th to 255 th gradations when the digital video data DATA is input with 8 bits of data.

The average image level calculating section 172 calculates the average image level APL by averaging the sum of the luminance information Y calculated by the luminance and chrominance information calculating section 171. [ That is, the average picture level APL means a luminance average value in one frame period. The maximum luminance control section 132 receives the average image level APL from the average image level calculating section 172 and outputs the maximum luminance when the average image level APL is high and outputs the maximum luminance when the average image level APL is low The maximum luminance is output at a low level. Thus, the present invention can reduce power consumption.

The lowest and highest gradation gamma voltage selector 133 divides the maximum luminance voltage and the minimum luminance voltage and then selects and outputs the lowest gradation gamma voltage and the maximum gradation gamma voltage. The lowest and highest gradation gamma voltage selector 133 selects and outputs the 0th gradation gamma voltage V0 and the first gradation gamma voltage V1 which are the lowest gray level. The lowest and highest gradation gamma voltage selector 133 also selects and outputs the 255th gradation gamma voltage V255 which is the highest gradation.

The voltage dividing circuit 135 divides the lowest gradation gamma voltage and the highest gradation gamma voltage using a resistor string (R-string) to output the 0th to 255th gamma voltages (V0 to V255). That is, the voltage dividing circuit 135 divides the 0th, 1st, and 255th gradation gamma voltages (G0, G1, G255) to output the 0th to 255th gamma voltages (V0 to V255). The voltage dividing circuit 135 includes first to hth (h is a natural number) voltage dividing circuit. For example, when the organic light emitting diode display device includes R pixels (R), G pixels (G), and B pixels (B), the voltage dividing circuit 135 is divided into R (Red) voltage dividing circuits 135a ), A G (Green) voltage dividing circuit 135b, and a B (Blue) voltage dividing circuit 135c.

The tap voltage output section 134 supplies a plurality of tap voltages to the voltage dividing circuit 135. The tap voltage is a voltage that serves as a reference of the partial pressure of the voltage divider circuit 135. The tap voltage output section 134 includes first through h-th tap voltage output sections. For example, the tap voltage output unit 134 may include an R tap voltage output unit 134a, a G tap voltage output unit 134b, and a B tap voltage output unit 134c as shown in FIG. The voltage dividing circuit 135 divides the 0th, 1st, and 255th gradation gamma voltages (G0, G1, G255) and the plurality of tap voltages when a plurality of tap voltages are supplied to divide the 0th to 255th gamma voltages V0 To V255.

When the organic light emitting diode display device includes R pixels (R), G pixels (G), and B pixels (B), the R pixel (R), G pixel The R data voltage supplied to the R pixel R, the G data voltage supplied to the G pixel G, and the B data voltage supplied to the B pixel B need to be controlled differently do. Referring to FIG. 6, since the luminous efficiency of the G pixel G is highest and the luminous efficiency of the B pixel B is the lowest, the B data voltage must be larger than the R data voltage and the G data voltage in order to express the same gradation , The R data voltage must be greater than the G data voltage. Therefore, since the gamma voltage for generating the R data voltage, the gamma voltage for generating the G data voltage, and the gamma voltage for generating the B data voltage must be different, the tap voltage output portion 134 and the voltage dividing circuit 135 The R gamma voltage is output using the R tap voltage output portion 134a and the R voltage dividing circuit 135a and the G gamma voltage is output using the G tap voltage output portion 134b and the G voltage dividing circuit 135b, And outputs the B gamma voltage using the B tap voltage output portion 134c and the B voltage divider circuit 135c.

In the embodiment of the present invention, the organic light emitting diode display device includes R pixel (R), G pixel (G), and B pixel (B), and the voltage dividing circuit 135 includes an R voltage dividing circuit 135a, Tap tap voltage output section 134b and a B tap voltage circuit section 135c. Tap voltage output section 134 includes R tap voltage output section 134a, G tap voltage output section 134b, and B tap tap voltage output section 134c. It should be noted that the present invention is not limited thereto. When the organic light emitting diode display includes first to hth color pixels, the voltage dividing circuit 135 includes first to hth voltage dividing circuits, and the tap voltage outputting unit 134 includes first to fourth tap And a voltage output unit. It should be noted that the first through h-th color pixels may be implemented in any known pixel form such as an RGB pixel, an RGBW pixel, and an RGBYCM pixel. However, the first to h-th gamma voltages output from the gamma voltage generating circuit will vary depending on the luminous efficiency of the first to h-th color pixels as shown in FIG.

7 is a circuit diagram showing the gamma voltage generating circuit in detail. 7, the reference luminance controller 131, the maximum luminance controller 132, the lowest and highest gradation gamma voltage selector 133, the tap voltage output unit 134, And the voltage dividing circuit 135 will be described in detail. In FIG. 7, the R tap voltage output section 134a and the R voltage dividing circuit 135a are mainly described. However, the G tap voltage output section 134b and the B tap voltage output section 134c are substantially the same as the R tap voltage output section 134a, and the G voltage divider circuit 135b, the B voltage divider circuit 135c, Is substantially the same as the description of the R voltage dividing circuit 135a.

7, the reference luminance controller 131 includes a first maximum luminance voltage selector 131a, a minimum luminance voltage selector 131b, first and second resistance strings R1 and R2, And a luminance voltage selection unit 131c.

The first maximum luminance voltage selector 131a includes a first multiplexer MUX1 and an output buffer B. [ The first multiplexer MUX1 receives the first maximum luminance voltage selection signal Smax1 and outputs i (i is a natural number equal to or greater than 2) output from the first resistor row R1 in accordance with the first maximum luminance voltage selection signal Smax1. ) Voltage is outputted as the first maximum luminance voltage (Vmax1). The first resistor row R1 divides the first reference voltage REF1 and the low potential voltage VSS to output i voltages. The output buffer B serves as a voltage follower. In FIG. 7, although the output buffer B has been described as being implemented by an operational amplifier (op-amp), it should be noted that it is not limited thereto. As a result, the set vendor can vary the first maximum luminance voltage Vmax1 by adjusting the first maximum luminance voltage selection signal Smax1 input to the first maximum luminance voltage selector 131a.

The minimum luminance voltage selection unit 131b includes an operational amplifier op-amp and a variable resistor VR. The variable resistor VR receives the minimum luminance voltage selection signal Smin and is selected as one of resistance values j (j is a natural number of 2 or more) according to the minimum luminance voltage selection signal Smin. The operational amplifier op-amp amplifies the voltage difference between the second reference voltage REF2 input to the first terminal and the voltage variable according to the resistance value of the variable resistor VR input to the second terminal at a predetermined compensation ratio And outputs it. As a result, the set vendor can vary the minimum luminance voltage Vmin by adjusting the minimum luminance voltage selection signal Smin input to the minimum luminance voltage selection unit 131b.

The second maximum luminance voltage selection unit 131c includes a second multiplexer MUX2 and an output buffer B. [

The second resistor row R2 divides the minimum luminance voltage Vmin and the first maximum luminance voltage Vmax1 to output k (k is a natural number of 2 or more) voltages. The second multiplexer MUX2 receives the second maximum luminance voltage selection signal Smax2 and receives from the second resistor row R2 a voltage of 1 (1 is a natural number satisfying 2? L? K) Receive input. The second multiplexer MUX2 outputs any one of the 1 voltages according to the second maximum luminance voltage selection signal Smax2 as the second maximum luminance voltage Vmax2. The output buffer B serves as a voltage follower. As a result, the set vendor can vary the second maximum luminance voltage Vmax2 by adjusting the second maximum luminance voltage selection signal Smax2 input to the second maximum luminance voltage selection unit 131c.

The set maker can vary the first and second maximum luminance voltages Vmax1 and Vmax2 and the minimum luminance voltage Vmin by using the reference luminance controller 131 so that the maximum luminance of the display panel 10 The minimum luminance can be varied.

The maximum luminance control section 132 includes a look-up table (LUT), third and fourth multiplexers MUX3 and MUX4, and an output buffer B. [

The look-up table LUT receives the average picture level APL as an input address and outputs the third maximum luminance voltage selection signal Smax3 stored at the input address to the third multiplexer MUX3. The third multiplexer MUX3 receives the enable signal Se for determining whether to control the third maximum luminance voltage Vmax3 output from the maximum luminance controller 132 according to the average picture level. The third multiplexer MUX3 selects one of the third maximum luminance voltage selection signal Smax3 and the fourth maximum luminance voltage selection signal Smax4 output from the look-up table LUT according to the enable signal Se Select the signal. The fourth maximum luminance voltage selection signal Smax4 is a signal for selecting the third maximum luminance voltage Vmax3 when the third maximum luminance voltage Vmax3 is not controlled according to the average picture level. Therefore, the third multiplexer MUX3 outputs the third maximum luminance voltage selection signal Smax3 when applying the average picture level, and outputs the fourth maximum luminance voltage selection signal Smax4 when the average picture level is not applied do.

The third resistor row R3 divides the minimum luminance voltage Vmin and the second maximum luminance voltage Vmax2 to output m (m is a natural number of 2 or more) voltages. The fourth multiplexer MUX4 receives the third or fourth maximum luminance voltage selection signal Smax3 / Smax4 from the third multiplexer MUX3 and receives n of the m voltages from the third resistor row R3 Lt; = m < = m). The third multiplexer MUX3 outputs any one of the n voltages according to the third or fourth maximum luminance voltage selection signal Smax3 / Smax4 as the third maximum luminance voltage Vmax3. The output buffer B serves as a voltage follower. As a result, the present invention can vary the third maximum luminance voltage Vmax3 by analyzing the average picture level every one frame period and adjusting the third maximum luminance voltage selection signal Smax3 according to the average picture level. As a result, the present invention can reduce power consumption.

The lowest and highest gradation gamma voltage selector 133 is connected to the 0th gradation gamma voltage selector 133a, the 1st gradation gamma voltage selector 133b, the 255th gradation gamma voltage selector 133c, (R4).

The fourth resistor row R4 divides the minimum luminance voltage Vmin and the third maximum luminance voltage Vmax3 to output p (p is a natural number of 2 or more) voltages. Each of the 0th gradation gamma voltage selection unit 133a, the 1st gradation gamma voltage selection unit 133b and the 255th gradation gamma voltage selection unit 133c includes a fifth multiplexer MUX5 and an output buffer B . The fifth multiplexer MUX5 receives the rth gradation gamma voltage selection signal Svr and inputs voltages of q (q is a natural number satisfying 2? P? Q) among the p number of voltages in the fourth resistor row R4 Receive. The fifth multiplexer MUX5 outputs any one of the q voltages according to the rth gradation gamma voltage selection signal Svr as the rth gradation gamma voltage Vr. For example, the fifth multiplexer MUX5 of the 0th gradation gamma voltage selecting section 133a receives the 0th gradation gamma voltage selecting signal Sv0 and outputs q voltage . The fifth multiplexer MUX5 outputs any one of q voltages according to the 0 < th > gradation gamma voltage selection signal Sv0 to the 0 < th > gradation gamma voltage V0. The output buffer B serves as a voltage follower. On the other hand, the q voltages input to the fifth multiplexer MUX5 of the 0-th gradation gamma voltage selection unit 133a, the first gradation gamma voltage selection unit 133b, and the 255th gradation gamma voltage selection unit 133c are It can be a different voltage.

The R tap voltage output section 134a includes first to s (tap number) s (n is a natural number) tap voltage selection section. 7, the R tap voltage output unit 134a includes the first to fifth tap voltage selectors 210, 220, 230, 240 and 250, but it should be noted that the R tap voltage output unit 134a is not limited thereto.

The taps voltage selection unit includes a fifth resistor row R5, a sixth multiplexer MUX6, and an output buffer B (t is a natural number satisfying 1? T? S). The fifth resistor row R5 divides the output voltage of the first gradation gamma voltage V1 or the output voltage of the t-1th tap voltage selector and the output voltage of the (t + 1) th tap voltage selector or the 255th gradation gamma voltage V255 And u (u is a natural number of 2 or more) voltages. The sixth multiplexer MUX6 receives the t-tap voltage selection signal Stt and outputs any one of the u voltages output from the fifth resistor row R5 according to the t-tap voltage selection signal Stt R voltage dividing circuit 135a. For example, the sixth multiplexer MUX6 of the first tap voltage selector 210 receives the first tap voltage selection signal St1 and outputs the fifth tap voltage selection signal St1 according to the first tap voltage selection signal St1. R voltage dividing circuit 135a to any one of the u voltages outputted from the R voltage dividing circuit 135a. The fifth resistor row R5 divides the first gradation gamma voltage V1 and the output voltage of the second tap voltage selector 220 and outputs u voltages. The output buffer B serves as a voltage follower.

The R voltage dividing circuit 135a receives the 0th gradation gamma voltage V0, the first gradation gamma voltage V1 and the 255th gradation gamma voltage V255 from the lowest and highest gradation gamma voltage selector 133. The R voltage dividing circuit 135a receives the first through the s tap voltages Vtap1 through Vtaps from the R tap voltage output section 134a. The R voltage dividing circuit 135a divides the 0th gradation gamma voltage V0, the 1st gradation gamma voltage V1, the 255th gradation gamma voltage V255 and the 1st through the s tap voltages Vtap1 through Vtaps into a resistance column To output the 0th to 255th gradation gamma voltages (V0 to V255). 7, the R tap voltage output unit 134a has been described mainly on the output of the first to fifth tap voltages Vtap1, Vtap2, Vtap3, Vtap4, and Vtap5, but it should be noted that the R tap voltage output unit 134a is not limited thereto.

On the other hand, each of the first to s-tap voltages (Vtap1 to Vtaps) is a voltage that serves as a reference for dividing the R divided voltage circuit 135a. For example, as shown in FIG. 7, the R voltage dividing circuit 135a divides the first gray-scale gamma voltage V1 and the first tap voltage Vtap1 by using the resistance string to generate the second through fourteenth gray- V14). 7, the first tap voltage Vtap1 is output as the 15th gradation gamma voltage V15, the second tap voltage Vtap2 is output as the 31st gradation gamma voltage V31, Vtap3 is output as the 63rd gradation gamma voltage V63 and the fourth tap voltage Vtap4 is output as the 127th gradation gamma voltage V127 and the fifth tap voltage Vtap5 is output as the 191st gradation gamma voltage V191 ). However, it should be noted that the present invention is not limited to this.

As a result, since the luminous efficiency of the R pixel (R), the G pixel (G), and the B pixel (B) are different from each other, the tap voltage output section 134 and the voltage divider circuit 135 are used to drive the R pixel R, the G pixel G, and the B pixel B can be controlled differently. As a result, the present invention can adjust the color coordinates of the light generated by the light emission of the R pixel, the G pixel, and the B pixel.

On the other hand, the first to fourth maximum luminance voltage selection signals Smax1, Smax2, Smax3 and Smax4, the minimum luminance voltage selection signal Smin, the 0th gradation gamma voltage selection signal Sv0, Sv1), the 255th gradation gamma voltage selection signal Sv255, and the first through nth tap voltage selection signals St1 through Stn are designed so that they can be arbitrarily selected by the set maker. For example, the first to fourth maximum luminance voltage selection signals Smax1, Smax2, Smax3 and Smax4, the minimum luminance voltage selection signal Smin, the 0th gradation gamma voltage selection signal Sv0, The signal Sv1, the 255th gradation gamma voltage selection signal Sv255, and the 1st to the s tap voltage selection signals St1 to Sts can be designed by the set maker to be selected by the switch.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 20: data driving circuit
30: gamma voltage generating circuit 40: scan driving circuit
50: timing controller 60: host system
70: average picture level analysis unit 121: data register
122: shift register 123: two-line latch
124: DAC 125: Output circuit
131: reference brightness controller 132: maximum brightness controller
133: Lowest and highest gradation gamma voltage selector
134: tap voltage output section 135: voltage divider circuit

Claims (15)

A reference luminance controller for controlling the maximum luminance voltage and the minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel;
A minimum and a maximum gradation gamma voltage selector for dividing the maximum luminance voltage and the minimum luminance voltage and selecting and outputting the lowest gradation gamma voltage and the maximum gradation gamma voltage; And
And a voltage dividing circuit for dividing the lowest gradation gamma voltage and the highest gradation gamma voltage to output a plurality of gamma voltages,
Wherein the reference brightness controller comprises:
A first resistance string for dividing the first reference voltage and the low potential voltage and outputting i (i is a natural number of 2 or more) voltages;
A first maximum luminance voltage selector including a first multiplexer for outputting one of the i voltages to a first maximum luminance voltage according to a first maximum luminance voltage selection signal;
A minimum luminance voltage selection unit for amplifying a voltage difference between voltages varying according to a resistance value of a variable resistor varying according to a second reference voltage and a minimum luminance voltage selection signal at a predetermined compensation ratio and outputting the amplified voltage as a minimum luminance voltage;
A second resistance column for dividing the first maximum luminance voltage and the minimum luminance voltage and outputting k (k is a natural number of 2 or more) voltage; And
(1 " l < = l < k) among the k voltages from the second resistance series, and selects one of the l voltages according to the second maximum luminance voltage selection signal as a second And a second multiplexer for outputting the maximum luminance voltage at a maximum luminance voltage. delete The method according to claim 1,
A maximum luminance controller for adjusting a maximum luminance voltage from the reference luminance controller according to an average picture level analyzed every one frame period; And
Further comprising a tap voltage outputting section for supplying a plurality of tap voltages to the voltage dividing circuit as a reference for dividing the voltage of the voltage dividing circuit in addition to the lowest gradation gamma voltage and the highest gradation gamma voltage. The method of claim 3,
Wherein the maximum luminance controller comprises:
A look-up table which receives the average picture level as an input address and outputs a value stored in the input address as a third maximum luminance voltage selection signal;
A third maximum luminance voltage selection signal and a fourth maximum luminance voltage selection signal according to an enable signal for determining whether to control the third maximum luminance voltage outputted from the maximum luminance control unit according to the average picture level, A third multiplexer for selecting a second multiplexer;
A third resistance string for dividing the second maximum luminance voltage and the minimum luminance voltage and outputting m (m is a natural number of 2 or more) voltages; And
(N is a natural number satisfying 2? N? M) out of the m number of voltages from the third resistance series, and selects one of the n voltages according to the third or fourth maximum luminance voltage selection signal And a fourth multiplexer for outputting one at a third maximum luminance voltage,
Wherein the fourth maximum luminance voltage selection signal is a signal for selecting the third maximum luminance voltage when the third maximum luminance voltage is not controlled according to the average picture level. 5. The method of claim 4,
Wherein the minimum and maximum gradation gamma voltage selection unit comprises:
A fourth resistor string for dividing the third maximum luminance voltage and the minimum luminance voltage and outputting p (p is a natural number of 2 or more) voltages;
(Q is a natural number satisfying 2? Q? P) among the p voltages from the fourth resistance series, and selects any one of the q voltages according to the r-gradation gamma voltage selection signal as the r And a fifth multiplexer for outputting the gray-scale gamma voltage,
Wherein the r is 0, 1, or 255 when the digital video data is 8 bits. 6. The method of claim 5,
Wherein the voltage dividing circuit includes first to h-th (h is a natural number) voltage dividing circuit,
Wherein each of the first to h < th >
The 0th to 255th gradation gamma voltages are output by dividing the 0th gradation gamma voltage, the 1st gradation gamma voltage, the 255th gradation gamma voltage, and the 1st through the s (s is a natural number) And a gamma voltage generating circuit. The method according to claim 6,
Wherein the tap voltage output unit includes first to h-th tap voltage output units for outputting tap voltages to be supplied to the first to h-th voltage dividing circuits, respectively,
Each of the first through h-th tap voltage output units includes s (s is a natural number) tap voltage selectors,
(T is a natural number satisfying 1? T? S)
(U is a natural number of 2 or more) voltages by dividing the output voltage of the first tone gamma voltage or the t-1 tap voltage selection unit and the output voltage of the t + 1 tap voltage selection unit or the 255th tone gamma voltage 5 resistance heat; And
And a sixth multiplexer with any one of said u voltages as a t-tap voltage according to a t-tap voltage selection signal. A display panel on which data lines and scan lines are formed;
A data driving circuit for converting the digital video data into an analog data voltage using a gamma voltage and supplying the data voltage to the data lines;
A gate driving circuit sequentially supplying a scan pulse synchronized with the data voltage to the scan lines; And
And a gamma voltage generating circuit for supplying the gamma voltage to the data driving circuit,
The gamma voltage generating circuit includes:
A reference luminance controller for controlling the maximum luminance voltage and the minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel;
A minimum and a maximum gradation gamma voltage selector for dividing the maximum luminance voltage and the minimum luminance voltage and selecting and outputting the lowest gradation gamma voltage and the maximum gradation gamma voltage; And
And a voltage dividing circuit for dividing the lowest gradation gamma voltage and the highest gradation gamma voltage to output a plurality of gamma voltages,
Wherein the reference brightness controller comprises:
A first resistance string for dividing the first reference voltage and the low potential voltage and outputting i (i is a natural number of 2 or more) voltages;
A first maximum luminance voltage selector including a first multiplexer for outputting one of the i voltages to a first maximum luminance voltage according to a first maximum luminance voltage selection signal;
A minimum luminance voltage selection unit for amplifying a voltage difference between voltages varying according to a resistance value of a variable resistor varying according to a second reference voltage and a minimum luminance voltage selection signal at a predetermined compensation ratio and outputting the amplified voltage as a minimum luminance voltage;
A second resistance column for dividing the first maximum luminance voltage and the minimum luminance voltage and outputting k (k is a natural number of 2 or more) voltage; And
(1 " l < = l < k) among the k voltages from the second resistance series, and selects one of the l voltages according to the second maximum luminance voltage selection signal as a second And a second multiplexer for outputting the second maximum luminance voltage at a maximum luminance voltage. delete 9. The method of claim 8,
The gamma voltage generating circuit includes:
A maximum luminance controller for adjusting a maximum luminance voltage from the reference luminance controller according to an average picture level analyzed every one frame period; And
Further comprising a tap voltage output section for supplying a plurality of tap voltages as a reference for dividing the voltage of the voltage dividing circuit to the voltage dividing circuit in addition to the lowest gradation gamma voltage and the highest gradation gamma voltage. 11. The method of claim 10,
Wherein the maximum luminance controller comprises:
A look-up table which receives the average picture level as an input address and outputs a value stored in the input address as a third maximum luminance voltage selection signal;
A third maximum luminance voltage selection signal and a fourth maximum luminance voltage selection signal according to an enable signal for determining whether to control the third maximum luminance voltage outputted from the maximum luminance control unit according to the average picture level, A third multiplexer for selecting a second multiplexer;
A third resistance string for dividing the second maximum luminance voltage and the minimum luminance voltage and outputting m (m is a natural number of 2 or more) voltages; And
(N is a natural number satisfying 2? N? M) out of the m number of voltages from the third resistance series, and selects one of the n voltages according to the third or fourth maximum luminance voltage selection signal And a fourth multiplexer for outputting one at a third maximum luminance voltage,
And the fourth maximum luminance voltage selection signal is a signal for selecting the third maximum luminance voltage when the third maximum luminance voltage is not controlled according to the average picture level. 12. The method of claim 11,
Wherein the minimum and maximum gradation gamma voltage selection unit comprises:
A fourth resistor string for dividing the third maximum luminance voltage and the minimum luminance voltage and outputting p (p is a natural number of 2 or more) voltages;
(Q is a natural number satisfying 2? Q? P) among the p voltages from the fourth resistance series, and selects any one of the q voltages according to the r-gradation gamma voltage selection signal as the r And a fifth multiplexer for outputting the gray-scale gamma voltage,
And r is 0, 1, or 255 when the digital video data is 8 bits. 13. The method of claim 12,
Wherein the voltage dividing circuit includes first to h-th (h is a natural number) voltage dividing circuit,
Wherein each of the first to h < th >
The 0th to 255th gradation gamma voltages are output by dividing the 0th gradation gamma voltage, the 1st gradation gamma voltage, the 255th gradation gamma voltage, and the 1st through the s (s is a natural number) And an organic light emitting diode (OLED) display device. 14. The method of claim 13,
Wherein the tap voltage output unit includes first to h-th tap voltage output units for outputting tap voltages to be supplied to the first to h-th voltage dividing circuits, respectively,
Each of the first through h-th tap voltage output units includes s (s is a natural number) tap voltage selectors,
(T is a natural number satisfying 1? T? S)
(U is a natural number of 2 or more) voltages by dividing the output voltage of the first tone gamma voltage or the t-1 tap voltage selection unit and the output voltage of the t + 1 tap voltage selection unit or the 255th tone gamma voltage 5 resistance heat; And
And a sixth multiplexer with any one of the u voltages as a t-tap voltage according to a t-tap voltage selection signal. 11. The method of claim 10,
Further comprising an average picture level analyzing unit for calculating luminance and chrominance information from the digital video data and then averaging the sum of the luminance information to calculate the average picture level and outputting the average picture level to the maximum luminance control unit And an organic light emitting diode (OLED) display device.

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