KR20130068547A - Gamma voltage generation circuit and organic light emitting diode display device including the same - Google Patents

Abstract

PURPOSE: A gamma voltage generation circuit and an organic light emitting diode display device including the same are provided to reduce power consumption by varying a maximum brightness voltage according to an average picture level. CONSTITUTION: A standard brightness controller(131) controls a maximum brightness voltage and a minimum brightness voltage in order to control the maximum brightness and minimum brightness of a display panel. A minimum and maximum gradation gamma voltage selection unit(133) selects and outputs a minimum gradation gamma voltage and a maximum gradation gamma voltage after dividing the maximum brightness voltage and the minimum brightness voltage. A voltage dividing circuit outputs multiple gamma voltages by dividing the minimum gradation gamma voltage and the maximum gradation gamma voltage.

Description

GAMMA VOLTAGE GENERATION CIRCUIT AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a gamma voltage generator circuit and an organic light emitting diode display device including the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been used . Among the flat panel display devices, the organic light emitting diode display device is capable of low voltage driving, is thin, has excellent viewing angles, and has a fast response speed. An active matrix type organic light emitting diode display device in which a plurality of pixels are arranged in a matrix form to display an image is widely used in organic light emitting diode display devices.

The display panel of the OLED display device receives a scan signal from a scan driver circuit and receives a data voltage from the data driver circuit to display an image. In this case, the data driving circuit converts digital video data input from a timing controller into an analog data voltage using the gamma voltage output from the gamma voltage generating circuit.

On the other hand, the conventional gamma voltage generation circuit cannot vary the maximum luminance voltage and the minimum luminance voltage output from the reference luminance control unit. Therefore, a module maker for manufacturing a display panel is required to design a TV, monitor, notebook, mobile phone, etc. It is inconvenient to set the maximum brightness voltage and the minimum brightness voltage of the reference brightness control part after setting the maximum brightness and the minimum brightness of the display panel through pre-coordination with the set maker who assembles the information equipment. In addition, in the conventional gamma voltage generation circuit, the maximum luminance voltage and the minimum luminance voltage output from the reference luminance controller cannot be changed. Therefore, the design of the driving TFT (thin film transistor) of the organic light emitting diode display device must be changed so that the maximum luminance of the display panel can be achieved. There is an inconvenience of changing the minimum luminance.

The present invention provides a gamma voltage generator circuit capable of varying a maximum luminance voltage and a minimum luminance voltage output from a reference luminance controller and a display device including the same.

A gamma voltage generation circuit according to an exemplary embodiment of the present invention includes a reference luminance controller controlling a maximum luminance voltage and a minimum luminance voltage to adjust the maximum luminance and the minimum luminance of a display panel; A minimum and maximum gray gamma voltage selector configured to select and output a minimum gray gamma voltage and a maximum gray gamma voltage after dividing the maximum luminance voltage and the minimum luminance voltage; And a voltage dividing circuit for dividing the lowest gray level gamma voltage and the highest gray level gamma voltage to output a plurality of gamma voltages.

According to an exemplary embodiment, a display device includes: a display panel on which data lines and scan lines are formed; A data driving circuit converting digital video data into an analog data voltage using a gamma voltage and supplying the data voltage to the data lines; A gate driving circuit sequentially supplying scan pulses synchronized with the data voltages to the scan lines; And a gamma voltage generator circuit for supplying the gamma voltage to the data driver circuit, wherein the gamma voltage generator circuit controls the maximum luminance voltage and the minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel. A reference luminance controller; A minimum and maximum gray gamma voltage selector configured to select and output a minimum gray gamma voltage and a maximum gray gamma voltage after dividing the maximum luminance voltage and the minimum luminance voltage; And a voltage divider circuit for dividing the lowest gray level gamma voltage and the highest gray level gamma voltage to output a plurality of gamma voltages.

The present invention can vary the maximum luminance voltage and the minimum luminance voltage output from the reference luminance controller of the gamma voltage generation circuit. As a result, the present invention enables the set maker to adjust the maximum and minimum luminance by changing the maximum and minimum luminance voltages of the reference luminance control unit.

Further, the present invention can analyze the average image level every frame period and vary the maximum luminance voltage according to the average image level. As a result, the present invention can reduce power consumption.

Furthermore, the present invention can control gamma voltages of R pixels, G pixels, and B pixels having different luminous efficiencies differently. As a result, the present invention can adjust the color coordinates of light produced by the light emission of the R pixel, the G pixel, and the B pixel.

1 is a block diagram schematically illustrating an organic light emitting diode display as an example of a display device according to an exemplary embodiment of the present invention.
2 is a block diagram showing a source drive IC.
3 is a block diagram schematically illustrating a gamma voltage generation circuit.
4 is a diagram illustrating a maximum luminance and a minimum luminance of a display device according to an exemplary embodiment of the present invention.
5 is a block diagram schematically illustrating an average image level analyzer.
FIG. 6 is a view showing luminous efficiency according to gray levels of an R organic light emitting diode, a G organic light emitting diode, and a B organic light emitting diode.
7 is a circuit diagram showing a gamma voltage generating circuit in detail.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

1 is a block diagram schematically illustrating an organic light emitting diode display as an example of a display device according to an exemplary embodiment of the present invention. Referring to FIG. 1, an organic light emitting diode display according to an exemplary embodiment of the present invention may include a display panel 10, a data driving circuit 20, a gamma voltage generation circuit 30, a scan driving circuit 40, and a timing controller ( 50), host system 60, and the like. The display panel 10 according to an exemplary embodiment of the present invention includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode. The display device may be implemented as one of flat panel display devices such as an organic light emitting diode (OLED). In the following embodiment, the display panel 10 is exemplified based on the organic light emitting diode device, but the present invention is not limited thereto.

The display panel 10 displays an image under the control of the timing controller 50. The display panel 10 includes upper and lower substrates. The upper substrate of the display panel 10 serves as an encapsulation substrate. In the lower substrate of the display panel 10, a pixel array in which pixels are arranged in a matrix form is formed in cell regions defined by data lines and scan lines. Each pixel of the pixel array of the display panel 10 includes at least one switching thin film transistor (TFT), a driving TFT, an organic light emitting diode device, and at least one capacitor. Each of the pixels controls the current flowing through the organic light emitting diode element by using the switching TFT and the driving TFT to display an image. On the other hand, it should be noted that the switching TFT and the driving TFT will be described below mainly formed of a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The display panel 10 may display an image in the form of bottom emission and top emission depending on the pixel structure.

The data driver circuit 20 includes a plurality of source drive ICs. The source drive ICs receive the data timing control signal DCS and the digital video data DATA from the timing controller 50. In addition, the source drive ICs are supplied with a gamma voltage supplied from the gamma voltage generation circuit 30. Source drive ICs convert digital video data (DATA) to analog data voltages using gamma voltages. The source drive ICs supply a data voltage to the data lines of the display panel 10. A detailed description of the source drive IC will be described later with reference to FIG. 2, and a detailed description of the gamma voltage generation circuit 30 will be described later with reference to FIG. 3.

The scan driving circuit 40 sequentially supplies scan pulses synchronized with the data voltage to the scan lines of the display panel 10 under the control of the timing controller 50. The scan driving circuit 40 sequentially shifts and outputs a gate start pulse supplied from the timing controller 50 according to the gate shift clock, and outputs the output of the shift register and the shift register. A level shifter for converting to a swing width suitable for driving the TFT, an output buffer, and the like.

The timing controller 50 receives digital video data DATA from the host system 60 through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 50 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a dot clock, and the like. The timing controller 50 generates timing control signals for controlling the operation timing of the data driving circuit 20 and the scan driving circuit 40 based on the timing signal. The timing control signals include a scan timing control signal GCS for controlling the operation timing of the scan driving circuit 40 and a data timing control signal DCS for controlling the operation timing of the data driving circuit 20. The timing controller 50 outputs the scan timing control signal GCS to the scan driving circuit 40, and outputs the data timing control signal DCS to the data driving circuit 20.

The scan timing control signal GCS includes a gate start pulse, a gate shift clock, a gate output enable signal, and the like. The gate start pulse controls the timing of the first gate pulse. The gate shift clock is a clock signal for shifting the gate start pulse. The gate output enable signal controls the output timing of the scan driving circuit 40.

The data timing control signal DCS includes a source start pulse, a source sampling clock, a source output enable signal, and the like. The source start pulse controls the start point of data sampling of the source drive ICs. The source sampling clock is a clock signal that controls the sampling operation of the source drive ICs based on the rising or falling edge. If the digital video data DATA to be input to the source drive ICs is transmitted using a mini LVDS (Low Voltage Differential Signaling) interface specification, the source start pulse and the source sampling clock may be omitted. The source output enable signal controls the output timing of the source drive ICs.

2 is a block diagram illustrating a source drive IC. Referring to FIG. 2, the source drive IC includes a data register 121, a shift register 122, a two line latch 123, a digital-to-analog converter (DAC) 124, an output circuit 125, and the like. Include.

The data register 121 converts the digital video data DATA received from the timing controller 50 into parallel data and supplies them to the two line latches 123. The shift register 122 sequentially generates the sampling clock by shifting the source start pulse SSP according to the source sampling clock SSC. The two-line latch 123 samples the digital video data DATA input from the data register 121 on the basis of the sampling clock sequentially input from the shift register 122 and performs low logic of the source output enable signal SOE. In response to the voltage, the latched data is output simultaneously with the two-line latch of the other source drive ICs. The DAC 124 receives the gamma voltage from the gamma voltage generation circuit 30 and converts the digital video data DATA input from the two-line latch 123 into an analog data voltage using the gamma voltage. For example, when 8 bits of digital video data DATA are supplied, the digital video data DATA is represented by 256 pieces of data having 0 to 255 gray levels G0 to G255. Can be. In this case, the DAC 124 receives the 0th to 255th gamma voltages V0 to V255 from the gamma voltage generation circuit 30, and 256 gamma voltages V0 to V1 corresponding to the values of the digital video data DATA. Output any one of V255). The output circuit 125 supplies a data voltage to the data lines through an output buffer in response to the low logic voltage of the source output enable signal SOE.

3 is a block diagram schematically illustrating a gamma voltage generation circuit. Referring to FIG. 3, the gamma voltage generation circuit 30 includes a reference luminance controller 131, a maximum luminance controller 132, a minimum and maximum gray gamma voltage selector 133, a tap voltage output unit 134, and a divided voltage. Circuit 135.

The reference luminance controller 131 controls the maximum luminance voltage and the minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel 10. For example, the set company may control the maximum luminance voltage using the reference luminance controller 131 to adjust the maximum luminance of the display panel 10 from 600 nit to 400 nit as shown in FIG. 4. In addition, the set company may control the minimum luminance voltage using the reference luminance controller 131 to adjust the minimum luminance of the display panel 10 to 0 nit. Since the driving TFT of the pixel of the present invention is formed of a P-type MOSFET, lowering the minimum luminance voltage can reduce power consumption. Therefore, the present invention has an advantage of reducing power consumption by adjusting the minimum luminance voltage to the minimum using the reference luminance controller 131.

The maximum brightness controller 132 analyzes an average picture level (APL) every frame period and controls the maximum brightness voltage according to the analyzed average picture level APL. The average image level APL may be calculated from the average image level analyzer 70 as shown in FIG. 5. The average image level analyzer 70 receives the digital video data DATA from the host system 60, calculates the luminance and the color difference information YCbCr from the digital video data DATA, and then calculates the luminance information Y. Using this, the average image level APL is calculated. The average image level analyzer 70 outputs the average image level APL to the maximum luminance controller 132 of the gamma voltage generation circuit 30.

Referring to FIG. 5, the average image level analyzer 70 includes a luminance and color difference information calculator 171 and an average image level calculator 172. The luminance and color difference information calculating unit 171 calculates the luminance and color difference information YCbCr from the digital video data DATA as shown in Equations 1 to 3 below.

In Equations 1 to 3, R denotes red data, G denotes green data, and B denotes blue data. When the digital video data DATA is input as 8 bits of data, the red data R, the green data G, and the blue data B are expressed in the 0th to 255th gray levels.

The average image level calculator 172 calculates an average image level APL by averaging the sum of the luminance information Y calculated from the luminance and the color difference information calculator 171. In other words, the average image level APL means the average luminance value in one frame period. The maximum luminance control unit 132 receives the average image level APL from the average image level calculation unit 172, outputs the maximum luminance high when the average image level APL is high, and lowers the average image level APL. If the maximum brightness is low. For this reason, the present invention can reduce power consumption.

The minimum and maximum gray gamma voltage selector 133 divides the maximum luminance voltage and the minimum luminance voltage and selects and outputs the minimum gray gamma voltage and the maximum gray gamma voltage. The lowest and highest gray gamma voltage selector 133 selects and outputs the zeroth gray gamma voltage V0 and the first gray gamma voltage V1 which are the lowest gray levels. Also, the lowest and highest gray gamma voltage selector 133 selects and outputs the 255th gray gamma voltage V255 which is the highest gray level.

The voltage dividing circuit 135 divides the minimum gray gamma voltage and the maximum gray gamma voltage by using the resistor string R-string and outputs the 0 th to 255 gamma voltages V0 to V255. That is, the voltage dividing circuit 135 divides the zeroth, first, and 255th gamma voltages G0, G1, and G255 to output the 0th to 255th gamma voltages V0 to V255. The voltage dividing circuit 135 includes first to hth (h is a natural number) voltage dividing circuit. For example, when the organic light emitting diode display device includes R pixels R, G pixels, and B pixels B, the voltage divider circuit 135 may have an R (Red) voltage divider circuit 135A as shown in FIG. 5. ), G (Green) voltage divider circuit 135B, and B (Blue) voltage divider circuit 135C.

The tap voltage output unit 134 supplies a plurality of tap voltages to the voltage dividing circuit 135. The tap voltage is a voltage serving as a voltage divider reference of the voltage dividing circuit 135. The tap voltage output unit 134 includes first to hth tap voltage output units. For example, the tap voltage output unit 134 may include an R tap voltage output unit 134A, a G tap voltage output unit 134B, and a B tap voltage output unit 134C as shown in FIG. 5. When the plurality of tap voltages are supplied, the voltage dividing circuit 135 divides the zeroth, first, and 255th gamma voltages G0, G1, and G255 from the plurality of tap voltages to form the 0th to 255th gamma voltages V0. ~ V255).

On the other hand, when the organic light emitting diode display device includes R pixels R, G pixels, and B pixels B, as shown in FIG. 6, R pixels R, G pixels, and B pixels are illustrated. Since the luminous efficiency of (B) is different, the R data voltage supplied to the R pixel R, the G data voltage supplied to the G pixel G, and the B data voltage supplied to the B pixel B should be controlled differently. do. Referring to FIG. 6, since the luminous efficiency of the G pixel G is the highest and the luminous efficiency of the B pixel B is the lowest, the B data voltage must be greater than the R data voltage and the G data voltage to express the same gray scale. R data voltage must be greater than G data voltage. Therefore, since the gamma voltage for generating the R data voltage, the gamma voltage for generating the G data voltage, and the gamma voltage for generating the B data voltage should be different, the tap voltage output unit 134 and the voltage divider circuit 135 must be different. R gamma voltage is output using the R tap voltage output unit 134A and the R voltage divider circuit 135A, and G gamma voltage is output using the G tap voltage output unit 134B and the G voltage divider circuit 135B. The B gamma voltage is output using the B tap voltage output unit 134C and the B voltage divider circuit 135C.

In an embodiment of the present invention, the organic light emitting diode display device includes an R pixel R, a G pixel G, and a B pixel B, and the voltage divider circuit 135 includes an R voltage divider circuit 135A and a G voltage divider circuit. 135B, and a B voltage divider circuit 135C, wherein the tap voltage output section 134 includes an R tap voltage output section 134A, a G tap voltage output section 134B, and a B tap voltage output section 134C. Although described based on including, it should be noted that it is not limited thereto. When the organic light emitting diode display includes pixels of the first to hth colors, the voltage dividing circuit 135 includes the first to hth voltage dividing circuits, and the tap voltage output unit 134 includes the first to fourth taps. It may include a voltage output unit. In addition, it should be noted that the pixels of the first to hth colors may be implemented in any known pixel form such as RGB pixels, RGBW pixels, and RGBYCM pixels. However, the first to h-th gamma voltages output by the gamma voltage generation circuit will vary depending on the luminous efficiency of the pixels of the first to h-th colors as shown in FIG. 6.

7 is a circuit diagram illustrating a gamma voltage generation circuit in detail. Hereinafter, referring to FIG. 7, the reference luminance controller 131, the maximum luminance controller 132, the minimum and maximum gray gamma voltage selection unit 133, the tap voltage output unit 134, and the gamma voltage generation circuit 30 are described with reference to FIG. 7. And each of the voltage dividing circuit 135 will be described in detail. In FIG. 7, the R tap voltage output unit 134a and the R voltage divider circuit 135a are described. However, the G tap voltage output unit 134b and the B tap voltage output unit 134c are substantially the same as the descriptions of the R tap voltage output unit 134a, and the G voltage divider circuit 135b and the B voltage divider circuit 135c are provided. Is substantially the same as the description of the R voltage dividing circuit 135a.

Referring to FIG. 7, the reference luminance controller 131 includes a first maximum luminance voltage selector 131a, a minimum luminance voltage selector 131b, first and second resistor strings R1 and R2, and a second maximum. A luminance voltage selector 131c is included.

The first maximum luminance voltage selector 131a includes a first multiplexer MUX1 and an output buffer B. The first multiplexer MUX1 receives the first maximum luminance voltage selection signal Smax1 and outputs i from the first resistor string R1 according to the first maximum luminance voltage selection signal Smax1 (i is a natural number of 2 or more). The voltage of any one of) voltages is output as the first maximum luminance voltage Vmax1. The first resistor string R1 divides the first reference voltage REF1 and the low potential voltage VSS to output i voltages. The output buffer B serves as a voltage follower. In FIG. 7, the output buffer B is described as being implemented as an operational amplifier (op-amp), but it should be noted that the present invention is not limited thereto. As a result, the set company may vary the first maximum luminance voltage Vmax1 by adjusting the first maximum luminance voltage selection signal Smax1 input to the first maximum luminance voltage selector 131a.

The minimum luminance voltage selector 131b includes an operational amplifier op-amp and a variable resistor VR. The variable resistor VR receives a minimum luminance voltage selection signal Smin and is selected as one of j resistance values (j is a natural number of two or more) according to the minimum luminance voltage selection signal Smin. The operational amplifier op-amp amplifies a voltage difference between the second reference voltage REF2 input to the first terminal and the voltage variable according to the resistance value of the variable resistor VR input to the second terminal at a predetermined compensation ratio. To print. As a result, the set company may vary the minimum luminance voltage Vmin by adjusting the minimum luminance voltage selection signal Smin input to the minimum luminance voltage selector 131b.

The second maximum luminance voltage selector 131c includes a second multiplexer MUX2 and an output buffer B.

The second resistor string R2 divides the minimum luminance voltage Vmin and the first maximum luminance voltage Vmax1 and outputs k voltages, where k is a natural number of two or more. The second multiplexer MUX2 receives the second maximum luminance voltage selection signal Smax2 and receives l voltages (l is a natural number satisfying 2 ≦ l ≦ k) of k voltages from the second resistor string R2. Get input. The second multiplexer MUX2 outputs one of the l voltages as the second maximum luminance voltage Vmax2 according to the second maximum luminance voltage selection signal Smax2. The output buffer B serves as a voltage follower. As a result, the set company may vary the second maximum luminance voltage Vmax2 by adjusting the second maximum luminance voltage selection signal Smax2 input to the second maximum luminance voltage selector 131c.

In summary, the set company may vary the first and second maximum luminance voltages Vmax1 and Vmax2 and the minimum luminance voltage Vmin by using the reference luminance controller 131. The minimum luminance can be varied.

The maximum luminance controller 132 includes a look-up table LUT, third and fourth multiplexers MUX3 and MUX4, and an output buffer B.

The look-up table LUT receives the average image level APL as an input address, and outputs the third maximum luminance voltage selection signal Smax3 stored in the input address to the third multiplexer MUX3. The third multiplexer MUX3 receives an enable signal Se that determines whether to control the third maximum luminance voltage Vmax3 output from the maximum luminance controller 132 according to the average image level. The third multiplexer MUX3 includes one of the third maximum luminance voltage selection signal Smax3 and the fourth maximum luminance voltage selection signal Smax4 output from the look-up table LUT according to the enable signal Se. Select the signal. The fourth maximum luminance voltage selection signal Smax4 is a signal for selecting the third maximum luminance voltage Vmax3 when the third maximum luminance voltage Vmax3 is not controlled according to the average image level. Accordingly, the third multiplexer MUX3 outputs the third maximum luminance voltage selection signal Smax3 when the average image level is applied, and outputs the fourth maximum luminance voltage selection signal Smax4 when the average image level is not applied. do.

The third resistor string R3 divides the minimum luminance voltage Vmin and the second maximum luminance voltage Vmax2 and outputs m voltages (m is a natural number of two or more). The fourth multiplexer MUX4 receives the third or fourth maximum luminance voltage selection signal Smax3 / Smax4 from the third multiplexer MUX3, and n of n voltages from the third resistor string R3 is 2 Natural voltages satisfying ≤n≤m) are input. The third multiplexer MUX3 outputs one of the n voltages as the third maximum luminance voltage Vmax3 according to the third or fourth maximum luminance voltage selection signal Smax3 / Smax4. The output buffer B serves as a voltage follower. As a result, the present invention can vary the third maximum luminance voltage Vmax3 by analyzing the average image level every frame period and adjusting the third maximum luminance voltage selection signal Smax3 according to the average image level. As a result, the present invention can reduce power consumption.

The lowest and highest gray gamma voltage selector 133 may include a zeroth grayscale gamma voltage selector 133a, a first grayscale gamma voltage selector 133b, a 255th grayscale gamma voltage selector 133c, and a fourth resistor string. (R4).

The fourth resistor string R4 divides the minimum luminance voltage Vmin and the third maximum luminance voltage Vmax3 to output p (p is a natural number of 2 or more) voltages. Each of the zeroth grayscale gamma voltage selector 133a, the first grayscale gamma voltage selector 133b, and the 255th grayscale gamma voltage selector 133c includes a fifth multiplexer MUX5 and an output buffer B. FIG. . The fifth multiplexer MUX5 receives the r-th gamma voltage selection signal Svr and inputs q (q is a natural number satisfying 2 ≦ p ≦ q) of p voltages of the fourth resistor string R4. Receive. The fifth multiplexer MUX5 outputs one of q voltages as the r-th gamma voltage Vr according to the r-th gamma voltage selection signal Svr. For example, the fifth multiplexer MUX5 of the zeroth grayscale gamma voltage selector 133a receives the zeroth grayscale gamma voltage selection signal Sv0 and receives q voltages among the p voltages of the fourth resistor string R4. Receive the input. The fifth multiplexer MUX5 outputs any one of q voltages as the zeroth grayscale gamma voltage V0 according to the zeroth grayscale gamma voltage selection signal Sv0. The output buffer B serves as a voltage follower. On the other hand, q voltages input to the fifth multiplexer MUX5 of the zeroth grayscale gamma voltage selector 133a, the first grayscale gamma voltage selector 133b, and the 255th grayscale gamma voltage selector 133c are respectively. It may be different voltages.

The R tap voltage output unit 134a includes first to s th tap voltage selection units. In FIG. 7, the R tap voltage output unit 134a includes the first to fifth tap voltage selectors 210, 220, 230, 240, and 250, but the present disclosure is not limited thereto.

T (t is a natural number satisfying 1 ≦ t ≦ s) The tap voltage selector includes a fifth resistor string R5, a sixth multiplexer MUX6, and an output buffer B. The fifth resistor string R5 divides the output voltage of the first gray gamma voltage V1 or the t-1 tap voltage selector and the output voltage of the t + 1 tap voltage selector or the 255th gray gamma voltage V255. Therefore, u (u is a natural number of two or more) voltages are output. The sixth multiplexer MUX6 receives the t-th tap voltage selection signal Stt and receives any one of u voltages output from the fifth resistor string R5 according to the t-th tap voltage selection signal Stt. It outputs to the R voltage dividing circuit 135a. For example, the sixth multiplexer MUX6 of the first tap voltage selector 210 receives the first tap voltage select signal St1 and, according to the first tap voltage select signal St1, the fifth resistor string ( The voltage of any one of u voltages output from R5) is output to the R voltage divider circuit 135a. The fifth resistor string R5 divides the output voltages of the first gray gamma voltage V1 and the second tap voltage selector 220 to output u voltages. The output buffer B serves as a voltage follower.

The R voltage dividing circuit 135a receives the zeroth gray gamma voltage V0, the first gray gamma voltage V1, and the 255th gray gamma voltage V255 from the lowest and highest gray gamma voltage selector 133. The R voltage divider circuit 135a receives the first through s th tap voltages Vtap1 ˜ Vtaps from the R tap voltage output unit 134a. The R voltage dividing circuit 135a includes a zeroth gamma voltage V0, a first gray gamma voltage V1, a 255th gamma voltage V255, and a first through s-th tap voltage Vtap1 through Vtaps. By dividing by using the second to 255th gamma voltage (V0 ~ V255) is output. In FIG. 7, the R tap voltage output unit 134a has been described mainly for outputting the first to fifth tap voltages Vtap1, Vtap2, Vtap3, Vtap4, and Vtap5, but the present disclosure is not limited thereto.

On the other hand, each of the first to s-th tap voltages Vtap1 to Vtaps is a reference voltage when the R voltage dividing circuit 135a is divided. For example, as shown in FIG. 7, the R voltage dividing circuit 135a divides the first gray gamma voltage V1 and the first tap voltage Vtap1 by using a resistor string to divide the second to fourteenth gray gamma voltages V2 to 14. V14) can be generated. In addition, in FIG. 7, the first tap voltage Vtap1 is output as the fifteenth gray gamma voltage V15, the second tap voltage Vtap2 is output as the thirty-first gray gamma voltage V31, and the third tap voltage Vtap3 is output as the 63rd gray gamma voltage V63, the fourth tap voltage Vtap4 is output as the 127th gray gamma voltage V127, and the fifth tap voltage Vtap5 is the 191th gray gamma voltage V191. Note that the output is shown as), but the present invention is not limited thereto.

As a result, in the present invention, since the luminous efficiency of the R pixel R, the G pixel G, and the B pixel B is different, the R pixel (using the tap voltage output unit 134 and the voltage dividing circuit 135) is used. The gamma voltages of R, G pixels, and B pixels can be controlled differently. As a result, the present invention can adjust the color coordinates of light produced by the light emission of the R pixel, the G pixel, and the B pixel.

Meanwhile, the first to fourth maximum luminance voltage selection signals Smax1, Smax2, Smax3, and Smax4, the minimum luminance voltage selection signal Smin, the zeroth gray gamma voltage selection signal Sv0, and the first grayscale gamma voltage selection signal ( Sv1), the 255th gamma voltage selection signal Sv255, and the first to nth tap voltage selection signals St1 to Stn are designed to be arbitrarily selected by a set company. For example, the first to fourth maximum luminance voltage selection signals Smax1, Smax2, Smax3, and Smax4, the minimum luminance voltage selection signal Smin, the zeroth gray gamma voltage selection signal Sv0, and the first gray level gamma voltage selection The signal Sv1, the 255th gamma voltage selection signal Sv255, and the first to s-th tap voltage selection signals St1 to Sts may be designed to be selected by a set company by a switch.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 20: data driving circuit
30: gamma voltage generating circuit 40: scan driving circuit
50: timing controller 60: host system
70: average image level analyzer 121: data register
122: shift register 123: 2-line latch
124: DAC 125: output circuit
131: reference luminance control unit 132: maximum luminance control unit
133: lowest and highest gray gamma voltage selector
134: tap voltage output unit 135: voltage divider circuit

Claims (15)

A reference luminance controller controlling the maximum luminance voltage and the minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel;
A minimum and maximum gray gamma voltage selector configured to select and output a minimum gray gamma voltage and a maximum gray gamma voltage after dividing the maximum luminance voltage and the minimum luminance voltage; And
And a divider circuit for dividing the lowest gray level gamma voltage and the highest gray level gamma voltage to output a plurality of gamma voltages. 3. The method of claim 2,
The reference luminance control unit,
A first resistor string for dividing the first reference voltage and the low potential voltage to output i (i is two or more natural numbers) voltages;
A first maximum luminance voltage selector including a first multiplexer configured to output one of the i voltages as a first maximum luminance voltage according to a first maximum luminance voltage selection signal;
A minimum luminance voltage selector configured to amplify a voltage difference between a second reference voltage and a voltage that varies according to a resistance value of a variable resistor that is changed according to a minimum luminance voltage selection signal at a predetermined compensation ratio, and output the minimum luminance voltage;
A second resistor string for dividing the first maximum luminance voltage and the minimum luminance voltage and outputting k (k is a natural number of 2 or more) voltages; And
A voltage of l (l is a natural number satisfying 2 ≦ l ≦ k) voltages of the k voltages is input from the second resistor string, and any one of the l voltages is selected according to a second maximum luminance voltage selection signal. And a second maximum luminance voltage selector including a second multiplexer for outputting the maximum luminance voltage. 3. The method of claim 2,
A maximum luminance controller which adjusts the maximum luminance voltage from the reference luminance controller according to the average image level analyzed for each frame period; And
And a tap voltage output unit for supplying a plurality of tap voltages, which are divided voltage references of the voltage dividing circuit, to the voltage dividing circuit in addition to the minimum gray gamma voltage and the maximum gray gamma voltage. The method of claim 3, wherein
The maximum brightness control unit,
A look-up table which receives the average image level as an input address and outputs a third maximum luminance voltage selection signal based on a value stored in the input address;
Any one of the third and fourth maximum luminance voltage selection signals according to an enable signal for determining whether to control the third maximum luminance voltage output from the maximum luminance controller according to the average image level. A third multiplexer for selecting;
A third resistor string for dividing the second maximum luminance voltage and the minimum luminance voltage to output m (m is a natural number of two or more) voltages; And
N (n is a natural number satisfying 2 ≦ n ≦ m) voltages of the m voltages are input from the third resistor string, and any one of the n voltages is applied according to the third or fourth maximum luminance voltage selection signal. A fourth multiplexer for outputting one to a third maximum luminance voltage,
And the fourth maximum luminance voltage selection signal is a signal for selecting the third maximum luminance voltage when the third maximum luminance voltage is not controlled according to the average image level. The method of claim 4, wherein
The lowest and highest gray level gamma voltage selection unit,
A fourth resistor string for dividing the third maximum luminance voltage and the minimum luminance voltage to output p (p is a natural number of 2 or more) voltages;
Q (q is a natural number satisfying 2 ≦ q ≦ p) voltages of the p voltages are input from the fourth resistor string, and any one of the q voltages is set according to the r-th gamma voltage selection signal. A fifth multiplexer for outputting a gray gamma voltage,
And r is 0, 1, or 255 when the digital video data is 8 bits. The method of claim 5, wherein
The voltage dividing circuit includes first to hth (h is a natural number) voltage dividing circuit,
Each of the first to hh voltage divider circuits may include:
Outputting the 0th to 255th gamma voltage by dividing the zeroth gray gamma voltage, the first gray gamma voltage, the 255th gray gamma voltage, and the first to sth (s is a natural number) tap voltages using a resistor string. Gamma voltage generation circuit, characterized in that. The method according to claim 6,
The tap voltage output unit includes first to h-th tap voltage output units configured to output tap voltages to be supplied to each of the first to hth voltage divider circuits.
Each of the first to h-th tap voltage output parts includes s tap voltage selection parts (s is a natural number),
T (t is a natural number satisfying 1≤t≤s) Tap voltage selection unit,
Outputting u (u is a natural number of two or more) voltages by dividing the output voltage of the first gray level gamma voltage or the t-1 tap voltage selector and the output voltage of the t + 1 tap voltage selector or the 255 gray level gamma voltage 5 resistance heat; And
And a sixth multiplexer as one of the u voltages as the t-th tap voltage according to the t-th tap voltage selection signal. A display panel on which data lines and scan lines are formed;
A data driving circuit converting digital video data into an analog data voltage using a gamma voltage and supplying the data voltage to the data lines;
A gate driving circuit sequentially supplying scan pulses synchronized with the data voltages to the scan lines; And
A gamma voltage generation circuit supplying the gamma voltage to the data driving circuit,
The gamma voltage generation circuit,
A reference luminance controller controlling a maximum luminance voltage and a minimum luminance voltage to adjust the maximum luminance and the minimum luminance of the display panel;
A minimum and maximum gray gamma voltage selector configured to select and output a minimum gray gamma voltage and a maximum gray gamma voltage after dividing the maximum luminance voltage and the minimum luminance voltage; And
And a voltage dividing circuit for dividing the lowest gray level gamma voltage and the highest gray level gamma voltage to output a plurality of gamma voltages. The method of claim 8,
The reference luminance control unit,
A first resistor string for dividing the first reference voltage and the low potential voltage to output i (i is two or more natural numbers) voltages;
A first maximum luminance voltage selector including a first multiplexer configured to output one of the i voltages as a first maximum luminance voltage according to a first maximum luminance voltage selection signal;
A minimum luminance voltage selector configured to amplify a voltage difference between a second reference voltage and a voltage that varies according to a resistance value of a variable resistor that is changed according to a minimum luminance voltage selection signal at a predetermined compensation ratio, and output the minimum luminance voltage;
A second resistor string for dividing the first maximum luminance voltage and the minimum luminance voltage and outputting k (k is a natural number of 2 or more) voltages; And
A voltage of l (l is a natural number satisfying 2 ≦ l ≦ k) voltages of the k voltages is input from the second resistor string, and any one of the l voltages is selected according to a second maximum luminance voltage selection signal. And a second maximum luminance voltage selector including a second multiplexer outputting the maximum luminance voltage. The method of claim 9,
The gamma voltage generation circuit,
A maximum luminance controller which adjusts the maximum luminance voltage from the reference luminance controller according to the average image level analyzed for each frame period; And
And a tap voltage output unit configured to supply a plurality of tap voltages, which are divided voltage reference of the voltage dividing circuit, to the voltage dividing circuit in addition to the lowest gray level gamma voltage and the highest gray level gamma voltage. 11. The method of claim 10,
The maximum brightness control unit,
A look-up table which receives the average image level as an input address and outputs a third maximum luminance voltage selection signal based on a value stored in the input address;
Any one of the third and fourth maximum luminance voltage selection signals according to an enable signal for determining whether to control the third maximum luminance voltage output from the maximum luminance controller according to the average image level. A third multiplexer for selecting;
A third resistor string for dividing the second maximum luminance voltage and the minimum luminance voltage to output m (m is a natural number of two or more) voltages; And
N (n is a natural number satisfying 2 ≦ n ≦ m) voltages of the m voltages are input from the third resistor string, and any one of the n voltages is applied according to the third or fourth maximum luminance voltage selection signal. A fourth multiplexer for outputting one to a third maximum luminance voltage,
And the fourth maximum luminance voltage selection signal is a signal for selecting the third maximum luminance voltage when the third maximum luminance voltage is not controlled according to the average image level. The method of claim 11,
The lowest and highest gray level gamma voltage selection unit,
A fourth resistor string for dividing the third maximum luminance voltage and the minimum luminance voltage to output p (p is a natural number of 2 or more) voltages;
Q (q is a natural number satisfying 2 ≦ q ≦ p) voltages of the p voltages are input from the fourth resistor string, and any one of the q voltages is set according to the r-th gamma voltage selection signal. A fifth multiplexer for outputting a gray gamma voltage,
And r is 0, 1, or 255 when the digital video data is 8 bits. 13. The method of claim 12,
The voltage dividing circuit includes first to hth (h is a natural number) voltage dividing circuit,
Each of the first to hh voltage divider circuits may include:
Outputting the 0th to 255th gamma voltage by dividing the zeroth gray gamma voltage, the first gray gamma voltage, the 255th gray gamma voltage, and the first to sth (s is a natural number) tap voltages using a resistor string. An organic light emitting diode display device. The method of claim 13,
The tap voltage output unit includes first to h-th tap voltage output units configured to output tap voltages to be supplied to each of the first to hth voltage divider circuits.
Each of the first to h-th tap voltage output parts includes s tap voltage selection parts (s is a natural number),
T (t is a natural number satisfying 1≤t≤s) Tap voltage selection unit,
Outputting u (u is a natural number of two or more) voltages by dividing the output voltage of the first gray level gamma voltage or the t-1 tap voltage selector and the output voltage of the t + 1 tap voltage selector or the 255 gray level gamma voltage 5 resistance heat; And
And a sixth multiplexer having any one of the u voltages as the t th tap voltage according to the t th tap voltage selection signal. The method of claim 9,
After calculating luminance and color difference information from the digital video data, the average image level is calculated by averaging the sum of the luminance information and outputting the average image level to the maximum luminance control unit. An organic light emitting diode display device.

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