KR20200077375A - Light Emitting Display Device - Google Patents

Abstract

An objective of the present invention is to provide a technology capable of stably displaying high quality without causing any distortion of a moving image. A light emitting display device includes: a gate transistor disposed between a data line and a data holding unit to control the connection of the data line and the data holding unit; a transfer transistor disposed between the data holding unit and the gate of the driving transistor to control the connection between the data holding unit and the driving transistor; and a reset transistor disposed between the gate of the driving transistor and a second power line having a potential different from that of the first power line to control the connection between the gate of the driving transistor and the second power line, wherein after data in one frame is written to the data holding units of all the pixels, the timing at which the transfer transistor is turned on is controlled, and the data of the data holding unit is written to the gate of the reset driving transistor.

Description

Light Emitting Display Device

The present invention relates to a light emitting display device.

In a conventional active matrix display device, a pixel value is written as a voltage value for a pixel for each gate line, and the pixel display is updated line by line, that is, for each row or column.

On the other hand, an image displayed on such a display device is generally acquired by a camera equipped with an image sensor.

In the case of moving picture shooting, the shutter method is largely divided into a rolling shutter method in which pixel values are sequentially acquired, and a global shutter method in which pixel values are collectively acquired at the same time from all pixels. By using, you can accurately capture the movement of the subject.

Patent Document 1, which is an example of the prior art, discloses a technique for correcting a rolling shutter deformation with high precision with respect to imaged image data.

Patent Document 1: Japanese Patent Publication No. 2017-59998

However, even in the case of a moving image captured by the global shutter method as in the above-mentioned conventional technology, there is a problem that the displayed image is displayed with deformation and the image with deformation is perceived according to the change rate of the relative position of the camera and the subject.

The present invention has been made in light of the above, and an object of the present invention is to provide a technique capable of stably displaying high quality without causing distortion in a moving image.

The present invention to achieve the object by solving the above-described problems is a light emitting display device in which a plurality of pixels in which a driving transistor is disposed between a first power supply line and a light emitting element is arranged in a matrix, each of the plurality of pixels being data A gate transistor for controlling the connection between the line and the data holding part, a transfer transistor for controlling the connection between the data holding part and the gate of the driving transistor, and a second power supply line having a potential different from the gate of the driving transistor and the first power supply line. A reset transistor for controlling the connection is provided, and after the data in one frame is written to the data holding unit of all pixels, the timing at which the transfer transistor is turned ON is controlled, so that the gate of the reset driving transistor is controlled. It is a light emitting display device in which data of the data holding section is written.

In the light emitting display device, the timing at which the transfer transistor is turned on is the same for all the pixels, the gate of the reset driving transistor is the potential of the second power line, and the data of the data holding unit is simultaneously written in all the pixels. It is desirable to be.

In the light-emitting display device, the gate reset of the driving transistor may be performed after data in one frame is written to the data holding unit of all pixels.

Alternatively, in the light emitting display device, the gate reset of the driving transistor may be performed while data in one frame is being written to the data holding unit.

Alternatively, in the light emitting display device, the pulse width of the first pulse that turns on the gate transistor is greater than the pulse width of the second pulse that turns on the transfer transistor, and the pulse width of the second pulse is the reset transistor. It may be larger than the pulse width of the third pulse that is turned on.

Alternatively, in the light-emitting display device, the first pulse that turns on the gate transistor, the second pulse that turns on the transfer transistor, and the third pulse that turns on the reset transistor have a potential when turned ON. It may be higher than the potential of the power supply line, and the potential when turned OFF may be lower than the potential of the first power supply line.

Alternatively, in the light emitting display device, the timing at which the transfer transistor is turned on is delayed to be different between the gate lines, and the reset gate of the driving transistor may be the potential of the second power line.

Alternatively, the light emitting display device may switch between an operation mode in which the timing at which the transfer transistor is turned ON is simultaneous in all pixels and an operation mode controlled for each gate line, and the gate of the reset driving transistor is the first 2 The potential of the power supply line may be sufficient.

According to the present invention, it is possible to provide a technique capable of stably high-quality display without causing distortion in a moving image.

1 is a block diagram showing the overall configuration of a light emitting display device according to an embodiment.
FIG. 2 is a diagram showing a pixel circuit of pixels surrounded by a broken line shown in FIG. 1.
3 is a first timing chart for explaining the pixel circuit operation of the pixel illustrated in FIG. 2.
4 is a second timing chart for explaining the pixel circuit operation of the pixel illustrated in FIG. 2.
5 is a block diagram schematically showing a modification of the overall configuration of the light emitting display device according to the embodiment.

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated with reference to attached drawing.

However, this invention is not limited to interpreting by description of the following embodiment.

<Embodiment>

1 is a block diagram showing the overall configuration of a light emitting display device 10 according to the present embodiment.

The light emitting display device 10 shown in FIG. 1 includes a control unit 11, a data driver 12, a gate driver 13, a signal controller 14, a power voltage generator 15, and a matrix A plurality of pixels 100 disposed in an image is provided.

1, only a portion of the plurality of pixels 100 is extracted and illustrated in 3 rows X 3 columns, but it is assumed that more pixels are arranged than those shown in FIG.

The control unit 11 outputs a control signal for controlling the data driver 12, the gate driver 13, and the signal controller 14.

The data driver 12 is a driving circuit that outputs data signals to a plurality of data lines Data based on a control signal from the control unit 11.

In the data driver 12, for example, an RGB signal included in a control signal from the control unit 11 is input to the first latch circuit, and the output signal of the first latch circuit is gamma corrected and input to the second latch circuit. , The output signal of the second latch circuit is input to a DA (Digital to Analog) converter and outputs a data signal.

The gate driver 13 outputs a gate signal to each of a plurality of gate lines (Gate(n), Gate(n+1), Gate(n+2)) based on a control signal from the control unit 11 Is a driving circuit.

The gate driver 13 is configured to include, for example, a shift register provided with a plurality of storages.

Also, n is a natural number.

The signal control unit 14 includes a transmission signal control unit 141 and a reset signal control unit 142.

The transmission signal control unit 141 is a signal generation circuit that generates a transmission signal (Trans) for each row based on a signal from the control unit 11 and controls the timing to output it.

The reset signal control unit 142 is a signal generation circuit that generates a reset signal (Reset) for each row based on a signal from the control unit 11 and controls the timing to output it.

The power supply voltage generator 15 is a voltage control circuit in which a high voltage power supply line of the high power supply voltage V _DD and a low voltage power supply line of the low power supply voltage V _SS are connected to control these voltages.

FIG. 2 is a diagram showing a pixel circuit of a pixel 100 surrounded by a broken line shown in FIG. 1.

In the pixel 100 shown in Fig. 2, transistors 101, 102, 103, 104, which are thin film transistors (TFTs), capacitive elements 105, 106, and light emitting elements 107 are provided.

Here, the transistors 101, 102, 103, and 104 are n-type TFTs, but the present invention is not limited to this, and the pixel circuit may be constructed of p-type TFTs.

Also, the transistor 101 is a gate transistor, the transistor 102 is a transfer transistor, the transistor 103 is a driving transistor, and the transistor 104 is a reset transistor.

In addition, in FIG. 2, a high voltage power line of a data line (Data), a gate line (Gate), a transfer signal line (Trans), a reset signal line (Reset), and a first power line, a high power voltage (V _DD ), and a second A low voltage power supply line of a low power supply voltage (V _SS ), which is a power supply line, is shown.

Also, the high power supply voltage V _DD and the low power supply voltage V _SS are fixed voltages, and the high power supply voltage V _DD is greater than the low power supply voltage V _SS .

Also, FIG. 2 shows a first node N1, a second node N2, and a third node N3.

The first node N1 is a node connected to one of the source drain of the transistor 101, one of the source drain of the transistor 102, and one electrode of the capacitor 105, and is a data holding unit.

The second node N2 is a node connected to the other of the source drain of the transistor 102, the gate of the transistor 103, one of the source drain of the transistor 104, and one electrode of the capacitive element 106. to be.

The third node N3 is a node connected to one of the source drain of the transistor 103, the other electrode of the capacitive element 106, and the anode of the light emitting element 107.

The gate of the transistor 101, which is the first transistor, is connected to the gate line Gate, one of the source drain is connected to the first node N1, and the other of the source drain is connected to the data line Data.

The gate of the second transistor, the transistor 102, is connected to the transfer signal line Trans, one of the source drain is connected to the first node N1, and the other of the source drain is connected to the second node N2. .

The gate of the transistor 103, which is the third transistor, is connected to the second node N2, one of the source drain is connected to the third node N3, and the other of the source drain is the first of the high power voltage V _DD . 1 It is connected to the high voltage power supply line which is the power supply line.

The gate of the fourth transistor, the transistor 104, is connected to the reset signal line Reset, one of the source drain is connected to the second node N2, and the other of the source drain is the second of the low power supply voltage V _SS . It is connected to a low voltage power supply line which is a power supply line.

One electrode of the capacitive element 105 which is the first capacitive element is connected to the first node N1, and the other electrode is connected to the low voltage power supply line which is the second power supply line of the low power supply voltage V _SS .

One electrode of the capacitive element 106 which is the second capacitive element is connected to the second node N2, and the other electrode is connected to the third node N3.

The anode of the light emitting element 107 is connected to the third node N3, and the cathode is connected to the low voltage power supply line which is the second power supply line of the low power supply voltage V _SS .

Next, the operation of the pixel circuit shown in Fig. 2 will be described.

3 is a first timing chart for explaining the pixel circuit operation of the pixel 100 shown in FIG. 2.

In FIG. 3, the voltage of the 0th to Nth gate lines (V _Gate(i) (i=0, 1, ..., N)), the voltage of the reset signal line (V _Reset ), and the voltage of the transfer signal line (V) _Trans ) is shown.

The voltage of the gate line (V _{Gate_i} ), the voltage of the reset signal line (V _Reset ), and the voltage of the transfer signal line (V _Trans ) are all of V(L) and V(H).

In addition, the relationship between V(L) and V(H) in each wiring is V(L) <V(H).

First, as illustrated in FIG. 3, the gate driver 13 turns on the transistor 101 by sequentially outputting a gate signal from the i=0 gate line to the i=N gate line, and the pixel 100 is turned on. Data signals are written to the first node N1, which is a data holding unit installed in each.

Then, after the data signal is written to the gate line where i=N, the reset signal control unit 142 turns on the transistor 104 by outputting a reset signal to all the pixels 100, and the second installed in each of the pixels 100. The voltage of the second node N2 is set to Vss by connecting the node N2 to the low voltage power supply line.

In this way, the data of the previous frame amount held in each pixel is reset.

Next, in a state in which the second node N2 of all pixels is reset, the transfer signal control unit 141 turns on the transistor 102 by outputting the transfer signal to all the pixels 100, and the first node N1 The charge of s is simultaneously transferred from all the pixels to the second node N2.

Thereby, the transistor 103 is turned on or off according to the charge of the second node N2.

Since the voltage of the third node N3 does not change when the transistor 103 is OFF, the light emitting element 107 does not emit light.

When the transistor 103 is turned on, the voltage of the third node N3 is turned on according to the charge of the second node N2, so that the current of the second node N2 flows through the transistor 103. , The light emitting element 107 emits light according to this current.

As described above, according to FIG. 3, a gate signal is sequentially output to each gate line, a data signal is accumulated at the first node N1, and a reset signal is set for all pixels after all the gate signals for one frame are output. By outputting, all the second nodes N2 are reset, the transfer signal is output to all the pixels in the state where the second node N2 is reset, and the charge accumulated in the first node N1 is simultaneously third in all the pixels. By transmitting to the node N3, pixel display update is performed simultaneously on the entire screen.

However, the present invention is not limited to the form shown in FIG. 3, and the reset of the second node N2 does not have to be performed after all gate signals of one frame amount are output.

That is, the second node N2 may be reset at a timing written to the middle of one frame in the first node N1.

4 is a second timing chart for explaining the pixel circuit operation of the pixel 100 shown in FIG. 2.

In the timing chart shown in FIG. 4, the output timing of the gate signal and the transfer signal is the same as the timing chart shown in FIG. 3, but the output timing of the reset signal is data to the first node N1 provided in each of the pixels 100. This is when the signal is written.

Since the transistor 102 installed between the first node N1 and the second node N2 is OFF, the second node N2 while the data signal is being written to the first node N1 as shown in FIG. 4. ) May be reset.

In addition, in FIGS. 3 and 4, the pulse width of the gate signal Gate, which is the first pulse, is greater than the pulse width of the transmission signal, which is the second pulse, and the pulse width of the transmission signal Trans, which is the second pulse, is the third pulse. It may be larger than the pulse width of the reset signal Reset.

It is required to consider the timing relationship between the data signal and the gate signal when the pixel value is written to the first node N1, but the timing is the same in charge transfer from the first node N1 to the second node N2. There is no need to consider the relationship, and also, for the reset, since the source of the transistor 104 is fixed at Vss, if the source potential is the same size as that of the transistor 102 higher than Vss, the driving current is large and the operation speed is fast. to be.

In addition, the first pulse that turns on the transistor 101, the second pulse that turns on the transistor 102, and the third pulse that turns on the transistor 103 have a potential that is higher than the high power voltage V _DD when it is turned on. It may be high, and the potential at the time of OFF may be lower than the low power supply voltage V _SS .

Accordingly, the ON/OFF control of each transistor is reliably performed, the data signal is written when each transistor is turned ON, and the transfer from the first node N1 to the second node N2 is performed smoothly while each transistor is performed The leakage current when it is OFF can be reduced to suppress fluctuations in the amount of charge held in the first node N1 and the second node N2.

In addition, the transistor characteristics of the transistor 101 and the transistor characteristics of the transistor 102 are the same, and the magnitude of the voltage (V _Gate(i) (i=0, 1, ... N), which is the pulse amplitude of the gate signal, The voltage (V _Reset ), which is the pulse amplitude of the reset signal, is preferably set to the same level.

This is for setting the ON state of the transistor 101 and the ON state of the transistor 102 to the same degree.

In addition, although the light emitting display device 10 illustrated in FIG. 1 includes a transmission signal control unit 141, the present invention is not limited thereto.

Instead of the transfer signal control unit 141, a transfer signal buffer unit for delaying the transfer signal may be provided.

It is possible to suppress ground bounce by, for example, sequentially varying the delay in the transfer signal buffer unit for each gate line or for each gate line group including a plurality of gate lines.

Alternatively, the delay may be randomly changed within a time period when all the pixels appear to be ON at the same time.

Alternatively, instead of the transmission signal control unit 141, a transmission signal timing control unit that controls the timing of the transmission signal for each line may be provided.

When the timing at which the transistor 102, which is the transfer transistor is turned on, is controlled by the transfer signal timing control unit for each gate line, it is also possible to perform a video display shot by a rolling shutter method.

For example, it is possible to perform the same display as the conventional display device by turning on the transfer signal Trans after a certain period of time in which the gate signal is turned off in each pixel.

Alternatively, the operation mode in which the transmission signal control unit 141 simultaneously turns on all the pixels and the operation mode for controlling the timing of turning on the transistor 102 which is the transmission transistor like the transmission signal timing control unit for each gate line may be switchable.

When the operation mode is switchable as described above, it is possible to stably display high-quality images of a variety of moving images regardless of the method during shooting.

In addition, although the light emitting display device 10 shown in FIG. 1 outputs a transmission signal Trans and a reset signal for each row, the present invention is not limited to this.

5 is a block diagram schematically showing a modification of the overall configuration of the light emitting display device according to the present embodiment.

In the light emitting display device 10a illustrated in FIG. 5, the signal control unit 14 is disposed at the position of the power supply voltage generating unit 15 in the light emitting display device 10 illustrated in FIG. 1, and the signal control unit 14 ), the power supply voltage generator 15 is disposed, and the transfer signal Trans and the reset signal Reset are output for each column by controlling timing.

In this way, the transfer signal Trans and the reset signal Reset may be output for each column.

As described above, according to the light emitting display device according to the present embodiment, the written pixel value is temporarily held at the first node N1, and the timing at which the pixel value is written is controlled for the reset second node N2. By doing so, high-quality display can be stably performed without causing distortion in the moving image.

In particular, by making the timing at which the pixel values are written to the second node N2 at the same time in all the pixels, it is possible to stably display a high quality without causing distortion.

Further, in the light emitting display device according to the present embodiment, the pixel value is reset by the reset transistor before the pixel value is written, whereby a black display state can be inserted, and motion blur of a moving image can be reduced.

In addition, the present invention is not limited to the above-described embodiments, but also includes various modifications in which elements are added, deleted, or converted for the above-described configuration.

10, 10a: Light-emitting display device
11: Control
12: data driver
13: gate driver
14: signal control
15: power supply voltage generator
100: pixel
101, 102, 103, 104: transistor
105, 106: capacitive element
107: light emitting element
141: transmission signal control unit
142: reset signal control unit

Claims (8)

A light emitting display device in which a plurality of pixels in which driving transistors are disposed between a first power line and a light emitting element are arranged in a matrix,
Each of the plurality of pixels,
A gate transistor for controlling the connection of the data line and the data holding unit,
A transfer transistor for controlling the connection between the data holding unit and the gate of the driving transistor;
And a reset transistor for controlling the connection of the gate of the driving transistor and a second power line having a potential different from the first power line,
After the data in one frame is written to the data holding portion of all the pixels, the timing at which the transfer transistor is turned ON is controlled, so that the data of the data holding portion is written to the reset gate of the driving transistor. Device.
According to claim 1,
The timing at which the transfer transistor is turned ON is the same for all pixels,
The reset gate of the driving transistor is the potential of the second power line,
The data of the data holding unit is simultaneously written in all pixels.
The method according to claim 1 or 2,
The gate reset of the driving transistor is performed after data in one frame is written to the data holding unit of all pixels.
The method according to claim 1 or 2,
The gate reset of the driving transistor is performed while data in one frame is written to the data holding unit.
The method according to claim 1 or 2,
The pulse width of the first pulse that turns on the gate transistor is greater than the pulse width of the second pulse that turns on the transfer transistor,
The pulse width of the second pulse is greater than the pulse width of the third pulse that turns on the reset transistor.
The method according to claim 1 or 2,
The first pulse for turning on the gate transistor, the second pulse for turning on the transfer transistor, and the third pulse for turning on the reset transistor have a potential higher than that of the first power line when turned ON and turned OFF. A light emitting display device having a potential at a time lower than that of the first power line.
According to claim 1,
The timing at which the transfer transistor is turned on is delayed to be different between gate lines,
The gate of the reset driving transistor is a potential of the second power line.
According to claim 1,
The timing at which the transfer transistor is turned ON can be switched between an operation mode in which all pixels are synchronized and an operation mode for controlling each gate line,
The gate of the reset driving transistor is a potential of the second power line.

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