JP2012208318A - Pulse generation circuit, pulse generation method, scanning circuit, display device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse generation circuit, capable of generating a pulse signal of a desired transition speed by a self circuit operation, and to provide its generation method, a scanning circuit using the pulse generation circuit, a display device using the scanning circuit, and an electronic apparatus having the display device.SOLUTION: The pulse generation circuit includes two switch elements that are connected in series between two power supplies and complementarily performs on/off operation according to an input pulse logic, and that generates a pulse signal of a desired transition speed in annihilation of pulse. Out of the two power supplies, one power supply in the same polarity side as that of the input pulse is defined as a fixed power supply voltage, and the other power supply is configured to be switchable among a plurality of power-supply voltages.

Description

  The present disclosure relates to a pulse generation circuit, a pulse generation method, a scanning circuit, a display device, and an electronic apparatus, and in particular, uses a pulse generation circuit that generates a pulse signal having a desired transition speed, a generation method thereof, and the pulse generation circuit. The present invention relates to a scanning circuit, a display device using the scanning circuit, and an electronic apparatus including the display device.

  The pulse generation circuit is generally known as a circuit that generates a pulse signal having a fast falling or rising transition speed, that is, a steep falling or rising waveform. On the other hand, as one type of pulse generation circuit, there is a pulse generation circuit that generates a pulse signal with a desired transition speed, that is, a slow falling or rising waveform when the pulse disappears.

  For example, a pulse generation circuit that generates a pulse signal with a gradual falling or rising waveform when the pulse disappears is used as an output circuit that outputs a scanning pulse with a gradual falling waveform in a scanning circuit of a display device. (For example, refer to Patent Document 1).

  This prior art employs a configuration in which a power supply voltage with a gradual falling waveform is generated on a discrete substrate outside the display panel. Then, by using the power supply voltage with a gradual falling waveform as the power supply voltage of the final stage buffer in the output circuit of the scanning circuit on the display panel, and using the transition speed of the falling edge, the pulse voltage disappears. A scanning pulse with a gradual falling waveform is output (generated).

JP 2008-181039 A

  As in the prior art described in Patent Document 1, when the configuration using the transition speed of the falling of the power supply voltage generated by the discrete board is employed, the number of parts increases by the provision of the discrete board, and the cost increases. Therefore, it becomes an obstacle to miniaturization and cost reduction of the display device.

  Therefore, the present disclosure provides a pulse generation circuit capable of generating a pulse signal having a desired transition speed by a circuit operation of the pulse generation circuit itself, a generation method thereof, a scanning circuit using the pulse generation circuit, a display device using the scanning circuit, and An object is to provide an electronic device including the display device.

In order to achieve the above object, the present disclosure provides:
In a pulse generation circuit having two switch elements connected in series between two power supplies and performing on / off operations complementarily according to the logic of an input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The other power source of the two power sources can be switched between a plurality of power source voltages.

  This pulse generation circuit is used as an output circuit in various scanning circuits. A scanning circuit using this pulse generation circuit is used as the scanning circuit in a display device. A display device using this scanning circuit is used as a display portion in various electronic devices.

  In the pulse generation circuit configured as described above, one power supply is a fixed power supply voltage, while the other power supply is switched between a plurality of power supply voltages, so that the two switch elements are connected in common at the switching timing. Coupling enters the output node, which is a node. This coupling acts to suppress a sudden change in the potential of the output node. Due to the effect of this coupling, the transition speed of the output pulse becomes slow. As a result, the pulse generation circuit can generate a pulse signal having a desired transition speed when the pulse disappears by the circuit operation of the circuit itself.

  According to the present disclosure, the transition speed of the output pulse can be slowed by the action of coupling at the time of switching the voltage of the other power supply, so that a pulse signal having a desired transition speed can be generated by the circuit operation of the pulse generation circuit itself.

It is explanatory drawing about the pulse generation circuit which produces | generates the positive polarity pulse signal which concerns on embodiment of this indication, (A) is a circuit example of a pulse generation circuit, (B) is the waveform of each part of a pulse generation circuit, respectively Show. It is explanatory drawing about the pulse generation circuit which produces | generates a negative polarity pulse signal, (A) is a circuit example of a pulse generation circuit, (B) has each shown the waveform of each part of a pulse generation circuit. It is a system configuration diagram showing an outline of a basic configuration of an active matrix organic EL display device to which the present disclosure is applied. It is a circuit diagram which shows an example of the concrete circuit structure of a pixel (pixel circuit). It is a timing waveform diagram with which it uses for description of the basic circuit operation | movement of the organic electroluminescence display to which this indication is applied. FIG. 7 is an operation explanatory diagram (No. 1) of basic circuit operations of an organic EL display device to which the present disclosure is applied. It is operation | movement explanatory drawing (the 2) of basic circuit operation | movement of the organic electroluminescence display to which this indication is applied. FIG. 6 is a characteristic diagram for explaining (A) a problem caused by variation in threshold voltage V _th of a drive transistor and (B) explaining a problem caused by variation in mobility μ of the drive transistor. It is a wave form diagram which shows the pulse waveform of the writing scanning signal WS in the case of signal writing & mobility correction. It is a block diagram which shows an example of a structure of a writing scanning circuit. It is a perspective view which shows the external appearance of the television set to which this indication is applied. It is the perspective view which shows the external appearance of the digital camera to which this indication is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. It is a perspective view showing appearance of a notebook personal computer to which the present disclosure is applied. It is a perspective view showing appearance of a video camera to which the present disclosure is applied. It is an external view showing a mobile phone to which the present disclosure is applied, (A) is a front view in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) Is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view.

Hereinafter, modes for carrying out the technology of the present disclosure (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The description will be given in the following order.
1. 1. Pulse generation circuit 1-1. Circuit configuration 1-2. Circuit operation 1-3. Modified example 1-4. Action, effect Display device (example of organic EL display device)
2-1. System configuration 2-2. Basic circuit operation 2-3. Pulse waveform of address scanning signal WS 2-4. 2. Write scanning circuit Electronic equipment Composition of this disclosure

<1. Pulse generation circuit>
[1-1. Circuit configuration]
FIG. 1 is an explanatory diagram of a pulse generation circuit according to an embodiment of the present disclosure. In FIG. 1, (A) shows a circuit example of a pulse generation circuit, and (B) shows a waveform of each part of the pulse generation circuit.

In FIG. 1A, the pulse generation circuit P _{1 according} to the embodiment of the present disclosure has a configuration in which, for example, two (two stages) buffers B ₁₁ and B ₁₂ are connected in cascade. Here, a positive pulse signal that activates a high level (logic “1”) is input, and the pulse signal is inverted twice by the buffers B ₁₁ and B ₁₂ to obtain the same positive polarity as the input pulse. A pulse signal shall be output.

The front-stage buffer B ₁₁ is connected in series between the power supply line L ₁₁ and the power supply line L _12, and has two switch elements that perform ON / OFF operations complementarily according to the logic of the input pulse. ing. For example, a P channel MOS transistor P ₁₁ and an N channel MOS transistor N ₁₁ are used as the two switch elements.

That is, the preceding-stage buffer B ₁₁ has a circuit configuration of a CMOS inverter including a P-channel MOS transistor P ₁₁ and an N-channel MOS transistor N ₁₁ . The power supply line L ₁₁ is a fixed power supply with a positive power supply voltage V _DD , and the power supply line L ₁₂ is a fixed power supply with a negative power supply voltage V _SS .

In the preceding buffer B ₁₁ , the gate electrode and the drain electrode of the P channel MOS transistor P ₁₁ and the N channel MOS transistor N ₁₁ are connected in common. The gate common connection node of these MOS transistors P ₁₁ and N ₁₁ is the input terminal (input node) of the buffer B ₁₁ , that is, the circuit input terminal of the pulse generation circuit P _{1 according to} the present embodiment.

The drain common connection node of the MOS transistors P ₁₁ and N ₁₁ is an output terminal (output node) of the buffer B ₁₁ . The source electrode of P channel MOS transistor P ₁₁ is connected to power supply line L ₁₁ of power supply voltage V _DD , and the source electrode of N channel MOS transistor N ₁₁ is connected to power supply line L ₁₂ of power supply voltage V _SS .

The latter stage (final stage) buffer B ₁₂ is connected in series between the power supply line L ₁₁ and the power supply line L _13, and includes two switch elements that complementarily perform on / off operations according to the logic of the input pulse. It is the composition which has. As with the previous buffer B ₁₁ , for example, a P-channel MOS transistor P ₁₂ and an N-channel MOS transistor N ₁₂ are used as the two switch elements.

In other words, the subsequent buffer B ₁₂ has a circuit configuration of a CMOS inverter including a P-channel MOS transistor P ₁₂ and an N-channel MOS transistor N ₁₂ . Power line L ₁₁ is a fixed power source, the power line L ₁₃ is a variable power supply. Details of the variable power supply voltage V _SSP of the power supply line L ₁₃ will be described later.

In the subsequent buffer B ₁₂ , the gate electrode and the drain electrode of the P channel MOS transistor P ₁₂ and the N channel MOS transistor N ₁₂ are connected in common. The gate common connection node of these MOS transistors P ₁₂ and N ₁₂ becomes the input terminal (input node) of the buffer B _{12 and} the output terminal of the preceding buffer B ₁₁ , that is, the drains of the MOS transistors P ₁₁ and N ₁₁ . Connected to the common connection node.

The drain common connection node of the MOS transistors P ₁₂ and N ₁₂ is an output terminal (output node) of the buffer B ₁₂ , that is, a circuit output terminal of the pulse generation circuit P _{1 according to} the present embodiment. The source electrode of the P channel MOS transistor P ₁₂ is connected to the power line L ₁₁ of the fixed power source, and the source electrode of the N channel MOS transistor N ₁₂ is connected to the power source line L ₁₃ of the variable power source.

Here, the power supply line L ₁₃ is separated from the power supply line L ₁₂ of the power supply voltage V _SS , and the power supply voltage V _SSP can be switched between a plurality of power supply voltages. As an example, assuming that the positive power supply voltage V _DD is about 15 V, the power supply voltage V _SSP of the power supply line L ₁₃ is set to 0 V (= V _SS ) as the first power supply voltage. The second power supply voltage can be switched between these first and second power supply voltages, for example, a voltage higher than about half of the positive power supply voltage V _DD , for example, about 2V to 3V. However, the numerical values of the power supply voltage V _SSP illustrated here are merely examples, and are not limited to these numerical values.

The switching of the power supply voltage V _SSP of the power supply line L ₁₃ is preferably instantaneously performed at the same timing in synchronism with the switching timing of on / off of the two switch elements, that is, the MOS transistors P ₁₂ and N _12. . As a result of this instantaneous switching, the power supply voltage V _SSP of the power supply line L ₁₃ changes in a pulse form from the first power supply voltage to the second power supply voltage. That is, the power supply voltage V _SSP of the power supply line L ₁₃ is a pulsed variable power supply voltage.

[1-2. Circuit operation]
Next, the circuit operation of the pulse generation circuit P _{1 according to} the embodiment of the present disclosure having the above-described configuration will be described with reference to the waveform diagram of FIG.

For example, it is assumed that the pulse generation circuit P ₁ receives a positive pulse signal (a) that sets a low level to V _SS , a high level to V _DD , and a high level state to an active state. When the input pulse signal (a) becomes high level (time t ₁ ), the N-channel MOS transistor N ₁₁ is turned on (conducted) in the previous buffer B ₁₁ and the P-channel MOS transistor P ₁₁ is turned off ( (Not conducting) state. Then, the potential (b) at the output end of the preceding stage buffer B ₁₁ , that is, the input end of the succeeding stage buffer B ₁₂ becomes low level (= V _SS ).

In the subsequent buffer B ₁₂ , when the potential (b) at the input terminal becomes a low level, the P-channel MOS transistor P ₁₂ is turned on and the N-channel MOS transistor N ₁₂ is turned off. At this time, the power supply voltage of the power line L ₁₃ of the variable power supply has a first power supply voltage V _SS. When the P-channel MOS transistor P ₁₂ is turned on, the potential (c) at the output terminal becomes high (= V _DD ), that is, a positive output pulse (c) is generated at the output terminal. To do.

Subsequently, when the positive polarity pulse signal (a) disappears (time t ₂ ), that is, when the pulse signal (a) transitions from a high level to a low level, the P-channel MOS transistor P ₁₁ is turned on in the preceding buffer B ₁₁ . N-channel MOS transistor N ₁₁ is turned off. Then, the potential (b) at the output terminal of the preceding-stage buffer B ₁₁ , that is, the input terminal of the subsequent-stage buffer B ₁₂ becomes high level.

Further, when the potential (b) at the input end of the subsequent buffer B ₁₂ becomes high, the N-channel MOS transistor N ₁₂ is turned on and the P-channel MOS transistor P ₁₂ is turned off. At this time, in synchronization with the ON / OFF switching timing of the MOS transistors N ₁₂ and P ₁₂ (preferably at the same timing), the power supply voltage V _SSP (d) of the power supply line L ₁₃ of the variable power supply is The power supply voltage V _SS is switched instantaneously (that is, in a pulse form) to the second power supply voltage (for example, about 2 V to 3 V).

Here, if the power supply voltage V _SSP (d) of the power supply line L ₁₃ is fixed to the first power supply voltage V _SS , the N-channel MOS transistor N ₁₂ is turned on, whereby the output terminal potential (c) Transitions abruptly (instantaneously) from a high level (= V _DD ) to a low level (= V _SS ). That is, the positive output pulse (c) disappears instantaneously as shown by the broken line in the waveform (c) of FIG.

On the other hand, the power supply voltage V _SSP (d) of the power supply line L ₁₃ is switched instantaneously (that is, in a pulse form) in synchronization with the ON / OFF switching timing of the MOS transistors N ₁₂ and P _12. Thus, the transition waveform of the falling edge of the output pulse (c) changes as follows. That is, when the power supply voltage V _SSP (d) of the power supply line L ₁₃ is instantaneously switched (that is, rises) in a pulse shape, a parasitic is interposed between the source electrode and the output terminal of the N-channel MOS transistor N _12. A positive potential jumps into the output terminal due to capacitive coupling by the capacitor C _p .

The positive potential that jumps into the output terminal due to this capacitive coupling suppresses a sudden change in the output terminal potential, that is, the output pulse (c) from the high level to the low level when the N-channel MOS transistor N ₁₂ is turned on. Acts as follows. As a result of the action due to the capacitive coupling, the transition speed at which the output pulse (c) falls from the high level to the low level is slow, that is, the falling transition waveform is more gradual than when there is no capacitive coupling. Become.

Here, the transition speed at which the output pulse (c) falls from the high level to the low level is determined by the coupling amount of the positive potential that jumps into the output terminal by capacitive coupling. This amount of coupling is determined by the voltage value of the second power supply voltage of the power supply voltage V _SSP (d) of the power supply line L ₁₃ . That is, by arbitrarily setting the voltage value of the second power supply voltage, a pulse signal that achieves a desired transition speed when the pulse disappears due to the circuit operation of the pulse generation circuit P ₁ itself, that is, the circuit operation with capacitive coupling. Can be generated.

[1-3. Modified example]
In the above embodiment, the case where the pulse generation circuit P ₁ generates a positive pulse signal has been described as an example. However, the technology of the present disclosure is limited to application to generation of a positive pulse signal. The present invention is not limited to this, and can be similarly applied to the case of generating a negative pulse signal. A pulse generation circuit that generates a negative pulse signal will be described below as a pulse generation circuit P _{2 according} to a modification with reference to FIG. 2 shows (A) is a circuit example of the pulse generating circuit P _2, the (B) is a pulse generating circuit P ₂ of each part of the waveform, respectively.

As is clear from the comparison between FIG. 1A and FIG. 2A, the pulse generation circuit P _{2 according} to this modification example is basically the same as the pulse generation circuit P _{1 according} to the above-described embodiment. It is the same. That is, in the pulse generation circuit P ₂ , for example, two (two stages) buffers B ₁₁ and B ₁₂ are connected in cascade, and these buffers B ₁₁ and B ₁₂ have a circuit configuration of a CMOS inverter. On the other hand, it differs from the pulse generation circuit P _{1 according} to the above-described embodiment in the following points.

That is, in the last stage (back stage) buffer B ₁₂ , in the pulse generation circuit P _{1 according} to the above-described embodiment, the power source line L ₁₃ on the negative power source side is separated from the power source line L ₁₂ of the front stage buffer B ₁₁ , and the power source the power supply voltage of the line L ₁₃ has been made variable. On the other hand, in the pulse generation circuit P _{2 according} to this modification, the power supply line L ₁₄ on the positive power supply side is separated from the power supply line L ₁₁ of the preceding buffer B ₁₁ , and the power supply voltage V _DDP of the power supply line L ₁₄ is obtained. Switchable. The power supply voltage V _DDP of the power supply line L ₁₄ is switched in synchronism (preferably at the same timing) with the on / off switching timing of the MOS transistors N ₁₂ and P ₁₂ .

As an example of the power supply voltage V _DDP of the power supply line L ₁₄ , assuming that the positive power supply voltage V _DD is about 15 V, the first power supply voltage is 15 V (= V _DD ). The second power supply voltage is lower than the positive power supply voltage V _DD and higher than about half of the positive power supply voltage V _DD , for example, about 12V to 13V. The power supply voltage V _DDP of the power supply line L ₁₄ can be switched between the first and second power supply voltages. However, the numerical values of the power supply voltage V _DDP exemplified here are only examples, and are not limited to these numerical values.

For example, the pulse generation circuit P ₂ configured as described above is supplied with a negative pulse signal (a) that sets the low level to V _SS , the high level to V _DD , and the low level state to the active state. . As for the specific circuit operation, basically, the same circuit operation as in the case of the pulse generation circuit P _{1 according} to the above-described embodiment is performed. What is different from the case of the pulse generation circuit P ₁ is the circuit operation of the buffer B _{12 at} the subsequent stage when the input pulse signal (a) transitions from the low level to the high level (time t ₂ ).

Specifically, in the subsequent buffer B _12, MOS transistors N _12, in synchronism with the switching timing of the P ₁₂ on / off (preferably at the same time), the power supply voltage V of the power supply line L ₁₄ of the variable power supply _DDP (d) switches instantaneously (that is, in a pulse form) from the first power supply voltage V _DD to the second power supply voltage (for example, about 12V to 13V).

Here, if the power supply voltage V _DDP (d) of the power supply line L ₁₄ is fixed to the power supply voltage V _DD , the P-channel MOS transistor P ₁₂ is turned on, so that the potential (c) at the output terminal is low. A transition is made steeply (instantaneously) from the level (= V _SS ) to the high level (= V _DD ). That is, the negative output pulse (c) disappears instantaneously as shown by the broken line in the waveform (c) of FIG.

On the other hand, the power supply voltage V _DDP (d) of the power supply line L ₁₄ is switched instantaneously (that is, in a pulse form) in synchronization with the ON / OFF switching timing of the MOS transistors N ₁₂ and P _12. Thus, the transition waveform of the rising edge of the output pulse (c) changes as follows. That is, the power supply voltage V _DDP (d) of the power supply line L ₁₄ is instantaneously switched to a pulse shape (that is, falls), thereby interposing between the source electrode and the output terminal of the P-channel MOS transistor P _12. a negative potential jump at the output end by capacitive coupling due to the parasitic capacitance C _p.

The negative potential jumping into the output terminal due to this capacitive coupling suppresses the sudden change of the output terminal potential, that is, the output pulse (c) from the low level to the high level when the P-channel MOS transistor P ₁₂ is turned on. Acts as follows. As a result of the action due to the capacitive coupling, the transition speed at which the output pulse (c) falls from the low level to the high level is slow, that is, the rising transition waveform is more gradual than when there is no capacitive coupling. Become.

[1-4. Action, effect]
As described above, the present embodiment and its modification have two switch elements connected in series between two power supplies and performing on / off operations complementarily according to the logic of the input pulse, A pulse generation circuit that generates a pulse signal having a desired transition speed when the pulse disappears has the following configuration. That is, of the two power supplies, one power supply on the same polarity side as the input pulse is set to a fixed power supply voltage, and the other power supply can be switched between a plurality of power supply voltages.

  Thus, while one power supply is a fixed power supply voltage, the other power supply is switched between a plurality of power supply voltages, so that the output that is the common connection node of the two switch elements at the switching timing. Capacitive coupling enters the node. This capacitive coupling acts to suppress a sudden change in the potential of the output node. Due to the action of this capacitive coupling, the transition speed of the output pulse becomes slow. As a result, the pulse generation circuit can generate a pulse signal having a desired transition speed when the pulse disappears by the circuit operation of the circuit itself.

  In the above-described embodiment and its modification, a pulse generation circuit in which two stages of buffers are cascade-connected has been described as an example. However, the number of stages of buffers may be one, or three or more. If the buffer is a pulse generation circuit having a single-stage configuration, the technique of the present disclosure may be applied to the buffer. In the case of a pulse generation circuit having a configuration of three or more stages, the main buffer is used for the final-stage buffer. The disclosed technique may be applied.

  Here, the complementary ON / OFF operation according to the logic of the input pulse means that one switch element is turned on when the logic is “1”, as is apparent from the description of the circuit operation described above. When the other switch element is turned off and the logic is “0”, the reverse operation is performed.

Of the two power supplies, one power supply having the same polarity as the input pulse is the positive power supply of the power supply voltage V _{DD in} the previous embodiment, and the negative power supply voltage _{VSS in} the modification. Power source. The other power supply, in the above embodiment becomes a variable power supply line L _13, in the modified example thereof is variable power supply line L _14.

  In the above-described embodiment and its modification, the other power source can be switched between the first and second power supply voltages, but is not limited to switching between the two power supply voltages. You may make it switch between three or more power supply voltages. By increasing the number of power supply voltages and switching the power supply voltage of the other power supply in multiple stages, the transition speed (transition waveform) of the generated pulse signal can be controlled more finely.

  As described above, the pulse generation circuit according to the present embodiment and the modification thereof, that is, the pulse generation circuit capable of generating a pulse signal having a desired transition speed when the pulse disappears can be used as follows. . For example, in a display device in which a pixel having a mobility correction function, which will be described later, is arranged, it can be used as a final stage buffer in a scanning circuit that performs scanning for writing a signal to each pixel.

  Alternatively, it can also be used as an application in which a waveform shaping circuit is arranged in the subsequent stage and a pulse width changing circuit that changes the pulse width in combination with the waveform shaping circuit is configured. Specifically, a pulse signal having a desired transition waveform when the pulse disappears is generated by the preceding pulse generation circuit, and a waveform of the rectangular wave pulse signal is generated in the subsequent waveform shaping circuit with reference to an arbitrary threshold level. By shaping, a pulse signal having a wider pulse width than the input pulse can be generated.

  However, the use illustrated here is only an example, and the use of the pulse generation circuit according to the present embodiment and its modification is not limited to these uses. Hereinafter, in the former application, that is, in a display device in which pixels having a mobility correction function are arranged, the application of the present disclosure is used as a final stage buffer in a scanning circuit that performs scanning for writing a signal to each pixel. An example will be specifically described.

<2. Display device>
[2-1. System configuration]
FIG. 3 is a system configuration diagram illustrating an outline of a basic configuration of an active matrix display device to which the present disclosure is applied.

  The active matrix display device is a display device that controls the current flowing through the electro-optical element by an active element provided in the same pixel as the electro-optical element, for example, an insulated gate field effect transistor. As the insulated gate field effect transistor, a TFT (Thin Film Transistor thin film transistor) is typically used.

  Here, as an example, an active matrix organic EL display device that uses a current-driven electro-optical element, for example, an organic EL element, whose light emission luminance changes according to a current value flowing through the device, as a light-emitting element of a pixel (pixel circuit). This case will be described as an example.

  As shown in FIG. 3, the organic EL display device 10 according to this application example includes a plurality of pixels 20 including organic EL elements, a pixel array unit 30 in which the pixels 20 are two-dimensionally arranged in a matrix, The driving circuit unit is arranged around the pixel array unit 30. The drive circuit unit includes a write scanning circuit 40, a power supply scanning circuit 50, a signal output circuit 60, and the like, and drives each pixel 20 of the pixel array unit 30.

  Here, when the organic EL display device 10 supports color display, one pixel (unit pixel) which is a unit for forming a color image is composed of a plurality of sub-pixels (sub-pixels), and each of the sub-pixels is This corresponds to the pixel 20 in FIG. More specifically, in a display device that supports color display, one pixel includes, for example, a sub-pixel that emits red (Red) light, a sub-pixel that emits green (G) light, and blue (Blue). B) It is composed of three sub-pixels of sub-pixels that emit light.

  However, one pixel is not limited to a combination of RGB three primary color subpixels, and one pixel may be configured by adding one or more color subpixels to the three primary color subpixels. Is possible. More specifically, for example, one pixel is formed by adding a sub-pixel that emits white (W) light to improve luminance, or at least emits complementary color light to expand the color reproduction range. It is also possible to configure one pixel by adding one subpixel.

The pixel array unit 30 includes scanning lines 31 _{1 to} 31 _m and power supply lines 32 _{1 to} 32 _m along the row direction (the arrangement direction of the pixels in the pixel row) with respect to the arrangement of the pixels 20 in m rows and n columns. Are wired for each pixel row. Furthermore, signal lines 33 _{1 to} 33 _n are wired for each pixel column along the column direction (pixel arrangement direction of the pixel column) with respect to the arrangement of the pixels 20 in the m rows and the n columns.

The scanning lines 31 _{1 to} 31 _m are connected to the output ends of the corresponding rows of the writing scanning circuit 40, respectively. The power supply lines 32 _{1 to} 32 _m are connected to the output ends of the corresponding rows of the power supply scanning circuit 50, respectively. The signal lines 33 _{1 to} 33 _n are connected to the output ends of the corresponding columns of the signal output circuit 60, respectively.

  The pixel array unit 30 is usually formed on a transparent insulating substrate such as a glass substrate. Thereby, the organic EL display device 10 has a flat panel structure. The drive circuit for each pixel 20 in the pixel array section 30 can be formed using an amorphous silicon TFT or a low-temperature polysilicon TFT. When using low-temperature polysilicon TFTs, as shown in FIG. 3, the write scanning circuit 40, the power supply scanning circuit 50, and the signal output circuit 60 also have a display panel (substrate) 70 that forms the pixel array section 30. Can be implemented on top.

The write scanning circuit 40 is configured by a shift register circuit that sequentially shifts (transfers) the start pulse sp in synchronization with the clock pulse ck. The writing scanning circuit 40, upon a signal voltage writing of the video signal to each pixel 20 of the pixel array unit 30, the writing scanning signal WS to the scanning lines 31 (31 ₁ ~31 _m) a (WS ₁ to WS _m) By sequentially supplying the pixels 20, the pixels 20 of the pixel array unit 30 are sequentially scanned (line-sequential scanning) in units of rows. Details of the configuration of the write scanning circuit 40 will be described later.

The power supply scanning circuit 50 includes a shift register circuit that sequentially shifts the start pulse sp in synchronization with the clock pulse ck. The power supply scanning circuit 50 can be switched between the first power supply potential V _ccp and the second power supply potential V _ini that is lower than the first power supply potential V _ccp in synchronization with the line sequential scanning by the write scanning circuit 40. The power supply potential DS (DS _{1 to} DS _m ) is supplied to the power supply line 32 (32 _{1 to} 32 _m ). As will be described later, light emission / non-light emission control of the pixel 20 is performed by switching V _ccp / V _ini of the power supply potential DS.

The signal output circuit 60 includes a signal voltage V _sig and a reference voltage V _{ofs of} a video signal corresponding to luminance information supplied from a signal supply source (not shown) (hereinafter may be simply referred to as “signal voltage”). And are selectively output. Here, the reference voltage V _ofs is a potential serving as a reference for the signal voltage V _sig of the video signal (for example, a potential corresponding to the black level of the video signal), and is used in threshold correction processing described later.

The signal voltage V _sig / reference voltage V _ofs output from the signal output circuit 60 is scanned by the write scanning circuit 40 with respect to each pixel 20 of the pixel array unit 30 via the signal line 33 (33 _{1 to} 33 _n ). Are written in units of pixel rows selected by. In other words, the signal output circuit 60 adopts a line sequential writing driving form in which the signal voltage V _sig is written in units of rows (lines).

(Pixel circuit)
FIG. 6 is a circuit diagram illustrating an example of a specific circuit configuration of the pixel (pixel circuit) 20. The light-emitting portion of the pixel 20 includes an organic EL element 21 that is a current-driven electro-optical element whose emission luminance changes according to the value of a current flowing through the device.

  As shown in FIG. 6, the pixel 20 includes an organic EL element 21 and a drive circuit that drives the organic EL element 21 by passing a current through the organic EL element 21. The organic EL element 21 has a cathode electrode connected to a common power supply line 34 that is wired in common to all the pixels 20 (so-called solid wiring).

  The drive circuit that drives the organic EL element 21 has a configuration including a drive transistor 22, a write transistor 23, a storage capacitor 24, and an auxiliary capacitor 25. N-channel TFTs can be used as the driving transistor 22 and the writing transistor 23. However, the combination of the conductivity types of the drive transistor 22 and the write transistor 23 shown here is merely an example, and is not limited to these combinations.

The drive transistor 22 has one electrode (source / drain electrode) connected to the anode electrode of the organic EL element 21 and the other electrode (source / drain electrode) connected to the power supply line 32 (32 _{1 to} 32 _m ). ing.

In the write transistor 23, one electrode (source / drain electrode) is connected to the signal line 33 (33 _{1 to} 33 _n ), and the other electrode (source / drain electrode) is connected to the gate electrode of the drive transistor 22. . The gate electrode of the writing transistor 23 is connected to the scanning line 31 (31 _{1 to} 31 _m ).

  In the driving transistor 22 and the writing transistor 23, one electrode is a metal wiring electrically connected to the source / drain region, and the other electrode is a metal wiring electrically connected to the drain / source region. Say. Further, depending on the potential relationship between one electrode and the other electrode, if one electrode becomes a source electrode, it becomes a drain electrode, and if the other electrode also becomes a drain electrode, it becomes a source electrode.

  The storage capacitor 24 has one electrode connected to the gate electrode of the drive transistor 22, and the other electrode connected to the other electrode of the drive transistor 22 and the anode electrode of the organic EL element 21.

  The auxiliary capacitor 25 has one electrode connected to the anode electrode of the organic EL element 21 and the other electrode connected to the common power supply line 34. The auxiliary capacitor 25 is provided as necessary in order to compensate for the insufficient capacity of the organic EL element 21 and to increase the video signal write gain to the storage capacitor 24. That is, the auxiliary capacitor 25 is not an essential component and can be omitted when the equivalent capacitance of the organic EL element 21 is sufficiently large.

  Here, the other electrode of the auxiliary capacitor 25 is connected to the common power supply line 34. However, the connection destination of the other electrode is not limited to the common power supply line 34, and may be a fixed potential node. That's fine. By connecting the other electrode of the auxiliary capacitor 25 to a node of a fixed potential, the intended purpose of compensating the shortage of the capacity of the organic EL element 21 and increasing the video signal write gain to the holding capacitor 24 can be achieved. it can.

In the pixel 20 configured as described above, the writing transistor 23 becomes conductive in response to a high active writing scanning signal WS applied to the gate electrode from the writing scanning circuit 40 through the scanning line 31. Thereby, the write transistor 23 samples the signal voltage V _sig of the video signal or the reference voltage V _ofs supplied from the signal output circuit 60 through the signal line 33 and writes it in the pixel 20. The written signal voltage V _sig or reference voltage V _ofs is applied to the gate electrode of the driving transistor 22 and held in the holding capacitor 24.

When the power supply potential DS of the power supply line 32 (32 _{1 to} 32 _m ) is at the first power supply potential V _ccp , the driving transistor 22 has one electrode as a drain electrode and the other electrode as a source electrode in a saturation region. Operate. As a result, the drive transistor 22 is supplied with current from the power supply line 32 and drives the organic EL element 21 to emit light by current drive. More specifically, the drive transistor 22 operates in the saturation region, thereby supplying the organic EL element 21 with a drive current having a current value corresponding to the voltage value of the signal voltage V _sig held in the storage capacitor 24. The organic EL element 21 is caused to emit light by current driving.

Further, when the power supply potential DS is switched from the first power supply potential V _ccp to the second power supply potential V _ini , the drive transistor 22 operates as a switching transistor with one electrode serving as a source electrode and the other electrode serving as a drain electrode. As a result, the drive transistor 22 stops supplying the drive current to the organic EL element 21 and puts the organic EL element 21 into a non-light emitting state. That is, the drive transistor 22 also has a function as a transistor that controls light emission / non-light emission of the organic EL element 21.

  By the switching operation of the drive transistor 22, a period during which the organic EL element 21 is in a non-light emitting state (non-light emitting period) is provided, and the ratio (duty) of the light emitting period and the non-light emitting period of the organic EL element 21 can be controlled. . By this duty control, afterimage blurring caused by light emission of pixels over one display frame period can be reduced, so that the quality of moving images can be particularly improved.

Of the first and second power supply potentials V _ccp and V _ini selectively supplied from the power supply scanning circuit 50 through the power supply line 32, the first power supply potential V _ccp is a drive current for driving the organic EL element 21 to emit light. The power supply potential is supplied to the driving transistor 22. The second power supply potential V _ini is a power supply potential for applying a reverse bias to the organic EL element 21. The second power supply potential V _ini is a potential lower than the reference voltage V _ofs , for example, a potential lower than V _ofs −V _th when the threshold voltage of the driving transistor 22 is V _th , preferably V _ofs −V _th. Is set to a sufficiently lower potential.

[2-2. Basic circuit operation]
Subsequently, a basic circuit operation of the organic EL display device 10 having the above-described configuration will be described with reference to operation explanatory diagrams of FIGS. 6 and 7 based on a timing waveform diagram of FIG. In the operation explanatory diagrams of FIGS. 6 and 7, the write transistor 23 is illustrated by a switch symbol for simplification of the drawing.

In the timing waveform diagram of FIG. 4, the potential of the scanning line 31 (write scanning signal) WS, the potential of the power supply line 32 (power supply potential) DS, the potential of the signal line 33 (V _sig / V _ofs ), Changes in the gate potential V _g and the source potential V _s are shown.

(Light emission period of the previous display frame)
In the timing waveform diagram of FIG. 4, before the time t ₁₁ is the light emission period of the organic EL element 21 in the previous display frame. During the light emission period of the previous display frame, the potential DS of the power supply line 32 is at the first power supply potential (hereinafter referred to as “high potential”) V _ccp , and the writing transistor 23 is in a non-conductive state.

At this time, the drive transistor 22 is designed to operate in a saturation region. As a result, as shown in FIG. _6A , the drive current (drain-source current) I _ds corresponding to the gate-source voltage V _gs of the drive transistor 22 is organically _transmitted from the power supply line 32 through the drive transistor 22. It is supplied to the EL element 21. Accordingly, the organic EL element 21 emits light with a luminance corresponding to the current value of the drive current I _ds .

(Threshold correction preparation period)
At time t _11, it enters a new display frame of line sequential scanning (current display frame). Then, as shown in FIG. 6B, the second power source in which the potential DS of the power supply line 32 is sufficiently lower than V _ofs −V _{th with} respect to the reference voltage V _ofs of the signal line 33 from the high potential V _ccp. The potential (hereinafter referred to as “low potential”) V _ini is switched.

Here, the threshold voltage of the organic EL element 21 is V _thel , and the potential (cathode potential) of the common power supply line 34 is V _cath . At this time, if the low potential V _ini is V _ini <V _thel + V _cath , the source potential V _s of the drive transistor 22 becomes substantially equal to the low potential V _ini , so that the organic EL element 21 is in a reverse bias state and is quenched. To do.

Next, when the potential WS of the scanning line 31 transitions from the low potential side to the high potential side at time t ₁₂ , the writing transistor 23 becomes conductive as illustrated in FIG. 6C. At this time, since the reference voltage V _ofs is supplied from the signal output circuit 60 to the signal line 33, the gate potential V _g of the drive transistor 22 becomes the reference voltage V _ofs . The source potential V _s of the drive transistor 22 is at a potential sufficiently lower than the reference voltage V _ofs , that is, the low potential V _ini .

At this time, the gate-source voltage V _gs of the driving transistor 22 becomes V _ofs −V _ini . Here, if V _ofs −V _ini is not larger than the threshold voltage V _th of the drive transistor 22, threshold correction processing described later cannot be performed, so that a potential relationship of V _ofs −V _ini > V _th is set. There is a need.

As described above, the process of fixing the gate potential V _g of the driving transistor 22 to the reference voltage V _ofs and fixing (determining) the source potential V _s to the low potential V _ini is a threshold value described later. This is a preparation (threshold correction preparation) process before the correction process (threshold correction operation) is performed. Therefore, the reference voltage V _ofs and the low potential V _ini become the initialization potentials of the gate potential V _g and the source potential V _s of the driving transistor 22.

(Threshold correction period)
Next, at time t ₁₃ , as shown in FIG. 6D, when the potential DS of the power supply line 32 is switched from the low potential V _ini to the high potential V _ccp , the gate potential V _g of the drive transistor 22 is changed to the reference voltage. The threshold correction process is started in a state where V _ofs is maintained. That is, the source potential V _s of the drive transistor 22 starts to increase toward the potential obtained by subtracting the threshold voltage V _th of the drive transistor 22 from the gate potential V _g .

For convenience, the initialization potential V _ofs of the gate potential V _g of the driving transistor 22 as a reference, the source potential V _s towards the potential obtained by subtracting the threshold voltage V _th of the drive transistor 22 from the initialization potential V _ofs The changing process is called a threshold correction process. As the threshold correction process proceeds, the gate-source voltage V _gs of the drive transistor 22 eventually converges to the threshold voltage V _th of the drive transistor 22. A voltage corresponding to the threshold voltage V _th is held in the holding capacitor 24.

In the period for performing the threshold correction process (threshold correction period), the organic EL element 21 is cut off in order to prevent current from flowing exclusively to the storage capacitor 24 side and not to the organic EL element 21 side. As described above, the potential V _cath of the common power supply line 34 is set.

Next, at time t ₁₄ , the potential WS of the scanning line 31 transitions to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. At this time, the gate electrode of the driving transistor 22 is electrically disconnected from the signal line 33 to be in a floating state. However, since the gate-source voltage V _gs is equal to the threshold voltage V _th of the drive transistor 22, the drive transistor 22 is in a cutoff state. Accordingly, the drain-source current I _ds does not flow through the driving transistor 22.

(Signal writing & mobility correction period)
Next, at time t ₁₅ , as shown in FIG. 7B, the potential of the signal line 33 is switched from the reference voltage V _ofs to the signal voltage V _sig of the video signal. Subsequently, at time t ₁₆ , the potential WS of the scanning line 31 transitions to the high potential side, so that the writing transistor 23 becomes conductive as shown in FIG. 7C, and the signal voltage V _{sig of the} video signal. Are sampled and written into the pixel 20.

By writing the signal voltage V _sig by the writing transistor 23, the gate potential V _g of the driving transistor 22 becomes the signal voltage V _sig . When the drive transistor 22 is driven by the signal voltage V _sig of the video signal, the threshold voltage V _th of the drive transistor 22 is canceled with the voltage corresponding to the threshold voltage V _th held in the holding capacitor 24. Details of the principle of threshold cancellation will be described later.

At this time, the organic EL element 21 is in a cutoff state (high impedance state). Therefore, the current (drain-source current I _ds ) flowing from the power supply line 32 to the drive transistor 22 in accordance with the signal voltage V _sig of the video signal flows into the equivalent capacitor and the auxiliary capacitor 25 of the organic EL element 21. Thereby, charging of the equivalent capacity of the organic EL element 21 and the auxiliary capacity 25 is started.

As the equivalent capacitance and the auxiliary capacitance 25 of the organic EL element 21 are charged, the source potential V _s of the drive transistor 22 increases with time. At this time, the pixel-to-pixel variation in the threshold voltage V _th of the drive transistor 22 has already been canceled, and the drain-source current I _ds of the drive transistor 22 depends on the mobility μ of the drive transistor 22. Note that the mobility μ of the drive transistor 22 is the mobility of the semiconductor thin film constituting the channel of the drive transistor 22.

Here, it is assumed that the ratio of the holding voltage V _gs of the holding capacitor 24 to the signal voltage V _sig of the video signal, that is, the write gain G is 1 (ideal value). Then, the source potential V _s of the drive transistor 22 rises to the potential of V _ofs −V _th + ΔV, so that the gate-source voltage V _gs of the drive transistor 22 becomes V _sig −V _ofs + V _th −ΔV.

That is, the increase ΔV of the source potential Vs of the driving transistor 22 is subtracted from the voltage (V _sig −V _ofs + V _th ) held in the holding capacitor 24, in other words, the charge stored in the holding capacitor 24 is discharged. Acts like In other words, the increase ΔV of the source potential Vs is negatively fed back to the storage capacitor 24. Therefore, the increase ΔV of the source potential V _s becomes a feedback amount of negative feedback.

Thus, the drain flowing through the driving transistor 22 - gate with the feedback amount ΔV corresponding to the source current I _ds - by applying the negative feedback to the source voltage V _gs, the drain of the driving transistor 22 - the source current I _ds The dependence on mobility μ can be negated. This canceling process is a mobility correction process for correcting the variation of the mobility μ of the driving transistor 22 for each pixel.

More specifically, since the drain-source current I _ds increases as the signal amplitude V _in (= V _sig −V _ofs ) of the video signal written to the gate electrode of the drive transistor 22 increases, the feedback amount of negative feedback The absolute value of ΔV also increases. Therefore, mobility correction processing according to the light emission luminance level is performed.

Furthermore, when a constant signal amplitude V _in of the video signal, since the greater the absolute value of the feedback amount ΔV of the mobility μ is large enough negative feedback of the drive transistor 22, to remove the variation of the mobility μ for each pixel Can do. Therefore, it can be said that the feedback amount ΔV of the negative feedback is a correction amount of the mobility correction process. Details of the principle of mobility correction will be described later.

(Light emission period)
Next, at time t ₁₇ , the potential WS of the scanning line 31 transitions to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. 7D. As a result, the gate electrode of the driving transistor 22 is electrically disconnected from the signal line 33 and is in a floating state.

Here, when the gate electrode of the drive transistor 22 is in a floating state, the storage capacitor 24 is connected between the gate and the source of the drive transistor 22, thereby interlocking with the fluctuation of the source potential V _s of the drive transistor 22. Thus, the gate potential V _g also varies.

Thus, the operation in which the gate potential V _g of the drive transistor 22 varies in conjunction with the variation of the source potential V _s , in other words, while maintaining the gate-source voltage V _gs retained in the retention capacitor 24. The operation of increasing the gate potential V _g and the source potential V _s is a bootstrap operation.

The gate electrode of the drive transistor 22 is in a floating state, and at the same time, the drain-source current I _{ds of the} drive transistor 22 starts to flow through the organic EL element 21, so that the anode of the organic EL element 21 corresponds to the current I _ds. The potential increases.

When the anode potential of the organic EL element 21 exceeds V _thel + V _cath , the drive current starts to flow through the organic EL element 21, so that the organic EL element 21 starts to emit light. The increase in the anode potential of the organic EL element 21 is none other than the increase in the source potential V _s of the drive transistor 22. When the source potential V _s of the driving transistor 22 rises, the gate potential V _g of the driving transistor 22 also rises in conjunction with the bootstrap operation of the storage capacitor 24.

At this time, when it is assumed that the bootstrap gain is 1 (ideal value), the increase amount of the gate potential V _g becomes equal to the increase amount of the source potential V _s . Therefore, during the light emission period, the gate-source voltage V _gs of the drive transistor 22 is kept constant at V _sig −V _ofs + V _th −ΔV. At time t ₁₈ , the potential of the signal line 33 is switched from the signal voltage V _{sig of the} video signal to the reference voltage V _ofs .

In the series of circuit operations described above, processing operations for threshold correction preparation, threshold correction, signal voltage V _sig writing (signal writing), and mobility correction are executed in one horizontal scanning period (1H). Further, the processing operations of the signal writing and mobility correction are concurrently executed in the period from time t ₁₆ -t _17.

[Division threshold correction]
Here, the case where the driving method in which the threshold value correction process is executed only once is described as an example, but this driving method is only an example and is not limited to this driving method. For example, in addition to the 1H period in which the threshold correction process is performed together with the mobility correction and the signal writing process, the threshold correction process is performed a plurality of times while being divided over a plurality of horizontal scanning periods preceding the 1H period. It is also possible to adopt a driving method for performing threshold correction.

  According to this division threshold correction driving method, even if the time allocated as one horizontal scanning period is shortened due to the increase in the number of pixels associated with high definition, sufficient time is provided for a plurality of horizontal scanning periods as the threshold correction period. Can be secured. Therefore, even if the time allocated as one horizontal scanning period is shortened, a sufficient time can be secured as the threshold correction period, so that the threshold correction process can be reliably executed.

[Principle of threshold cancellation]
Here, the principle of threshold cancellation (that is, threshold correction) of the drive transistor 22 will be described. The drive transistor 22 operates as a constant current source because it is designed to operate in the saturation region. As a result, the organic EL element 21 is supplied with a constant drain-source current (drive current) I _ds given by the following equation (1) from the drive transistor 22.
I _ds = (1/2) · μ (W / L) C _ox (V _gs −V _th ) ² (1)
Here, W is the channel width of the driving transistor 22, L is the channel length, and C _ox is the gate capacitance per unit area.

FIG. 8A shows the characteristics of the drain-source current I _ds versus the gate-source voltage V _gs of the driving transistor 22. As shown in the characteristic diagram of FIG. 8A, if the cancel process (correction process) for the variation of the threshold voltage V _th of the driving transistor 22 for each pixel is not performed, the gate is obtained when the threshold voltage V _th is V _th1. - a drain corresponding to the source voltage V _gs - source current I _ds becomes I _ds1.

On the other hand, when the threshold voltage V _th is _{V th2 (V th2> V th1} ), the same gate - drain corresponding to the source voltage V _gs - source current I _{ds I ds2 (I ds2 <I ds1} ) become. That is, when the threshold voltage V _th of the drive transistor 22 varies, the drain-source current I _ds varies even if the gate-source voltage V _gs is constant.

On the other hand, in the pixel (pixel circuit) 20 having the above configuration, as described above, the gate-source voltage V _gs of the driving transistor 22 at the time of light emission is V _sig −V _ofs + V _th −ΔV. Therefore, when this is substituted into the equation (1), the drain-source current I _ds is expressed by the following equation (2).
I _ds = (1/2) · μ (W / L) C _ox (V _sig −V _ofs −ΔV) ² (2)

That is, the term of the threshold voltage V _th of the drive transistor 22 is canceled, and the drain-source current I _ds supplied from the drive transistor 22 to the organic EL element 21 does not depend on the threshold voltage V _th of the drive transistor 22. . As a result, even if the threshold voltage V _th of the drive transistor 22 varies from pixel to pixel due to variations in the manufacturing process of the drive transistor 22 and changes over time, the drain-source current I _ds does not vary. 21 emission luminance can be kept constant.

[Principle of mobility correction]
Next, the principle of mobility correction of the drive transistor 22 will be described. FIG. 8B shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the drive transistor 22 and a pixel B having a relatively low mobility μ of the drive transistor 22 are compared. When the driving transistor 22 is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels like the pixel A and the pixel B.

In a state where the mobility μ varies between the pixel A and the pixel B, for example, the signal amplitude V _in (= V _sig −V _ofs ) of the same level is written to both the pixels A and B to the gate electrode of the drive transistor 22. Consider the case. In this case, if no not corrected mobility mu, drain flows to the pixel A having the high mobility mu - source current I _ds1 'and the drain flowing through the pixel B having the low mobility mu - source current I _ds2' and There will be a big difference between the two. As described above, when a large difference occurs between the pixels in the drain-source current I _ds due to the variation of the mobility μ from pixel to pixel, the uniformity of the screen is impaired.

Here, as is clear from the transistor characteristic equation of the equation (1) described above, the drain-source current I _ds increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 8B, the feedback amount ΔV ₁ of the pixel A having a high mobility μ is larger than the feedback amount ΔV ₂ of the pixel B having a low mobility μ.

Therefore, by applying negative feedback to the gate-source voltage Vgs with a feedback amount ΔV corresponding to the drain-source current I _ds of the driving transistor 22 by mobility correction processing, negative feedback is increased as the mobility μ increases. It will be. As a result, variation in mobility μ for each pixel can be suppressed.

Specifically, when applying a correction of the feedback amount [Delta] V ₁ at the pixel A having the high mobility mu, drain - source current I _ds larger drops from I _ds1 'to I _ds1. On the other hand, since the feedback amount [Delta] V ₂ small pixels B mobility μ is small, the drain - source current I _ds becomes lowered from I _ds2 'to I _ds2, not lowered so much. Consequently, the drain of the pixel A - drain-source current I _ds1 and the pixel B - to become nearly equal to the source current I _ds2, variations among the pixels of the mobility μ is corrected.

In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel B having a low mobility μ. That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current I _ds .

Therefore, the drain of the driving transistor 22 - with the feedback amount ΔV corresponding to the source current I _ds, the gate - by applying the negative feedback to the source voltage V _gs, the drain of pixels having different mobilities mu - source current I _ds The current value is made uniform. As a result, variation in mobility μ for each pixel can be corrected. That is, the feedback amount (correction amount) ΔV corresponding to the current flowing through the drive transistor 22 (drain-source current I _ds ) with respect to the gate-source voltage V _gs of the drive transistor 22, that is, the storage capacitor 24. On the other hand, the process of applying negative feedback is the mobility correction process.

[2-3. Pulse waveform of write scan signal WS]
As is apparent from the above description of the basic circuit operation, the correction period of the mobility correction processing performed in parallel with the writing processing of the signal voltage V _sig of the video signal depends on the pulse width of the writing scanning signal WS. Determined. In order to perform this mobility correction processing adaptively according to the signal voltage V _sig of the video signal, the write scanning circuit 40 has a transition waveform (a falling waveform in this example) when the pulse disappears, as shown in FIG. ) Is generated (the transient response is slow), and the write scanning signal WS is generated (see Patent Document 1).

Here, the reason why the mobility correction process can be adaptively performed according to the signal voltage V _sig of the video signal by making the falling waveform of the write scanning signal WS gentle (smoothed) is shown in FIG. This will be described with reference to waveform diagrams.

By setting the falling waveform of the write scan signal WS to a gentle waveform, the gate-source voltage of the write transistor 23 is cut off when the threshold voltage V _{th (WS)} of the write transistor 23 is reached. , Transition from the conductive state to the non-conductive state. Here, as an example, a case where the signal voltage V _sig is 5V and a case where it is 2V will be described as examples.

When V _sig = 5V, the write transistor 23 is cut off when the gate-source voltage becomes a cut-off voltage, that is, 5V + V _{th (WS)} . Therefore, the mobility correction time when V _sig = 5 V is relatively short. On the other hand, when V _sig = 2V, the write transistor 23 is cut off when the gate-source voltage becomes a cut-off voltage, that is, 2V + V _{th (WS)} . Therefore, the mobility correction time when V _sig = 2V is longer than that when V _sig = 5V.

Thus, by setting the falling waveform of the write scanning signal WS to a gentle waveform, the optimum mobility correction time can be set corresponding to the signal voltage V _sig of the video signal. As a result, the dependence on the mobility μ of the drain-source current I _ds of the drive transistor 22 is more reliably canceled over the entire level range (all gradations) of the signal voltage V _sig from the black level to the white level. That is, it is possible to more reliably correct the variation of the mobility μ for each pixel.

[2-4. Write scanning circuit]
Next, a specific configuration of the write scan circuit 40 that generates (outputs) the write scan signal WS having a gentle falling waveform used in the signal write & mobility correction process will be described.

  FIG. 10 is a block diagram showing an example of the configuration of the write scanning circuit 40. As shown in FIG. 10, the write scanning circuit 40 according to this example includes a shift register 41, a level shift circuit (L / S) 42, and an output circuit 43. The level shift circuit 42 and the output circuit 43 include The pixel array unit 30 is provided for each pixel row.

  Here, although illustration is omitted for simplification of the drawing, a logic circuit or the like is also provided for each pixel row. In this logic circuit, as the write scan signal WS, two series of scan pulses, that is, a scan pulse for determining a threshold correction period and a scan pulse for determining a signal write & mobility correction period are generated.

The shift register 41 sequentially outputs (shifts) the shift pulse from each shift stage (transfer stage) by sequentially shifting (transferring) the start pulse sp in synchronization with the clock pulse ck. The shift pulse is supplied as a write scanning signal (pulse) WS to each of the scanning lines 31 _{1 to} 31 _m of the pixel array section 30 through the level shift circuit 42 and the output circuit 43.

  The level shift circuit 42 level-shifts the logic level shift pulse output from the shift register 41 to a level shift pulse that can drive each pixel 20 on the display panel 70. The level-shifted shift pulse is supplied to the output circuit 43 via the logic circuit, for example.

The output circuit 30 includes a plurality of cascaded buffers 431 _{1 to} 431 _i . In the output circuit 30, the buffer B ₁₂ at the subsequent stage of the pulse generation circuit P _{1 according} to the above-described embodiment can be used as the buffer 431 _{i at the} final stage. In this example, due to the use of N-channel transistor as the writing transistor 23 of the pixel 20, so that the use of the following buffer B ₁₂ of the pulse generating circuit P _1. When using a P-channel transistor as the writing transistor 23, it is sufficient to use the following buffer B ₁₂ of the pulse generating circuit P ₂ according to the modification previously described.

As described above, in the output circuit 30 of the write scanning circuit 40 that generates the write scan signal WS having a gentle transition waveform at the time of extinction of the pulse, the buffer 431 _{i in the} final stage is related to the above-described embodiment or its modification. By using the pulse generation circuit, the following actions and effects can be obtained.

In other words, according to the pulse generation circuits P ₁ and P ₂ according to the above-described embodiment or its modification, the pulse generation circuits P ₁ and P ₂ themselves are operated by the circuit operation, that is, the circuit operation accompanied by capacitive coupling. A pulse signal having a desired transition speed (transient response) when extinguished can be generated. Therefore, unlike the prior art described in Patent Document 1, it is not necessary to use a power supply voltage with a gentle transition waveform generated on a discrete substrate outside the display panel 70.

  In other words, it is not necessary to generate a power supply voltage having a gentle transition waveform on a discrete substrate outside the display panel 70. This eliminates the need for a discrete substrate for generating a power supply voltage with a gradual transition waveform, that is, reduces the number of components provided outside the display panel 70, thereby reducing the size and cost of the display device. Can do.

  In the above application example, the case where the present invention is applied to an organic EL display device using an organic EL element as the electro-optical element of the pixel 20 has been described as an example. However, the present disclosure is not limited to this application example. Absent. That is, the present disclosure is also applied to a display device using a current-driven electro-optical element (light-emitting element) such as an inorganic EL element, an LED element, or a semiconductor laser element whose emission luminance changes according to the current value flowing through the device. it can. More specifically, a pixel having a mobility correction function for correcting the mobility of a drive transistor that drives a current-driven electro-optic element is arranged, and the mobility correction is adaptively performed according to the luminance level of the pixel. This function is applicable to all display devices configured to perform the above.

<3. Electronic equipment>
The display device according to the present disclosure described above is displayed on a display unit (display device) of an electronic device in any field that displays a video signal input to the electronic device or a video signal generated in the electronic device as an image or a video. Applicable. As an example, the present invention can be applied to various electronic devices shown in FIGS. 11 to 15, such as a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, and a display unit such as a video camera.

  As described above, by using the display device according to the present disclosure as the display unit in electronic devices in various fields, it is possible to contribute to the reduction in size and cost of various electronic devices. That is, as described above, the display device according to the present disclosure can reduce the number of components provided outside the display panel 70, and thus the display device can be reduced in size and cost. Therefore, in various electronic devices, it can contribute to size reduction and cost reduction of the device main body.

  The display device according to the present disclosure also includes a module-shaped device having a sealed configuration. As an example, a display module formed by attaching a facing portion such as transparent glass to the pixel array portion is applicable. Note that the display module may be provided with a circuit unit for inputting / outputting a signal and the like from the outside to the pixel array unit, an FPC (flexible printed circuit), and the like.

  Specific examples of electronic devices to which the present disclosure is applied will be described below.

  FIG. 11 is a perspective view illustrating an appearance of a television set to which the present disclosure is applied. The television set according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is manufactured by using the organic EL display device according to the present disclosure as the video display screen unit 101. The

  12A and 12B are perspective views illustrating an external appearance of a digital camera to which the present disclosure is applied, in which FIG. 12A is a perspective view seen from the front side, and FIG. 12B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present disclosure as the display unit 112.

  FIG. 13 is a perspective view illustrating an appearance of a notebook personal computer to which the present disclosure is applied. The notebook personal computer according to this application example includes a main body 121 including a keyboard 122 operated when inputting characters and the like, a display unit 123 that displays an image, and the like, and the display device according to the present disclosure is used as the display unit 123. It is produced by this.

  FIG. 14 is a perspective view illustrating an appearance of a video camera to which the present disclosure is applied. The video camera according to this application example includes a main body 131, a lens 132 for shooting an object on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using a display device.

  FIG. 15 is an external view showing a mobile terminal device to which the present disclosure is applied, for example, a mobile phone, in which (A) is a front view in an open state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. A cellular phone according to this application example includes an upper casing 141, a lower casing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub-display 145, a picture light 146, a camera 147, and the like. Then, by using the display device according to the present disclosure as the display 144 or the sub display 145, the mobile phone according to the application example is manufactured.

<4. Configuration of the present disclosure>
In addition, this indication can take the following structures.
(1) having two switch elements connected in series between two power supplies and performing on / off operations complementarily according to the logic of the input pulse;
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The other power source of the two power sources can be switched between a plurality of power source voltages.
(2) The pulse generating circuit according to (1), wherein the other power source of the two power sources switches a power source voltage in synchronization with a switching timing of the two switch elements.
(3) The pulse generation circuit according to (2), wherein the other power source of the two power sources switches the power source voltage at the same timing as the switching timing of the two switch elements.
(4) The pulse generation circuit according to any one of (1) to (3), wherein the two switch elements are a P-channel MOS transistor and an N-channel MOS transistor.
(5) The pulse generating circuit according to (4), wherein the two switch elements constitute a CMOS inverter.
(6) The pulse generation circuit according to any one of (4) and (5), wherein the other power source delays a transition speed of an output pulse by an action of a potential jumping into a circuit output terminal at a switching timing.
(7) The potential jumps into the circuit output terminal by capacitive coupling due to a parasitic capacitance interposed between the source electrode of the P-channel MOS transistor or the N-channel MOS transistor and the circuit output terminal. The pulse generation circuit described.
(8) Consists of a plurality of cascaded buffers,
The last stage buffer of the plurality of buffers is configured by the two switch elements,
The pulse generating circuit according to any one of (1) to (7), wherein the other power source is separated from the other power source of the preceding buffer.
(9) In pulse generation in a pulse generation circuit that is connected in series between two power supplies and has two switch elements that complementarily perform on / off operations according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
A pulse generation method for switching the other power source of the two power sources between a plurality of power source voltages.
(10) having two switch elements connected in series between two power supplies and performing on / off operations complementarily according to the logic of the input pulse;
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The other power source of the two power sources can be switched between a plurality of power source voltages. A scanning circuit using a pulse generation circuit as a final stage buffer that outputs a scanning pulse.
(11) a pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
A scanning circuit that scans each pixel of the pixel array unit,
As the final stage buffer of the output circuit, the scanning circuit,
Two switch elements connected in series between two power supplies and performing ON / OFF operations complementarily according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The display device using a pulse generation circuit, wherein the other power source of the two power sources can be switched between a plurality of power source voltages.
(12) The pixel corrects the mobility of the driving transistor by applying negative feedback to the potential difference between the gate and the source of the driving transistor with a correction amount corresponding to the current flowing through the driving transistor that drives the electro-optic element. Has the function of mobility correction to
The display device according to (11), wherein the scanning circuit drives a writing transistor that writes a signal to a gate of the driving transistor by a scanning pulse generated by the pulse generation circuit.
(13) a pixel array unit in which pixels are two-dimensionally arranged in a matrix;
A scanning circuit that scans each pixel of the pixel array unit,
The scanning circuit, as its final stage buffer,
Two switch elements connected in series between two power supplies and performing ON / OFF operations complementarily according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The other power source of the two power sources can be switched between a plurality of power source voltages. Electronic equipment having a display device using a pulse generation circuit.

P ₁ , P ₂ ... pulse generation circuit, B ₁₁ , B ₁₂ ... buffer, 10 ... organic EL display device, 20 ... pixel, 21 ... organic EL element, 22 ... drive transistor, 23 ... write transistor, 24 ... storage capacitor, 25 ... auxiliary capacitor, 30 ... pixel array _{section, 31 (31 1 ~31 m)} ... scanning _{line, 32 (32 1 ~32 m)} ... power supply _{line, 33 (33 1 ~33 n)} ... signal line, 34 ... Common power supply line, 40 ... write scanning circuit, 41 ... shift register, 42 ... level shift circuit, 43 ... output circuit, 431 _{1 to} 431 _i ... buffer, 50 ... power supply scanning circuit, 60 ... signal output circuit, 70 ... Display panel

Claims (13)

Two switch elements connected in series between two power supplies and performing ON / OFF operations complementarily according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The other power source of the two power sources can be switched between a plurality of power source voltages. The pulse generation circuit according to claim 1, wherein the other power source of the two power sources switches a power source voltage in synchronization with a switching timing of the two switch elements. The pulse generation circuit according to claim 2, wherein the other power source of the two power sources switches the power source voltage at the same timing as the switching timing of the two switch elements. The pulse generation circuit according to claim 1, wherein the two switch elements are a P-channel MOS transistor and an N-channel MOS transistor. The pulse generation circuit according to claim 4, wherein the two switch elements constitute a CMOS inverter. The pulse generation circuit according to claim 4, wherein the other power source delays the transition speed of the output pulse by the action of a potential jumping into the circuit output terminal at the switching timing. The pulse generation according to claim 6, wherein the potential jumps into the circuit output terminal by capacitive coupling due to a parasitic capacitance interposed between a source electrode of the P-channel MOS transistor or the N-channel MOS transistor and the circuit output terminal. circuit. Consists of multiple cascaded buffers,
The last stage buffer of the plurality of buffers is configured by the two switch elements,
The pulse generation circuit according to claim 1, wherein the other power source is separated from the other power source of the preceding buffer. In pulse generation in a pulse generation circuit having two switch elements connected in series between two power supplies and performing on / off operations complementarily according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
A pulse generation method for switching the other power source of the two power sources between a plurality of power source voltages. Two switch elements connected in series between two power supplies and performing ON / OFF operations complementarily according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The other power source of the two power sources can be switched between a plurality of power source voltages. A scanning circuit using a pulse generation circuit as a final stage buffer that outputs a scanning pulse. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
A scanning circuit that scans each pixel of the pixel array unit,
As the final stage buffer of the output circuit, the scanning circuit,
Two switch elements connected in series between two power supplies and performing ON / OFF operations complementarily according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The display device using a pulse generation circuit, wherein the other power source of the two power sources can be switched between a plurality of power source voltages. The pixel has a mobility that corrects the mobility of the driving transistor by applying negative feedback to the potential difference between the gate and the source of the driving transistor with a correction amount corresponding to the current flowing through the driving transistor that drives the electro-optical element. Has the function of correction,
The display device according to claim 11, wherein the scanning circuit drives a writing transistor that writes a signal to a gate of the driving transistor by a scanning pulse generated by the pulse generation circuit. A pixel array unit in which pixels are two-dimensionally arranged in a matrix,
A scanning circuit that scans each pixel of the pixel array unit,
The scanning circuit, as its final stage buffer,
Two switch elements connected in series between two power supplies and performing ON / OFF operations complementarily according to the logic of the input pulse,
Of the two power supplies, one power supply on the same polarity side as the input pulse is a fixed power supply voltage,
The other power source of the two power sources can be switched between a plurality of power source voltages. Electronic equipment having a display device using a pulse generation circuit.

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