KR20130046149A - Light emitting diode display - Google Patents

Abstract

PURPOSE: An LED display device is provided to correct electron mobility characteristic deviations of operating switching elements by reducing source voltage changes by reducing gate-source voltages. CONSTITUTION: A data switching element(Tr_DS) is controlled according to a scan signal of a scan line. A merge switching element(Tr_MG) is controlled according to a merge signal of a merge line. An operating switching element(Tr_DR) is controlled according to a voltage of a second node. A light emitting control switching element(Tr_EM) is controlled according to a light emitting control signal of a light emitting control line. A reset switching element(Tr_RS) is controlled according to a reset signal of a reset line.

Description

Light emitting diode display device {LIGHT EMITTING DIODE DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode display device, and more particularly, to a light emitting diode display device capable of improving image quality by reducing variation in electron mobility characteristics between driving switching elements.

The pixels of the light emitting diode display include a driving switching element which is a constant current element. The current driving capability of the driving switching elements of these pixels is greatly influenced by their electron mobility characteristics. Therefore, reducing the electron mobility characteristic deviation among these driving switching elements is essential to improve the image quality of the display device.

In the related art, since the magnitude of the gate-source voltage applied to the driving switching element during the correction time is large, the amount of change in the source voltage is inevitably large, and thus, the correction time should be set as short as possible. That is, in the related art, when the correction time is long, the source voltage is rapidly saturated to a specific voltage because the source voltage change amount is large, and thus the electron mobility characteristic of the driving switching device is not properly corrected. Therefore, conventionally, this correction time has to be set considerably shorter.

However, if the correction time is set short, the following problem occurs.

That is, as the display device becomes larger, the length of the scan line increases, so that the resistance and capacitance components of the scan line also increase. Then, a deviation occurs in the arrival time to the target voltage (the voltage in the active state) between the scan signal supplied to the pixel connected to the front end of this scan line and the scan signal supplied to the pixel connected to the rear end of this scan line, and the gate Delay occurs. If this gate delay occurs, the scan signal does not reach the target voltage within the correction time, and thus the electron mobility characteristic of the driving switching element cannot be corrected within the above-described correction time.

Accordingly, there is still a problem in that a current difference in current driving capability between the driving switching elements is still present, resulting in a luminance difference between each pixel, thereby degrading image quality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and even if the correction time is set longer than before, the gate-source voltage of the driving switching element is reduced by using a capacitor to reduce the source voltage variation. It is an object of the present invention to provide a light emitting diode display device capable of correcting mobility characteristic deviations.

A light emitting diode display device according to the present invention for achieving the above object includes a plurality of pixels for displaying an image; A data switching element in which each pixel is controlled according to a scan signal from the scan line, and connected between the data line and the first node; A merge switching device controlled according to a merge signal from a merge line and connected between the first node and a second node; A driving switching element controlled according to the voltage of the second node and connected between a third node and a fourth node; A light emission control switching element controlled according to a light emission control signal from the light emission control line and connected between the first drive line for transmitting a first drive voltage and the third node; A light emitting diode connected between the fourth node and a second driving line transmitting a second driving voltage; A reset switching element controlled according to a reset signal from a reset line and connected to a third driving line for transmitting a third driving voltage to the fourth node; An initialization switching element controlled according to an initialization signal from an initialization line and connected between the first node and a reference line for transmitting a reference voltage; A first capacitor connected between the first node and the third node; A second capacitor connected to the first driving line and the third node; And a third capacitor connected between the first node and the second node; The light emission control signal, reset signal, initialization signal, merge signal, and scan signal change to an active state or an inactive state based on a threshold voltage detection period, a data write / mobility correction period, and a light emission period that are sequentially generated; The merge switching device is turned on during the threshold voltage detection period so that the initialization voltage is applied to the second node so that the threshold voltage of the driving switching device is stored between the second node and the third node; The data switching device is turned on during the data / write mobility correction period, a merge switching device is turned off, and a data signal is applied to the second node so that the third node is driven by the current of the fourth node. It is characterized in that the potential of.

The reset signal, the initialization signal and the merge signal are kept in an active state during the threshold voltage detection period, while the light emission control signal and the scan signal are kept in an inactive state; The reset signal and the scan signal remain active during the data write / mobility correction period, while the light emission control signal, the initialization signal and the merge signal remain in an inactive state; The light emission control signal and the merge signal are kept in an active state during the light emission period, while the reset signal, the initialization signal and the scan signal are kept in an inactive state; The data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period.

The reset signal is maintained in an active state during the threshold voltage detection period, the emission control signal is maintained in an inactive state, the initialization signal has an active state and an inactive state sequentially, and the scan signal is sequentially Has an inactive state and an active state; The reset signal and the scan signal remain active during the data write / mobility correction period, while the light emission control signal, the initialization signal and the merge signal remain in an inactive state; The light emission control signal and the merge signal are kept in an active state during the light emission period, while the reset signal, the initialization signal and the scan signal are kept in an inactive state; The data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period.

The length of the period during which the initialization signal remains active during the threshold voltage detection period is longer than the length of the period during which the initialization signal remains inactive; The length of the period during which the scan signal remains inactive during the threshold voltage detection period is longer than the length of the period during which the scan signal remains active; The length of the period during which the initialization signal remains active during the threshold voltage detection period is equal to the length of the period during which the scan signal remains active during the threshold voltage detection period and the data write / mobility correction period. It features.

the nth (n is a natural number) pixel and the n + 1th pixel sequentially display images; Phases of the scan signal supplied to the nth pixel and the initialization signal supplied to the n + 1th pixel are the same; The scan line connected to the data switching device of the n th pixel and the initialization line connected to the initialization switching device of the n + 1 th pixel are connected to each other.

The data switching device, the merge switching device, the driving switching device, the light emission control switching device, the reset switching device and the initialization switching device are all p-type transistors.

The relationship between the first driving voltage, the second driving voltage, the third driving voltage, the threshold voltage of the driving switching element, and the threshold voltage of the light emitting element satisfies Equation 1 and Equation 2 below.

(1)

(First driving voltage-reference power supply)> (threshold voltage-reference voltage of the driving switching element);

(2)

(Third drive voltage-second drive voltage) < (threshold voltage-second drive voltage of light emitting element).

Still another light emitting diode display device according to the present invention for achieving the above object includes a plurality of pixels for displaying an image; A data switching element in which each pixel is controlled according to a scan signal from the scan line, and connected between the data line and the first node; A merge switching device controlled according to a merge signal from a merge line and connected between the first node and a second node; A driving switching element controlled according to the voltage of the second node and connected between the first driving line and a third node for transmitting a first driving voltage; A light emitting diode connected between the third node and a second driving line transmitting a second driving voltage; A reset switching element controlled according to a reset signal from a reset line and connected between the third node and a third drive line for transmitting a third drive voltage; An initialization switching element controlled according to an initialization signal from an initialization line and connected between the first node and a reference line for transmitting a reference voltage; A first capacitor connected between the first node and the third node; A second capacitor connected between the third node and a second drive line; And a third capacitor connected between the first node and the second node; The reset signal, initialization signal, merge signal, and scan signal change to an active state or an inactive state based on sequentially generated initialization period, threshold voltage detection period, data write / mobility correction period, and light emission period; The merge switching device is turned on during the threshold voltage detection period so that the initialization voltage is applied to the second node so that the threshold voltage of the driving switching device is stored between the second node and the third node; The data switching device is turned on during the data / write mobility correction period, a merge switching device is turned off, and a data signal is applied to the second node so that the third node is driven by the current of the fourth node. It is characterized in that the potential of.

The reset signal, the initialization signal and the merge signal are kept in an active state during the initialization period, while the scan signal is kept in an inactive state; The initialization signal and the merge signal remain active during the threshold voltage detection period, while the reset signal and scan signal remain in an inactive state; The scan signal remains active during the data write / mobility correction period, while the reset signal, initialization signal, and merge signal remain inactive; The merge signal is kept in an active state during the light emitting period, while the reset signal, initialization signal and scan signal are kept in an inactive state; The data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period.

The reset signal, the initialization signal and the merge signal are kept in an active state during the initialization period, while the scan signal is kept in an inactive state; The reset signal is maintained in an inactive state during the threshold voltage detection period, the initialization signal has an active state and an inactive state sequentially, the merge signal has an active state and an inactive state sequentially, and the scan The signals sequentially have an inactive state and an active state; The scan signal remains active during the data write / mobility correction period, while the reset signal, initialization signal, and merge signal remain inactive; The merge signal is kept in an active state during the light emitting period, while the reset signal, initialization signal and scan signal are kept in an inactive state; The data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period.

The length of the period during which the initialization signal remains active during the threshold voltage detection period is longer than the length of the period during which the initialization signal remains inactive; The length of the period during which the scan signal remains inactive during the threshold voltage detection period is longer than the length of the period during which the scan signal remains active; And a length of a period during which the initialization signal remains active during the initialization period and a threshold voltage detection period, and a length of a period during which the scan signal remains active during the threshold voltage detection period and a data write / mobility correction period. Is characterized by the same.

the nth (n is a natural number) pixel and the n + 1th pixel sequentially display images; Phases of the scan signal supplied to the nth pixel and the initialization signal supplied to the n + 1th pixel are the same; The scan line connected to the data switching device of the n th pixel and the initialization line connected to the initialization switching device of the n + 1 th pixel are connected to each other.

The data switching element, the merge switching element, the driving switching element, the reset switching element and the initialization switching element are all characterized in that the n-type transistor.

The relationship between the third driving voltage, the reference voltage, the threshold voltage of the driving switching element, and the threshold voltage of the light emitting element satisfies Equation 3 below.

(Equation 3)

Third drive voltage <(threshold voltage-threshold voltage of drive switching element) <threshold voltage of light emitting diode.

The light emitting diode display device according to the present invention has the following effects.

First, in the present invention, the saturation time of the source voltage can be delayed by reducing the gate-source voltage of the driving switching element by using the third capacitor and the parasitic capacitor to reduce the source voltage change amount, thereby making the correction time more accurate than before. Even if it is set long, the deviation of the electron mobility characteristic of a drive switching element can be corrected. As a result, the target voltage (the voltage in the active state) between the scan signal supplied to the pixel connected to the front end of the scan line and the scan signal supplied to the pixel connected to the rear end of the scan line by the resistance and capacitance components of the scan line. Even if a deviation occurs in the arrival time of, it is possible to minimize the correction error due to this deviation by increasing the above-described correction time.

Second, since the third capacitor is removed and the original data signal is multiplied by an integer during the light emission period, the driving switching element is applied to the driving switching element by the gate-source voltage, so that linearity between the data signal and the current (correction current) can be maintained.

1 is a view showing a light emitting diode display device according to an embodiment of the present invention;
2 is a diagram showing a circuit configuration of a pixel according to a first embodiment of the present invention.
3 is a timing diagram of a light emission control signal, a reset signal, an initialization signal, a merge signal, a scan signal, and a data signal supplied to the pixel of FIG.
4A to 4C are diagrams for describing an operation of a pixel according to an exemplary embodiment of the present invention.
5 is a diagram illustrating another timing diagram of a light emission control signal, a reset signal, an initialization signal, a merge signal, and a scan signal supplied to the pixel of FIG.
FIG. 6 is a timing diagram of applied signals of respective pixels when the signals of FIG. 5 are supplied to a plurality of pixels arranged vertically.
7 illustrates a circuit configuration of a pixel according to a second embodiment of the present invention.
8 is a timing diagram of a reset signal, an initialization signal, a merge signal, a scan signal, and a data signal supplied to the pixel of FIG. 2.
9 is a diagram illustrating another timing diagram of a reset signal, an initialization signal, a merge signal, and a scan signal supplied to the pixel of FIG. 7.
FIG. 10 is a timing diagram of applied signals for each pixel when the signals of FIG. 9 are supplied to a plurality of pixels arranged vertically.
11 is a view for explaining the effect of the present invention.

1 is a view showing a light emitting diode display device according to an embodiment of the present invention.

As shown in FIG. 1, a light emitting diode display device according to an exemplary embodiment of the present invention includes a display unit DSP, a system SYS, a control driver CD, a data driver DD, a timing controller TC, and a power supply. It includes a supply unit (PS).

The display unit DSP includes a plurality of pixels PXL, a plurality of scan lines SL1 through SLi for transmitting a plurality of scan signals for sequentially driving the pixels PXL in units of horizontal lines, and a plurality of data. Lines DL1 to DLj and power supply lines. Although not shown, the display part DSP further includes a plurality of initialization lines, reset lines, merge lines, and light emission control lines. Here, the number of scan lines, the number of initialization lines, the number of reset lines, the number of merge lines, and the number of emission control lines may be the same.

These pixels PXL are arranged in a matrix on the display unit DSP. The pixels PXL are divided into a red pixel PXL displaying red, a green pixel PXL displaying green, and a blue pixel PXL displaying blue.

The system SYS outputs the vertical synchronization signal, the horizontal synchronization signal, the clock signal, and the image data through the interface circuit through a low voltage differential signaling (LVDS) transmitter of the graphic controller. The vertical / horizontal synchronizing signal and the clock signal output from the system SYS are supplied to the timing controller TC. In addition, image data sequentially output from the system SYS is supplied to the timing controller TC.

The timing controller TC generates a data control signal, a scan control signal, and a light emission control signal by using the horizontal synchronizing signal, the vertical synchronizing signal, and the clock signal inputted to the data controller DD and the control driver CD. Supply.

After the data driver DD samples the image data according to the data control signal from the timing controller TC, a sampling image corresponding to one horizontal line every horizontal time (1H, 2H, ...) The data are latched and the latched image data is supplied to the data lines DL1 to DLj. That is, the data driver DD converts the image data from the timing controller TC into an analog pixel signal (data signal) by using the gamma voltage input from the power supply unit PS to the data lines DL1 to DLj. Supply.

The control driver CD outputs scan pulses, initialization signals, reset signals, merge signals, and light emission control signals according to the control signal from the timing controller TC. In this case, the control driver sequentially outputs i scan signals from the first scan signal to the i-th scan signal every frame, and sequentially outputs i initialization signals from the first initialization signal to the i-th initialization signal every frame. And outputs i reset signals sequentially from the first reset signal to the i reset signal every frame, and sequentially outputs the i merge signals from the first merge signal to the i-th merge signal every frame. In addition, the i emission control signals are sequentially output from the first emission control signal to the i th emission control signal every frame, and the i detection signals are sequentially output from the first detection signal to the i th detection signal every frame. do.

The power supply PS generates a gamma voltage, a first driving voltage Vdd, a second driving voltage Vss, a third driving voltage Voff, and a reference voltage Vref required for driving the pixel PXL.

In this case, the first driving voltage VDD may be a constant voltage of about 10 [V] or more, the second driving voltage VSS may be a constant voltage of 0 [V], and the third driving voltage Voff may be 0. It may be a constant voltage of [V] to 2 [V], and the reference voltage (Vref) may be a constant voltage having a magnitude of 8 [V]. On the other hand, the data signal supplied to the data line may have a voltage of 0 [V] to 7 [V] depending on the gray level.

1st Example

FIG. 2 is a diagram showing a circuit configuration of a pixel according to the first embodiment of the present invention, and FIG. 2 is a diagram showing a circuit configuration included in any one pixel of FIG.

As illustrated in FIG. 2, one pixel PXL includes a data switching device Tr_DS, a merge switching device Tr_MG, a driving switching device Tr_DR, a light emission control switching device Tr_EM, and a reset switching device Tr_RS. ), An initialization switching device Tr_IT, a light emitting diode OLED, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

The data switching element Tr_DS is controlled according to the scan signal SC from the scan line and is connected between the data line DL and the first node N1.

The merge switching element Tr_MG is controlled according to the merge signal MG from the merge line and is connected between the first node N1 and the second node N2.

The driving switching element Tr_DR is controlled according to the voltage of the second node N2 and is connected between the third node N3 and the fourth node N4.

The light emission control switching element Tr_EM is controlled according to the light emission control signal EM from the light emission control line, and is connected between the first drive line and the third node N3. The first driving voltage Vdd generated from the first driving power source is applied to the first driving line.

The reset switching element Tr_RS is controlled according to the reset signal RS from the reset line and is connected to the fourth node N4 and the third driving line. The third driving line Voff generated from the third driving power source is applied to the third driving line.

The initialization switching element Tr_IT is controlled according to the initialization signal IT from the initialization line and is connected between the first node N1 and the reference line. The reference voltage Vref generated from the reference power source is applied to this reference line.

The light emitting diode OLED is connected between the fourth node N4 and the second driving line. That is, the anode electrode of the light emitting diode OLED is connected to the fourth node N4, and the cathode electrode is connected to the second driving line. The second driving line Vss generated from the second driving power source is applied to the second driving line.

The first capacitor C1 is connected between the first node N1 and the third node N3.

The second capacitor C2 is connected to the first driving line and the third node N3.

The third capacitor C3 is connected between the first node N1 and the second node N2.

3 is a timing diagram of an emission control signal EM, a reset signal RS, an initialization signal IT, a merge signal MG, a scan signal SC, and a data signal Vdata supplied to the pixel of FIG. 2; And it is a figure which shows the voltage of each node.

As shown in FIG. 3, the emission control signal EM, the reset signal RS, the initialization signal IT, the merge signal MG, and the scan signal SC are sequentially generated threshold voltage detection periods Tth. It changes to an active state or an inactive state based on the data write / mobility correction period Td / m and the light emission period Te. Herein, the active state of a signal means a state in which the signal can be turned on when the signal is supplied to the corresponding switching element. On the other hand, the inactive state of a signal means a state in which the signal can be turned off when the signal is supplied to the switching device. For example, when the switching element is p type, the active state of the signal supplied thereto means a low level voltage having a relatively low potential. On the other hand, the inactive state means a high level voltage having a relatively high potential.

During the threshold voltage detection period Tth, the reset signal RS, the initialization signal IT, and the merge signal MG are maintained in an active state (a low level voltage). On the other hand, during this period, the light emission control signal EM and the scan signal SC remain in an inactive state (high level voltage).

During the data write / mobility correction period Td / m, the reset signal RS and the scan signal SC are maintained in an active state (a low level voltage). On the other hand, during this period, the light emission control signal EM, the initialization signal IT and the merge signal MG remain in an inactive state (high level voltage). On the other hand, the data signal Vdata corresponding to the pixel is supplied to the data line DL during the data write / mobility correction period Td / m.

During the light emission period Te, the light emission control signal EM and the merge signal MG are maintained in an active state (a low level voltage). On the other hand, during this period, the reset signal RS, the initialization signal IT and the scan signal SC remain in an inactive state (high level voltage).

In FIG. 3, V_N3 denotes the voltage of the third node N3, V_N2 denotes the voltage of the second node N2, and V_N1 denotes the voltage of the first node N1.

Hereinafter, the operation of the pixel according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3, and FIGS. 4A to 4C.

4A to 4C are diagrams for describing an operation of a pixel according to an exemplary embodiment of the present invention.

1) Threshold voltage detection period ( Tth )

First, referring to FIGS. 2, 3, and 4A, the operation of a pixel in the threshold voltage detection period Tth will be described.

During the threshold voltage detection period Tth, as shown in FIG. 3, the reset signal RS, the initialization signal IT, and the merge signal MG remain in an active state. On the other hand, the emission control signal EM and the scan signal SC remain inactive during this period.

In response to these signals, the reset switching element Tr_RS receives the reset signal RS in the active state, the initialization switch Tr_IT receives the initialization signal IT in the active state, and the merge signal MG in the active state. ) Is supplied with the merge switching element Tr_MG. On the other hand, the light emission control switching device Tr_EM supplied with the light emission control signal EM in the inactive state and the data switching device Tr_DS supplied with the scan signal SC in the inactive state are turned off. Therefore, the circuit of FIG. 2 may be represented by an equivalent circuit as shown in FIG. 4A.

That is, as shown in FIG. 4A, the voltage of the first node N1 (or the second node N2) is changed to the level of the reference voltage Vref. On the other hand, the third node N3 has been maintained at the first driving voltage Vdd applied during the light emission period Te in the previous frame. Accordingly, the reference voltage Vref is applied to the gate electrode of the driving switching element Tr_DR, and the first driving voltage Vdd is applied to the source electrode of the driving switching element Tr_DR. At this time, the difference voltage Vdd-Vref between the first driving voltage Vdd and the reference voltage Vref is set larger than the difference voltage Vthdr-Vref between the threshold voltage of the driving switching element Tr_DR and the reference voltage Vref. Therefore, this driving switching element Tr_DR is turned on. As the charge moves from the third node N3 to the fourth node N4 through the turned-on driving switching element Tr_DR, the voltage of the third node N3 drops. The voltage of the third node N3 gradually drops so that the voltage between the gate electrode and the source electrode of the driving switching device Tr_DR (hereinafter, the gate-source voltage) becomes the threshold voltage Vth of the driving switching device Tr_DR. Upon reaching this drive switching element Tr_DR is turned off. At this time, the threshold voltage Vthdr of the driving switching device Tr_DR is stored in the first capacitor C1. As shown in FIG. 4A, the voltage of the first node N1 (or the second node N2) at the time when the driving switching device Tr_DR is turned on is maintained at the level of the reference voltage Vref. The voltage of the third node N3 is maintained at the level of the difference voltage Vref-Vth between the reference voltage Vref and the threshold voltage Vthdr of the driving switching element Tr_DR.

Meanwhile, the difference voltage Voff-Vref between the third driving voltage Voff and the second driving voltage Vss is the difference voltage Vthel between the threshold voltage Vthel and the second driving voltage Vss of the light emitting diode OLED. Since it is set smaller than -Vss, even when the driving switching device Tr_DR is turned on, no current is supplied to the light emitting diode OLED, so that the light emitting diode OLED is turned off during this threshold voltage detection period Tth. Maintain state. That is, the light emitting diode OLED does not emit light even if the driving switching element Tr_DR is turned on during this threshold voltage detection period Tth.

As such, the threshold voltage of the driving switching element Tr_DR is detected during the threshold voltage detection period Tth and stored in the first capacitor C1.

2) Data entry Of Mobility correction period ( Td / m)

Next, referring to FIGS. 2, 3, and 4B, the operation of the pixel in the data writing / mobility correction period Td / m will be described.

During the data write / mobility correction period Td / m, as shown in Fig. 3, the reset signal RS and the scan signal SC remain in an active state. On the other hand, during this period, the light emission control signal EM, the initialization signal IT and the merge signal MG remain in an inactive state. On the other hand, the data signal Vdata corresponding to the pixel is supplied to the data line DL during the data write / mobility correction period Td / m.

According to the signals, the reset switching device Tr_RS receiving the reset signal RS in the active state and the data switching device Tr_DS receiving the scan signal SC in the active state are turned on. On the other hand, the light emission control switching device Tr_EM receives the light emission control signal EM in the inactive state, the initialization switch device Tr_IT receiving the initialization signal IT in the inactive state and the merge signal MG in the inactive state. ). The merge switching element Tr_MG supplied with () is turned off. Therefore, the circuit of FIG. 2 may be represented by an equivalent circuit as shown in FIG. 4B.

That is, as the data signal Vdata is supplied to the first node N1 through the data line DL, the voltage of the first node N1 is the voltage Vdata obtained by adding the data signal Vdata and the reference voltage Vref. + Vref). That is, as shown in FIG. 3, the voltage of the first node N1 drops. At this time, the voltage of the second node N2 also decreases due to the coupling phenomenon by the third capacitor C3. As a result, the driving switching device Tr_DR is turned on.

As the driving switching element Tr_DR is turned on during the data writing / mobility correction period Td / m, the current Id flows through the turned-on driving switching element Tr_DR. The electron mobility of this driving switching element Tr_DR is affected. In other words, the potential of the source electrode N3 of the driving switching element Tr_DR changes in a direction proportional to the electron mobility characteristic of the driving switching element Tr_DR. For example, if the electron mobility characteristic of the driving switching element Tr_DR is not good, the source of the driving switching element Tr_DR during the correction time (the time corresponding to the length of the data writing / mobility correction period Td / m) Since the charge from the electrode N3 quickly escapes, the potential V_N3 of this source electrode N3 will decrease relatively more during this particular period. On the contrary, if the electron mobility characteristic of the driving switching element Tr_DR is good, the charge is slowly released from the source electrode N3 of the driving switching element Tr_DR during the correction time, so that the potential of the source electrode N3 is reduced. V_N3) will decrease relatively less. The gate-source voltage Vgs is corrected according to this source voltage change amount (reduction amount ΔV). That is, the gate-source voltage Vgs of the driving switching device Tr_DR having poor electron mobility characteristics will be relatively high, and conversely, the gate-source voltage Vgs of the driving switching device Tr_DR having good electron mobility characteristics will be increased. Will be relatively low. Accordingly, variation in driving current between driving switching elements Tr_DR having different electron mobility characteristics can be minimized. ΔV in FIG. 4B is a change in source voltage proportional to the electron mobility (μ) characteristic of the driving switching element Tr_DR, and is defined by Equation 1 below.

In Equation 1, Id denotes a current flowing through the driving switching element Tr_DR, Δt denotes a correction time described above, Cc2 denotes a capacitance of the second capacitor C2, and μ denotes an electron mobility. The specific time described above refers to the data write / mobility correction period Td / m, which means that the scan signal SC remains active.

As shown in Equation 1, the source voltage change amount ΔV is proportional to the current and the correction time, and is inversely proportional to the capacity of the second capacitor C2.

Meanwhile, the current Id flowing through the driving switching device Tr_DR may be represented by Equation 2 below.

In Equation 2, Cc3 denotes the capacitance of the third capacitor C3, Cpc denotes the capacitance of the parasitic capacitor, and β denotes the gain of the driving switching element Tr_DR.

In particular, according to the present invention, the magnitude of the gate-source voltage Vgs is smaller than the voltage of the data signal Vdata applied to the first node N1 during the data write / mobility correction period Td / m. That is, the parasitic capacitor Cp is formed between the gate electrode and the source electrode of the driving switching element Tr_DR, and the gate of the driving switching element Tr_DR is formed by the parasitic capacitor Cp and the third capacitor C3. The source voltage Vgs is maintained at a voltage smaller than the voltage of the data signal Vdata. That is, the gate-source voltage Vgs corresponds to a voltage obtained by dividing the voltage of the data signal Vdata by the capacitance of the third capacitor C3 and the capacitance of the parasitic capacitor Cp.

That is, this gate-source voltage Vgs is defined by the following equation.

As such, the gate-source voltage Vgs of the driving switching device Tr_DR is changed by the third capacitor C3 and the parasitic capacitor Cp during the data writing / mobility correction period Td / m. Since it becomes smaller than the voltage of the data signal Vdata applied to, the current (correction current) generated by this driving switching element Tr_DR can be made smaller than before. The small current means that the amount of change (tilt) of ΔV is reduced in accordance with Equation (1). This means that even if the correction time Δt is set long, the electron mobility characteristic deviation of the driving switching element Tr_DR can be stably corrected. That is, since the gate-source voltage Vgs applied to the driving switching element Tr_DR during the correction time is large, the source voltage change amount ΔV must be relatively large, and thus the correction time should be set as short as possible. There was a limitation. That is, in the related art, when the correction time is long, the source voltage change ΔV is large, so that the source voltage rapidly saturates to a specific voltage and the electron mobility characteristic of the driving switching element Tr_DR is not properly corrected.

However, in the present invention, the gate-source voltage Vgs of the driving switching device Tr_DR is reduced by using the third capacitor C3 and the parasitic capacitor Cp to reduce the source voltage change amount ΔV, thereby saturating the source voltage. Time can be delayed, and thus, even if the correction time is set longer than before, the electron mobility characteristic deviation of the driving switching element Tr_DR can be corrected. As a result, a target voltage (active) is generated between the scan signal SC supplied to the pixel connected to the front end of the scan line and the scan signal SC supplied to the pixel connected to the rear end of the scan line by the resistance and capacitance components of the scan line. Even if a deviation occurs in the arrival time to the state (voltage to the state), it is possible to minimize the correction error due to this deviation by increasing the above-described correction time.

3) emission period ( Te )

Next, referring to FIGS. 2, 3, and 4C, the operation of the pixel in the light emission period Te will be described.

During the data write / mobility correction period Td / m, as shown in Fig. 3, the light emission control signal EM and the merge signal MG remain in an active state. On the other hand, during this period, the reset signal RS, the initialization signal IT and the scan signal SC remain in an inactive state.

According to the signals, the light emission control switching device Tr_EM supplied with the active light emission control signal EM and the merge switching device Tr_MG supplied with the active merge signal MG are turned on. On the other hand, the reset switching device Tr_RS receives the reset signal RS in the inactive state, the initialization switching device Tr_IT receives the initialization signal IT in the inactive state, and the scan signal SC in the inactive state. The supplied t-scan switching element is turned off. Therefore, the circuit of FIG. 2 may be represented by an equivalent circuit as shown in FIG. 4C.

That is, the correction data voltage Vdata 'and the first driving voltage Vdd that are corrected according to the electron mobility characteristics are applied to the gate electrode (the first node N1 or the second node N2) of the driving switching element Tr_DR. The sum of the voltages Vdata` + Vdd is applied, the first driving voltage Vdd is applied to the source electrode (third node N3) of the driving switching element Tr_DR, and the driving switching element Tr_DR Is applied to the threshold voltage Vthel of the light emitting diode OLED. In this case, the gate-source voltage Vgs of the driving switching device Tr_DR during the light emission period Te may be expressed by Equation 4 below.

In Equation 4, k means a proportionality constant.

During this light emission period Te, the driving switching element Tr_DR is turned on by the correction data voltage Vdata` to generate a driving current. This driving current is supplied to the light emitting diode OLED, whereby the light emitting diode OLED emits light. In particular, during the light emitting period Te, the third capacitor C3 is removed from the circuit due to the turn-on of the switching device, so that the voltage of the data signal Vdata divided by the third capacitor C3 becomes original. The data signal Vdata is restored. To be precise, as shown in equation (4), this divided data signal Vdata is restored to a value obtained by multiplying the original data signal Vdata by an integer (1-k mu). As such, the third capacitor C3 is removed during this light emission period Te, and a value obtained by multiplying the original data signal Vdata by an integer is applied to the driving switching device Tr_DR by the gate-source voltage Vgs. Linearity between the data signal Vdata and the current (correction current) can be maintained.

Meanwhile, the pixel illustrated in FIG. 2 may receive the following signals instead of the signal illustrated in FIG. 3.

FIG. 5 is a diagram illustrating another timing diagram of the emission control signal EM, the reset signal RS, the initialization signal IT, the merge signal MG, and the scan signal SC supplied to the pixel of FIG. 2.

As shown in Fig. 5, during the threshold voltage detection period Tth, the reset signal RS is kept in an active state (low level voltage), and the light emission control signal EM is in an inactive state (high level voltage). Is maintained. During this period, the initialization signal IT sequentially has an active state (low level voltage) and an inactive state (high level voltage), and the scan signal SC is sequentially inactive (high level voltage). ) And an active state (a low level voltage).

During the data write / mobility correction period Td / m, the reset signal RS and the scan signal SC are maintained in an active state (a low level voltage). On the other hand, during this period, the light emission control signal EM, the initialization signal IT and the merge signal MG remain in an inactive state (high level voltage). At this time, the data signal Vdata corresponding to the pixel is supplied to the data line DL during the data write / mobility correction period Td / m.

During the light emission period Te, the light emission control signal EM and the merge signal MG are maintained in an active state (a low level voltage). On the other hand, during this period, the reset signal RS, the initialization signal IT and the scan signal SC remain in an inactive state (high level voltage).

On the other hand, during the threshold voltage detection period Tth, the length of the period during which the initialization signal IT is maintained in the active state (low voltage) maintains the initialization signal IT in the inactive state (high level voltage). It may be set longer than the length of the period.

Further, during the threshold voltage detection period Tth, the length of the period during which the scan signal SC is maintained in an inactive state (voltage of high level) is maintained in the scan signal SC in an active state (voltage of low level). It may be set longer than the length of the period.

In addition, during the threshold voltage detection period Tth, the length of the period during which the initialization signal IT is maintained in the active state (low-level voltage), the threshold voltage detection period Tth, and the data write / mobility correction period Td / During m), the length of the period during which the scan signal SC is maintained in an active state (a low level voltage) may be the same.

Meanwhile, the set of signals illustrated in FIG. 5 are applied at different timings for the pixels arranged in the vertical direction, which will be described in more detail with reference to FIG. 6.

6 is a diagram illustrating a timing diagram of applied signals for each pixel when the signals of FIG. 5 are supplied to a plurality of pixels arranged vertically.

The set of signals EM_n, RS_n, IT_n, MG_n, and SC_n shown in FIG. 6A are signals supplied to the n-th pixel, and the set of signals shown in FIG. EM_n + 1, RS_n + 1, IT_n + 1, MG_n + 1, SC_n + 1) are signals supplied to the n + 1th pixel. Here, the n th pixel refers to any one of j pixels located in the n th pixel row (commonly connected to the n th scan line), and the n + 1 th pixel is located in the n + 1 th pixel row (n th One of j pixels (commonly connected to a +1 scan line).

As shown in FIG. 6, it can be seen that scan signals SC_n and SC_n + 1 to be supplied to each pixel are sequentially output. Specifically, it can be seen that the scan signal SC_n + 1 supplied to the n + 1th pixel is output later than the scan signal SC_n supplied to the nth pixel. As described above, the scan signals SC_n and SC_n + 1 for each pixel are delayed and output by the pulse width in the active state. Similarly, other signals, that is, the emission control signals EM_n and EM_n + 1, the reset signals RS_n and RS_n + 1, the initialization signals IT_n and IT_n + 1 and the merge signals MG_n and MG_n + 1. The pixel is delayed by one pulse width of the scan signal for each pixel and output.

As the set of signals are delayed and output in every horizontal period, the output timing of the scan signal SC supplied to one pixel and the output timing of the initialization signal IT supplied to any other pixel are different. In this case, two different signals may be commonly output through a single line.

That is, as shown in FIG. 6, the output timing of the scan signal SC_n supplied to the n-th pixel and the output timing of the initialization signal IT_n + 1 supplied to the n + 1 th pixel located later than this pixel. This coincides with each other and the pulse width of the scan signal SC_n in the active state and the pulse width of the initialization signal IT_n + 1 in the active state. As such, when the output timings of the different types of signals supplied to two different pixels are identical and the pulse widths are the same, for example, the scan signal SC_n supplied to the nth pixel and the n + 1th pixel are provided. The supplied initialization signal IT_n + 1 may be supplied through the same line. That is, the scan signal SC_n supplied to the nth pixel is transmitted by the nth scan line, and the initialization signal IT_n + 1 supplied to the n + 1th pixel is transmitted by the n + 1 initialization line. In this case, the scan signal SC_n and the initialization signal INT_n + 1 may be simultaneously transmitted using only one of the nth scan line and the n + 1th initialization lines. In such a case, the side effect of reducing the size and cost of the circuit is generated by removing any unused line from the circuit.

Second Example

FIG. 7 is a diagram showing a circuit configuration of a pixel according to the second embodiment of the present invention, and FIG. 7 is a diagram showing a circuit configuration included in any one pixel of FIG.

As illustrated in FIG. 7, one pixel includes a data switching device Tr_DS, a merge switching device Tr_MG, a driving switching device Tr_DR, a reset switching device Tr_RS, an initialization switching device Tr_IT, and a light emitting diode. OLED, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

The data switching element Tr_DS is controlled according to the scan signal SC from the scan line and is connected between the data line DL and the first node N1.

The merge switching element Tr_MG is controlled according to the merge signal MG from the merge line and is connected between the first node N1 and the second node N2.

The driving switching element Tr_DR is controlled according to the voltage of the second node N2 and is connected between the first driving line and the third node N3. The first driving voltage Vdd generated from the first driving power source is applied to the first driving line.

The reset switching element Tr_RS is controlled according to the reset signal RS from the reset line and is connected between the third node N3 and the third driving line. The third driving line Voff generated from the third driving power source is applied to the third driving line.

The initialization switching element Tr_IT is controlled according to the initialization signal IT from the initialization line and is connected between the first node N1 and the reference line for transmitting the reference voltage Vref. The reference voltage Vref generated from the reference power source is applied to this reference line.

The light emitting diode OLED is connected between the third node N3 and the second driving line. That is, the anode electrode of the light emitting diode OLED is connected to the third node N3, and the cathode electrode is connected to the second driving line. The second driving line Vss generated from the second driving power source is applied to the second driving line.

The first capacitor C1 is connected between the first node N1 and the third node N3.

The second capacitor C2 is connected between the third node N3 and the second driving line.

The third capacitor C3 is connected between the first node N1 and the second node N2.

FIG. 8 is a timing diagram illustrating a reset signal RS, an initialization signal IT, a merge signal MG, a scan signal SC, and a data signal Vdata supplied to the pixel of FIG. 2.

As shown in FIG. 8, the reset signal RS, the initialization signal IT, the merge signal MG, and the scan signal SC are sequentially generated an initialization period Tit, a threshold voltage detection period Tth, It changes to an active state or an inactive state based on the data write / mobility correction period Td / m and the light emission period Te. Herein, the active state of a signal means a state in which the signal can be turned on when the signal is supplied to the corresponding switching element. On the other hand, the inactive state of a signal means a state in which the signal can be turned off when the signal is supplied to the switching device. For example, when the switching element is n type, the active state of the signal supplied thereto means a high level voltage having a relatively high potential. On the other hand, the inactive state refers to a low level voltage having a relatively low potential.

During the initialization period Tit, the reset signal RS, the initialization signal IT, and the merge signal MG are maintained in an active state (high level voltage). On the other hand, during this period, the scan signal SC is kept in an inactive state (voltage at a low level).

During the threshold voltage detection period Tth, the initialization signal IT and the merge signal MG are maintained in an active state (high level voltage). On the other hand, during this period, the reset signal RS and the scan signal SC remain in an inactive state (a low level voltage).

During the data write / mobility correction period Td / m, the scan signal SC is maintained in an active state (high level voltage). On the other hand, during this period, the reset signal RS, the initialization signal IT, and the merge signal MG remain in an inactive state (a low level voltage). Meanwhile, the data signal Vdata corresponding to the pixel is supplied to the data line DL during the data writing / mobility correction period Td / m.

During the light emission period Te, the merge signal MG is maintained in an active state (high level voltage). On the other hand, the reset signal RS, the initialization signal IT and the scan signal SC are maintained in an inactive state (a low level voltage).

Meanwhile, the difference voltage Vref-Vthrd between the reference voltage Vref and the threshold voltage of the driving switching element Tr_DR is set to be greater than the third driving voltage Voff and smaller than the threshold voltage Vthel of the light emitting diode OLED. do.

The circuit of the pixel according to the second embodiment also performs the same operation as the circuit of the pixel according to the first embodiment described above. Thus, the circuit of the pixel according to the second embodiment also has the same effect as the circuit of the pixel of the first embodiment.

Meanwhile, the pixel shown in FIG. 7 may receive the following signals instead of the signal shown in FIG. 8.

FIG. 9 is a diagram illustrating another timing diagram of the reset signal RS, the initialization signal IT, the merge signal MG, and the scan signal SC supplied to the pixel of FIG. 7.

As illustrated in FIG. 9, the reset signal RS, the initialization signal IT, and the merge signal MG are maintained in an active state (high level voltage) during the initialization period Tit. On the other hand, during this period, the scan signal SC is kept in an inactive state (voltage at a low level).

The reset signal RS is maintained in an inactive state during the threshold voltage detection period Tth. During this period, the initialization signal IT sequentially has an active state (high level voltage) and an inactive state (low level voltage), and the merge signal is sequentially an active state (high level voltage) and inactive state. (Low level voltage), and the scan signal SC sequentially has an inactive state (low level voltage) and an active state (high level voltage).

During the data write / mobility correction period Td / m, the scan signal SC is maintained in an active state (high level voltage). On the other hand, during this period, the reset signal RS, the initialization signal IT, and the merge signal MG remain in an inactive state (a low level voltage). Meanwhile, the data signal Vdata corresponding to the pixel is supplied to the data line DL during the data writing / mobility correction period Td / m.

During the light emission period Te, the merge signal MG is maintained in an active state (high level voltage). On the other hand, during this period, the reset signal RS, the initialization signal IT, and the scan signal SC remain in an inactive state (low level voltage).

At this time, during the threshold voltage detection period Tth, the length of the period during which the initialization signal IT is maintained in an active state (voltage of high level) is maintained in the initialization signal IT in an inactive state (voltage of low level). It may be longer than the length of the period.

Further, during the threshold voltage detection period Tth, the length of the period during which the scan signal SC is maintained in an inactive state (low level voltage) is such that the scan signal SC is maintained in an active state (high level voltage). It can be longer than the length of the period.

In addition, during the initialization period Tit and the threshold voltage detection period Tth, the length of the period during which the initialization signal IT is maintained in an active state (voltage of a high level), the threshold voltage detection period Tth, and the data write / movement During the walking period Td / m, the length of the period during which the scan signal SC is maintained in an active state (voltage of a high level) may be the same.

Meanwhile, the set of signals illustrated in FIG. 9 are applied at different timings for the pixels arranged in the vertical direction, which will be described in more detail with reference to FIG. 10.

FIG. 10 is a diagram illustrating a timing diagram of signals applied to each pixel when the signals of FIG. 9 are supplied to a plurality of pixels arranged vertically.

The set of signals RS_n, IT_n, SC_n, and MG_n shown in FIG. 10A are signals supplied to the n-th pixel, and the set of signals RS_n + shown in FIG. 10B. 1, IT_n + 1, SC_n + 1, and MG_n + 1) are signals supplied to the n + 1th pixel. Here, the n th pixel refers to any one of j pixels located in the n th pixel row (commonly connected to the n th scan line), and the n + 1 th pixel is located in the n + 1 th pixel row (n th One of j pixels (commonly connected to a +1 scan line).

As shown in FIG. 10, it can be seen that scan signals SC_n and SC_n + 1 to be supplied to each pixel are sequentially output. Specifically, it can be seen that the scan signal SC_n + 1 supplied to the n + 1th pixel is output later than the scan signal SC_n supplied to the nth pixel. As described above, the scan signals SC_n and SC_n + 1 for each pixel are delayed and output by the pulse width in the active state. Similarly, other signals, that is, reset signals RS_n and RS_n + 1, initialization signals IT_n and IT_n + 1, and merge signals MG_n and MG_n + 1, are also delayed by one pulse width of the scan signal for each pixel. And output.

As the set of signals are delayed and output in every horizontal period, the output timing of the scan signal SC supplied to one pixel and the output timing of the initialization signal IT supplied to any other pixel are different. In this case, two different signals may be commonly output through a single line.

That is, as shown in FIG. 10, the output timing of the scan signal SC_n supplied to the n-th pixel and the output timing of the initialization signal IT_n + 1 supplied to the n + 1th pixel located later than this pixel. This coincides with each other and the pulse width of the scan signal SC_n in the active state and the pulse width of the initialization signal IT_n + 1 in the active state. As such, when the output timings of the different types of signals supplied to two different pixels are identical and the pulse widths are the same, for example, the scan signal SC_n supplied to the nth pixel and the n + 1th pixel are provided. The supplied initialization signal IT_n + 1 may be supplied through the same line. That is, the scan signal SC_n supplied to the nth pixel is transmitted by the nth scan line, and the initialization signal IT_n + 1 supplied to the n + 1th pixel is transmitted by the n + 1 initialization line. In this case, the scan signal SC_n and the initialization signal INT_n + 1 may be simultaneously transmitted using only one of the nth scan line and the n + 1th initialization lines. In such a case, the side effect of reducing the size and cost of the circuit is generated by removing any unused line from the circuit.

11 is a view for explaining the effect of the present invention.

FIG. 11A shows the voltage V1 of the first node N1, the voltage Vg of the gate electrode of the driving switching element Tr_DR, and the driving switching in the circuit configuration of the pixel according to the first embodiment of the present invention. FIG. 11B shows the voltage Vs of the source electrode of the element Tr_DR, and FIG. 11B shows the voltage V1 of the first node N1 and the driving switching element Tr_DR in the circuit configuration of the conventional pixel. A diagram showing the voltage Vs of the source electrode.

The gate delay means that the scan signal SC supplied to the scan line is delayed by the resistance and capacitance components of the scan line. In other words, as the gate delay increases, the time until the scan signal SC supplied to the scan line reaches the voltage corresponding to the active state and the time to reach the voltage corresponding to the inactive state are falling. time) increases.

As shown in FIG. 11A, according to the circuit of the pixel according to the first exemplary embodiment of the present invention, when the gate electrode has a low gate delay and a voltage Vs of the source electrode when the gate delay is high. It can be seen that the difference ΔVμ between the voltage Vs of the source electrode of the low gate delay is much smaller than in the related art. This means that the circuit of the pixel according to the present invention has a smaller correction error than in the prior art.

Meanwhile, the merge signal MG and the scan signal SC in FIG. 5 may have an inverted form. That is, the merge signal MG such that the length of the period during which the merge signal MG in the inactive state is kept in the inactive state is the same as the length of the period during which the scan signal SC in the FIG. 5 remains in the active state. ) May further extend the length of the pulse width (the pulse width corresponding to the period of the inactive state). In other words, the pulse width of the merge signal MG in FIG. 5 is further extended in the direction of the threshold voltage detection period Tth in order to further extend the length of the pulse width (the pulse width corresponding to the period of the inactive state). By setting the width (the pulse width corresponding to the period of the inactive state) and the length of the pulse width (the pulse width corresponding to the period of the active state) of the scan signal SC, the merge signal MG becomes the scan signal. It is also possible to have a form that is 180 degrees out of phase with respect to (SC).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

DL: data line Tr_DS: data switching element
Tr_MG: Merge Switching Device Tr_EM: Light Emitting Switching Device
Tr_DR: Drive Switching Device Tr_IT: Initial Switching Device
Tr_RS: Reset Switching Device SC: Scan Signal
MG: merge signal IT: reset signal
RS: reset signal EM: light emission control signal
Vdata: data signal Vref: reference voltage
Vdd: first drive voltage Vss: second drive voltage
Voff: third driving voltage N #: #th node
C #: capacitor # OLED: light emitting diode

Claims (14)

A plurality of pixels for displaying an image;
Each pixel,
A data switching element controlled according to a scan signal from the scan line and connected between the data line and the first node;
A merge switching device controlled according to a merge signal from a merge line and connected between the first node and a second node;
A driving switching element controlled according to the voltage of the second node and connected between a third node and a fourth node;
A light emission control switching element controlled according to a light emission control signal from the light emission control line and connected between the first drive line for transmitting a first drive voltage and the third node;
A light emitting diode connected between the fourth node and a second driving line transmitting a second driving voltage;
A reset switching element controlled according to a reset signal from a reset line and connected to a third driving line for transmitting a third driving voltage to the fourth node;
An initialization switching element controlled according to an initialization signal from an initialization line and connected between the first node and a reference line for transmitting a reference voltage;
A first capacitor connected between the first node and the third node;
A second capacitor connected to the first driving line and the third node; And
A third capacitor connected between the first node and the second node;
The light emission control signal, reset signal, initialization signal, merge signal, and scan signal change to an active state or an inactive state based on a threshold voltage detection period, a data write / mobility correction period, and a light emission period that are sequentially generated;
The merge switching device is turned on during the threshold voltage detection period so that the initialization voltage is applied to the second node so that the threshold voltage of the driving switching device is stored between the second node and the third node; And,
During the data / write mobility correction period, the data switching device is turned on and a merge switching device is turned off so that a data signal is applied to the second node so that the potential of the third node is caused by the current of the fourth node. Light emitting diode display device characterized in that the correction. The method of claim 1,
The reset signal, the initialization signal and the merge signal are kept in an active state during the threshold voltage detection period, while the light emission control signal and the scan signal are kept in an inactive state;
The reset signal and the scan signal remain active during the data write / mobility correction period, while the light emission control signal, the initialization signal and the merge signal remain in an inactive state;
The light emission control signal and the merge signal are kept in an active state during the light emission period, while the reset signal, the initialization signal and the scan signal are kept in an inactive state; And,
And a data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period. The method of claim 1,
The reset signal is maintained in an active state during the threshold voltage detection period, the emission control signal is maintained in an inactive state, the initialization signal has an active state and an inactive state sequentially, and the scan signal is sequentially Has an inactive state and an active state;
The reset signal and the scan signal remain active during the data write / mobility correction period, while the light emission control signal, the initialization signal and the merge signal remain in an inactive state;
The light emission control signal and the merge signal are kept in an active state during the light emission period, while the reset signal, the initialization signal and the scan signal are kept in an inactive state; And,
And a data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period. The method of claim 3, wherein
The length of the period during which the initialization signal remains active during the threshold voltage detection period is longer than the length of the period during which the initialization signal remains inactive;
The length of the period during which the scan signal remains inactive during the threshold voltage detection period is longer than the length of the period during which the scan signal remains active; And,
The length of the period during which the initialization signal remains active during the threshold voltage detection period is equal to the length of the period during which the scan signal remains active during the threshold voltage detection period and the data write / mobility correction period. Light emitting diode display device. The method of claim 4, wherein
the nth (n is a natural number) pixel and the n + 1th pixel sequentially display images;
Phases of the scan signal supplied to the nth pixel and the initialization signal supplied to the n + 1th pixel are the same; And,
And a scan line connected to the data switching element of the nth pixel and an initialization line connected to the initialization switching element of the n + 1th pixel. The method of claim 1,
And the data switching element, the merge switching element, the driving switching element, the light emission control switching element, the reset switching element and the initialization switching element are all p-type transistors. The method of claim 1,
Wherein the relationship between the first driving voltage, the second driving voltage, the third driving voltage, the threshold voltage of the driving switching element, and the threshold voltage of the light emitting element satisfies Equation 1 and Equation 2 below. ;
(Equation 1)
(First driving voltage-reference power supply)> (threshold voltage-reference voltage of the driving switching element);
(Equation 2)
(Third drive voltage-second drive voltage) < (threshold voltage-second drive voltage of light emitting element). A plurality of pixels for displaying an image;
Each pixel,
A data switching element controlled according to a scan signal from the scan line and connected between the data line and the first node;
A merge switching device controlled according to a merge signal from a merge line and connected between the first node and a second node;
A driving switching element controlled according to the voltage of the second node and connected between the first driving line and a third node for transmitting a first driving voltage;
A light emitting diode connected between the third node and a second driving line transmitting a second driving voltage;
A reset switching element controlled according to a reset signal from a reset line and connected between the third node and a third drive line for transmitting a third drive voltage;
An initialization switching element controlled according to an initialization signal from an initialization line and connected between the first node and a reference line for transmitting a reference voltage;
A first capacitor connected between the first node and the third node;
A second capacitor connected between the third node and a second drive line; And
A third capacitor connected between the first node and a second node;
The reset signal, initialization signal, merge signal, and scan signal change to an active state or an inactive state based on sequentially generated initialization period, threshold voltage detection period, data write / mobility correction period, and light emission period;
The merge switching device is turned on during the threshold voltage detection period so that the initialization voltage is applied to the second node so that the threshold voltage of the driving switching device is stored between the second node and the third node; And,
During the data / write mobility correction period, the data switching device is turned on and a merge switching device is turned off so that a data signal is applied to the second node so that the potential of the third node is caused by the current of the fourth node. Light emitting diode display device characterized in that the correction. The method of claim 8,
The reset signal, the initialization signal and the merge signal are kept in an active state during the initialization period, while the scan signal is kept in an inactive state;
The initialization signal and the merge signal remain active during the threshold voltage detection period, while the reset signal and scan signal remain in an inactive state;
The scan signal remains active during the data write / mobility correction period, while the reset signal, initialization signal, and merge signal remain inactive;
The merge signal is kept in an active state during the light emitting period, while the reset signal, initialization signal and scan signal are kept in an inactive state; And,
And a data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period. The method of claim 8,
The reset signal, the initialization signal and the merge signal are kept in an active state during the initialization period, while the scan signal is kept in an inactive state;
The reset signal is maintained in an inactive state during the threshold voltage detection period, the initialization signal has an active state and an inactive state sequentially, the merge signal has an active state and an inactive state sequentially, and the scan The signals sequentially have an inactive state and an active state;
The scan signal remains active during the data write / mobility correction period, while the reset signal, initialization signal, and merge signal remain inactive;
The merge signal is kept in an active state during the light emitting period, while the reset signal, initialization signal and scan signal are kept in an inactive state; And,
And a data signal corresponding to the pixel is supplied to the data line during the data writing / mobility correction period. 11. The method of claim 10,
The length of the period during which the initialization signal remains active during the threshold voltage detection period is longer than the length of the period during which the initialization signal remains inactive;
The length of the period during which the scan signal remains inactive during the threshold voltage detection period is longer than the length of the period during which the scan signal remains active; And,
The length of the period during which the initialization signal remains active during the initialization period and the threshold voltage detection period is equal to the length of the period during which the scan signal remains active during the threshold voltage detection period and the data write / mobility correction period. A light emitting diode display device, characterized in that. The method of claim 11,
the nth (n is a natural number) pixel and the n + 1th pixel sequentially display images;
Phases of the scan signal supplied to the nth pixel and the initialization signal supplied to the n + 1th pixel are the same; And,
And a scan line connected to the data switching element of the nth pixel and an initialization line connected to the initialization switching element of the n + 1th pixel. The method of claim 8,
And the data switching element, the merge switching element, the driving switching element, the reset switching element and the initialization switching element are all n-type transistors. The method of claim 8,
A light emitting diode display device in which a relationship between the third driving voltage, the reference voltage, the threshold voltage of the driving switching element, and the threshold voltage of the light emitting element satisfies Equation 3 below;
(Equation 3)
Third drive voltage <(threshold voltage-threshold voltage of drive switching element) <threshold voltage of light emitting diode.

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