KR20200072956A - display device - Google Patents

Abstract

The present invention relates to a display device capable of enabling different types of display devices having a pixel-free notch area to indicate the same brightness in pixel areas separated from each other. The display device includes: a substrate including a first pixel area, and a second pixel area and a third pixel area which are spaced apart from each other while being separately extended from the first pixel area to have a smaller area than the first pixel area; first, second and third pixels provided to the first, second and third pixel areas, respectively; and a dummy line placed between the second pixel area and the third pixel area, which are spaced apart from each other, so that the resistance of lines supplying an initialization voltage (Vini) to each of the second pixels of the second pixel area and each of the third pixels of the third pixel area can have the same resistance value as lines supplying an initialization voltage (Vini) to the first pixels of the first pixel area. Therefore, the display device is capable of solving a brightness compensation error due to a level difference between initialization voltages of areas spaced apart from each other in a structure in which a middle wire is cut by a notch area (B).

Description

Display device

The present invention relates to a display device, and more particularly, to a display device having the same luminance in pixel regions separated from each other in a heterogeneous display device having a notch area.

The display device includes a plurality of pixels including a display element, and each pixel includes wirings and a plurality of transistors connected to the wirings to drive the display element. The wires may have different load values depending on the length. In the final image provided by the display device, a luminance difference due to a difference in load values may occur.

An object of the present invention is to provide a display device capable of canceling characteristic variations that may occur within the same panel.

Another object of the present invention is to provide a display device capable of having uniform brightness regardless of region.

Another object of the present invention is to provide a display device capable of solving a luminance deviation of a release display device including a notch.

Another object of the present invention is to provide a display device capable of compensating for load deviation in a heterogeneous display device.

To achieve this object, the display device according to the present invention includes a first pixel area, a second pixel area and a third pixel area that are spaced apart from each other and extend from the first pixel area and have a smaller area than the first pixel area. Board; First, second and third pixels provided in each of the first, second and third pixel areas; The resistance of the line supplying the initialization voltage Vini to the second pixels in the second pixel region and the third pixels in the third pixel region causes the initialization voltage Vini to be applied to the first pixels in the first pixel region. It characterized in that it comprises a dummy line (dummy line) disposed between the second pixel area and the third pixel area spaced from each other to have the same resistance value as the line to be supplied.

A detailed feature of the display device according to the present invention is that the second pixel areas spaced from each other have the same area.

A detailed feature of the display device according to the present invention is that the second pixel areas spaced apart from each other are spaced apart between pixel-free notch areas where pixels are not formed.

A detailed feature of the display device according to the present invention is that the dummy line is formed along the inner edge of the pixel-free notched area.

A detailed feature of the display device according to the present invention is that the lengths of the initialization voltage supply lines in the first pixel region are longer than the lengths of the initialization voltage supply lines in the second pixel region and the third pixel region.

A detailed feature of the display device according to the present invention is that the dummy line connects the gate lines of the second pixel area and the third pixel area spaced apart from each other so as to have the same resistance value as the gate lines of the first pixel area.

A detailed feature of the display device according to the present invention may include the first, second, and third pixels of an organic light emitting diode.

The detailed characteristics of the display device according to the present invention may display the same luminance between the second pixel area and the third pixel area spaced apart from each other.

The display device according to the present invention can exhibit the following effects.

First, it is possible to resolve the characteristic deviation due to the process deviation on the left and right of the panel.

Second, it is possible to compensate for the load deviation of the heterogeneous display device.

Third, it is possible to remove the luminance deviation of the heterogeneous display device.

1 is a plan view showing a display device according to the present invention.
2 is a block diagram showing an embodiment of a pixel and a driver according to the present invention.
3 is an exemplary view showing a resistance component according to an initialization supply line disposed in each pixel area.
4 is an exemplary view showing luminance deviation of a spaced apart pixel region when a notch region is formed.
5 is an exemplary view showing an initialization supply line disposed in each pixel area.
FIG. 6 is an enlarged view of a portion “C” of FIG. 5.
7 is a sectional view taken along line I-I' of "C1" in FIG. 6;
8 is an exemplary view illustrating an arrangement area of a dummy line in the display device according to the present invention.
FIG. 9 is an enlarged view of a portion “D” of FIG. 8.
10 is a cross-sectional view taken along the line II-II' in “D1” of FIG. 9.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are exemplified only for the purpose of illustrating the embodiments of the present invention, and the embodiments of the present invention can be implemented in various forms, and It should not be interpreted as being limited to the described embodiments.

The present invention can be applied to various changes and may have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure form, and it should be understood as including all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from other components. For example, the first component may be referred to as the second component without departing from the scope of the present invention, and similarly, the second component may also be referred to as the first component.

When an element is said to be "connected" or "connected" to another component, it is understood that other components may be directly connected to or connected to the other component, but there may be other components in between. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there are no other components in the middle. Other expressions that describe the relationship between the components, such as "between" and "immediately between" or "neighboring" and "directly neighboring to" should be interpreted as well.

Terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises" or "haves" are intended to indicate that a disclosed feature, number, step, operation, component, part, or combination thereof exists, one or more other features or numbers, It should be understood that the existence or addition possibilities of steps, actions, components, parts or combinations thereof are not excluded in advance.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms such as those defined in a commonly used dictionary should be interpreted to indicate meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined in the present application. Does not.

On the other hand, when an embodiment can be implemented differently, functions or operations specified in a specific block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be executed substantially simultaneously, or the blocks may be performed backwards depending on related functions or operations.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a substrate SUB and pixels PXL1, PXL2, PXL3 (hereinafter referred to as PXL) provided on the substrate SUB, and the substrate SUB. It is provided and includes a driving unit for driving the pixels PXL, and a wiring unit (not shown) connecting the pixels PXL and the driving unit.

The substrate SUB includes a plurality of regions, and at least two of them have different areas. In one example, the substrate SUB may have two regions, and the two regions may have different areas. In addition, in one example, the substrate SUB may have three regions. In this case, all three areas may have different areas, or only two of the three areas may have different areas. In one example, the substrate SUB may have four or more regions.

In the following embodiment, for convenience of description, it is illustrated that the substrate SUB includes three regions, that is, first to third regions A1, A2, and A3. The first to third regions A1, A2, and A3 are illustrated as having a substantially rectangular shape, respectively, but a closed polygon, a circle, an ellipse, etc. including curved sides, such as a straight line and a curved line It may be provided in a variety of shapes, such as semi-circle, semi-ellipse including the side made.

The first to third regions A1, A2, and A3 each have pixel regions PXA1, PXA2, PXA3; hereinafter, PXA, and peripheral regions PPA1, PPA2, PPA3; hereinafter PPA. The pixel areas PXA are areas in which pixels PXL displaying an image are provided. Each pixel PXL will be described later. The peripheral areas PPA are areas in which pixels PXL are not provided, and are areas in which an image is not displayed. The peripheral areas PPA are provided with a driving unit for driving the pixels PXL, and a part of a wiring (not shown) connecting the pixels PXL and the driving unit. The peripheral areas PPA correspond to the bezel in the final display device, and the width of the bezel may be determined according to the width of the peripheral area.

The first to third regions A1, A2, and A3 are described as follows.

The first area A1 has the largest area among the first to third areas A1, A2, and A3. The first area A1 has a first pixel area PXA1 in which an image is displayed and a first peripheral area PPA1 surrounding at least a portion of the first pixel area PXA1.

The first pixel area PXA1 is provided in a shape corresponding to the shape of the first area A1. In one embodiment of the present invention, the first pixel area PXA1 has a first width W1 in a first direction DR1 and a second direction DR2 crossing the first direction DR1. As a result, it may have a first length L1.

The first peripheral area PPA1 is provided on at least one side of the first pixel area PXA1. In one embodiment of the present invention, the first peripheral area PPA1 surrounds the circumference of the first pixel area PXA1, and the second area A2 and the third area A3, which will be described later, are It can be provided anywhere except the arranged part. In one embodiment of the present invention, the first peripheral area PPA1 may include a horizontal portion extending in the width direction and a vertical portion extending in the length direction. The vertical portion of the first peripheral area PPA1 is provided as a pair spaced apart from each other along the width direction of the first pixel area PXA1.

The second area A2 has a smaller area than the first area A1. The second area A2 has a second pixel area PXA2 where an image is displayed and a second peripheral area PPA2 surrounding at least a portion of the second pixel area PXA2.

The second pixel area PXA2 is provided in a shape corresponding to the shape of the second area A2. In an embodiment of the present invention, the second pixel area PXA2 has a second width W2 smaller than the first width W1 of the first area A1. The second pixel area PXA2 may have a second length L2 smaller than the first length L1 of the first area A1. The second pixel area PXA2 is provided in a form protruding from the first pixel area PXA1 and is directly connected to the first pixel area PXA1. In other words, in the second pixel area PXA2, an edge portion closest to the first pixel area PXA1 coincides with an edge of the first pixel area PXA1.

The second peripheral area PPA2 is provided on at least one side of the second pixel area PXA2. In one embodiment of the present invention, the second peripheral area PPA2 surrounds the second pixel area PXA2, and the first pixel area PXA1 and the second pixel area PXA2 are connected. Parts may not be provided. In one embodiment of the present invention, the second peripheral area PPA2 may also include a horizontal portion extending in the width direction and a vertical portion extending in the length direction. The vertical portion of the second peripheral area PPA2 may be provided as a pair spaced apart from each other along the width direction of the second pixel area PXA2.

The third area A3 has a smaller area than the first area A1. The third area A3 may have the same area as the second area A2 or may have a different area. The third area A3 includes a third pixel area PXA3 in which an image is displayed and a third peripheral area PPA3 surrounding at least a portion of the third pixel area PXA3.

The third pixel area PXA3 is provided in a shape corresponding to the shape of the third area A3. In one embodiment of the present invention, the third pixel area PXA3 has a third width W3 smaller than the first width W1 of the first area A1. The third pixel area PXA3 may have a third length L3 smaller than the first length L1 of the first area A1. The second width W2 and the third width W3 may be the same, and the second length L2 and the third length L3 may be the same. In addition, the second width W2 and the third width W3 may be different from each other, and the second length L2 and the third length L3 may be different from each other.

The third pixel area PXA3 is provided in a form protruding from the first pixel area PXA1, and is directly connected to the first pixel area PXA1. In other words, in the third pixel area PXA3, an edge portion closest to the third pixel area PXA3 coincides with an edge of the first pixel area PXA1.

The third peripheral area PPA3 is provided on at least one side of the third pixel area PXA3. According to an embodiment of the present invention, the third peripheral area PPA3 surrounds the third pixel area PXA3, and the first pixel area PXA1 and the third pixel area PXA3 are connected. Parts may not be provided. In one embodiment of the present invention, the third peripheral area PPA3 may also include a horizontal portion extending in the width direction and a vertical portion extending in the length direction. The vertical portion of the third peripheral area PPA3 may also be provided as a pair spaced apart from each other along the width direction of the first pixel area PXA1.

In one embodiment of the present invention, the third area A3 may have a shape that is line-symmetric with the second area A2, in which case each component of the third area A3 is provided. The arrangement relationship may be substantially the same as in the second region A2 except for some wiring.

In an embodiment of the present invention, the vertical portions of the first peripheral region PPA1 may be connected to some of the vertical portions of the second peripheral region PPA2 and the third peripheral region PPA3, respectively. For example, the left vertical portion of the first peripheral region PPA1 and the left vertical portion of the second peripheral region PPA2 may be connected. The right vertical portion of the first peripheral region PPA1 and the right vertical portion of the third peripheral region PPA3 may be connected. In addition, the width W4 of the left vertical portion of the first peripheral region PPA1 and the left vertical portion of the second peripheral region PPA2 may be the same. The width W5 of the right vertical portion of the first peripheral region PPA1 and the right vertical portion of the third peripheral region PPA3 may be the same.

The width W4 of the left vertical portion of the first peripheral region PPA1 and the second peripheral region PPA2 is the width W5 of the right vertical portion of the first peripheral region PPA1 and the third peripheral region PPA3. ), but may be different. For example, the width W4 of the left vertical portion of the first peripheral region PPA1 and the second peripheral region PPA2 is the right vertical side of the first peripheral region PPA1 and the third peripheral region PPA3. It may be smaller than the width W5 of the negative.

The pixels PXL are provided in the pixel areas PXA on the substrate SUB, that is, in the first to third pixel areas PXA1, PXA2, and PXA3. Each pixel PXL may be provided in a plurality as a minimum unit for displaying an image. The pixels PXL may include an organic light emitting device that emits color light. Each pixel PXL may emit any one of red, green, and blue colors, but is not limited thereto, and may emit colors such as cyan, magenta, yellow, and white.

The pixels PXL include first pixels PXL1 arranged in the first pixel area PXA1, second pixels PXL2 arranged in a second pixel area PXA2, and third pixel areas ( PXA3) and the third pixels PXL3. In one embodiment of the present invention, the first to third pixels PXL1 and PXL2 PXL3 are provided in plural, respectively, and a row extending in the first direction DR1 and a column extending in the second direction DR2 It can be arranged in a row form along. However, the arrangement form of the first to third pixels PXL1, PXL2, and PXL3 is not particularly limited, and may be arranged in various forms. For example, the first pixels PXL1 may be arranged such that the first direction DR1 is a row direction, but the second pixels PXL2 are different directions than the first direction DR1, for example For example, the first direction DR1 may be arranged such that an oblique direction becomes a row direction. Also, it is needless to say that the third pixels PXL3 may be arranged in the same direction or different directions from the first pixels PXL1 and/or the second pixels PXL2. Alternatively, in another embodiment of the present invention, the row direction may be the second direction DR2 and the column direction may be the first direction DR1.

The driving unit provides a signal to each pixel through a wiring unit, thereby controlling the driving of each pixel PXL. In FIG. 1, a wiring unit is omitted for convenience of description.

The driver includes scan drivers (SDV1, SDV2, SDV3; SDV) that provide scan signals to each pixel along a scan line, and light-emitting drivers (EDV1, EDV2) that provide emission control signals to each pixel along the emission control line. , EDV3 (hereinafter referred to as EDV), and a data driver DDV that provides data signals to each pixel along a data line, and a timing controller (not shown). The timing control unit controls the scan driving unit SDV, the light emitting driving unit EDV, and the data driving unit DDV.

In one embodiment of the present invention, the scan drivers SDV include a first scan driver SDV1 connected to the first pixels PXL1 and a second scan driver SDV2 connected to the second pixels PXL2. A third scan driver SDV3 connected to the third pixels PXL3 may be included. In one embodiment of the present invention, the light emission driving units EDV include a first light emission driving unit EDV1 connected to the first pixels PXL1 and a second light emission driving unit EDV2 connected to the second pixels PXL2. A third emission driver EDV3 connected to the third pixels PXL3 may be included.

The first scan driver SDV1 may be disposed in a vertical portion of the first peripheral area PPA1. The vertical portion of the first peripheral region PPA1 is provided as a pair spaced apart from each other along the width direction of the first pixel region PXA1, and the first scan driver SDV1 includes the first peripheral region PPA1. ) May be disposed on at least one of the vertical portions. The first scan driver SDV1 may extend long in a length direction of the first peripheral area PPA1.

In a similar manner, the second scan driver SDV2 may be disposed in the second peripheral region PPA2 and the third scan driver SDV3 may be disposed in the third peripheral region PPA3.

In one embodiment of the present invention, the scan drivers SDV may be directly mounted on the substrate SUB. When the scan drivers SDV are directly mounted on the substrate SUB, they may be formed together in the process of forming the pixels PXL. However, the location or method of providing the scan drivers SDV is not limited thereto, and may be provided in a chip on glass formed on a separate chip, or a printed circuit board. It may be mounted on and connected to the substrate SUB through a connecting member.

The first emission driving unit EDV1 may also be disposed in a vertical portion of the first peripheral area PPA1, similar to the first scan driving unit SDV1. The first emission driving part EDV1 may be disposed on at least one of the vertical parts of the first peripheral area PPA1. The first light emission driving unit EDV1 may extend long in a length direction of the first peripheral area PPA1.

In a similar manner, the second emission driving unit EDV2 may be disposed in the second peripheral region PPA2 and the third emission driving unit EDV3 may be disposed in the third peripheral region PPA3.

In one embodiment of the present invention, the emission driving units EDV may be directly mounted on the substrate SUB. When the emission driving units EDV are directly mounted on the substrate SUB, they may be formed together in the process of forming the pixels PXL. However, the location or method of providing the light emitting driving units EDV is not limited thereto, and may be provided in a chip on glass formed on a separate chip, or a printed circuit board. It may be mounted on and connected to the substrate SUB through a connecting member.

In one embodiment of the present invention, the scan driving units SDV and the light emitting driving units EDV are adjacent to each other and are shown as an example in which only one of the vertical pair of peripheral areas PPA is formed. , But is not limited to this, the arrangement may be changed in various ways. For example, the first scan driver SDV1 is on one side of the vertical portion of the first peripheral region PPA1, and the first light-emitting driver EDV1 is on the other side of the vertical portion of the first peripheral region PPA1. Can be provided. Alternatively, the first scan driver SDV1 may be provided on both sides of the vertical portion of the first peripheral region PPA1, and the first light emission driver EDV1 may be provided on the vertical portion of the first peripheral region PPA1. It can only be provided on one side.

The data driver DDV may be disposed in the first peripheral area PPA1. In particular, the data driving part DDV may be disposed at a horizontal part of the first peripheral area PPA1. The data driving part DDV may be elongated along the width direction of the first peripheral area PPA1.

In an embodiment of the present invention, the positions of the scan drivers SDV, the light emitting drivers EDV, and/or the data driver DDV may be changed with each other as necessary.

The timing controller (not shown) may include the first to third scan drivers SDV1, SDV2, and SDV3 in various ways, the first to third light emitting drivers EDV1, EDV2, EDV3, and the data driver DDV. ) May be connected through a wire, and the position to be disposed is not particularly limited. For example, the timing control unit is mounted on a printed circuit board, and the first to third scan drivers SDV1, SDV2, SDV3 and first to third light emitting drivers EDV1 are mounted through a flexible printed circuit board. , EDV2, EDV3, and the data driver DDV, and the printed circuit board may be disposed at various positions, such as one side of the substrate SUB or the back side of the substrate SUB.

In various embodiments of the present invention, the shape of the substrate SUB may be variously changed. For example, it may have a polygonal shape. Each of the first to third regions A1, A2, and A3 is a closed polygon including a side of a straight line, a circle, an ellipse, etc. including a side made of a curve, It may be provided in various shapes, such as a semicircle, a semi-ellipse, including sides made of straight lines and curves.

In various embodiments of the present invention, the first, second, and third pixels may include organic light emitting diodes.

According to various embodiments of the present invention, the second pixel area and the third pixel area spaced apart from each other may have the same area or different areas.

2 is a block diagram illustrating an embodiment of a pixel and a driver according to an embodiment of the present invention.

Referring to FIG. 2, a display device according to an exemplary embodiment of the present invention may include pixels PXL, a driving unit, and a wiring unit. The pixels PXL include first to third pixels PXL1, PXL2, and PXL3, and the driver includes first to third scan drivers SDV1, SDV2, and SDV3, and first to third light emitting drivers EDV1 , EDV2, EDV3, a data driver DDV, and a timing controller TC. In FIG. 2, positions of the first to third scan drivers SDV1, SDV2, and SDV3, the first to third light emitting drivers EDV1, EDV2, EDV3, data driver DDV, and timing controller TC are shown in FIG. It is set for convenience of description, and when an actual display device is implemented, it may be disposed at another location within the display device. For example, the data driver DDV is disposed in a region adjacent to the second region A2 and the third region A3 than the first region A1, but is not limited thereto. For example, the data driver DDV may be disposed in an area adjacent to the first area A1.

The wiring unit provides a signal of the driving unit to each pixel PXL, and may include scan lines, data lines, and emission control lines, a power line, and an initialization power line (not shown). The scan lines include first to third scan lines S11 to S1n, S21 and S22, S31 and S32 respectively connected to the first to third pixels PXL1, PXL2 and PXL3, and the emission control lines are The first to third emission control lines E11 to E1n, E21 and E22, E31 and E32 connected to the first to third pixels PXL1, PXL2, and PXL3, respectively, may be included. The data lines D1 to Dm and the power line may be connected to the first to third pixels PXL1, PXL2, and PXL3.

The first pixels PXL1 are positioned in the first pixel area PXA1. The first pixels PXL1 may be connected to the first scan lines S11 to S1n, the first emission control lines E11 to E1n, and the data lines D1 to Dm. The first pixels PXL1 receive data signals from the data lines D1 to Dm when the scan signals are supplied from the first scan lines S11 to S1n. The first pixels PXL1 supplied with the data signal may control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via an organic light emitting device (not shown).

The second pixels PXL2 are positioned in the second pixel area PXA2. The second pixels PXL2 are connected to the second scan lines S21 and S22, the second emission control lines E21 and E22, and the data lines D1 to D3. The second pixels PXL2 receive data signals from the data lines D1 to D3 when the scan signals are supplied from the second scan lines S21 and S22. The second pixels PXL2 supplied with the data signal control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the organic light emitting device.

Additionally, in FIG. 2, the second pixel area PXA2 is formed by two second scan lines S21 and S22, two second emission control lines E21 and E22, and three data lines D1 to D3. ), the six second pixels PXL2 are positioned, but the present invention is not limited thereto. That is, a plurality of second pixels PXL2 are disposed corresponding to the size of the second pixel area PXA2, and the second scan lines and the second emission control lines correspond to the second pixels PXL2. And the number of data lines can be variously set.

The third pixels PXL3 may include a third pixel area divided by third scan lines S31 and S32, third light emission control lines E31 and E32, and data lines Dm-2 to Dm. PXA3). The third pixels PXL3 receive data signals from the data lines Dm-2 to Dm when the scan signals are supplied from the third scan lines S31 and S32. The third pixels PXL3 supplied with the data signal may control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the organic light emitting device.

Additionally, in FIG. 2, the third pixel area is formed by two third scan lines S31 and S32, two third emission control lines E31 and E32, and three data lines Dm-2 to Dm. Although it is illustrated that six third pixels PXL3 are positioned in (PXA3), the present invention is not limited thereto. That is, a plurality of third pixels PXL3 are disposed corresponding to the size of the third pixel area PXA3, and the third scan lines, the third emission control lines, and the third pixels PXL3 correspond to the third pixels PXL3. The number of data lines can be variously set.

The first scan driver SDV1 may supply a scan signal to the first scan lines S11 to S1n in response to the first gate control signal GCS1 from the timing controller TC. In one example, the first scan driver SDV1 may sequentially supply the scan signal to the first scan lines S11 to S1n. When the scan signal is sequentially supplied to the first scan lines S11 to S1n, the first pixels PXL1 may be sequentially selected in units of horizontal lines.

The second scan driver SDV2 may supply the scan signal to the second scan lines S21 and S22 in response to the second gate control signal GCS2 from the timing controller TC. For example, the second scan driver SDV2 may sequentially supply the scan signal to the second scan lines S21 and S22. When the scan signal is sequentially supplied to the second scan lines S21 and S22, the second pixels PXL2 may be sequentially selected in units of horizontal lines.

The third scan driver SDV3 may supply the scan signal to the third scan lines S31 and S32 in response to the third gate control signal GCS3 from the timing controller TC. For example, the third scan driver SDV3 may sequentially supply the scan signal to the third scan lines S31 and S32. When the scan signal is sequentially supplied to the third scan lines S31 and S32, the third pixels PXL3 may be sequentially selected in units of horizontal lines.

The first emission driver EDV1 may supply the emission control signal to the first emission control lines E11 to E1n in response to the fourth gate control signal GCS4 from the timing controller TC. In one example, the first emission driver EDV1 may sequentially supply the emission control signals to the first emission control lines E11 to E1n.

Here, the emission control signal may be set to a wider width than the scan signal. For example, the emission control signal supplied to the i (i is a natural number) first emission control line E1i is a scan signal supplied to the i-1th first scan line S1i-1 and the i th first scan line It may be supplied so as to overlap at least a part of the scan signal supplied to (S1i).

The second emission driving unit EDV2 may supply the emission control signal to the second emission control lines E21 and E22 in response to the fifth gate control signal GCS5 from the timing controller TC. For example, the second emission driving unit EDV2 may sequentially supply the emission control signals to the second emission control lines E21 and E22.

The third emission driver EDV3 may supply the emission control signal to the third emission control lines E31 and E32 in response to the sixth gate control signal GCS6 from the timing controller TC. In one example, the third emission driver EDV3 may sequentially supply the emission control signals to the third emission control lines E31 and E32.

Additionally, the emission control signal is set to a gate-off voltage (for example, a high voltage) so that the transistor included in the pixels PXL is turned off, and the scan signal includes a transistor included in the pixels PXL. It can be set to a gate-on voltage (eg, a low voltage) so that it can be turned on.

The data driver DDV may supply a data signal to the data lines D1 to Dm in response to the data control signal DCS. The data signal supplied to the data lines D1 to Dm may be supplied to the pixels PXL selected by the scan signal.

The timing controller TC supplies the gate control signals GCS1 to GCS6 generated based on timing signals supplied from the outside to the scan drivers SDV and the light emitting drivers EDV, and the data control signal DCS ) To the data driver DDV. Each of the gate control signals GCS1 to GCS6 may include start pulse and clock signals. The start pulse may control the timing of the first scan signal or the first emission control signal. Clock signals can be used to shift the start pulse.

The source start pulse and clock signals may be included in the data control signal DCS. The source start pulse can control the starting point of sampling of data. Clock signals can be used to control the sampling operation.

Meanwhile, when the display device is sequentially driven, the first scan driver SDV1 may receive the last output signal of the second scan driver SDV2 as a start pulse. In this case, the first scan driver SDV1 and the second scan driver SDV2 may share control signals, and accordingly, the timing controller TC transmits the gate control signal GCS2 to the second scan driver SDV2. The gate control signal GSC1 may not be supplied to the first scan driver SDV1.

Similarly, when a separate scan driver for driving the first pixels PXL1 is added to the lower portion of the third scan driver SDV3, the added scan driver and the third scan driver SDV3 share a control signal. Can. In addition, the scan driver to be added may receive the last scan signal of the third scan driver SDV3 as a start pulse.

In addition, when the display device is sequentially driven, the first emission driver EDV1 may receive the last output signal of the second emission driver EDV2 as a start pulse. In this case, the first emission driving unit EDV1 and the second emission driving unit EDV2 may share control signals, and accordingly, the timing controller TC transmits the gate control signal GCS5 to the second emission driving unit EDV2. The gate control signal GCS4 may not be supplied to the first emission driver EDV1.

Similarly, when a separate light emitting driver for driving the first pixels PXL1 is added to the lower portion of the third light emitting driver EDV3, the added light emitting driver and the third light emitting driver EDV3 share the control signal. Can. In addition, the added emission driver may receive the last emission control signal of the third emission driver EDV3 as a start pulse.

Meanwhile, as illustrated in FIG. 3, the lengths of the initialization voltage supply lines of the second pixel area PXA2 and the third pixel area PXA3 are relatively larger than the lengths of the initialization voltage supply lines of the first pixel area PXA1. short. Since the intermediate wiring is cut by the notch region B, luminance compensation reflecting the sampled value cannot be properly performed due to the difference in the level of the initialization voltage.

In addition, in a heterogeneous display device having a pixel-free notch area B, the wiring is cut off from the center by the notch area B. Accordingly, a deviation in driving characteristics of the second pixels arranged in the second pixel area PXA2 and the third pixels arranged in the third pixel area PXA3 may not be canceled out, and thus a luminance deviation may occur. That is, in order to sense the threshold voltage of the driving transistor included in each pixel region, the line width or thickness of the initialization voltage (Vini) supply line that supplies initialization power through the gate electrode of the driving transistor in each pixel region is the second pixel region. A difference may be expressed in the (PXA2) and the third pixel area (PXA2). Accordingly, a difference may occur in the level of the initialization voltage V _{ini in the} 2 pixel area PXA2 and the 3rd pixel area PXA2, and a deviation may occur in the compensation values of the pixels included in each area.

5 is initialized through a gate electrode of a driving transistor in each pixel region to sense threshold voltages of the driving transistors included in the first to third pixel regions PXA1, PXA2, and PXA3 and each pixel disposed in each region. It is an exemplary view showing an initialization voltage (Vini) supply line for supplying power, and FIG. 6 is an enlarged view showing a portion “C” of FIG. 5. As illustrated, the same metal line as the source/drain electrode of the driving transistor is disposed on the initialization supply line Vini. 7 is a cross-sectional view taken along line I-I' for the portion “C1” of FIG. 6. As illustrated, a first interlayer insulating film (ILD1: 102) is disposed on the gate insulating film (GI: 101), an initialization voltage of the same metal on the same layer as the gate electrode on the first interlayer insulating film 102 A supply line (Vini: 105) is arranged. A second interlayer insulating layer (ILD2: 103) is disposed on the initialization voltage supply line 105. The same metal line (SD: 106) as the source/drain electrode of the driving transistor is disposed on the second interlayer insulating layer 103, and a protective layer (PAS: 104) is formed thereon.

In a preferred embodiment of the present invention, a difference in compensation values of pixels included in each region is prevented from occurring due to a difference in level between the initialization voltage V _ini in the second pixel region PXA2 and the third pixel region PXA2. To do this, as illustrated in FIG. 8, a dummy line disposed between two pixel areas PXA2 and PXA3 may be included. That is, the resistance of the line that supplies the initialization voltage V _ini to the second pixels of the second pixel area A2 and the third pixels of the third pixel area PXA3 is the first pixel of the first pixel area. Dummy lines are disposed along the inner edges of the second pixel area PXA2 and the third pixel area PXA3 spaced apart from each other so as to have the same resistance value as the line that supplies the initialization voltage V _ini to the fields. . The dummy line is connected to reach a panel portion between the second pixel area PXA2 and the second peripheral area PPA2 and adjacent to the side notch area of the third pixel area PXA3. .

FIG. 9 is an enlarged view of a portion “D” of FIG. 8. As shown in FIG. 6, it can be seen that, unlike the example of FIG. 6, the initialization voltage supply line V _ini line of the second pixel area PXA2 extends from the pixel area toward the notch area, and is disposed on the dummy line thereon. have.

10 is a cross-sectional view taken along line II-II' in the area "D1" in FIG. As illustrated, a first interlayer insulating film (ILD1: 102) is disposed on the gate insulating film (GI: 101), an initialization voltage of the same metal on the same layer as the gate electrode on the first interlayer insulating film 102 The supply line V _ini 105 extends from the pixel area to the notch area. A second interlayer insulating layer (ILD2: 103) is disposed on the extended initialization voltage supply line 105. The same metal line (SD: 106) as the source/drain electrode of the driving transistor is disposed on the second interlayer insulating layer 103. At this time, the dummy line 107 of the same metal material is disposed on the same layer and the same layer as the metal line 106 through the contact hole at the upper portion of the extended initialization voltage supply line 105, and a protective layer ( PAS: 104) is formed.

As shown through the above description, due to the notch formation, the horizontal wiring is cut off from the center, and the difference in driving characteristics due to the left and right process deviation in the two pixel areas spaced apart from each other may offset the left and right luminance deviation through the dummy line.

Although described above with reference to preferred embodiments of the present invention, those skilled in the art variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You can understand that you can.

101: gate insulating film 102: first interlayer insulating film
103: second interlayer insulating film 104: protective layer
105: initialization voltage supply line 106: metal line
107: dummy line

Claims (8)

A first pixel region, a substrate having a second pixel region and a third pixel region that are spaced apart from each other and extending from each of the first pixel region and having a smaller area than the first pixel region;
First, second and third pixels provided in each of the first, second and third pixel areas;
The resistance of the lines supplying the initialization voltage Vini to the second pixels in the second pixel area and the third pixels in the third pixel area is the initialization voltage Vini to the first pixels in the first pixel area. And a dummy line disposed between the second pixel area and the third pixel area spaced apart from each other so as to have the same resistance value as the lines supplying. The display device according to claim 1, wherein the second pixel area and the third pixel area spaced apart from each other have the same area. The display device of claim 1, wherein the second pixel area and the third pixel area spaced apart from each other are spaced apart between pixel-free notch areas in which no pixels are formed. The display device according to claim 3, wherein the dummy line is formed along an inner edge of the pixel-free notched area. The display device of claim 1, wherein lengths of the initialization voltage supply lines in the first pixel area are longer than lengths of the initialization voltage supply lines in the second pixel area and the third pixel area. The method of claim 5, wherein the dummy line is connected to the initialization voltage supply line of the second pixel area and the third pixel area spaced from each other so as to have the same resistance value as the resistance value of the initialization voltage supply lines of the first pixel area. Display device. The display device of claim 1, wherein the first, second, and third pixels include an organic light emitting diode. The display device according to claim 1, wherein the second pixel area and the third pixel area spaced apart from each other exhibit the same luminance.

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